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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
2 * pbm.h: UltraSparc PCI controller software state.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 */
6
7#ifndef __SPARC64_PBM_H
8#define __SPARC64_PBM_H
9
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/ioport.h>
13#include <linux/spinlock.h>
14
15#include <asm/io.h>
16#include <asm/page.h>
17#include <asm/oplib.h>
David S. Millere87dc352006-06-21 18:18:47 -070018#include <asm/prom.h>
David S. Miller2b1e5972006-06-29 15:07:37 -070019#include <asm/of_device.h>
David S. Miller7c963ad2005-05-31 16:57:59 -070020#include <asm/iommu.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
22/* The abstraction used here is that there are PCI controllers,
23 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
24 * underneath. Each PCI bus module uses an IOMMU (shared by both
25 * PBMs of a controller, or per-PBM), and if a streaming buffer
26 * is present, each PCI bus module has it's own. (ie. the IOMMU
27 * might be shared between PBMs, the STC is never shared)
28 * Furthermore, each PCI bus module controls it's own autonomous
29 * PCI bus.
30 */
31
Linus Torvalds1da177e2005-04-16 15:20:36 -070032struct pci_controller_info;
33
34/* This contains the software state necessary to drive a PCI
35 * controller's IOMMU.
36 */
David S. Miller688cb302005-10-13 22:15:24 -070037struct pci_iommu_arena {
38 unsigned long *map;
39 unsigned int hint;
40 unsigned int limit;
41};
42
Linus Torvalds1da177e2005-04-16 15:20:36 -070043struct pci_iommu {
44 /* This protects the controller's IOMMU and all
45 * streaming buffers underneath.
46 */
47 spinlock_t lock;
48
David S. Miller688cb302005-10-13 22:15:24 -070049 struct pci_iommu_arena arena;
50
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 /* IOMMU page table, a linear array of ioptes. */
52 iopte_t *page_table; /* The page table itself. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54 /* Base PCI memory space address where IOMMU mappings
55 * begin.
56 */
57 u32 page_table_map_base;
58
59 /* IOMMU Controller Registers */
60 unsigned long iommu_control; /* IOMMU control register */
61 unsigned long iommu_tsbbase; /* IOMMU page table base register */
62 unsigned long iommu_flush; /* IOMMU page flush register */
63 unsigned long iommu_ctxflush; /* IOMMU context flush register */
64
65 /* This is a register in the PCI controller, which if
66 * read will have no side-effects but will guarantee
67 * completion of all previous writes into IOMMU/STC.
68 */
69 unsigned long write_complete_reg;
70
Linus Torvalds1da177e2005-04-16 15:20:36 -070071 /* In order to deal with some buggy third-party PCI bridges that
72 * do wrong prefetching, we never mark valid mappings as invalid.
73 * Instead we point them at this dummy page.
74 */
75 unsigned long dummy_page;
76 unsigned long dummy_page_pa;
77
David S. Miller7c963ad2005-05-31 16:57:59 -070078 /* CTX allocation. */
79 unsigned long ctx_lowest_free;
80 unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
81
Linus Torvalds1da177e2005-04-16 15:20:36 -070082 /* Here a PCI controller driver describes the areas of
83 * PCI memory space where DMA to/from physical memory
84 * are addressed. Drivers interrogate the PCI layer
85 * if their device has addressing limitations. They
86 * do so via pci_dma_supported, and pass in a mask of
87 * DMA address bits their device can actually drive.
88 *
89 * The test for being usable is:
90 * (device_mask & dma_addr_mask) == dma_addr_mask
91 */
92 u32 dma_addr_mask;
93};
94
David S. Miller51e85132005-10-13 21:10:08 -070095extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
97/* This describes a PCI bus module's streaming buffer. */
98struct pci_strbuf {
99 int strbuf_enabled; /* Present and using it? */
100
101 /* Streaming Buffer Control Registers */
102 unsigned long strbuf_control; /* STC control register */
103 unsigned long strbuf_pflush; /* STC page flush register */
104 unsigned long strbuf_fsync; /* STC flush synchronization reg */
105 unsigned long strbuf_ctxflush; /* STC context flush register */
106 unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */
107 unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */
108 volatile unsigned long *strbuf_flushflag; /* The flush flag itself */
109
110 /* And this is the actual flush flag area.
111 * We allocate extra because the chips require
112 * a 64-byte aligned area.
113 */
114 volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
115};
116
117#define PCI_STC_FLUSHFLAG_INIT(STC) \
118 (*((STC)->strbuf_flushflag) = 0UL)
119#define PCI_STC_FLUSHFLAG_SET(STC) \
120 (*((STC)->strbuf_flushflag) != 0UL)
121
122/* There can be quite a few ranges and interrupt maps on a PCI
123 * segment. Thus...
124 */
125#define PROM_PCIRNG_MAX 64
126#define PROM_PCIIMAP_MAX 64
127
128struct pci_pbm_info {
129 /* PCI controller we sit under. */
130 struct pci_controller_info *parent;
131
132 /* Physical address base of controller registers. */
133 unsigned long controller_regs;
134
135 /* Physical address base of PBM registers. */
136 unsigned long pbm_regs;
137
David S. Millerbb6743f42005-07-04 13:26:04 -0700138 /* Physical address of DMA sync register, if any. */
139 unsigned long sync_reg;
140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 /* Opaque 32-bit system bus Port ID. */
142 u32 portid;
143
David S. Millerbade5622006-02-09 22:05:54 -0800144 /* Opaque 32-bit handle used for hypervisor calls. */
145 u32 devhandle;
146
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 /* Chipset version information. */
148 int chip_type;
149#define PBM_CHIP_TYPE_SABRE 1
150#define PBM_CHIP_TYPE_PSYCHO 2
151#define PBM_CHIP_TYPE_SCHIZO 3
152#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
153#define PBM_CHIP_TYPE_TOMATILLO 5
154 int chip_version;
155 int chip_revision;
156
157 /* Name used for top-level resources. */
David S. Millere87dc352006-06-21 18:18:47 -0700158 char *name;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159
160 /* OBP specific information. */
David S. Millere87dc352006-06-21 18:18:47 -0700161 struct device_node *prom_node;
162 struct linux_prom_pci_ranges *pbm_ranges;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 int num_pbm_ranges;
David S. Millere87dc352006-06-21 18:18:47 -0700164 struct linux_prom_pci_intmap *pbm_intmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 int num_pbm_intmap;
David S. Millere87dc352006-06-21 18:18:47 -0700166 struct linux_prom_pci_intmask *pbm_intmask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 u64 ino_bitmap;
168
169 /* PBM I/O and Memory space resources. */
170 struct resource io_space;
171 struct resource mem_space;
172
173 /* Base of PCI Config space, can be per-PBM or shared. */
174 unsigned long config_space;
175
176 /* State of 66MHz capabilities on this PBM. */
177 int is_66mhz_capable;
178 int all_devs_66mhz;
179
180 /* This PBM's streaming buffer. */
181 struct pci_strbuf stc;
182
183 /* IOMMU state, potentially shared by both PBM segments. */
184 struct pci_iommu *iommu;
185
186 /* PCI slot mapping. */
187 unsigned int pci_first_slot;
188
189 /* Now things for the actual PCI bus probes. */
190 unsigned int pci_first_busno;
191 unsigned int pci_last_busno;
192 struct pci_bus *pci_bus;
193};
194
195struct pci_controller_info {
196 /* List of all PCI controllers. */
197 struct pci_controller_info *next;
198
199 /* Each controller gets a unique index, used mostly for
200 * error logging purposes.
201 */
202 int index;
203
204 /* Do the PBMs both exist in the same PCI domain? */
205 int pbms_same_domain;
206
207 /* The PCI bus modules controlled by us. */
208 struct pci_pbm_info pbm_A;
209 struct pci_pbm_info pbm_B;
210
211 /* Operations which are controller specific. */
212 void (*scan_bus)(struct pci_controller_info *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 void (*base_address_update)(struct pci_dev *, int);
214 void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
215
216 /* Now things for the actual PCI bus probes. */
217 struct pci_ops *pci_ops;
218 unsigned int pci_first_busno;
219 unsigned int pci_last_busno;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220};
221
222/* PCI devices which are not bridges have this placed in their pci_dev
223 * sysdata member. This makes OBP aware PCI device drivers easier to
224 * code.
225 */
226struct pcidev_cookie {
227 struct pci_pbm_info *pbm;
David S. Millerde8d28b2006-06-22 16:18:54 -0700228 struct device_node *prom_node;
David S. Miller2b1e5972006-06-29 15:07:37 -0700229 struct of_device *op;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230 struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
231 int num_prom_regs;
232 struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
233 int num_prom_assignments;
234};
235
236/* Currently these are the same across all PCI controllers
237 * we support. Someday they may not be...
238 */
239#define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */
240#define PCI_IRQ_INO 0x0000003f /* Interrupt Number */
241
242#endif /* !(__SPARC64_PBM_H) */