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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
34
Jesse Barnes585fb112008-07-29 11:54:06 -070035#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080037#include "intel_ringbuffer.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070038#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070039#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010040#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020041#include <drm/intel-gtt.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020042#include <linux/backlight.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070043#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020044#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010045#include <linux/pm_qos.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070046
Linus Torvalds1da177e2005-04-16 15:20:36 -070047/* General customization:
48 */
49
50#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52#define DRIVER_NAME "i915"
53#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070054#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Jesse Barnes317c35d2008-08-25 15:11:06 -070056enum pipe {
57 PIPE_A = 0,
58 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080059 PIPE_C,
60 I915_MAX_PIPES
Jesse Barnes317c35d2008-08-25 15:11:06 -070061};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080062#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -070063
Paulo Zanonia5c961d2012-10-24 15:59:34 -020064enum transcoder {
65 TRANSCODER_A = 0,
66 TRANSCODER_B,
67 TRANSCODER_C,
68 TRANSCODER_EDP = 0xF,
69};
70#define transcoder_name(t) ((t) + 'A')
71
Jesse Barnes80824002009-09-10 15:28:06 -070072enum plane {
73 PLANE_A = 0,
74 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080075 PLANE_C,
Jesse Barnes80824002009-09-10 15:28:06 -070076};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080077#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -080078
Ville Syrjälä06da8da2013-04-17 17:48:51 +030079#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
80
Eugeni Dodonov2b139522012-03-29 12:32:22 -030081enum port {
82 PORT_A = 0,
83 PORT_B,
84 PORT_C,
85 PORT_D,
86 PORT_E,
87 I915_MAX_PORTS
88};
89#define port_name(p) ((p) + 'A')
90
Paulo Zanonib97186f2013-05-03 12:15:36 -030091enum intel_display_power_domain {
92 POWER_DOMAIN_PIPE_A,
93 POWER_DOMAIN_PIPE_B,
94 POWER_DOMAIN_PIPE_C,
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
102};
103
104#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107#define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
108
Egbert Eich1d843f92013-02-25 12:06:49 -0500109enum hpd_pin {
110 HPD_NONE = 0,
111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
113 HPD_CRT,
114 HPD_SDVO_B,
115 HPD_SDVO_C,
116 HPD_PORT_B,
117 HPD_PORT_C,
118 HPD_PORT_D,
119 HPD_NUM_PINS
120};
121
Chris Wilson2a2d5482012-12-03 11:49:06 +0000122#define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700128
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700129#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800130
Daniel Vetter6c2b7c12012-07-05 09:50:24 +0200131#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
134
Daniel Vettere7b903d2013-06-05 13:34:14 +0200135struct drm_i915_private;
136
Daniel Vettere2b78262013-06-07 23:10:03 +0200137enum intel_dpll_id {
138 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
140 DPLL_ID_PCH_PLL_A,
141 DPLL_ID_PCH_PLL_B,
142};
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100143#define I915_NUM_PLLS 2
144
Daniel Vetter53589012013-06-05 13:34:16 +0200145struct intel_dpll_hw_state {
Daniel Vetter66e985c2013-06-05 13:34:20 +0200146 uint32_t dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +0200147 uint32_t dpll_md;
Daniel Vetter66e985c2013-06-05 13:34:20 +0200148 uint32_t fp0;
149 uint32_t fp1;
Daniel Vetter53589012013-06-05 13:34:16 +0200150};
151
Daniel Vetter46edb022013-06-05 13:34:12 +0200152struct intel_shared_dpll {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 int refcount; /* count of number of CRTCs sharing this PLL */
154 int active; /* count of number of active CRTCs (i.e. DPMS on) */
155 bool on; /* is the PLL actually active? Disabled during modeset */
Daniel Vetter46edb022013-06-05 13:34:12 +0200156 const char *name;
157 /* should match the index in the dev_priv->shared_dplls array */
158 enum intel_dpll_id id;
Daniel Vetter53589012013-06-05 13:34:16 +0200159 struct intel_dpll_hw_state hw_state;
Daniel Vetter15bdd4c2013-06-05 13:34:23 +0200160 void (*mode_set)(struct drm_i915_private *dev_priv,
161 struct intel_shared_dpll *pll);
Daniel Vettere7b903d2013-06-05 13:34:14 +0200162 void (*enable)(struct drm_i915_private *dev_priv,
163 struct intel_shared_dpll *pll);
164 void (*disable)(struct drm_i915_private *dev_priv,
165 struct intel_shared_dpll *pll);
Daniel Vetter53589012013-06-05 13:34:16 +0200166 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
167 struct intel_shared_dpll *pll,
168 struct intel_dpll_hw_state *hw_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100171/* Used by dp and fdi links */
172struct intel_link_m_n {
173 uint32_t tu;
174 uint32_t gmch_m;
175 uint32_t gmch_n;
176 uint32_t link_m;
177 uint32_t link_n;
178};
179
180void intel_link_compute_m_n(int bpp, int nlanes,
181 int pixel_clock, int link_clock,
182 struct intel_link_m_n *m_n);
183
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300184struct intel_ddi_plls {
185 int spll_refcount;
186 int wrpll1_refcount;
187 int wrpll2_refcount;
188};
189
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190/* Interface history:
191 *
192 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100193 * 1.2: Add Power Management
194 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100195 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000196 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
198 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 */
200#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000201#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202#define DRIVER_PATCHLEVEL 0
203
Eric Anholt673a3942008-07-30 12:06:12 -0700204#define WATCH_COHERENCY 0
Chris Wilson23bc5982010-09-29 16:10:57 +0100205#define WATCH_LISTS 0
Chris Wilson42d6ab42012-07-26 11:49:32 +0100206#define WATCH_GTT 0
Eric Anholt673a3942008-07-30 12:06:12 -0700207
Dave Airlie71acb5e2008-12-30 20:31:46 +1000208#define I915_GEM_PHYS_CURSOR_0 1
209#define I915_GEM_PHYS_CURSOR_1 2
210#define I915_GEM_PHYS_OVERLAY_REGS 3
211#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
212
213struct drm_i915_gem_phys_object {
214 int id;
215 struct page **page_list;
216 drm_dma_handle_t *handle;
Chris Wilson05394f32010-11-08 19:18:58 +0000217 struct drm_i915_gem_object *cur_obj;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000218};
219
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700220struct opregion_header;
221struct opregion_acpi;
222struct opregion_swsci;
223struct opregion_asle;
224
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100225struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700226 struct opregion_header __iomem *header;
227 struct opregion_acpi __iomem *acpi;
228 struct opregion_swsci __iomem *swsci;
229 struct opregion_asle __iomem *asle;
230 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000231 u32 __iomem *lid_state;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100232};
Chris Wilson44834a62010-08-19 16:09:23 +0100233#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100234
Chris Wilson6ef3d422010-08-04 20:26:07 +0100235struct intel_overlay;
236struct intel_overlay_error_state;
237
Dave Airlie7c1c2872008-11-28 14:22:24 +1000238struct drm_i915_master_private {
239 drm_local_map_t *sarea;
240 struct _drm_i915_sarea *sarea_priv;
241};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800242#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300243#define I915_MAX_NUM_FENCES 32
244/* 32 fences + sign bit for FENCE_REG_NONE */
245#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800246
247struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200248 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000249 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100250 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800251};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000252
yakui_zhao9b9d1722009-05-31 17:17:17 +0800253struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100254 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800255 u8 dvo_port;
256 u8 slave_addr;
257 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100258 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400259 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800260};
261
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000262struct intel_display_error_state;
263
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700264struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200265 struct kref ref;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700266 u32 eir;
267 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700268 u32 ier;
Ben Widawskyb9a39062012-06-04 14:42:52 -0700269 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000270 u32 derrmr;
271 u32 forcewake;
Ben Widawsky9574b3f2012-04-26 16:03:01 -0700272 bool waiting[I915_NUM_RINGS];
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800273 u32 pipestat[I915_MAX_PIPES];
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100274 u32 tail[I915_NUM_RINGS];
275 u32 head[I915_NUM_RINGS];
Chris Wilson0f3b6842013-01-15 12:05:55 +0000276 u32 ctl[I915_NUM_RINGS];
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100277 u32 ipeir[I915_NUM_RINGS];
278 u32 ipehr[I915_NUM_RINGS];
279 u32 instdone[I915_NUM_RINGS];
280 u32 acthd[I915_NUM_RINGS];
Daniel Vetter7e3b8732012-02-01 22:26:45 +0100281 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
Chris Wilsondf2b23d2012-11-27 17:06:54 +0000282 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
Chris Wilson12f55812012-07-05 17:14:01 +0100283 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
Daniel Vetter7e3b8732012-02-01 22:26:45 +0100284 /* our own tracking of ring head and tail */
285 u32 cpu_ring_head[I915_NUM_RINGS];
286 u32 cpu_ring_tail[I915_NUM_RINGS];
Chris Wilson1d8f38f2010-10-29 19:00:51 +0100287 u32 error; /* gen6+ */
Ben Widawsky71e172e2012-08-20 16:15:13 -0700288 u32 err_int; /* gen7 */
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100289 u32 instpm[I915_NUM_RINGS];
290 u32 instps[I915_NUM_RINGS];
Ben Widawsky050ee912012-08-22 11:32:15 -0700291 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100292 u32 seqno[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000293 u64 bbaddr;
Daniel Vetter33f3f512011-12-14 13:57:39 +0100294 u32 fault_reg[I915_NUM_RINGS];
295 u32 done_reg;
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100296 u32 faddr[I915_NUM_RINGS];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200297 u64 fence[I915_MAX_NUM_FENCES];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700298 struct timeval time;
Chris Wilson52d39a22012-02-15 11:25:37 +0000299 struct drm_i915_error_ring {
300 struct drm_i915_error_object {
301 int page_count;
302 u32 gtt_offset;
303 u32 *pages[0];
Ben Widawsky8c123e52013-03-04 17:00:29 -0800304 } *ringbuffer, *batchbuffer, *ctx;
Chris Wilson52d39a22012-02-15 11:25:37 +0000305 struct drm_i915_error_request {
306 long jiffies;
307 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000308 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000309 } *requests;
310 int num_requests;
311 } ring[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000312 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000313 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000314 u32 name;
Chris Wilson0201f1e2012-07-20 12:41:01 +0100315 u32 rseqno, wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000316 u32 gtt_offset;
317 u32 read_domains;
318 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200319 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000320 s32 pinned:2;
321 u32 tiling:2;
322 u32 dirty:1;
323 u32 purgeable:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100324 s32 ring:4;
Chris Wilson93dfb402011-03-29 16:59:50 -0700325 u32 cache_level:2;
Chris Wilsonc724e8a2010-11-22 08:07:02 +0000326 } *active_bo, *pinned_bo;
327 u32 active_bo_count, pinned_bo_count;
Chris Wilson6ef3d422010-08-04 20:26:07 +0100328 struct intel_overlay_error_state *overlay;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000329 struct intel_display_error_state *display;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700330};
331
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100332struct intel_crtc_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100333struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200334struct intel_limit;
335struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100336
Jesse Barnese70236a2009-09-21 10:42:27 -0700337struct drm_i915_display_funcs {
Adam Jacksonee5382a2010-04-23 11:17:39 -0400338 bool (*fbc_enabled)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700339 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
340 void (*disable_fbc)(struct drm_device *dev);
341 int (*get_display_clock_speed)(struct drm_device *dev);
342 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200343 /**
344 * find_dpll() - Find the best values for the PLL
345 * @limit: limits for the PLL
346 * @crtc: current CRTC
347 * @target: target frequency in kHz
348 * @refclk: reference clock frequency in kHz
349 * @match_clock: if provided, @best_clock P divider must
350 * match the P divider from @match_clock
351 * used for LVDS downclocking
352 * @best_clock: best PLL values found
353 *
354 * Returns true on success, false on failure.
355 */
356 bool (*find_dpll)(const struct intel_limit *limit,
357 struct drm_crtc *crtc,
358 int target, int refclk,
359 struct dpll *match_clock,
360 struct dpll *best_clock);
Chris Wilsond2102462011-01-24 17:43:27 +0000361 void (*update_wm)(struct drm_device *dev);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800362 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
Paulo Zanoni4c4ff432013-05-24 11:59:17 -0300363 uint32_t sprite_width, int pixel_size,
364 bool enable);
Daniel Vetter47fab732012-10-26 10:58:18 +0200365 void (*modeset_global_resources)(struct drm_device *dev);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100366 /* Returns the active state of the crtc, and if the crtc is active,
367 * fills out the pipe-config with the hw state. */
368 bool (*get_pipe_config)(struct intel_crtc *,
369 struct intel_crtc_config *);
Eric Anholtf564048e2011-03-30 13:01:02 -0700370 int (*crtc_mode_set)(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -0700371 int x, int y,
372 struct drm_framebuffer *old_fb);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200373 void (*crtc_enable)(struct drm_crtc *crtc);
374 void (*crtc_disable)(struct drm_crtc *crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100375 void (*off)(struct drm_crtc *crtc);
Wu Fengguange0dac652011-09-05 14:25:34 +0800376 void (*write_eld)(struct drm_connector *connector,
377 struct drm_crtc *crtc);
Jesse Barnes674cf962011-04-28 14:27:04 -0700378 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700379 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700380 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
381 struct drm_framebuffer *fb,
382 struct drm_i915_gem_object *obj);
Jesse Barnes17638cd2011-06-24 12:19:23 -0700383 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
384 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100385 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700386 /* clock updates for mode set */
387 /* cursor updates */
388 /* render clock increase/decrease */
389 /* display clock increase/decrease */
390 /* pll clock increase/decrease */
Jesse Barnese70236a2009-09-21 10:42:27 -0700391};
392
Chris Wilson990bbda2012-07-02 11:51:02 -0300393struct drm_i915_gt_funcs {
394 void (*force_wake_get)(struct drm_i915_private *dev_priv);
395 void (*force_wake_put)(struct drm_i915_private *dev_priv);
396};
397
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100398#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
399 func(is_mobile) sep \
400 func(is_i85x) sep \
401 func(is_i915g) sep \
402 func(is_i945gm) sep \
403 func(is_g33) sep \
404 func(need_gfx_hws) sep \
405 func(is_g4x) sep \
406 func(is_pineview) sep \
407 func(is_broadwater) sep \
408 func(is_crestline) sep \
409 func(is_ivybridge) sep \
410 func(is_valleyview) sep \
411 func(is_haswell) sep \
412 func(has_force_wake) sep \
413 func(has_fbc) sep \
414 func(has_pipe_cxsr) sep \
415 func(has_hotplug) sep \
416 func(cursor_needs_physical) sep \
417 func(has_overlay) sep \
418 func(overlay_needs_physical) sep \
419 func(supports_tv) sep \
420 func(has_bsd_ring) sep \
421 func(has_blt_ring) sep \
Xiang, Haihaof72a1182013-05-28 19:22:22 -0700422 func(has_vebox_ring) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100423 func(has_llc) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100424 func(has_ddi) sep \
425 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200426
Damien Lespiaua587f772013-04-22 18:40:38 +0100427#define DEFINE_FLAG(name) u8 name:1
428#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200429
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500430struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200431 u32 display_mmio_offset;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700432 u8 num_pipes:3;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000433 u8 gen;
Damien Lespiaua587f772013-04-22 18:40:38 +0100434 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500435};
436
Damien Lespiaua587f772013-04-22 18:40:38 +0100437#undef DEFINE_FLAG
438#undef SEP_SEMICOLON
439
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800440enum i915_cache_level {
441 I915_CACHE_NONE = 0,
442 I915_CACHE_LLC,
443 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
444};
445
Kenneth Graunke2d04bef2013-04-22 00:53:49 -0700446typedef uint32_t gen6_gtt_pte_t;
447
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800448/* The Graphics Translation Table is the way in which GEN hardware translates a
449 * Graphics Virtual Address into a Physical Address. In addition to the normal
450 * collateral associated with any va->pa translations GEN hardware also has a
451 * portion of the GTT which can be mapped by the CPU and remain both coherent
452 * and correct (in cases like swizzling). That region is referred to as GMADR in
453 * the spec.
454 */
455struct i915_gtt {
456 unsigned long start; /* Start offset of used GTT */
457 size_t total; /* Total size GTT can map */
Ben Widawskybaa09f52013-01-24 13:49:57 -0800458 size_t stolen_size; /* Total size of stolen memory */
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800459
460 unsigned long mappable_end; /* End offset that we can CPU map */
461 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
462 phys_addr_t mappable_base; /* PA of our GMADR */
463
464 /** "Graphics Stolen Memory" holds the global PTEs */
465 void __iomem *gsm;
Ben Widawskya81cc002013-01-18 12:30:31 -0800466
467 bool do_idle_maps;
Ben Widawsky67167242013-06-27 16:30:18 -0700468 struct {
469 dma_addr_t addr;
470 struct page *page;
471 } scratch;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800472
473 /* global gtt ops */
Ben Widawskybaa09f52013-01-24 13:49:57 -0800474 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -0800475 size_t *stolen, phys_addr_t *mappable_base,
476 unsigned long *mappable_end);
Ben Widawskybaa09f52013-01-24 13:49:57 -0800477 void (*gtt_remove)(struct drm_device *dev);
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800478 void (*gtt_clear_range)(struct drm_device *dev,
479 unsigned int first_entry,
480 unsigned int num_entries);
481 void (*gtt_insert_entries)(struct drm_device *dev,
482 struct sg_table *st,
483 unsigned int pg_start,
484 enum i915_cache_level cache_level);
Kenneth Graunke2d04bef2013-04-22 00:53:49 -0700485 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
486 dma_addr_t addr,
487 enum i915_cache_level level);
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800488};
Ben Widawskya54c0c22013-01-24 14:45:00 -0800489#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800490
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100491struct i915_hw_ppgtt {
Ben Widawsky8f2c59f2012-09-24 08:55:51 -0700492 struct drm_device *dev;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100493 unsigned num_pd_entries;
494 struct page **pt_pages;
495 uint32_t pd_offset;
496 dma_addr_t *pt_dma_addr;
Daniel Vetterdef886c2013-01-24 14:44:56 -0800497
498 /* pte functions, mirroring the interface of the global gtt. */
499 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
500 unsigned int first_entry,
501 unsigned int num_entries);
502 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
503 struct sg_table *st,
504 unsigned int pg_start,
505 enum i915_cache_level cache_level);
Kenneth Graunke2d04bef2013-04-22 00:53:49 -0700506 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
507 dma_addr_t addr,
508 enum i915_cache_level level);
Ben Widawskyb7c36d22013-04-08 18:43:56 -0700509 int (*enable)(struct drm_device *dev);
Daniel Vetter3440d262013-01-24 13:49:56 -0800510 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100511};
512
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300513struct i915_ctx_hang_stats {
514 /* This context had batch pending when hang was declared */
515 unsigned batch_pending;
516
517 /* This context had batch active when hang was declared */
518 unsigned batch_active;
519};
Ben Widawsky40521052012-06-04 14:42:43 -0700520
521/* This must match up with the value previously used for execbuf2.rsvd1. */
522#define DEFAULT_CONTEXT_ID 0
523struct i915_hw_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300524 struct kref ref;
Ben Widawsky40521052012-06-04 14:42:43 -0700525 int id;
Ben Widawskye0556842012-06-04 14:42:46 -0700526 bool is_initialized;
Ben Widawsky40521052012-06-04 14:42:43 -0700527 struct drm_i915_file_private *file_priv;
528 struct intel_ring_buffer *ring;
529 struct drm_i915_gem_object *obj;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300530 struct i915_ctx_hang_stats hang_stats;
Ben Widawsky40521052012-06-04 14:42:43 -0700531};
532
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800533enum no_fbc_reason {
Chris Wilsonbed4a672010-09-11 10:47:47 +0100534 FBC_NO_OUTPUT, /* no outputs enabled to compress */
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800535 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
536 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
537 FBC_MODE_TOO_LARGE, /* mode too large for compression */
538 FBC_BAD_PLANE, /* fbc not supported on plane */
539 FBC_NOT_TILED, /* buffer not tiled */
Jesse Barnes9c928d12010-07-23 15:20:00 -0700540 FBC_MULTIPLE_PIPES, /* more than one pipe active */
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700541 FBC_MODULE_PARAM,
Damien Lespiau8a5729a2013-06-24 16:22:02 +0100542 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800543};
544
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800545enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300546 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800547 PCH_IBX, /* Ibexpeak PCH */
548 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300549 PCH_LPT, /* Lynxpoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700550 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800551};
552
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200553enum intel_sbi_destination {
554 SBI_ICLK,
555 SBI_MPHY,
556};
557
Jesse Barnesb690e962010-07-19 13:53:12 -0700558#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700559#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100560#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Jesse Barnesb690e962010-07-19 13:53:12 -0700561
Dave Airlie8be48d92010-03-30 05:34:14 +0000562struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100563struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000564
Daniel Vetterc2b91522012-02-14 22:37:19 +0100565struct intel_gmbus {
566 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000567 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100568 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100569 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100570 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100571 struct drm_i915_private *dev_priv;
572};
573
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100574struct i915_suspend_saved_registers {
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000575 u8 saveLBB;
576 u32 saveDSPACNTR;
577 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000578 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000579 u32 savePIPEACONF;
580 u32 savePIPEBCONF;
581 u32 savePIPEASRC;
582 u32 savePIPEBSRC;
583 u32 saveFPA0;
584 u32 saveFPA1;
585 u32 saveDPLL_A;
586 u32 saveDPLL_A_MD;
587 u32 saveHTOTAL_A;
588 u32 saveHBLANK_A;
589 u32 saveHSYNC_A;
590 u32 saveVTOTAL_A;
591 u32 saveVBLANK_A;
592 u32 saveVSYNC_A;
593 u32 saveBCLRPAT_A;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000594 u32 saveTRANSACONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800595 u32 saveTRANS_HTOTAL_A;
596 u32 saveTRANS_HBLANK_A;
597 u32 saveTRANS_HSYNC_A;
598 u32 saveTRANS_VTOTAL_A;
599 u32 saveTRANS_VBLANK_A;
600 u32 saveTRANS_VSYNC_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000601 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000602 u32 saveDSPASTRIDE;
603 u32 saveDSPASIZE;
604 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700605 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000606 u32 saveDSPASURF;
607 u32 saveDSPATILEOFF;
608 u32 savePFIT_PGM_RATIOS;
Jesse Barnes0eb96d62009-10-14 12:33:41 -0700609 u32 saveBLC_HIST_CTL;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000610 u32 saveBLC_PWM_CTL;
611 u32 saveBLC_PWM_CTL2;
Zhenyu Wang42048782009-10-21 15:27:01 +0800612 u32 saveBLC_CPU_PWM_CTL;
613 u32 saveBLC_CPU_PWM_CTL2;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000614 u32 saveFPB0;
615 u32 saveFPB1;
616 u32 saveDPLL_B;
617 u32 saveDPLL_B_MD;
618 u32 saveHTOTAL_B;
619 u32 saveHBLANK_B;
620 u32 saveHSYNC_B;
621 u32 saveVTOTAL_B;
622 u32 saveVBLANK_B;
623 u32 saveVSYNC_B;
624 u32 saveBCLRPAT_B;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000625 u32 saveTRANSBCONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800626 u32 saveTRANS_HTOTAL_B;
627 u32 saveTRANS_HBLANK_B;
628 u32 saveTRANS_HSYNC_B;
629 u32 saveTRANS_VTOTAL_B;
630 u32 saveTRANS_VBLANK_B;
631 u32 saveTRANS_VSYNC_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000632 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000633 u32 saveDSPBSTRIDE;
634 u32 saveDSPBSIZE;
635 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700636 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000637 u32 saveDSPBSURF;
638 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700639 u32 saveVGA0;
640 u32 saveVGA1;
641 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000642 u32 saveVGACNTRL;
643 u32 saveADPA;
644 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700645 u32 savePP_ON_DELAYS;
646 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000647 u32 saveDVOA;
648 u32 saveDVOB;
649 u32 saveDVOC;
650 u32 savePP_ON;
651 u32 savePP_OFF;
652 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700653 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000654 u32 savePFIT_CONTROL;
655 u32 save_palette_a[256];
656 u32 save_palette_b[256];
Jesse Barnes06027f92009-10-05 13:47:26 -0700657 u32 saveDPFC_CB_BASE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000658 u32 saveFBC_CFB_BASE;
659 u32 saveFBC_LL_BASE;
660 u32 saveFBC_CONTROL;
661 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000662 u32 saveIER;
663 u32 saveIIR;
664 u32 saveIMR;
Zhenyu Wang42048782009-10-21 15:27:01 +0800665 u32 saveDEIER;
666 u32 saveDEIMR;
667 u32 saveGTIER;
668 u32 saveGTIMR;
669 u32 saveFDI_RXA_IMR;
670 u32 saveFDI_RXB_IMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800671 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800672 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000673 u32 saveSWF0[16];
674 u32 saveSWF1[16];
675 u32 saveSWF2[3];
676 u8 saveMSR;
677 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800678 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000679 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000680 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000681 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000682 u8 saveCR[37];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200683 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000684 u32 saveCURACNTR;
685 u32 saveCURAPOS;
686 u32 saveCURABASE;
687 u32 saveCURBCNTR;
688 u32 saveCURBPOS;
689 u32 saveCURBBASE;
690 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700691 u32 saveDP_B;
692 u32 saveDP_C;
693 u32 saveDP_D;
694 u32 savePIPEA_GMCH_DATA_M;
695 u32 savePIPEB_GMCH_DATA_M;
696 u32 savePIPEA_GMCH_DATA_N;
697 u32 savePIPEB_GMCH_DATA_N;
698 u32 savePIPEA_DP_LINK_M;
699 u32 savePIPEB_DP_LINK_M;
700 u32 savePIPEA_DP_LINK_N;
701 u32 savePIPEB_DP_LINK_N;
Zhenyu Wang42048782009-10-21 15:27:01 +0800702 u32 saveFDI_RXA_CTL;
703 u32 saveFDI_TXA_CTL;
704 u32 saveFDI_RXB_CTL;
705 u32 saveFDI_TXB_CTL;
706 u32 savePFA_CTL_1;
707 u32 savePFB_CTL_1;
708 u32 savePFA_WIN_SZ;
709 u32 savePFB_WIN_SZ;
710 u32 savePFA_WIN_POS;
711 u32 savePFB_WIN_POS;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000712 u32 savePCH_DREF_CONTROL;
713 u32 saveDISP_ARB_CTL;
714 u32 savePIPEA_DATA_M1;
715 u32 savePIPEA_DATA_N1;
716 u32 savePIPEA_LINK_M1;
717 u32 savePIPEA_LINK_N1;
718 u32 savePIPEB_DATA_M1;
719 u32 savePIPEB_DATA_N1;
720 u32 savePIPEB_LINK_M1;
721 u32 savePIPEB_LINK_N1;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000722 u32 saveMCHBAR_RENDER_STANDBY;
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400723 u32 savePCH_PORT_HOTPLUG;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100724};
Daniel Vetterc85aa882012-11-02 19:55:03 +0100725
726struct intel_gen6_power_mgmt {
727 struct work_struct work;
Jesse Barnes52ceb902013-04-23 10:09:26 -0700728 struct delayed_work vlv_work;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100729 u32 pm_iir;
730 /* lock - irqsave spinlock that protectects the work_struct and
731 * pm_iir. */
732 spinlock_t lock;
733
734 /* The below variables an all the rps hw state are protected by
735 * dev->struct mutext. */
736 u8 cur_delay;
737 u8 min_delay;
738 u8 max_delay;
Jesse Barnes52ceb902013-04-23 10:09:26 -0700739 u8 rpe_delay;
Ben Widawsky31c77382013-04-05 14:29:22 -0700740 u8 hw_max;
Jesse Barnes1a01ab32012-11-02 11:14:00 -0700741
742 struct delayed_work delayed_resume_work;
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700743
744 /*
745 * Protects RPS/RC6 register access and PCU communication.
746 * Must be taken after struct_mutex if nested.
747 */
748 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100749};
750
Daniel Vetter1a240d42012-11-29 22:18:51 +0100751/* defined intel_pm.c */
752extern spinlock_t mchdev_lock;
753
Daniel Vetterc85aa882012-11-02 19:55:03 +0100754struct intel_ilk_power_mgmt {
755 u8 cur_delay;
756 u8 min_delay;
757 u8 max_delay;
758 u8 fmax;
759 u8 fstart;
760
761 u64 last_count1;
762 unsigned long last_time1;
763 unsigned long chipset_power;
764 u64 last_count2;
765 struct timespec last_time2;
766 unsigned long gfx_power;
767 u8 corr;
768
769 int c_m;
770 int r_t;
Daniel Vetter3e373942012-11-02 19:55:04 +0100771
772 struct drm_i915_gem_object *pwrctx;
773 struct drm_i915_gem_object *renderctx;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100774};
775
Wang Xingchaoa38911a2013-05-30 22:07:11 +0800776/* Power well structure for haswell */
777struct i915_power_well {
778 struct drm_device *device;
779 spinlock_t lock;
780 /* power well enable/disable usage count */
781 int count;
782 int i915_request;
783};
784
Daniel Vetter231f42a2012-11-02 19:55:05 +0100785struct i915_dri1_state {
786 unsigned allow_batchbuffer : 1;
787 u32 __iomem *gfx_hws_cpu_addr;
788
789 unsigned int cpp;
790 int back_offset;
791 int front_offset;
792 int current_page;
793 int page_flipping;
794
795 uint32_t counter;
796};
797
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100798struct intel_l3_parity {
799 u32 *remap_info;
800 struct work_struct error_work;
801};
802
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100803struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100804 /** Memory allocator for GTT stolen memory */
805 struct drm_mm stolen;
806 /** Memory allocator for GTT */
807 struct drm_mm gtt_space;
808 /** List of all objects in gtt_space. Used to restore gtt
809 * mappings on resume */
810 struct list_head bound_list;
811 /**
812 * List of objects which are not bound to the GTT (thus
813 * are idle and not used by the GPU) but still have
814 * (presumably uncached) pages still attached.
815 */
816 struct list_head unbound_list;
817
818 /** Usable portion of the GTT for GEM */
819 unsigned long stolen_base; /* limited to low memory (32-bit) */
820
821 int gtt_mtrr;
822
823 /** PPGTT used for aliasing the PPGTT with the GTT */
824 struct i915_hw_ppgtt *aliasing_ppgtt;
825
826 struct shrinker inactive_shrinker;
827 bool shrinker_no_lock_stealing;
828
829 /**
830 * List of objects currently involved in rendering.
831 *
832 * Includes buffers having the contents of their GPU caches
833 * flushed, not necessarily primitives. last_rendering_seqno
834 * represents when the rendering involved will be completed.
835 *
836 * A reference is held on the buffer while on this list.
837 */
838 struct list_head active_list;
839
840 /**
841 * LRU list of objects which are not in the ringbuffer and
842 * are ready to unbind, but are still in the GTT.
843 *
844 * last_rendering_seqno is 0 while an object is in this list.
845 *
846 * A reference is not held on the buffer while on this list,
847 * as merely being GTT-bound shouldn't prevent its being
848 * freed, and we'll pull it off the list in the free path.
849 */
850 struct list_head inactive_list;
851
852 /** LRU list of objects with fence regs on them. */
853 struct list_head fence_list;
854
855 /**
856 * We leave the user IRQ off as much as possible,
857 * but this means that requests will finish and never
858 * be retired once the system goes idle. Set a timer to
859 * fire periodically while the ring is running. When it
860 * fires, go retire requests.
861 */
862 struct delayed_work retire_work;
863
864 /**
865 * Are we in a non-interruptible section of code like
866 * modesetting?
867 */
868 bool interruptible;
869
870 /**
871 * Flag if the X Server, and thus DRM, is not currently in
872 * control of the device.
873 *
874 * This is set between LeaveVT and EnterVT. It needs to be
875 * replaced with a semaphore. It also needs to be
876 * transitioned away from for kernel modesetting.
877 */
878 int suspended;
879
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100880 /** Bit 6 swizzling required for X tiling */
881 uint32_t bit_6_swizzle_x;
882 /** Bit 6 swizzling required for Y tiling */
883 uint32_t bit_6_swizzle_y;
884
885 /* storage for physical objects */
886 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
887
888 /* accounting, useful for userland debugging */
889 size_t object_memory;
890 u32 object_count;
891};
892
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300893struct drm_i915_error_state_buf {
894 unsigned bytes;
895 unsigned size;
896 int err;
897 u8 *buf;
898 loff_t start;
899 loff_t pos;
900};
901
Daniel Vetter99584db2012-11-14 17:14:04 +0100902struct i915_gpu_error {
903 /* For hangcheck timer */
904#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
905#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
906 struct timer_list hangcheck_timer;
Daniel Vetter99584db2012-11-14 17:14:04 +0100907
908 /* For reset and error_state handling. */
909 spinlock_t lock;
910 /* Protected by the above dev->gpu_error.lock. */
911 struct drm_i915_error_state *first_error;
912 struct work_struct work;
Daniel Vetter99584db2012-11-14 17:14:04 +0100913
914 unsigned long last_reset;
915
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100916 /**
Daniel Vetterf69061b2012-12-06 09:01:42 +0100917 * State variable and reset counter controlling the reset flow
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100918 *
Daniel Vetterf69061b2012-12-06 09:01:42 +0100919 * Upper bits are for the reset counter. This counter is used by the
920 * wait_seqno code to race-free noticed that a reset event happened and
921 * that it needs to restart the entire ioctl (since most likely the
922 * seqno it waited for won't ever signal anytime soon).
923 *
924 * This is important for lock-free wait paths, where no contended lock
925 * naturally enforces the correct ordering between the bail-out of the
926 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100927 *
928 * Lowest bit controls the reset state machine: Set means a reset is in
929 * progress. This state will (presuming we don't have any bugs) decay
930 * into either unset (successful reset) or the special WEDGED value (hw
931 * terminally sour). All waiters on the reset_queue will be woken when
932 * that happens.
933 */
934 atomic_t reset_counter;
935
936 /**
937 * Special values/flags for reset_counter
938 *
939 * Note that the code relies on
940 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
941 * being true.
942 */
943#define I915_RESET_IN_PROGRESS_FLAG 1
944#define I915_WEDGED 0xffffffff
945
946 /**
947 * Waitqueue to signal when the reset has completed. Used by clients
948 * that wait for dev_priv->mm.wedged to settle.
949 */
950 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +0100951
Daniel Vetter99584db2012-11-14 17:14:04 +0100952 /* For gpu hang simulation. */
953 unsigned int stop_rings;
954};
955
Zhang Ruib8efb172013-02-05 15:41:53 +0800956enum modeset_restore {
957 MODESET_ON_LID_OPEN,
958 MODESET_DONE,
959 MODESET_SUSPENDED,
960};
961
Rodrigo Vivi41aa3442013-05-09 20:03:18 -0300962struct intel_vbt_data {
963 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
964 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
965
966 /* Feature bits */
967 unsigned int int_tv_support:1;
968 unsigned int lvds_dither:1;
969 unsigned int lvds_vbt:1;
970 unsigned int int_crt_support:1;
971 unsigned int lvds_use_ssc:1;
972 unsigned int display_clock_mode:1;
973 unsigned int fdi_rx_polarity_inverted:1;
974 int lvds_ssc_freq;
975 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
976
977 /* eDP */
978 int edp_rate;
979 int edp_lanes;
980 int edp_preemphasis;
981 int edp_vswing;
982 bool edp_initialized;
983 bool edp_support;
984 int edp_bpp;
985 struct edp_power_seq edp_pps;
986
987 int crt_ddc_pin;
988
989 int child_dev_num;
990 struct child_device_config *child_dev;
991};
992
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100993typedef struct drm_i915_private {
994 struct drm_device *dev;
Chris Wilson42dcedd2012-11-15 11:32:30 +0000995 struct kmem_cache *slab;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100996
997 const struct intel_device_info *info;
998
999 int relative_constants_mode;
1000
1001 void __iomem *regs;
1002
1003 struct drm_i915_gt_funcs gt;
1004 /** gt_fifo_count and the subsequent register write are synchronized
1005 * with dev->struct_mutex. */
1006 unsigned gt_fifo_count;
1007 /** forcewake_count is protected by gt_lock */
1008 unsigned forcewake_count;
1009 /** gt_lock is also taken in irq contexts. */
Luis R. Rodriguez99057c82012-11-29 12:45:06 -08001010 spinlock_t gt_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001011
1012 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1013
Daniel Vetter28c70f12012-12-01 13:53:45 +01001014
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001015 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1016 * controller on different i2c buses. */
1017 struct mutex gmbus_mutex;
1018
1019 /**
1020 * Base address of the gmbus and gpio block.
1021 */
1022 uint32_t gpio_mmio_base;
1023
Daniel Vetter28c70f12012-12-01 13:53:45 +01001024 wait_queue_head_t gmbus_wait_queue;
1025
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001026 struct pci_dev *bridge_dev;
1027 struct intel_ring_buffer ring[I915_NUM_RINGS];
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001028 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001029
1030 drm_dma_handle_t *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001031 struct resource mch_res;
1032
1033 atomic_t irq_received;
1034
1035 /* protects the irq masks */
1036 spinlock_t irq_lock;
1037
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001038 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1039 struct pm_qos_request pm_qos;
1040
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001041 /* DPIO indirect register protection */
Daniel Vetter09153002012-12-12 14:06:44 +01001042 struct mutex dpio_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001043
1044 /** Cached value of IMR to avoid reads in updating the bitfield */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001045 u32 irq_mask;
1046 u32 gt_irq_mask;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001047
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001048 struct work_struct hotplug_work;
Daniel Vetter52d7ece2012-12-01 21:03:22 +01001049 bool enable_hotplug_processing;
Egbert Eichb543fb02013-04-16 13:36:54 +02001050 struct {
1051 unsigned long hpd_last_jiffies;
1052 int hpd_cnt;
1053 enum {
1054 HPD_ENABLED = 0,
1055 HPD_DISABLED = 1,
1056 HPD_MARK_DISABLED = 2
1057 } hpd_mark;
1058 } hpd_stats[HPD_NUM_PINS];
Egbert Eich142e2392013-04-11 15:57:57 +02001059 u32 hpd_event_bits;
Egbert Eichac4c16c2013-04-16 13:36:58 +02001060 struct timer_list hotplug_reenable_timer;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001061
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001062 int num_plane;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001063
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001064 unsigned long cfb_size;
1065 unsigned int cfb_fb;
1066 enum plane cfb_plane;
1067 int cfb_y;
1068 struct intel_fbc_work *fbc_work;
1069
1070 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001071 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001072
1073 /* overlay */
1074 struct intel_overlay *overlay;
Ville Syrjälä2c6602d2013-02-08 23:13:35 +02001075 unsigned int sprite_scaling_enabled;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001076
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001077 /* backlight */
1078 struct {
1079 int level;
1080 bool enabled;
Jani Nikula8ba2d182013-04-12 15:18:37 +03001081 spinlock_t lock; /* bl registers and the above bl fields */
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001082 struct backlight_device *device;
1083 } backlight;
1084
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001085 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001086 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1087 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001088 bool no_aux_handshake;
1089
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001090 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1091 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1092 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1093
1094 unsigned int fsb_freq, mem_freq, is_ddr3;
1095
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001096 struct workqueue_struct *wq;
1097
1098 /* Display functions */
1099 struct drm_i915_display_funcs display;
1100
1101 /* PCH chipset type */
1102 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001103 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001104
1105 unsigned long quirks;
1106
Zhang Ruib8efb172013-02-05 15:41:53 +08001107 enum modeset_restore modeset_restore;
1108 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001109
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001110 struct i915_gtt gtt;
1111
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001112 struct i915_gem_mm mm;
Daniel Vetter87813422012-05-02 11:49:32 +02001113
Daniel Vetter87813422012-05-02 11:49:32 +02001114 /* Kernel Modesetting */
1115
yakui_zhao9b9d1722009-05-31 17:17:17 +08001116 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001117
Jesse Barnes27f82272011-09-02 12:54:37 -07001118 struct drm_crtc *plane_to_crtc_mapping[3];
1119 struct drm_crtc *pipe_to_crtc_mapping[3];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001120 wait_queue_head_t pending_flip_queue;
1121
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001122 int num_shared_dpll;
1123 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001124 struct intel_ddi_plls ddi_plls;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001125
Jesse Barnes652c3932009-08-17 13:31:43 -07001126 /* Reclocking support */
1127 bool render_reclock_avail;
1128 bool lvds_downclock_avail;
Zhao Yakui18f9ed12009-11-20 03:24:16 +00001129 /* indicates the reduced downclock for LVDS*/
1130 int lvds_downclock;
Jesse Barnes652c3932009-08-17 13:31:43 -07001131 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001132
Zhenyu Wangc48044112009-12-17 14:48:43 +08001133 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001134
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001135 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001136
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001137 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001138 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001139
Daniel Vetter20e4d402012-08-08 23:35:39 +02001140 /* ilk-only ips/rps state. Everything in here is protected by the global
1141 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001142 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001143
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001144 /* Haswell power well */
1145 struct i915_power_well power_well;
1146
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001147 enum no_fbc_reason no_fbc_reason;
Dave Airlie38651672010-03-30 05:34:13 +00001148
Jesse Barnes20bf3772010-04-21 11:39:22 -07001149 struct drm_mm_node *compressed_fb;
1150 struct drm_mm_node *compressed_llb;
Eric Anholt34dc4d42010-05-07 14:30:03 -07001151
Daniel Vetter99584db2012-11-14 17:14:04 +01001152 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001153
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001154 struct drm_i915_gem_object *vlv_pctx;
1155
Dave Airlie8be48d92010-03-30 05:34:14 +00001156 /* list of fbdev register on this device */
1157 struct intel_fbdev *fbdev;
Chris Wilsone953fd72011-02-21 22:23:52 +00001158
Jesse Barnes073f34d2012-11-02 11:13:59 -07001159 /*
1160 * The console may be contended at resume, but we don't
1161 * want it to block on it.
1162 */
1163 struct work_struct console_resume_work;
1164
Chris Wilsone953fd72011-02-21 22:23:52 +00001165 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001166 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001167
Ben Widawsky254f9652012-06-04 14:42:42 -07001168 bool hw_contexts_disabled;
1169 uint32_t hw_context_size;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001170
Damien Lespiau3e683202012-12-11 18:48:29 +00001171 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001172
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001173 struct i915_suspend_saved_registers regfile;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001174
1175 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1176 * here! */
1177 struct i915_dri1_state dri1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178} drm_i915_private_t;
1179
Chris Wilsonb4519512012-05-11 14:29:30 +01001180/* Iterate over initialised rings */
1181#define for_each_ring(ring__, dev_priv__, i__) \
1182 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1183 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1184
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001185enum hdmi_force_audio {
1186 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1187 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1188 HDMI_AUDIO_AUTO, /* trust EDID */
1189 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1190};
1191
Chris Wilsoned2f3452012-11-15 11:32:19 +00001192#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1193
Chris Wilson37e680a2012-06-07 15:38:42 +01001194struct drm_i915_gem_object_ops {
1195 /* Interface between the GEM object and its backing storage.
1196 * get_pages() is called once prior to the use of the associated set
1197 * of pages before to binding them into the GTT, and put_pages() is
1198 * called after we no longer need them. As we expect there to be
1199 * associated cost with migrating pages between the backing storage
1200 * and making them available for the GPU (e.g. clflush), we may hold
1201 * onto the pages after they are no longer referenced by the GPU
1202 * in case they may be used again shortly (for example migrating the
1203 * pages to a different memory domain within the GTT). put_pages()
1204 * will therefore most likely be called when the object itself is
1205 * being released or under memory pressure (where we attempt to
1206 * reap pages for the shrinker).
1207 */
1208 int (*get_pages)(struct drm_i915_gem_object *);
1209 void (*put_pages)(struct drm_i915_gem_object *);
1210};
1211
Eric Anholt673a3942008-07-30 12:06:12 -07001212struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00001213 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07001214
Chris Wilson37e680a2012-06-07 15:38:42 +01001215 const struct drm_i915_gem_object_ops *ops;
1216
Eric Anholt673a3942008-07-30 12:06:12 -07001217 /** Current space allocated to this object in the GTT, if any. */
1218 struct drm_mm_node *gtt_space;
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00001219 /** Stolen memory for this object, instead of being backed by shmem. */
1220 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07001221 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001222
Chris Wilson65ce3022012-07-20 12:41:02 +01001223 /** This object's place on the active/inactive lists */
Chris Wilson69dc4982010-10-19 10:36:51 +01001224 struct list_head ring_list;
1225 struct list_head mm_list;
Chris Wilson432e58e2010-11-25 19:32:06 +00001226 /** This object's place in the batchbuffer or on the eviction list */
1227 struct list_head exec_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001228
1229 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01001230 * This is set if the object is on the active lists (has pending
1231 * rendering and so a non-zero seqno), and is not set if it i s on
1232 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07001233 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001234 unsigned int active:1;
Eric Anholt673a3942008-07-30 12:06:12 -07001235
1236 /**
1237 * This is set if the object has been written to since last bound
1238 * to the GTT
1239 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001240 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001241
1242 /**
1243 * Fence register bits (if any) for this object. Will be set
1244 * as needed when mapped into the GTT.
1245 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02001246 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02001247 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02001248
1249 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001250 * Advice: are the backing pages purgeable?
1251 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001252 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02001253
1254 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001255 * Current tiling mode for the object.
1256 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001257 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01001258 /**
1259 * Whether the tiling parameters for the currently associated fence
1260 * register have changed. Note that for the purposes of tracking
1261 * tiling changes we also treat the unfenced register, the register
1262 * slot that the object occupies whilst it executes a fenced
1263 * command (such as BLT on gen2/3), as a "fence".
1264 */
1265 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001266
1267 /** How many users have pinned this object in GTT space. The following
1268 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1269 * (via user_pin_count), execbuffer (objects are not allowed multiple
1270 * times for the same batchbuffer), and the framebuffer code. When
1271 * switching/pageflipping, the framebuffer code has at most two buffers
1272 * pinned per crtc.
1273 *
1274 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1275 * bits with absolutely no headroom. So use 4 bits. */
Akshay Joshi0206e352011-08-16 15:34:10 -04001276 unsigned int pin_count:4;
Daniel Vetter778c3542010-05-13 11:49:44 +02001277#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
Eric Anholt673a3942008-07-30 12:06:12 -07001278
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001279 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01001280 * Is the object at the current location in the gtt mappable and
1281 * fenceable? Used to avoid costly recalculations.
1282 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001283 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01001284
1285 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001286 * Whether the current gtt mapping needs to be mappable (and isn't just
1287 * mappable by accident). Track pin and fault separate for a more
1288 * accurate mappable working set.
1289 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001290 unsigned int fault_mappable:1;
1291 unsigned int pin_mappable:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001292
Chris Wilsoncaea7472010-11-12 13:53:37 +00001293 /*
1294 * Is the GPU currently using a fence to access this buffer,
1295 */
1296 unsigned int pending_fenced_gpu_access:1;
1297 unsigned int fenced_gpu_access:1;
1298
Chris Wilson93dfb402011-03-29 16:59:50 -07001299 unsigned int cache_level:2;
1300
Daniel Vetter7bddb012012-02-09 17:15:47 +01001301 unsigned int has_aliasing_ppgtt_mapping:1;
Daniel Vetter74898d72012-02-15 23:50:22 +01001302 unsigned int has_global_gtt_mapping:1;
Chris Wilson9da3da62012-06-01 15:20:22 +01001303 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001304
Chris Wilson9da3da62012-06-01 15:20:22 +01001305 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01001306 int pages_pin_count;
Eric Anholt673a3942008-07-30 12:06:12 -07001307
Daniel Vetter1286ff72012-05-10 15:25:09 +02001308 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01001309 void *dma_buf_vmapping;
1310 int vmapping_count;
1311
Daniel Vetter185cbcb2010-11-06 12:12:35 +01001312 /**
Chris Wilson67731b82010-12-08 10:38:14 +00001313 * Used for performing relocations during execbuffer insertion.
1314 */
1315 struct hlist_node exec_node;
1316 unsigned long exec_handle;
Chris Wilson6fe4f142011-01-10 17:35:37 +00001317 struct drm_i915_gem_exec_object2 *exec_entry;
Chris Wilson67731b82010-12-08 10:38:14 +00001318
1319 /**
Eric Anholt673a3942008-07-30 12:06:12 -07001320 * Current offset of the object in GTT space.
1321 *
1322 * This is the same as gtt_space->start
1323 */
1324 uint32_t gtt_offset;
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001325
Chris Wilsoncaea7472010-11-12 13:53:37 +00001326 struct intel_ring_buffer *ring;
1327
Chris Wilson1c293ea2012-04-17 15:31:27 +01001328 /** Breadcrumb of last rendering to the buffer. */
Chris Wilson0201f1e2012-07-20 12:41:01 +01001329 uint32_t last_read_seqno;
1330 uint32_t last_write_seqno;
Chris Wilsoncaea7472010-11-12 13:53:37 +00001331 /** Breadcrumb of last fenced GPU access to the buffer. */
1332 uint32_t last_fenced_seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001333
Daniel Vetter778c3542010-05-13 11:49:44 +02001334 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08001335 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07001336
Eric Anholt280b7132009-03-12 16:56:27 -07001337 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01001338 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07001339
Jesse Barnes79e53942008-11-07 14:24:08 -08001340 /** User space pin count and filp owning the pin */
1341 uint32_t user_pin_count;
1342 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001343
1344 /** for phy allocated objects */
1345 struct drm_i915_gem_phys_object *phys_obj;
Eric Anholt673a3942008-07-30 12:06:12 -07001346};
Daniel Vetterb45305f2012-12-17 16:21:27 +01001347#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
Eric Anholt673a3942008-07-30 12:06:12 -07001348
Daniel Vetter62b8b212010-04-09 19:05:08 +00001349#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01001350
Eric Anholt673a3942008-07-30 12:06:12 -07001351/**
1352 * Request queue structure.
1353 *
1354 * The request queue allows us to note sequence numbers that have been emitted
1355 * and may be associated with active buffers to be retired.
1356 *
1357 * By keeping this list, we can avoid having to do questionable
1358 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1359 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1360 */
1361struct drm_i915_gem_request {
Zou Nan hai852835f2010-05-21 09:08:56 +08001362 /** On Which ring this request was generated */
1363 struct intel_ring_buffer *ring;
1364
Eric Anholt673a3942008-07-30 12:06:12 -07001365 /** GEM sequence number associated with this request. */
1366 uint32_t seqno;
1367
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001368 /** Position in the ringbuffer of the start of the request */
1369 u32 head;
1370
1371 /** Position in the ringbuffer of the end of the request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00001372 u32 tail;
1373
Mika Kuoppala0e50e962013-05-02 16:48:08 +03001374 /** Context related to this request */
1375 struct i915_hw_context *ctx;
1376
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001377 /** Batch buffer related to this request if any */
1378 struct drm_i915_gem_object *batch_obj;
1379
Eric Anholt673a3942008-07-30 12:06:12 -07001380 /** Time at which this request was emitted, in jiffies. */
1381 unsigned long emitted_jiffies;
1382
Eric Anholtb9624422009-06-03 07:27:35 +00001383 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07001384 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00001385
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001386 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00001387 /** file_priv list entry for this request */
1388 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001389};
1390
1391struct drm_i915_file_private {
1392 struct {
Luis R. Rodriguez99057c82012-11-29 12:45:06 -08001393 spinlock_t lock;
Eric Anholtb9624422009-06-03 07:27:35 +00001394 struct list_head request_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001395 } mm;
Ben Widawsky40521052012-06-04 14:42:43 -07001396 struct idr context_idr;
Mika Kuoppalae59ec132013-06-12 12:35:28 +03001397
1398 struct i915_ctx_hang_stats hang_stats;
Eric Anholt673a3942008-07-30 12:06:12 -07001399};
1400
Zou Nan haicae58522010-11-09 17:17:32 +08001401#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1402
1403#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1404#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1405#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1406#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1407#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1408#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1409#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1410#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1411#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1412#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1413#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1414#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1415#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1416#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1417#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1418#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1419#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1420#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07001421#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Jesse Barnes8ab43972012-10-25 12:15:42 -07001422#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1423 (dev)->pci_device == 0x0152 || \
1424 (dev)->pci_device == 0x015a)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01001425#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1426 (dev)->pci_device == 0x0106 || \
1427 (dev)->pci_device == 0x010A)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07001428#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03001429#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Zou Nan haicae58522010-11-09 17:17:32 +08001430#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonid567b072012-11-20 13:27:43 -02001431#define IS_ULT(dev) (IS_HASWELL(dev) && \
1432 ((dev)->pci_device & 0xFF00) == 0x0A00)
Zou Nan haicae58522010-11-09 17:17:32 +08001433
Jesse Barnes85436692011-04-06 12:11:14 -07001434/*
1435 * The genX designation typically refers to the render engine, so render
1436 * capability related checks should use IS_GEN, while display and other checks
1437 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1438 * chips, etc.).
1439 */
Zou Nan haicae58522010-11-09 17:17:32 +08001440#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1441#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1442#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1443#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1444#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07001445#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Zou Nan haicae58522010-11-09 17:17:32 +08001446
1447#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1448#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
Xiang, Haihaof72a1182013-05-28 19:22:22 -07001449#define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
Eugeni Dodonov3d29b842012-01-17 14:43:53 -02001450#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
Zou Nan haicae58522010-11-09 17:17:32 +08001451#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1452
Ben Widawsky254f9652012-06-04 14:42:42 -07001453#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Jesse Barnes93553602012-06-15 11:55:23 -07001454#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001455
Chris Wilson05394f32010-11-08 19:18:58 +00001456#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08001457#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1458
Daniel Vetterb45305f2012-12-17 16:21:27 +01001459/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1460#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1461
Zou Nan haicae58522010-11-09 17:17:32 +08001462/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1463 * rows, which changed the alignment requirements and fence programming.
1464 */
1465#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1466 IS_I915GM(dev)))
1467#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1468#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1469#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1470#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1471#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1472#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1473/* dsparb controlled by hw only */
1474#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1475
1476#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1477#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1478#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08001479
Damien Lespiauf5adf942013-06-24 18:29:34 +01001480#define HAS_IPS(dev) (IS_ULT(dev))
1481
Jesse Barneseceae482011-04-06 12:15:08 -07001482#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
Zou Nan haicae58522010-11-09 17:17:32 +08001483
Damien Lespiaudd93be52013-04-22 18:40:39 +01001484#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Paulo Zanoni86d52df2013-03-06 20:03:18 -03001485#define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
Damien Lespiau30568c42013-04-22 18:40:41 +01001486#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001487
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001488#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1489#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1490#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1491#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1492#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1493#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1494
Zou Nan haicae58522010-11-09 17:17:32 +08001495#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03001496#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08001497#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1498#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07001499#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03001500#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08001501
Daniel Vetterb7884eb2012-06-04 11:18:15 +02001502#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1503
Ben Widawskyf27b9262012-07-24 20:47:32 -07001504#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07001505
Ben Widawskyc8735b02012-09-07 19:43:39 -07001506#define GT_FREQUENCY_MULTIPLIER 50
1507
Chris Wilson05394f32010-11-08 19:18:58 +00001508#include "i915_trace.h"
1509
Eugeni Dodonov83b7f9a2012-03-23 11:57:18 -03001510/**
1511 * RC6 is a special power stage which allows the GPU to enter an very
1512 * low-voltage mode when idle, using down to 0V while at this stage. This
1513 * stage is entered automatically when the GPU is idle when RC6 support is
1514 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1515 *
1516 * There are different RC6 modes available in Intel GPU, which differentiate
1517 * among each other with the latency required to enter and leave RC6 and
1518 * voltage consumed by the GPU in different states.
1519 *
1520 * The combination of the following flags define which states GPU is allowed
1521 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1522 * RC6pp is deepest RC6. Their support by hardware varies according to the
1523 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1524 * which brings the most power savings; deeper states save more power, but
1525 * require higher latency to switch to and wake up.
1526 */
1527#define INTEL_RC6_ENABLE (1<<0)
1528#define INTEL_RC6p_ENABLE (1<<1)
1529#define INTEL_RC6pp_ENABLE (1<<2)
1530
Eric Anholtc153f452007-09-03 12:06:45 +10001531extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10001532extern int i915_max_ioctl;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001533extern unsigned int i915_fbpercrtc __always_unused;
1534extern int i915_panel_ignore_lid __read_mostly;
1535extern unsigned int i915_powersave __read_mostly;
Eugeni Dodonovf45b5552011-12-09 17:16:37 -08001536extern int i915_semaphores __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001537extern unsigned int i915_lvds_downclock __read_mostly;
Takashi Iwai121d5272012-03-20 13:07:06 +01001538extern int i915_lvds_channel_mode __read_mostly;
Keith Packard4415e632011-11-09 09:57:50 -08001539extern int i915_panel_use_ssc __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001540extern int i915_vbt_sdvo_panel_type __read_mostly;
Keith Packardc0f372b32011-11-16 22:24:52 -08001541extern int i915_enable_rc6 __read_mostly;
Keith Packard4415e632011-11-09 09:57:50 -08001542extern int i915_enable_fbc __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001543extern bool i915_enable_hangcheck __read_mostly;
Daniel Vetter650dc072012-04-02 10:08:35 +02001544extern int i915_enable_ppgtt __read_mostly;
Rodrigo Vivi0a3af262012-10-15 17:16:23 -03001545extern unsigned int i915_preliminary_hw_support __read_mostly;
Paulo Zanoni2124b722013-03-22 14:07:23 -03001546extern int i915_disable_power_well __read_mostly;
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03001547extern int i915_enable_ips __read_mostly;
Dave Airlieb3a83632005-09-30 18:37:36 +10001548
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001549extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1550extern int i915_resume(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001551extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1552extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1553
Linus Torvalds1da177e2005-04-16 15:20:36 -07001554 /* i915_dma.c */
Daniel Vetterd05c6172012-04-26 23:28:09 +02001555void i915_update_dri1_breadcrumb(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001556extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +11001557extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001558extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -07001559extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001560extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10001561extern void i915_driver_preclose(struct drm_device *dev,
1562 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001563extern void i915_driver_postclose(struct drm_device *dev,
1564 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001565extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001566#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11001567extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1568 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001569#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001570extern int i915_emit_box(struct drm_device *dev,
Chris Wilsonc4e7a412010-11-30 14:10:25 +00001571 struct drm_clip_rect *box,
1572 int DR1, int DR4);
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07001573extern int intel_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02001574extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001575extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1576extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1577extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1578extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1579
Jesse Barnes073f34d2012-11-02 11:13:59 -07001580extern void intel_console_resume(struct work_struct *work);
Dave Airlieaf6061a2008-05-07 12:15:39 +10001581
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582/* i915_irq.c */
Ben Gamarif65d9422009-09-14 17:48:44 -04001583void i915_hangcheck_elapsed(unsigned long data);
Chris Wilson527f9e92010-11-11 01:16:58 +00001584void i915_handle_error(struct drm_device *dev, bool wedged);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001586extern void intel_irq_init(struct drm_device *dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01001587extern void intel_hpd_init(struct drm_device *dev);
Chris Wilson990bbda2012-07-02 11:51:02 -03001588extern void intel_gt_init(struct drm_device *dev);
Chris Wilson16995a92012-10-18 11:46:10 +01001589extern void intel_gt_reset(struct drm_device *dev);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001590
Daniel Vetter742cbee2012-04-27 15:17:39 +02001591void i915_error_state_free(struct kref *error_ref);
1592
Keith Packard7c463582008-11-04 02:03:27 -08001593void
1594i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1595
1596void
1597i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1598
Chris Wilson3bd3c932010-08-19 08:19:30 +01001599#ifdef CONFIG_DEBUG_FS
1600extern void i915_destroy_error_state(struct drm_device *dev);
1601#else
1602#define i915_destroy_error_state(x)
1603#endif
1604
Keith Packard7c463582008-11-04 02:03:27 -08001605
Eric Anholt673a3942008-07-30 12:06:12 -07001606/* i915_gem.c */
1607int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1608 struct drm_file *file_priv);
1609int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1610 struct drm_file *file_priv);
1611int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1612 struct drm_file *file_priv);
1613int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1614 struct drm_file *file_priv);
1615int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1616 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001617int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1618 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001619int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1620 struct drm_file *file_priv);
1621int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1622 struct drm_file *file_priv);
1623int i915_gem_execbuffer(struct drm_device *dev, void *data,
1624 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05001625int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1626 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001627int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1628 struct drm_file *file_priv);
1629int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1630 struct drm_file *file_priv);
1631int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1632 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07001633int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1634 struct drm_file *file);
1635int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1636 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07001637int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1638 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001639int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1640 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001641int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1642 struct drm_file *file_priv);
1643int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1644 struct drm_file *file_priv);
1645int i915_gem_set_tiling(struct drm_device *dev, void *data,
1646 struct drm_file *file_priv);
1647int i915_gem_get_tiling(struct drm_device *dev, void *data,
1648 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -07001649int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1650 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07001651int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1652 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001653void i915_gem_load(struct drm_device *dev);
Chris Wilson42dcedd2012-11-15 11:32:30 +00001654void *i915_gem_object_alloc(struct drm_device *dev);
1655void i915_gem_object_free(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001656int i915_gem_init_object(struct drm_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01001657void i915_gem_object_init(struct drm_i915_gem_object *obj,
1658 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00001659struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1660 size_t size);
Eric Anholt673a3942008-07-30 12:06:12 -07001661void i915_gem_free_object(struct drm_gem_object *obj);
Chris Wilson42dcedd2012-11-15 11:32:30 +00001662
Chris Wilson20217462010-11-23 15:26:33 +00001663int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1664 uint32_t alignment,
Chris Wilson86a1ee22012-08-11 15:41:04 +01001665 bool map_and_fenceable,
1666 bool nonblocking);
Chris Wilson05394f32010-11-08 19:18:58 +00001667void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001668int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
Chris Wilsondd624af2013-01-15 12:39:35 +00001669int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Chris Wilson05394f32010-11-08 19:18:58 +00001670void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001671void i915_gem_lastclose(struct drm_device *dev);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001672
Chris Wilson37e680a2012-06-07 15:38:42 +01001673int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01001674static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1675{
Imre Deak67d5a502013-02-18 19:28:02 +02001676 struct sg_page_iter sg_iter;
Chris Wilson1cf83782012-10-10 12:11:52 +01001677
Imre Deak67d5a502013-02-18 19:28:02 +02001678 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
Imre Deak2db76d72013-03-26 15:14:18 +02001679 return sg_page_iter_page(&sg_iter);
Imre Deak67d5a502013-02-18 19:28:02 +02001680
1681 return NULL;
Chris Wilson9da3da62012-06-01 15:20:22 +01001682}
Chris Wilsona5570172012-09-04 21:02:54 +01001683static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1684{
1685 BUG_ON(obj->pages == NULL);
1686 obj->pages_pin_count++;
1687}
1688static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1689{
1690 BUG_ON(obj->pages_pin_count == 0);
1691 obj->pages_pin_count--;
1692}
1693
Chris Wilson54cf91d2010-11-25 18:00:26 +00001694int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07001695int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1696 struct intel_ring_buffer *to);
Chris Wilson54cf91d2010-11-25 18:00:26 +00001697void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
Chris Wilson9d7730912012-11-27 16:22:52 +00001698 struct intel_ring_buffer *ring);
Chris Wilson54cf91d2010-11-25 18:00:26 +00001699
Dave Airlieff72145b2011-02-07 12:16:14 +10001700int i915_gem_dumb_create(struct drm_file *file_priv,
1701 struct drm_device *dev,
1702 struct drm_mode_create_dumb *args);
1703int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1704 uint32_t handle, uint64_t *offset);
1705int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
Akshay Joshi0206e352011-08-16 15:34:10 -04001706 uint32_t handle);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001707/**
1708 * Returns true if seq1 is later than seq2.
1709 */
1710static inline bool
1711i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1712{
1713 return (int32_t)(seq1 - seq2) >= 0;
1714}
1715
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02001716int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1717int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson06d98132012-04-17 15:31:24 +01001718int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00001719int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001720
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001721static inline bool
Chris Wilson1690e1e2011-12-14 13:57:08 +01001722i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1723{
1724 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1725 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1726 dev_priv->fence_regs[obj->fence_reg].pin_count++;
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001727 return true;
1728 } else
1729 return false;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001730}
1731
1732static inline void
1733i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1734{
1735 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1736 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsonb8c3af72013-06-12 11:29:47 +01001737 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
Chris Wilson1690e1e2011-12-14 13:57:08 +01001738 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1739 }
1740}
1741
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001742void i915_gem_retire_requests(struct drm_device *dev);
Chris Wilsona71d8d92012-02-15 11:25:36 +00001743void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
Daniel Vetter33196de2012-11-14 17:14:05 +01001744int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02001745 bool interruptible);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001746static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1747{
1748 return unlikely(atomic_read(&error->reset_counter)
1749 & I915_RESET_IN_PROGRESS_FLAG);
1750}
1751
1752static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1753{
1754 return atomic_read(&error->reset_counter) == I915_WEDGED;
1755}
Chris Wilsona71d8d92012-02-15 11:25:36 +00001756
Chris Wilson069efc12010-09-30 16:53:18 +01001757void i915_gem_reset(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001758void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001759int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1760 uint32_t read_domains,
1761 uint32_t write_domain);
Chris Wilsona8198ee2011-04-13 22:04:09 +01001762int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
Chris Wilson1070a422012-04-24 15:47:41 +01001763int __must_check i915_gem_init(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001764int __must_check i915_gem_init_hw(struct drm_device *dev);
Ben Widawskyb9524a12012-05-25 16:56:24 -07001765void i915_gem_l3_remap(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001766void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001767void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07001768int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson20217462010-11-23 15:26:33 +00001769int __must_check i915_gem_idle(struct drm_device *dev);
Mika Kuoppala0025c072013-06-12 12:35:30 +03001770int __i915_add_request(struct intel_ring_buffer *ring,
1771 struct drm_file *file,
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001772 struct drm_i915_gem_object *batch_obj,
Mika Kuoppala0025c072013-06-12 12:35:30 +03001773 u32 *seqno);
1774#define i915_add_request(ring, seqno) \
Dan Carpenter854c94a2013-06-18 10:29:58 +03001775 __i915_add_request(ring, NULL, NULL, seqno)
Ben Widawsky199b2bc2012-05-24 15:03:11 -07001776int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1777 uint32_t seqno);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001778int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00001779int __must_check
1780i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1781 bool write);
1782int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02001783i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1784int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001785i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1786 u32 alignment,
Chris Wilson20217462010-11-23 15:26:33 +00001787 struct intel_ring_buffer *pipelined);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001788int i915_gem_attach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001789 struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01001790 int id,
1791 int align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001792void i915_gem_detach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001793 struct drm_i915_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001794void i915_gem_free_all_phys_object(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001795void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07001796
Chris Wilson467cffb2011-03-07 10:42:03 +00001797uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02001798i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1799uint32_t
Imre Deakd865110c2013-01-07 21:47:33 +02001800i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1801 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00001802
Chris Wilsone4ffd172011-04-04 09:44:39 +01001803int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1804 enum i915_cache_level cache_level);
1805
Daniel Vetter1286ff72012-05-10 15:25:09 +02001806struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1807 struct dma_buf *dma_buf);
1808
1809struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1810 struct drm_gem_object *gem_obj, int flags);
1811
Ben Widawsky254f9652012-06-04 14:42:42 -07001812/* i915_gem_context.c */
1813void i915_gem_context_init(struct drm_device *dev);
1814void i915_gem_context_fini(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07001815void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
Ben Widawskye0556842012-06-04 14:42:46 -07001816int i915_switch_context(struct intel_ring_buffer *ring,
1817 struct drm_file *file, int to_id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03001818void i915_gem_context_free(struct kref *ctx_ref);
1819static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
1820{
1821 kref_get(&ctx->ref);
1822}
1823
1824static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1825{
1826 kref_put(&ctx->ref, i915_gem_context_free);
1827}
1828
Mika Kuoppalac0bb6172013-06-12 12:35:29 +03001829struct i915_ctx_hang_stats * __must_check
1830i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring,
1831 struct drm_file *file,
1832 u32 id);
Ben Widawsky84624812012-06-04 14:42:54 -07001833int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1834 struct drm_file *file);
1835int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1836 struct drm_file *file);
Daniel Vetter1286ff72012-05-10 15:25:09 +02001837
Daniel Vetter76aaf222010-11-05 22:23:30 +01001838/* i915_gem_gtt.c */
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001839void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
Daniel Vetter7bddb012012-02-09 17:15:47 +01001840void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1841 struct drm_i915_gem_object *obj,
1842 enum i915_cache_level cache_level);
1843void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1844 struct drm_i915_gem_object *obj);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001845
Daniel Vetter76aaf222010-11-05 22:23:30 +01001846void i915_gem_restore_gtt_mappings(struct drm_device *dev);
Daniel Vetter74163902012-02-15 23:50:21 +01001847int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1848void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
Chris Wilsone4ffd172011-04-04 09:44:39 +01001849 enum i915_cache_level cache_level);
Chris Wilson05394f32010-11-08 19:18:58 +00001850void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
Daniel Vetter74163902012-02-15 23:50:21 +01001851void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
Ben Widawskyd7e50082012-12-18 10:31:25 -08001852void i915_gem_init_global_gtt(struct drm_device *dev);
1853void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1854 unsigned long mappable_end, unsigned long end);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001855int i915_gem_gtt_init(struct drm_device *dev);
Ben Widawskyd09105c2012-11-15 12:06:09 -08001856static inline void i915_gem_chipset_flush(struct drm_device *dev)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001857{
1858 if (INTEL_INFO(dev)->gen < 6)
1859 intel_gtt_chipset_flush();
1860}
1861
Daniel Vetter76aaf222010-11-05 22:23:30 +01001862
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01001863/* i915_gem_evict.c */
Chris Wilson20217462010-11-23 15:26:33 +00001864int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01001865 unsigned alignment,
1866 unsigned cache_level,
Chris Wilson86a1ee22012-08-11 15:41:04 +01001867 bool mappable,
1868 bool nonblock);
Chris Wilson6c085a72012-08-20 11:40:46 +02001869int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01001870
Chris Wilson9797fbf2012-04-24 15:47:39 +01001871/* i915_gem_stolen.c */
1872int i915_gem_init_stolen(struct drm_device *dev);
Chris Wilson11be49e2012-11-15 11:32:20 +00001873int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1874void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
Chris Wilson9797fbf2012-04-24 15:47:39 +01001875void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00001876struct drm_i915_gem_object *
1877i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08001878struct drm_i915_gem_object *
1879i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1880 u32 stolen_offset,
1881 u32 gtt_offset,
1882 u32 size);
Chris Wilson0104fdb2012-11-15 11:32:26 +00001883void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
Chris Wilson9797fbf2012-04-24 15:47:39 +01001884
Eric Anholt673a3942008-07-30 12:06:12 -07001885/* i915_gem_tiling.c */
Chris Wilsone9b73c62012-12-03 21:03:14 +00001886inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1887{
1888 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1889
1890 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1891 obj->tiling_mode != I915_TILING_NONE;
1892}
1893
Eric Anholt673a3942008-07-30 12:06:12 -07001894void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001895void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1896void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001897
1898/* i915_gem_debug.c */
Chris Wilson05394f32010-11-08 19:18:58 +00001899void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
Eric Anholt673a3942008-07-30 12:06:12 -07001900 const char *where, uint32_t mark);
Chris Wilson23bc5982010-09-29 16:10:57 +01001901#if WATCH_LISTS
1902int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07001903#else
Chris Wilson23bc5982010-09-29 16:10:57 +01001904#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07001905#endif
Chris Wilson05394f32010-11-08 19:18:58 +00001906void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1907 int handle);
1908void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
Eric Anholt673a3942008-07-30 12:06:12 -07001909 const char *where, uint32_t mark);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910
Ben Gamari20172632009-02-17 20:08:50 -05001911/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04001912int i915_debugfs_init(struct drm_minor *minor);
1913void i915_debugfs_cleanup(struct drm_minor *minor);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001914__printf(2, 3)
1915void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Ben Gamari20172632009-02-17 20:08:50 -05001916
Jesse Barnes317c35d2008-08-25 15:11:06 -07001917/* i915_suspend.c */
1918extern int i915_save_state(struct drm_device *dev);
1919extern int i915_restore_state(struct drm_device *dev);
1920
Daniel Vetterd8157a32013-01-25 17:53:20 +01001921/* i915_ums.c */
1922void i915_save_display_reg(struct drm_device *dev);
1923void i915_restore_display_reg(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001924
Ben Widawsky0136db52012-04-10 21:17:01 -07001925/* i915_sysfs.c */
1926void i915_setup_sysfs(struct drm_device *dev_priv);
1927void i915_teardown_sysfs(struct drm_device *dev_priv);
1928
Chris Wilsonf899fc62010-07-20 15:44:45 -07001929/* intel_i2c.c */
1930extern int intel_setup_gmbus(struct drm_device *dev);
1931extern void intel_teardown_gmbus(struct drm_device *dev);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02001932static inline bool intel_gmbus_is_port_valid(unsigned port)
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08001933{
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08001934 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08001935}
1936
1937extern struct i2c_adapter *intel_gmbus_get_adapter(
1938 struct drm_i915_private *dev_priv, unsigned port);
Chris Wilsone957d772010-09-24 12:52:03 +01001939extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1940extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02001941static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01001942{
1943 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1944}
Chris Wilsonf899fc62010-07-20 15:44:45 -07001945extern void intel_i2c_reset(struct drm_device *dev);
1946
Chris Wilson3b617962010-08-24 09:02:58 +01001947/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01001948extern int intel_opregion_setup(struct drm_device *dev);
1949#ifdef CONFIG_ACPI
1950extern void intel_opregion_init(struct drm_device *dev);
1951extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01001952extern void intel_opregion_asle_intr(struct drm_device *dev);
Len Brown65e082c2008-10-24 17:18:10 -04001953#else
Chris Wilson44834a62010-08-19 16:09:23 +01001954static inline void intel_opregion_init(struct drm_device *dev) { return; }
1955static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01001956static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Len Brown65e082c2008-10-24 17:18:10 -04001957#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001958
Jesse Barnes723bfd72010-10-07 16:01:13 -07001959/* intel_acpi.c */
1960#ifdef CONFIG_ACPI
1961extern void intel_register_dsm_handler(void);
1962extern void intel_unregister_dsm_handler(void);
1963#else
1964static inline void intel_register_dsm_handler(void) { return; }
1965static inline void intel_unregister_dsm_handler(void) { return; }
1966#endif /* CONFIG_ACPI */
1967
Jesse Barnes79e53942008-11-07 14:24:08 -08001968/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02001969extern void intel_modeset_init_hw(struct drm_device *dev);
Imre Deak7d708ee2013-04-17 14:04:50 +03001970extern void intel_modeset_suspend_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001971extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01001972extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001973extern void intel_modeset_cleanup(struct drm_device *dev);
Dave Airlie28d52042009-09-21 14:33:58 +10001974extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01001975extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1976 bool force_restore);
Daniel Vetter44cec742013-01-25 17:53:21 +01001977extern void i915_redisable_vga(struct drm_device *dev);
Adam Jacksonee5382a2010-04-23 11:17:39 -04001978extern bool intel_fbc_enabled(struct drm_device *dev);
Chris Wilson43a95392011-07-08 12:22:36 +01001979extern void intel_disable_fbc(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001980extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02001981extern void intel_init_pch_refclk(struct drm_device *dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001982extern void gen6_set_rps(struct drm_device *dev, u8 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07001983extern void valleyview_set_rps(struct drm_device *dev, u8 val);
1984extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
1985extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
Akshay Joshi0206e352011-08-16 15:34:10 -04001986extern void intel_detect_pch(struct drm_device *dev);
1987extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db52012-04-10 21:17:01 -07001988extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001989
Ben Widawsky2911a352012-04-05 14:47:36 -07001990extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001991int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1992 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07001993
Chris Wilson6ef3d422010-08-04 20:26:07 +01001994/* overlay */
Chris Wilson3bd3c932010-08-19 08:19:30 +01001995#ifdef CONFIG_DEBUG_FS
Chris Wilson6ef3d422010-08-04 20:26:07 +01001996extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001997extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
1998 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00001999
2000extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002001extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00002002 struct drm_device *dev,
2003 struct intel_display_error_state *error);
Chris Wilson3bd3c932010-08-19 08:19:30 +01002004#endif
Chris Wilson6ef3d422010-08-04 20:26:07 +01002005
Ben Widawskyb7287d82011-04-25 11:22:22 -07002006/* On SNB platform, before reading ring registers forcewake bit
2007 * must be set to prevent GT core from power down and stale values being
2008 * returned.
2009 */
Ben Widawskyfcca7922011-04-25 11:23:07 -07002010void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2011void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
Ben Widawsky67a37442012-02-09 10:15:20 +01002012int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
Ben Widawskyb7287d82011-04-25 11:22:22 -07002013
Ben Widawsky42c05262012-09-26 10:34:00 -07002014int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2015int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03002016
2017/* intel_sideband.c */
Jani Nikula64936252013-05-22 15:36:20 +03002018u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2019void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2020u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Jani Nikulaae992582013-05-22 15:36:19 +03002021u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
2022void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03002023u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2024 enum intel_sbi_destination destination);
2025void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2026 enum intel_sbi_destination destination);
Jesse Barnes0a073b82013-04-17 15:54:58 -07002027
Jesse Barnes855ba3b2013-04-17 15:54:57 -07002028int vlv_gpu_freq(int ddr_freq, int val);
2029int vlv_freq_opcode(int ddr_freq, int val);
Ben Widawsky42c05262012-09-26 10:34:00 -07002030
Keith Packard5f753772010-11-22 09:24:22 +00002031#define __i915_read(x, y) \
Andi Kleenf7000882011-10-13 16:08:51 -07002032 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
Ben Widawskyfcca7922011-04-25 11:23:07 -07002033
Keith Packard5f753772010-11-22 09:24:22 +00002034__i915_read(8, b)
2035__i915_read(16, w)
2036__i915_read(32, l)
2037__i915_read(64, q)
2038#undef __i915_read
2039
2040#define __i915_write(x, y) \
Andi Kleenf7000882011-10-13 16:08:51 -07002041 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
2042
Keith Packard5f753772010-11-22 09:24:22 +00002043__i915_write(8, b)
2044__i915_write(16, w)
2045__i915_write(32, l)
2046__i915_write(64, q)
2047#undef __i915_write
2048
2049#define I915_READ8(reg) i915_read8(dev_priv, (reg))
2050#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
2051
2052#define I915_READ16(reg) i915_read16(dev_priv, (reg))
2053#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
2054#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
2055#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
2056
2057#define I915_READ(reg) i915_read32(dev_priv, (reg))
2058#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
Zou Nan haicae58522010-11-09 17:17:32 +08002059#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
2060#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
Keith Packard5f753772010-11-22 09:24:22 +00002061
2062#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
2063#define I915_READ64(reg) i915_read64(dev_priv, (reg))
Zou Nan haicae58522010-11-09 17:17:32 +08002064
2065#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2066#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2067
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02002068/* "Broadcast RGB" property */
2069#define INTEL_BROADCAST_RGB_AUTO 0
2070#define INTEL_BROADCAST_RGB_FULL 1
2071#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08002072
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02002073static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2074{
2075 if (HAS_PCH_SPLIT(dev))
2076 return CPU_VGACNTRL;
2077 else if (IS_VALLEYVIEW(dev))
2078 return VLV_VGACNTRL;
2079 else
2080 return VGACNTRL;
2081}
2082
Ville Syrjälä2bb46292013-02-22 16:12:51 +02002083static inline void __user *to_user_ptr(u64 address)
2084{
2085 return (void __user *)(uintptr_t)address;
2086}
2087
Imre Deakdf977292013-05-21 20:03:17 +03002088static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2089{
2090 unsigned long j = msecs_to_jiffies(m);
2091
2092 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2093}
2094
2095static inline unsigned long
2096timespec_to_jiffies_timeout(const struct timespec *value)
2097{
2098 unsigned long j = timespec_to_jiffies(value);
2099
2100 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2101}
2102
Linus Torvalds1da177e2005-04-16 15:20:36 -07002103#endif