Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1 | /* |
| 2 | * QLogic Fibre Channel HBA Driver |
| 3 | * Copyright (c) 2003-2013 QLogic Corporation |
| 4 | * |
| 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
| 6 | */ |
| 7 | |
| 8 | #include <linux/vmalloc.h> |
| 9 | |
| 10 | #include "qla_def.h" |
| 11 | #include "qla_gbl.h" |
| 12 | |
| 13 | #include <linux/delay.h> |
| 14 | |
Pratik Mohanty | 804df80 | 2014-04-11 16:54:15 -0400 | [diff] [blame] | 15 | #define TIMEOUT_100_MS 100 |
| 16 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 17 | /* 8044 Flash Read/Write functions */ |
| 18 | uint32_t |
| 19 | qla8044_rd_reg(struct qla_hw_data *ha, ulong addr) |
| 20 | { |
| 21 | return readl((void __iomem *) (ha->nx_pcibase + addr)); |
| 22 | } |
| 23 | |
| 24 | void |
| 25 | qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val) |
| 26 | { |
| 27 | writel(val, (void __iomem *)((ha)->nx_pcibase + addr)); |
| 28 | } |
| 29 | |
| 30 | int |
| 31 | qla8044_rd_direct(struct scsi_qla_host *vha, |
| 32 | const uint32_t crb_reg) |
| 33 | { |
| 34 | struct qla_hw_data *ha = vha->hw; |
| 35 | |
| 36 | if (crb_reg < CRB_REG_INDEX_MAX) |
| 37 | return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]); |
| 38 | else |
| 39 | return QLA_FUNCTION_FAILED; |
| 40 | } |
| 41 | |
| 42 | void |
| 43 | qla8044_wr_direct(struct scsi_qla_host *vha, |
| 44 | const uint32_t crb_reg, |
| 45 | const uint32_t value) |
| 46 | { |
| 47 | struct qla_hw_data *ha = vha->hw; |
| 48 | |
| 49 | if (crb_reg < CRB_REG_INDEX_MAX) |
| 50 | qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value); |
| 51 | } |
| 52 | |
| 53 | static int |
| 54 | qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr) |
| 55 | { |
| 56 | uint32_t val; |
| 57 | int ret_val = QLA_SUCCESS; |
| 58 | struct qla_hw_data *ha = vha->hw; |
| 59 | |
| 60 | qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr); |
| 61 | val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum)); |
| 62 | |
| 63 | if (val != addr) { |
| 64 | ql_log(ql_log_warn, vha, 0xb087, |
| 65 | "%s: Failed to set register window : " |
| 66 | "addr written 0x%x, read 0x%x!\n", |
| 67 | __func__, addr, val); |
| 68 | ret_val = QLA_FUNCTION_FAILED; |
| 69 | } |
| 70 | return ret_val; |
| 71 | } |
| 72 | |
| 73 | static int |
| 74 | qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) |
| 75 | { |
| 76 | int ret_val = QLA_SUCCESS; |
| 77 | struct qla_hw_data *ha = vha->hw; |
| 78 | |
| 79 | ret_val = qla8044_set_win_base(vha, addr); |
| 80 | if (!ret_val) |
| 81 | *data = qla8044_rd_reg(ha, QLA8044_WILDCARD); |
| 82 | else |
| 83 | ql_log(ql_log_warn, vha, 0xb088, |
| 84 | "%s: failed read of addr 0x%x!\n", __func__, addr); |
| 85 | return ret_val; |
| 86 | } |
| 87 | |
| 88 | static int |
| 89 | qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) |
| 90 | { |
| 91 | int ret_val = QLA_SUCCESS; |
| 92 | struct qla_hw_data *ha = vha->hw; |
| 93 | |
| 94 | ret_val = qla8044_set_win_base(vha, addr); |
| 95 | if (!ret_val) |
| 96 | qla8044_wr_reg(ha, QLA8044_WILDCARD, data); |
| 97 | else |
| 98 | ql_log(ql_log_warn, vha, 0xb089, |
| 99 | "%s: failed wrt to addr 0x%x, data 0x%x\n", |
| 100 | __func__, addr, data); |
| 101 | return ret_val; |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | * qla8044_read_write_crb_reg - Read from raddr and write value to waddr. |
| 106 | * |
| 107 | * @ha : Pointer to adapter structure |
| 108 | * @raddr : CRB address to read from |
| 109 | * @waddr : CRB address to write to |
| 110 | * |
| 111 | */ |
| 112 | static void |
| 113 | qla8044_read_write_crb_reg(struct scsi_qla_host *vha, |
| 114 | uint32_t raddr, uint32_t waddr) |
| 115 | { |
| 116 | uint32_t value; |
| 117 | |
| 118 | qla8044_rd_reg_indirect(vha, raddr, &value); |
| 119 | qla8044_wr_reg_indirect(vha, waddr, value); |
| 120 | } |
| 121 | |
Pratik Mohanty | 804df80 | 2014-04-11 16:54:15 -0400 | [diff] [blame] | 122 | static int |
| 123 | qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1, |
| 124 | uint32_t mask) |
| 125 | { |
| 126 | unsigned long timeout; |
| 127 | uint32_t temp; |
| 128 | |
| 129 | /* jiffies after 100ms */ |
| 130 | timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); |
| 131 | do { |
| 132 | qla8044_rd_reg_indirect(vha, addr1, &temp); |
| 133 | if ((temp & mask) != 0) |
| 134 | break; |
| 135 | if (time_after_eq(jiffies, timeout)) { |
| 136 | ql_log(ql_log_warn, vha, 0xb151, |
| 137 | "Error in processing rdmdio entry\n"); |
| 138 | return -1; |
| 139 | } |
| 140 | } while (1); |
| 141 | |
| 142 | return 0; |
| 143 | } |
| 144 | |
| 145 | static uint32_t |
| 146 | qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha, |
| 147 | uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr) |
| 148 | { |
| 149 | uint32_t temp; |
| 150 | int ret = 0; |
| 151 | |
| 152 | ret = qla8044_poll_wait_for_ready(vha, addr1, mask); |
| 153 | if (ret == -1) |
| 154 | return -1; |
| 155 | |
| 156 | temp = (0x40000000 | addr); |
| 157 | qla8044_wr_reg_indirect(vha, addr1, temp); |
| 158 | |
| 159 | ret = qla8044_poll_wait_for_ready(vha, addr1, mask); |
| 160 | if (ret == -1) |
| 161 | return 0; |
| 162 | |
| 163 | qla8044_rd_reg_indirect(vha, addr3, &ret); |
| 164 | |
| 165 | return ret; |
| 166 | } |
| 167 | |
| 168 | |
| 169 | static int |
| 170 | qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha, |
| 171 | uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask) |
| 172 | { |
| 173 | unsigned long timeout; |
| 174 | uint32_t temp; |
| 175 | |
| 176 | /* jiffies after 100 msecs */ |
| 177 | timeout = jiffies + (HZ / 1000) * TIMEOUT_100_MS; |
| 178 | do { |
| 179 | temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2); |
| 180 | if ((temp & 0x1) != 1) |
| 181 | break; |
| 182 | } while (!time_after_eq(jiffies, timeout)); |
| 183 | |
| 184 | if (time_after_eq(jiffies, timeout)) { |
| 185 | ql_log(ql_log_warn, vha, 0xb152, |
| 186 | "Error in processing mdiobus idle\n"); |
| 187 | return -1; |
| 188 | } |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | static int |
| 194 | qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1, |
| 195 | uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value) |
| 196 | { |
| 197 | int ret = 0; |
| 198 | |
| 199 | ret = qla8044_poll_wait_for_ready(vha, addr1, mask); |
| 200 | if (ret == -1) |
| 201 | return -1; |
| 202 | |
| 203 | qla8044_wr_reg_indirect(vha, addr3, value); |
| 204 | qla8044_wr_reg_indirect(vha, addr1, addr); |
| 205 | |
| 206 | ret = qla8044_poll_wait_for_ready(vha, addr1, mask); |
| 207 | if (ret == -1) |
| 208 | return -1; |
| 209 | |
| 210 | return 0; |
| 211 | } |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 212 | /* |
| 213 | * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask, |
| 214 | * Shift Left,Right/OR/XOR with values RMW header and write value to waddr. |
| 215 | * |
| 216 | * @vha : Pointer to adapter structure |
| 217 | * @raddr : CRB address to read from |
| 218 | * @waddr : CRB address to write to |
| 219 | * @p_rmw_hdr : header with shift/or/xor values. |
| 220 | * |
| 221 | */ |
| 222 | static void |
| 223 | qla8044_rmw_crb_reg(struct scsi_qla_host *vha, |
| 224 | uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr) |
| 225 | { |
| 226 | uint32_t value; |
| 227 | |
| 228 | if (p_rmw_hdr->index_a) |
| 229 | value = vha->reset_tmplt.array[p_rmw_hdr->index_a]; |
| 230 | else |
| 231 | qla8044_rd_reg_indirect(vha, raddr, &value); |
| 232 | value &= p_rmw_hdr->test_mask; |
| 233 | value <<= p_rmw_hdr->shl; |
| 234 | value >>= p_rmw_hdr->shr; |
| 235 | value |= p_rmw_hdr->or_value; |
| 236 | value ^= p_rmw_hdr->xor_value; |
| 237 | qla8044_wr_reg_indirect(vha, waddr, value); |
| 238 | return; |
| 239 | } |
| 240 | |
| 241 | inline void |
| 242 | qla8044_set_qsnt_ready(struct scsi_qla_host *vha) |
| 243 | { |
| 244 | uint32_t qsnt_state; |
| 245 | struct qla_hw_data *ha = vha->hw; |
| 246 | |
| 247 | qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); |
| 248 | qsnt_state |= (1 << ha->portnum); |
| 249 | qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state); |
| 250 | ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n", |
| 251 | __func__, vha->host_no, qsnt_state); |
| 252 | } |
| 253 | |
| 254 | void |
| 255 | qla8044_clear_qsnt_ready(struct scsi_qla_host *vha) |
| 256 | { |
| 257 | uint32_t qsnt_state; |
| 258 | struct qla_hw_data *ha = vha->hw; |
| 259 | |
| 260 | qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); |
| 261 | qsnt_state &= ~(1 << ha->portnum); |
| 262 | qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state); |
| 263 | ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n", |
| 264 | __func__, vha->host_no, qsnt_state); |
| 265 | } |
| 266 | |
| 267 | /** |
| 268 | * |
| 269 | * qla8044_lock_recovery - Recovers the idc_lock. |
| 270 | * @ha : Pointer to adapter structure |
| 271 | * |
| 272 | * Lock Recovery Register |
| 273 | * 5-2 Lock recovery owner: Function ID of driver doing lock recovery, |
| 274 | * valid if bits 1..0 are set by driver doing lock recovery. |
| 275 | * 1-0 1 - Driver intends to force unlock the IDC lock. |
| 276 | * 2 - Driver is moving forward to unlock the IDC lock. Driver clears |
| 277 | * this field after force unlocking the IDC lock. |
| 278 | * |
| 279 | * Lock Recovery process |
| 280 | * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is |
| 281 | * greater than 0, then wait for the other driver to unlock otherwise |
| 282 | * move to the next step. |
| 283 | * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY |
| 284 | * register bits 1..0 and also set the function# in bits 5..2. |
| 285 | * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms. |
| 286 | * Wait for the other driver to perform lock recovery if the function |
| 287 | * number in bits 5..2 has changed, otherwise move to the next step. |
| 288 | * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0 |
| 289 | * leaving your function# in bits 5..2. |
| 290 | * e. Force unlock using the DRIVER_UNLOCK register and immediately clear |
| 291 | * the IDC_LOCK_RECOVERY bits 5..0 by writing 0. |
| 292 | **/ |
| 293 | static int |
| 294 | qla8044_lock_recovery(struct scsi_qla_host *vha) |
| 295 | { |
| 296 | uint32_t lock = 0, lockid; |
| 297 | struct qla_hw_data *ha = vha->hw; |
| 298 | |
| 299 | lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY); |
| 300 | |
| 301 | /* Check for other Recovery in progress, go wait */ |
| 302 | if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0) |
| 303 | return QLA_FUNCTION_FAILED; |
| 304 | |
| 305 | /* Intent to Recover */ |
| 306 | qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, |
| 307 | (ha->portnum << |
| 308 | IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER); |
| 309 | msleep(200); |
| 310 | |
| 311 | /* Check Intent to Recover is advertised */ |
| 312 | lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY); |
| 313 | if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum << |
| 314 | IDC_LOCK_RECOVERY_STATE_SHIFT_BITS)) |
| 315 | return QLA_FUNCTION_FAILED; |
| 316 | |
| 317 | ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n" |
| 318 | , __func__, ha->portnum); |
| 319 | |
| 320 | /* Proceed to Recover */ |
| 321 | qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, |
| 322 | (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | |
| 323 | PROCEED_TO_RECOVER); |
| 324 | |
| 325 | /* Force Unlock() */ |
| 326 | qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF); |
| 327 | qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK); |
| 328 | |
| 329 | /* Clear bits 0-5 in IDC_RECOVERY register*/ |
| 330 | qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0); |
| 331 | |
| 332 | /* Get lock() */ |
| 333 | lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK); |
| 334 | if (lock) { |
| 335 | lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); |
| 336 | lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum; |
| 337 | qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid); |
| 338 | return QLA_SUCCESS; |
| 339 | } else |
| 340 | return QLA_FUNCTION_FAILED; |
| 341 | } |
| 342 | |
| 343 | int |
| 344 | qla8044_idc_lock(struct qla_hw_data *ha) |
| 345 | { |
| 346 | uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0; |
| 347 | uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0; |
| 348 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
| 349 | |
| 350 | while (status == 0) { |
| 351 | /* acquire semaphore5 from PCI HW block */ |
| 352 | status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK); |
| 353 | |
| 354 | if (status) { |
| 355 | /* Increment Counter (8-31) and update func_num (0-7) on |
| 356 | * getting a successful lock */ |
| 357 | lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); |
| 358 | lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum; |
| 359 | qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id); |
| 360 | break; |
| 361 | } |
| 362 | |
| 363 | if (timeout == 0) |
| 364 | first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); |
| 365 | |
| 366 | if (++timeout >= |
| 367 | (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) { |
| 368 | tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); |
| 369 | func_num = tmo_owner & 0xFF; |
| 370 | lock_cnt = tmo_owner >> 8; |
| 371 | ql_log(ql_log_warn, vha, 0xb114, |
| 372 | "%s: Lock by func %d failed after 2s, lock held " |
| 373 | "by func %d, lock count %d, first_owner %d\n", |
| 374 | __func__, ha->portnum, func_num, lock_cnt, |
| 375 | (first_owner & 0xFF)); |
| 376 | if (first_owner != tmo_owner) { |
| 377 | /* Some other driver got lock, |
| 378 | * OR same driver got lock again (counter |
| 379 | * value changed), when we were waiting for |
| 380 | * lock. Retry for another 2 sec */ |
| 381 | ql_dbg(ql_dbg_p3p, vha, 0xb115, |
| 382 | "%s: %d: IDC lock failed\n", |
| 383 | __func__, ha->portnum); |
| 384 | timeout = 0; |
| 385 | } else { |
| 386 | /* Same driver holding lock > 2sec. |
| 387 | * Force Recovery */ |
| 388 | if (qla8044_lock_recovery(vha) == QLA_SUCCESS) { |
| 389 | /* Recovered and got lock */ |
| 390 | ret_val = QLA_SUCCESS; |
| 391 | ql_dbg(ql_dbg_p3p, vha, 0xb116, |
| 392 | "%s:IDC lock Recovery by %d" |
| 393 | "successful...\n", __func__, |
| 394 | ha->portnum); |
| 395 | } |
| 396 | /* Recovery Failed, some other function |
| 397 | * has the lock, wait for 2secs |
| 398 | * and retry |
| 399 | */ |
| 400 | ql_dbg(ql_dbg_p3p, vha, 0xb08a, |
| 401 | "%s: IDC lock Recovery by %d " |
| 402 | "failed, Retrying timout\n", __func__, |
| 403 | ha->portnum); |
| 404 | timeout = 0; |
| 405 | } |
| 406 | } |
| 407 | msleep(QLA8044_DRV_LOCK_MSLEEP); |
| 408 | } |
| 409 | return ret_val; |
| 410 | } |
| 411 | |
| 412 | void |
| 413 | qla8044_idc_unlock(struct qla_hw_data *ha) |
| 414 | { |
| 415 | int id; |
| 416 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
| 417 | |
| 418 | id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); |
| 419 | |
| 420 | if ((id & 0xFF) != ha->portnum) { |
| 421 | ql_log(ql_log_warn, vha, 0xb118, |
| 422 | "%s: IDC Unlock by %d failed, lock owner is %d!\n", |
| 423 | __func__, ha->portnum, (id & 0xFF)); |
| 424 | return; |
| 425 | } |
| 426 | |
| 427 | /* Keep lock counter value, update the ha->func_num to 0xFF */ |
| 428 | qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF)); |
| 429 | qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK); |
| 430 | } |
| 431 | |
| 432 | /* 8044 Flash Lock/Unlock functions */ |
| 433 | static int |
| 434 | qla8044_flash_lock(scsi_qla_host_t *vha) |
| 435 | { |
| 436 | int lock_owner; |
| 437 | int timeout = 0; |
| 438 | uint32_t lock_status = 0; |
| 439 | int ret_val = QLA_SUCCESS; |
| 440 | struct qla_hw_data *ha = vha->hw; |
| 441 | |
| 442 | while (lock_status == 0) { |
| 443 | lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK); |
| 444 | if (lock_status) |
| 445 | break; |
| 446 | |
| 447 | if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) { |
| 448 | lock_owner = qla8044_rd_reg(ha, |
| 449 | QLA8044_FLASH_LOCK_ID); |
| 450 | ql_log(ql_log_warn, vha, 0xb113, |
| 451 | "%s: flash lock by %d failed, held by %d\n", |
| 452 | __func__, ha->portnum, lock_owner); |
| 453 | ret_val = QLA_FUNCTION_FAILED; |
| 454 | break; |
| 455 | } |
| 456 | msleep(20); |
| 457 | } |
| 458 | qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum); |
| 459 | return ret_val; |
| 460 | } |
| 461 | |
| 462 | static void |
| 463 | qla8044_flash_unlock(scsi_qla_host_t *vha) |
| 464 | { |
| 465 | int ret_val; |
| 466 | struct qla_hw_data *ha = vha->hw; |
| 467 | |
| 468 | /* Reading FLASH_UNLOCK register unlocks the Flash */ |
| 469 | qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF); |
| 470 | ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK); |
| 471 | } |
| 472 | |
| 473 | |
| 474 | static |
| 475 | void qla8044_flash_lock_recovery(struct scsi_qla_host *vha) |
| 476 | { |
| 477 | |
| 478 | if (qla8044_flash_lock(vha)) { |
| 479 | /* Someone else is holding the lock. */ |
| 480 | ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n"); |
| 481 | } |
| 482 | |
| 483 | /* |
| 484 | * Either we got the lock, or someone |
| 485 | * else died while holding it. |
| 486 | * In either case, unlock. |
| 487 | */ |
| 488 | qla8044_flash_unlock(vha); |
| 489 | } |
| 490 | |
| 491 | /* |
| 492 | * Address and length are byte address |
| 493 | */ |
| 494 | static int |
| 495 | qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data, |
| 496 | uint32_t flash_addr, int u32_word_count) |
| 497 | { |
| 498 | int i, ret_val = QLA_SUCCESS; |
| 499 | uint32_t u32_word; |
| 500 | |
| 501 | if (qla8044_flash_lock(vha) != QLA_SUCCESS) { |
| 502 | ret_val = QLA_FUNCTION_FAILED; |
| 503 | goto exit_lock_error; |
| 504 | } |
| 505 | |
| 506 | if (flash_addr & 0x03) { |
| 507 | ql_log(ql_log_warn, vha, 0xb117, |
| 508 | "%s: Illegal addr = 0x%x\n", __func__, flash_addr); |
| 509 | ret_val = QLA_FUNCTION_FAILED; |
| 510 | goto exit_flash_read; |
| 511 | } |
| 512 | |
| 513 | for (i = 0; i < u32_word_count; i++) { |
| 514 | if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW, |
| 515 | (flash_addr & 0xFFFF0000))) { |
| 516 | ql_log(ql_log_warn, vha, 0xb119, |
| 517 | "%s: failed to write addr 0x%x to " |
| 518 | "FLASH_DIRECT_WINDOW\n! ", |
| 519 | __func__, flash_addr); |
| 520 | ret_val = QLA_FUNCTION_FAILED; |
| 521 | goto exit_flash_read; |
| 522 | } |
| 523 | |
| 524 | ret_val = qla8044_rd_reg_indirect(vha, |
| 525 | QLA8044_FLASH_DIRECT_DATA(flash_addr), |
| 526 | &u32_word); |
| 527 | if (ret_val != QLA_SUCCESS) { |
| 528 | ql_log(ql_log_warn, vha, 0xb08c, |
| 529 | "%s: failed to read addr 0x%x!\n", |
| 530 | __func__, flash_addr); |
| 531 | goto exit_flash_read; |
| 532 | } |
| 533 | |
| 534 | *(uint32_t *)p_data = u32_word; |
| 535 | p_data = p_data + 4; |
| 536 | flash_addr = flash_addr + 4; |
| 537 | } |
| 538 | |
| 539 | exit_flash_read: |
| 540 | qla8044_flash_unlock(vha); |
| 541 | |
| 542 | exit_lock_error: |
| 543 | return ret_val; |
| 544 | } |
| 545 | |
| 546 | /* |
| 547 | * Address and length are byte address |
| 548 | */ |
| 549 | uint8_t * |
| 550 | qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
| 551 | uint32_t offset, uint32_t length) |
| 552 | { |
| 553 | scsi_block_requests(vha->host); |
| 554 | if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4) |
| 555 | != QLA_SUCCESS) { |
| 556 | ql_log(ql_log_warn, vha, 0xb08d, |
| 557 | "%s: Failed to read from flash\n", |
| 558 | __func__); |
| 559 | } |
| 560 | scsi_unblock_requests(vha->host); |
| 561 | return buf; |
| 562 | } |
| 563 | |
| 564 | inline int |
| 565 | qla8044_need_reset(struct scsi_qla_host *vha) |
| 566 | { |
| 567 | uint32_t drv_state, drv_active; |
| 568 | int rval; |
| 569 | struct qla_hw_data *ha = vha->hw; |
| 570 | |
| 571 | drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 572 | drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); |
| 573 | |
| 574 | rval = drv_state & (1 << ha->portnum); |
| 575 | |
| 576 | if (ha->flags.eeh_busy && drv_active) |
| 577 | rval = 1; |
| 578 | return rval; |
| 579 | } |
| 580 | |
| 581 | /* |
| 582 | * qla8044_write_list - Write the value (p_entry->arg2) to address specified |
| 583 | * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between |
| 584 | * entries. |
| 585 | * |
| 586 | * @vha : Pointer to adapter structure |
| 587 | * @p_hdr : reset_entry header for WRITE_LIST opcode. |
| 588 | * |
| 589 | */ |
| 590 | static void |
| 591 | qla8044_write_list(struct scsi_qla_host *vha, |
| 592 | struct qla8044_reset_entry_hdr *p_hdr) |
| 593 | { |
| 594 | struct qla8044_entry *p_entry; |
| 595 | uint32_t i; |
| 596 | |
| 597 | p_entry = (struct qla8044_entry *)((char *)p_hdr + |
| 598 | sizeof(struct qla8044_reset_entry_hdr)); |
| 599 | |
| 600 | for (i = 0; i < p_hdr->count; i++, p_entry++) { |
| 601 | qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2); |
| 602 | if (p_hdr->delay) |
| 603 | udelay((uint32_t)(p_hdr->delay)); |
| 604 | } |
| 605 | } |
| 606 | |
| 607 | /* |
| 608 | * qla8044_read_write_list - Read from address specified by p_entry->arg1, |
| 609 | * write value read to address specified by p_entry->arg2, for all entries in |
| 610 | * header with delay of p_hdr->delay between entries. |
| 611 | * |
| 612 | * @vha : Pointer to adapter structure |
| 613 | * @p_hdr : reset_entry header for READ_WRITE_LIST opcode. |
| 614 | * |
| 615 | */ |
| 616 | static void |
| 617 | qla8044_read_write_list(struct scsi_qla_host *vha, |
| 618 | struct qla8044_reset_entry_hdr *p_hdr) |
| 619 | { |
| 620 | struct qla8044_entry *p_entry; |
| 621 | uint32_t i; |
| 622 | |
| 623 | p_entry = (struct qla8044_entry *)((char *)p_hdr + |
| 624 | sizeof(struct qla8044_reset_entry_hdr)); |
| 625 | |
| 626 | for (i = 0; i < p_hdr->count; i++, p_entry++) { |
| 627 | qla8044_read_write_crb_reg(vha, p_entry->arg1, |
| 628 | p_entry->arg2); |
| 629 | if (p_hdr->delay) |
| 630 | udelay((uint32_t)(p_hdr->delay)); |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | /* |
| 635 | * qla8044_poll_reg - Poll the given CRB addr for duration msecs till |
| 636 | * value read ANDed with test_mask is equal to test_result. |
| 637 | * |
| 638 | * @ha : Pointer to adapter structure |
| 639 | * @addr : CRB register address |
| 640 | * @duration : Poll for total of "duration" msecs |
| 641 | * @test_mask : Mask value read with "test_mask" |
| 642 | * @test_result : Compare (value&test_mask) with test_result. |
| 643 | * |
| 644 | * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED |
| 645 | */ |
| 646 | static int |
| 647 | qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr, |
| 648 | int duration, uint32_t test_mask, uint32_t test_result) |
| 649 | { |
| 650 | uint32_t value; |
| 651 | int timeout_error; |
| 652 | uint8_t retries; |
| 653 | int ret_val = QLA_SUCCESS; |
| 654 | |
| 655 | ret_val = qla8044_rd_reg_indirect(vha, addr, &value); |
| 656 | if (ret_val == QLA_FUNCTION_FAILED) { |
| 657 | timeout_error = 1; |
| 658 | goto exit_poll_reg; |
| 659 | } |
| 660 | |
| 661 | /* poll every 1/10 of the total duration */ |
| 662 | retries = duration/10; |
| 663 | |
| 664 | do { |
| 665 | if ((value & test_mask) != test_result) { |
| 666 | timeout_error = 1; |
| 667 | msleep(duration/10); |
| 668 | ret_val = qla8044_rd_reg_indirect(vha, addr, &value); |
| 669 | if (ret_val == QLA_FUNCTION_FAILED) { |
| 670 | timeout_error = 1; |
| 671 | goto exit_poll_reg; |
| 672 | } |
| 673 | } else { |
| 674 | timeout_error = 0; |
| 675 | break; |
| 676 | } |
| 677 | } while (retries--); |
| 678 | |
| 679 | exit_poll_reg: |
| 680 | if (timeout_error) { |
| 681 | vha->reset_tmplt.seq_error++; |
| 682 | ql_log(ql_log_fatal, vha, 0xb090, |
| 683 | "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n", |
| 684 | __func__, value, test_mask, test_result); |
| 685 | } |
| 686 | |
| 687 | return timeout_error; |
| 688 | } |
| 689 | |
| 690 | /* |
| 691 | * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB |
| 692 | * register specified by p_entry->arg1 and compare (value AND test_mask) with |
| 693 | * test_result to validate it. Wait for p_hdr->delay between processing entries. |
| 694 | * |
| 695 | * @ha : Pointer to adapter structure |
| 696 | * @p_hdr : reset_entry header for POLL_LIST opcode. |
| 697 | * |
| 698 | */ |
| 699 | static void |
| 700 | qla8044_poll_list(struct scsi_qla_host *vha, |
| 701 | struct qla8044_reset_entry_hdr *p_hdr) |
| 702 | { |
| 703 | long delay; |
| 704 | struct qla8044_entry *p_entry; |
| 705 | struct qla8044_poll *p_poll; |
| 706 | uint32_t i; |
| 707 | uint32_t value; |
| 708 | |
| 709 | p_poll = (struct qla8044_poll *) |
| 710 | ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr)); |
| 711 | |
| 712 | /* Entries start after 8 byte qla8044_poll, poll header contains |
| 713 | * the test_mask, test_value. |
| 714 | */ |
| 715 | p_entry = (struct qla8044_entry *)((char *)p_poll + |
| 716 | sizeof(struct qla8044_poll)); |
| 717 | |
| 718 | delay = (long)p_hdr->delay; |
| 719 | |
| 720 | if (!delay) { |
| 721 | for (i = 0; i < p_hdr->count; i++, p_entry++) |
| 722 | qla8044_poll_reg(vha, p_entry->arg1, |
| 723 | delay, p_poll->test_mask, p_poll->test_value); |
| 724 | } else { |
| 725 | for (i = 0; i < p_hdr->count; i++, p_entry++) { |
| 726 | if (delay) { |
| 727 | if (qla8044_poll_reg(vha, |
| 728 | p_entry->arg1, delay, |
| 729 | p_poll->test_mask, |
| 730 | p_poll->test_value)) { |
| 731 | /*If |
| 732 | * (data_read&test_mask != test_value) |
| 733 | * read TIMEOUT_ADDR (arg1) and |
| 734 | * ADDR (arg2) registers |
| 735 | */ |
| 736 | qla8044_rd_reg_indirect(vha, |
| 737 | p_entry->arg1, &value); |
| 738 | qla8044_rd_reg_indirect(vha, |
| 739 | p_entry->arg2, &value); |
| 740 | } |
| 741 | } |
| 742 | } |
| 743 | } |
| 744 | } |
| 745 | |
| 746 | /* |
| 747 | * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr, |
| 748 | * read ar_addr, if (value& test_mask != test_mask) re-read till timeout |
| 749 | * expires. |
| 750 | * |
| 751 | * @vha : Pointer to adapter structure |
| 752 | * @p_hdr : reset entry header for POLL_WRITE_LIST opcode. |
| 753 | * |
| 754 | */ |
| 755 | static void |
| 756 | qla8044_poll_write_list(struct scsi_qla_host *vha, |
| 757 | struct qla8044_reset_entry_hdr *p_hdr) |
| 758 | { |
| 759 | long delay; |
| 760 | struct qla8044_quad_entry *p_entry; |
| 761 | struct qla8044_poll *p_poll; |
| 762 | uint32_t i; |
| 763 | |
| 764 | p_poll = (struct qla8044_poll *)((char *)p_hdr + |
| 765 | sizeof(struct qla8044_reset_entry_hdr)); |
| 766 | |
| 767 | p_entry = (struct qla8044_quad_entry *)((char *)p_poll + |
| 768 | sizeof(struct qla8044_poll)); |
| 769 | |
| 770 | delay = (long)p_hdr->delay; |
| 771 | |
| 772 | for (i = 0; i < p_hdr->count; i++, p_entry++) { |
| 773 | qla8044_wr_reg_indirect(vha, |
| 774 | p_entry->dr_addr, p_entry->dr_value); |
| 775 | qla8044_wr_reg_indirect(vha, |
| 776 | p_entry->ar_addr, p_entry->ar_value); |
| 777 | if (delay) { |
| 778 | if (qla8044_poll_reg(vha, |
| 779 | p_entry->ar_addr, delay, |
| 780 | p_poll->test_mask, |
| 781 | p_poll->test_value)) { |
| 782 | ql_dbg(ql_dbg_p3p, vha, 0xb091, |
| 783 | "%s: Timeout Error: poll list, ", |
| 784 | __func__); |
| 785 | ql_dbg(ql_dbg_p3p, vha, 0xb092, |
| 786 | "item_num %d, entry_num %d\n", i, |
| 787 | vha->reset_tmplt.seq_index); |
| 788 | } |
| 789 | } |
| 790 | } |
| 791 | } |
| 792 | |
| 793 | /* |
| 794 | * qla8044_read_modify_write - Read value from p_entry->arg1, modify the |
| 795 | * value, write value to p_entry->arg2. Process entries with p_hdr->delay |
| 796 | * between entries. |
| 797 | * |
| 798 | * @vha : Pointer to adapter structure |
| 799 | * @p_hdr : header with shift/or/xor values. |
| 800 | * |
| 801 | */ |
| 802 | static void |
| 803 | qla8044_read_modify_write(struct scsi_qla_host *vha, |
| 804 | struct qla8044_reset_entry_hdr *p_hdr) |
| 805 | { |
| 806 | struct qla8044_entry *p_entry; |
| 807 | struct qla8044_rmw *p_rmw_hdr; |
| 808 | uint32_t i; |
| 809 | |
| 810 | p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr + |
| 811 | sizeof(struct qla8044_reset_entry_hdr)); |
| 812 | |
| 813 | p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr + |
| 814 | sizeof(struct qla8044_rmw)); |
| 815 | |
| 816 | for (i = 0; i < p_hdr->count; i++, p_entry++) { |
| 817 | qla8044_rmw_crb_reg(vha, p_entry->arg1, |
| 818 | p_entry->arg2, p_rmw_hdr); |
| 819 | if (p_hdr->delay) |
| 820 | udelay((uint32_t)(p_hdr->delay)); |
| 821 | } |
| 822 | } |
| 823 | |
| 824 | /* |
| 825 | * qla8044_pause - Wait for p_hdr->delay msecs, called between processing |
| 826 | * two entries of a sequence. |
| 827 | * |
| 828 | * @vha : Pointer to adapter structure |
| 829 | * @p_hdr : Common reset entry header. |
| 830 | * |
| 831 | */ |
| 832 | static |
| 833 | void qla8044_pause(struct scsi_qla_host *vha, |
| 834 | struct qla8044_reset_entry_hdr *p_hdr) |
| 835 | { |
| 836 | if (p_hdr->delay) |
| 837 | mdelay((uint32_t)((long)p_hdr->delay)); |
| 838 | } |
| 839 | |
| 840 | /* |
| 841 | * qla8044_template_end - Indicates end of reset sequence processing. |
| 842 | * |
| 843 | * @vha : Pointer to adapter structure |
| 844 | * @p_hdr : Common reset entry header. |
| 845 | * |
| 846 | */ |
| 847 | static void |
| 848 | qla8044_template_end(struct scsi_qla_host *vha, |
| 849 | struct qla8044_reset_entry_hdr *p_hdr) |
| 850 | { |
| 851 | vha->reset_tmplt.template_end = 1; |
| 852 | |
| 853 | if (vha->reset_tmplt.seq_error == 0) { |
| 854 | ql_dbg(ql_dbg_p3p, vha, 0xb093, |
| 855 | "%s: Reset sequence completed SUCCESSFULLY.\n", __func__); |
| 856 | } else { |
| 857 | ql_log(ql_log_fatal, vha, 0xb094, |
| 858 | "%s: Reset sequence completed with some timeout " |
| 859 | "errors.\n", __func__); |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | /* |
| 864 | * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr, |
| 865 | * if (value & test_mask != test_value) re-read till timeout value expires, |
| 866 | * read dr_addr register and assign to reset_tmplt.array. |
| 867 | * |
| 868 | * @vha : Pointer to adapter structure |
| 869 | * @p_hdr : Common reset entry header. |
| 870 | * |
| 871 | */ |
| 872 | static void |
| 873 | qla8044_poll_read_list(struct scsi_qla_host *vha, |
| 874 | struct qla8044_reset_entry_hdr *p_hdr) |
| 875 | { |
| 876 | long delay; |
| 877 | int index; |
| 878 | struct qla8044_quad_entry *p_entry; |
| 879 | struct qla8044_poll *p_poll; |
| 880 | uint32_t i; |
| 881 | uint32_t value; |
| 882 | |
| 883 | p_poll = (struct qla8044_poll *) |
| 884 | ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr)); |
| 885 | |
| 886 | p_entry = (struct qla8044_quad_entry *) |
| 887 | ((char *)p_poll + sizeof(struct qla8044_poll)); |
| 888 | |
| 889 | delay = (long)p_hdr->delay; |
| 890 | |
| 891 | for (i = 0; i < p_hdr->count; i++, p_entry++) { |
| 892 | qla8044_wr_reg_indirect(vha, p_entry->ar_addr, |
| 893 | p_entry->ar_value); |
| 894 | if (delay) { |
| 895 | if (qla8044_poll_reg(vha, p_entry->ar_addr, delay, |
| 896 | p_poll->test_mask, p_poll->test_value)) { |
| 897 | ql_dbg(ql_dbg_p3p, vha, 0xb095, |
| 898 | "%s: Timeout Error: poll " |
| 899 | "list, ", __func__); |
| 900 | ql_dbg(ql_dbg_p3p, vha, 0xb096, |
| 901 | "Item_num %d, " |
| 902 | "entry_num %d\n", i, |
| 903 | vha->reset_tmplt.seq_index); |
| 904 | } else { |
| 905 | index = vha->reset_tmplt.array_index; |
| 906 | qla8044_rd_reg_indirect(vha, |
| 907 | p_entry->dr_addr, &value); |
| 908 | vha->reset_tmplt.array[index++] = value; |
| 909 | if (index == QLA8044_MAX_RESET_SEQ_ENTRIES) |
| 910 | vha->reset_tmplt.array_index = 1; |
| 911 | } |
| 912 | } |
| 913 | } |
| 914 | } |
| 915 | |
| 916 | /* |
| 917 | * qla8031_process_reset_template - Process all entries in reset template |
| 918 | * till entry with SEQ_END opcode, which indicates end of the reset template |
| 919 | * processing. Each entry has a Reset Entry header, entry opcode/command, with |
| 920 | * size of the entry, number of entries in sub-sequence and delay in microsecs |
| 921 | * or timeout in millisecs. |
| 922 | * |
| 923 | * @ha : Pointer to adapter structure |
| 924 | * @p_buff : Common reset entry header. |
| 925 | * |
| 926 | */ |
| 927 | static void |
| 928 | qla8044_process_reset_template(struct scsi_qla_host *vha, |
| 929 | char *p_buff) |
| 930 | { |
| 931 | int index, entries; |
| 932 | struct qla8044_reset_entry_hdr *p_hdr; |
| 933 | char *p_entry = p_buff; |
| 934 | |
| 935 | vha->reset_tmplt.seq_end = 0; |
| 936 | vha->reset_tmplt.template_end = 0; |
| 937 | entries = vha->reset_tmplt.hdr->entries; |
| 938 | index = vha->reset_tmplt.seq_index; |
| 939 | |
| 940 | for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) { |
| 941 | p_hdr = (struct qla8044_reset_entry_hdr *)p_entry; |
| 942 | switch (p_hdr->cmd) { |
| 943 | case OPCODE_NOP: |
| 944 | break; |
| 945 | case OPCODE_WRITE_LIST: |
| 946 | qla8044_write_list(vha, p_hdr); |
| 947 | break; |
| 948 | case OPCODE_READ_WRITE_LIST: |
| 949 | qla8044_read_write_list(vha, p_hdr); |
| 950 | break; |
| 951 | case OPCODE_POLL_LIST: |
| 952 | qla8044_poll_list(vha, p_hdr); |
| 953 | break; |
| 954 | case OPCODE_POLL_WRITE_LIST: |
| 955 | qla8044_poll_write_list(vha, p_hdr); |
| 956 | break; |
| 957 | case OPCODE_READ_MODIFY_WRITE: |
| 958 | qla8044_read_modify_write(vha, p_hdr); |
| 959 | break; |
| 960 | case OPCODE_SEQ_PAUSE: |
| 961 | qla8044_pause(vha, p_hdr); |
| 962 | break; |
| 963 | case OPCODE_SEQ_END: |
| 964 | vha->reset_tmplt.seq_end = 1; |
| 965 | break; |
| 966 | case OPCODE_TMPL_END: |
| 967 | qla8044_template_end(vha, p_hdr); |
| 968 | break; |
| 969 | case OPCODE_POLL_READ_LIST: |
| 970 | qla8044_poll_read_list(vha, p_hdr); |
| 971 | break; |
| 972 | default: |
| 973 | ql_log(ql_log_fatal, vha, 0xb097, |
| 974 | "%s: Unknown command ==> 0x%04x on " |
| 975 | "entry = %d\n", __func__, p_hdr->cmd, index); |
| 976 | break; |
| 977 | } |
| 978 | /* |
| 979 | *Set pointer to next entry in the sequence. |
| 980 | */ |
| 981 | p_entry += p_hdr->size; |
| 982 | } |
| 983 | vha->reset_tmplt.seq_index = index; |
| 984 | } |
| 985 | |
| 986 | static void |
| 987 | qla8044_process_init_seq(struct scsi_qla_host *vha) |
| 988 | { |
| 989 | qla8044_process_reset_template(vha, |
| 990 | vha->reset_tmplt.init_offset); |
| 991 | if (vha->reset_tmplt.seq_end != 1) |
| 992 | ql_log(ql_log_fatal, vha, 0xb098, |
| 993 | "%s: Abrupt INIT Sub-Sequence end.\n", |
| 994 | __func__); |
| 995 | } |
| 996 | |
| 997 | static void |
| 998 | qla8044_process_stop_seq(struct scsi_qla_host *vha) |
| 999 | { |
| 1000 | vha->reset_tmplt.seq_index = 0; |
| 1001 | qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset); |
| 1002 | if (vha->reset_tmplt.seq_end != 1) |
| 1003 | ql_log(ql_log_fatal, vha, 0xb099, |
| 1004 | "%s: Abrupt STOP Sub-Sequence end.\n", __func__); |
| 1005 | } |
| 1006 | |
| 1007 | static void |
| 1008 | qla8044_process_start_seq(struct scsi_qla_host *vha) |
| 1009 | { |
| 1010 | qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset); |
| 1011 | if (vha->reset_tmplt.template_end != 1) |
| 1012 | ql_log(ql_log_fatal, vha, 0xb09a, |
| 1013 | "%s: Abrupt START Sub-Sequence end.\n", |
| 1014 | __func__); |
| 1015 | } |
| 1016 | |
| 1017 | static int |
| 1018 | qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha, |
| 1019 | uint32_t flash_addr, uint8_t *p_data, int u32_word_count) |
| 1020 | { |
| 1021 | uint32_t i; |
| 1022 | uint32_t u32_word; |
| 1023 | uint32_t flash_offset; |
| 1024 | uint32_t addr = flash_addr; |
| 1025 | int ret_val = QLA_SUCCESS; |
| 1026 | |
| 1027 | flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1); |
| 1028 | |
| 1029 | if (addr & 0x3) { |
| 1030 | ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n", |
| 1031 | __func__, addr); |
| 1032 | ret_val = QLA_FUNCTION_FAILED; |
| 1033 | goto exit_lockless_read; |
| 1034 | } |
| 1035 | |
| 1036 | ret_val = qla8044_wr_reg_indirect(vha, |
| 1037 | QLA8044_FLASH_DIRECT_WINDOW, (addr)); |
| 1038 | |
| 1039 | if (ret_val != QLA_SUCCESS) { |
| 1040 | ql_log(ql_log_fatal, vha, 0xb09c, |
| 1041 | "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n", |
| 1042 | __func__, addr); |
| 1043 | goto exit_lockless_read; |
| 1044 | } |
| 1045 | |
| 1046 | /* Check if data is spread across multiple sectors */ |
| 1047 | if ((flash_offset + (u32_word_count * sizeof(uint32_t))) > |
| 1048 | (QLA8044_FLASH_SECTOR_SIZE - 1)) { |
| 1049 | /* Multi sector read */ |
| 1050 | for (i = 0; i < u32_word_count; i++) { |
| 1051 | ret_val = qla8044_rd_reg_indirect(vha, |
| 1052 | QLA8044_FLASH_DIRECT_DATA(addr), &u32_word); |
| 1053 | if (ret_val != QLA_SUCCESS) { |
| 1054 | ql_log(ql_log_fatal, vha, 0xb09d, |
| 1055 | "%s: failed to read addr 0x%x!\n", |
| 1056 | __func__, addr); |
| 1057 | goto exit_lockless_read; |
| 1058 | } |
| 1059 | *(uint32_t *)p_data = u32_word; |
| 1060 | p_data = p_data + 4; |
| 1061 | addr = addr + 4; |
| 1062 | flash_offset = flash_offset + 4; |
| 1063 | if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) { |
| 1064 | /* This write is needed once for each sector */ |
| 1065 | ret_val = qla8044_wr_reg_indirect(vha, |
| 1066 | QLA8044_FLASH_DIRECT_WINDOW, (addr)); |
| 1067 | if (ret_val != QLA_SUCCESS) { |
| 1068 | ql_log(ql_log_fatal, vha, 0xb09f, |
| 1069 | "%s: failed to write addr " |
| 1070 | "0x%x to FLASH_DIRECT_WINDOW!\n", |
| 1071 | __func__, addr); |
| 1072 | goto exit_lockless_read; |
| 1073 | } |
| 1074 | flash_offset = 0; |
| 1075 | } |
| 1076 | } |
| 1077 | } else { |
| 1078 | /* Single sector read */ |
| 1079 | for (i = 0; i < u32_word_count; i++) { |
| 1080 | ret_val = qla8044_rd_reg_indirect(vha, |
| 1081 | QLA8044_FLASH_DIRECT_DATA(addr), &u32_word); |
| 1082 | if (ret_val != QLA_SUCCESS) { |
| 1083 | ql_log(ql_log_fatal, vha, 0xb0a0, |
| 1084 | "%s: failed to read addr 0x%x!\n", |
| 1085 | __func__, addr); |
| 1086 | goto exit_lockless_read; |
| 1087 | } |
| 1088 | *(uint32_t *)p_data = u32_word; |
| 1089 | p_data = p_data + 4; |
| 1090 | addr = addr + 4; |
| 1091 | } |
| 1092 | } |
| 1093 | |
| 1094 | exit_lockless_read: |
| 1095 | return ret_val; |
| 1096 | } |
| 1097 | |
| 1098 | /* |
| 1099 | * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory |
| 1100 | * |
| 1101 | * @vha : Pointer to adapter structure |
| 1102 | * addr : Flash address to write to |
| 1103 | * data : Data to be written |
| 1104 | * count : word_count to be written |
| 1105 | * |
| 1106 | * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED |
| 1107 | */ |
| 1108 | static int |
| 1109 | qla8044_ms_mem_write_128b(struct scsi_qla_host *vha, |
| 1110 | uint64_t addr, uint32_t *data, uint32_t count) |
| 1111 | { |
| 1112 | int i, j, ret_val = QLA_SUCCESS; |
| 1113 | uint32_t agt_ctrl; |
| 1114 | unsigned long flags; |
| 1115 | struct qla_hw_data *ha = vha->hw; |
| 1116 | |
| 1117 | /* Only 128-bit aligned access */ |
| 1118 | if (addr & 0xF) { |
| 1119 | ret_val = QLA_FUNCTION_FAILED; |
| 1120 | goto exit_ms_mem_write; |
| 1121 | } |
| 1122 | write_lock_irqsave(&ha->hw_lock, flags); |
| 1123 | |
| 1124 | /* Write address */ |
| 1125 | ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0); |
| 1126 | if (ret_val == QLA_FUNCTION_FAILED) { |
| 1127 | ql_log(ql_log_fatal, vha, 0xb0a1, |
| 1128 | "%s: write to AGT_ADDR_HI failed!\n", __func__); |
| 1129 | goto exit_ms_mem_write_unlock; |
| 1130 | } |
| 1131 | |
| 1132 | for (i = 0; i < count; i++, addr += 16) { |
| 1133 | if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET, |
| 1134 | QLA8044_ADDR_QDR_NET_MAX)) || |
| 1135 | (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET, |
| 1136 | QLA8044_ADDR_DDR_NET_MAX)))) { |
| 1137 | ret_val = QLA_FUNCTION_FAILED; |
| 1138 | goto exit_ms_mem_write_unlock; |
| 1139 | } |
| 1140 | |
| 1141 | ret_val = qla8044_wr_reg_indirect(vha, |
| 1142 | MD_MIU_TEST_AGT_ADDR_LO, addr); |
| 1143 | |
| 1144 | /* Write data */ |
| 1145 | ret_val += qla8044_wr_reg_indirect(vha, |
| 1146 | MD_MIU_TEST_AGT_WRDATA_LO, *data++); |
| 1147 | ret_val += qla8044_wr_reg_indirect(vha, |
| 1148 | MD_MIU_TEST_AGT_WRDATA_HI, *data++); |
| 1149 | ret_val += qla8044_wr_reg_indirect(vha, |
| 1150 | MD_MIU_TEST_AGT_WRDATA_ULO, *data++); |
| 1151 | ret_val += qla8044_wr_reg_indirect(vha, |
| 1152 | MD_MIU_TEST_AGT_WRDATA_UHI, *data++); |
| 1153 | if (ret_val == QLA_FUNCTION_FAILED) { |
| 1154 | ql_log(ql_log_fatal, vha, 0xb0a2, |
| 1155 | "%s: write to AGT_WRDATA failed!\n", |
| 1156 | __func__); |
| 1157 | goto exit_ms_mem_write_unlock; |
| 1158 | } |
| 1159 | |
| 1160 | /* Check write status */ |
| 1161 | ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, |
| 1162 | MIU_TA_CTL_WRITE_ENABLE); |
| 1163 | ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, |
| 1164 | MIU_TA_CTL_WRITE_START); |
| 1165 | if (ret_val == QLA_FUNCTION_FAILED) { |
| 1166 | ql_log(ql_log_fatal, vha, 0xb0a3, |
| 1167 | "%s: write to AGT_CTRL failed!\n", __func__); |
| 1168 | goto exit_ms_mem_write_unlock; |
| 1169 | } |
| 1170 | |
| 1171 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1172 | ret_val = qla8044_rd_reg_indirect(vha, |
| 1173 | MD_MIU_TEST_AGT_CTRL, &agt_ctrl); |
| 1174 | if (ret_val == QLA_FUNCTION_FAILED) { |
| 1175 | ql_log(ql_log_fatal, vha, 0xb0a4, |
| 1176 | "%s: failed to read " |
| 1177 | "MD_MIU_TEST_AGT_CTRL!\n", __func__); |
| 1178 | goto exit_ms_mem_write_unlock; |
| 1179 | } |
| 1180 | if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) |
| 1181 | break; |
| 1182 | } |
| 1183 | |
| 1184 | /* Status check failed */ |
| 1185 | if (j >= MAX_CTL_CHECK) { |
| 1186 | ql_log(ql_log_fatal, vha, 0xb0a5, |
| 1187 | "%s: MS memory write failed!\n", |
| 1188 | __func__); |
| 1189 | ret_val = QLA_FUNCTION_FAILED; |
| 1190 | goto exit_ms_mem_write_unlock; |
| 1191 | } |
| 1192 | } |
| 1193 | |
| 1194 | exit_ms_mem_write_unlock: |
| 1195 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 1196 | |
| 1197 | exit_ms_mem_write: |
| 1198 | return ret_val; |
| 1199 | } |
| 1200 | |
| 1201 | static int |
| 1202 | qla8044_copy_bootloader(struct scsi_qla_host *vha) |
| 1203 | { |
| 1204 | uint8_t *p_cache; |
| 1205 | uint32_t src, count, size; |
| 1206 | uint64_t dest; |
| 1207 | int ret_val = QLA_SUCCESS; |
| 1208 | struct qla_hw_data *ha = vha->hw; |
| 1209 | |
| 1210 | src = QLA8044_BOOTLOADER_FLASH_ADDR; |
| 1211 | dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR); |
| 1212 | size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE); |
| 1213 | |
| 1214 | /* 128 bit alignment check */ |
| 1215 | if (size & 0xF) |
| 1216 | size = (size + 16) & ~0xF; |
| 1217 | |
| 1218 | /* 16 byte count */ |
| 1219 | count = size/16; |
| 1220 | |
| 1221 | p_cache = vmalloc(size); |
| 1222 | if (p_cache == NULL) { |
| 1223 | ql_log(ql_log_fatal, vha, 0xb0a6, |
| 1224 | "%s: Failed to allocate memory for " |
| 1225 | "boot loader cache\n", __func__); |
| 1226 | ret_val = QLA_FUNCTION_FAILED; |
| 1227 | goto exit_copy_bootloader; |
| 1228 | } |
| 1229 | |
| 1230 | ret_val = qla8044_lockless_flash_read_u32(vha, src, |
| 1231 | p_cache, size/sizeof(uint32_t)); |
| 1232 | if (ret_val == QLA_FUNCTION_FAILED) { |
| 1233 | ql_log(ql_log_fatal, vha, 0xb0a7, |
| 1234 | "%s: Error reading F/W from flash!!!\n", __func__); |
| 1235 | goto exit_copy_error; |
| 1236 | } |
| 1237 | ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n", |
| 1238 | __func__); |
| 1239 | |
| 1240 | /* 128 bit/16 byte write to MS memory */ |
| 1241 | ret_val = qla8044_ms_mem_write_128b(vha, dest, |
| 1242 | (uint32_t *)p_cache, count); |
| 1243 | if (ret_val == QLA_FUNCTION_FAILED) { |
| 1244 | ql_log(ql_log_fatal, vha, 0xb0a9, |
| 1245 | "%s: Error writing F/W to MS !!!\n", __func__); |
| 1246 | goto exit_copy_error; |
| 1247 | } |
| 1248 | ql_dbg(ql_dbg_p3p, vha, 0xb0aa, |
| 1249 | "%s: Wrote F/W (size %d) to MS !!!\n", |
| 1250 | __func__, size); |
| 1251 | |
| 1252 | exit_copy_error: |
| 1253 | vfree(p_cache); |
| 1254 | |
| 1255 | exit_copy_bootloader: |
| 1256 | return ret_val; |
| 1257 | } |
| 1258 | |
| 1259 | static int |
| 1260 | qla8044_restart(struct scsi_qla_host *vha) |
| 1261 | { |
| 1262 | int ret_val = QLA_SUCCESS; |
| 1263 | struct qla_hw_data *ha = vha->hw; |
| 1264 | |
| 1265 | qla8044_process_stop_seq(vha); |
| 1266 | |
| 1267 | /* Collect minidump */ |
| 1268 | if (ql2xmdenable) |
| 1269 | qla8044_get_minidump(vha); |
| 1270 | else |
| 1271 | ql_log(ql_log_fatal, vha, 0xb14c, |
| 1272 | "Minidump disabled.\n"); |
| 1273 | |
| 1274 | qla8044_process_init_seq(vha); |
| 1275 | |
| 1276 | if (qla8044_copy_bootloader(vha)) { |
| 1277 | ql_log(ql_log_fatal, vha, 0xb0ab, |
| 1278 | "%s: Copy bootloader, firmware restart failed!\n", |
| 1279 | __func__); |
| 1280 | ret_val = QLA_FUNCTION_FAILED; |
| 1281 | goto exit_restart; |
| 1282 | } |
| 1283 | |
| 1284 | /* |
| 1285 | * Loads F/W from flash |
| 1286 | */ |
| 1287 | qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH); |
| 1288 | |
| 1289 | qla8044_process_start_seq(vha); |
| 1290 | |
| 1291 | exit_restart: |
| 1292 | return ret_val; |
| 1293 | } |
| 1294 | |
| 1295 | /* |
| 1296 | * qla8044_check_cmd_peg_status - Check peg status to see if Peg is |
| 1297 | * initialized. |
| 1298 | * |
| 1299 | * @ha : Pointer to adapter structure |
| 1300 | * |
| 1301 | * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED |
| 1302 | */ |
| 1303 | static int |
| 1304 | qla8044_check_cmd_peg_status(struct scsi_qla_host *vha) |
| 1305 | { |
| 1306 | uint32_t val, ret_val = QLA_FUNCTION_FAILED; |
| 1307 | int retries = CRB_CMDPEG_CHECK_RETRY_COUNT; |
| 1308 | struct qla_hw_data *ha = vha->hw; |
| 1309 | |
| 1310 | do { |
| 1311 | val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE); |
| 1312 | if (val == PHAN_INITIALIZE_COMPLETE) { |
| 1313 | ql_dbg(ql_dbg_p3p, vha, 0xb0ac, |
| 1314 | "%s: Command Peg initialization " |
| 1315 | "complete! state=0x%x\n", __func__, val); |
| 1316 | ret_val = QLA_SUCCESS; |
| 1317 | break; |
| 1318 | } |
| 1319 | msleep(CRB_CMDPEG_CHECK_DELAY); |
| 1320 | } while (--retries); |
| 1321 | |
| 1322 | return ret_val; |
| 1323 | } |
| 1324 | |
| 1325 | static int |
| 1326 | qla8044_start_firmware(struct scsi_qla_host *vha) |
| 1327 | { |
| 1328 | int ret_val = QLA_SUCCESS; |
| 1329 | |
| 1330 | if (qla8044_restart(vha)) { |
| 1331 | ql_log(ql_log_fatal, vha, 0xb0ad, |
| 1332 | "%s: Restart Error!!!, Need Reset!!!\n", |
| 1333 | __func__); |
| 1334 | ret_val = QLA_FUNCTION_FAILED; |
| 1335 | goto exit_start_fw; |
| 1336 | } else |
| 1337 | ql_dbg(ql_dbg_p3p, vha, 0xb0af, |
| 1338 | "%s: Restart done!\n", __func__); |
| 1339 | |
| 1340 | ret_val = qla8044_check_cmd_peg_status(vha); |
| 1341 | if (ret_val) { |
| 1342 | ql_log(ql_log_fatal, vha, 0xb0b0, |
| 1343 | "%s: Peg not initialized!\n", __func__); |
| 1344 | ret_val = QLA_FUNCTION_FAILED; |
| 1345 | } |
| 1346 | |
| 1347 | exit_start_fw: |
| 1348 | return ret_val; |
| 1349 | } |
| 1350 | |
| 1351 | void |
Saurav Kashyap | c41afc9 | 2013-11-07 02:54:56 -0500 | [diff] [blame] | 1352 | qla8044_clear_drv_active(struct qla_hw_data *ha) |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1353 | { |
| 1354 | uint32_t drv_active; |
Saurav Kashyap | c41afc9 | 2013-11-07 02:54:56 -0500 | [diff] [blame] | 1355 | struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev); |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1356 | |
| 1357 | drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1358 | drv_active &= ~(1 << (ha->portnum)); |
| 1359 | |
| 1360 | ql_log(ql_log_info, vha, 0xb0b1, |
| 1361 | "%s(%ld): drv_active: 0x%08x\n", |
| 1362 | __func__, vha->host_no, drv_active); |
| 1363 | |
| 1364 | qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active); |
| 1365 | } |
| 1366 | |
| 1367 | /* |
| 1368 | * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw |
| 1369 | * @ha: pointer to adapter structure |
| 1370 | * |
| 1371 | * Note: IDC lock must be held upon entry |
| 1372 | **/ |
| 1373 | static int |
| 1374 | qla8044_device_bootstrap(struct scsi_qla_host *vha) |
| 1375 | { |
| 1376 | int rval = QLA_FUNCTION_FAILED; |
| 1377 | int i; |
| 1378 | uint32_t old_count = 0, count = 0; |
| 1379 | int need_reset = 0; |
| 1380 | uint32_t idc_ctrl; |
| 1381 | struct qla_hw_data *ha = vha->hw; |
| 1382 | |
| 1383 | need_reset = qla8044_need_reset(vha); |
| 1384 | |
| 1385 | if (!need_reset) { |
| 1386 | old_count = qla8044_rd_direct(vha, |
| 1387 | QLA8044_PEG_ALIVE_COUNTER_INDEX); |
| 1388 | |
| 1389 | for (i = 0; i < 10; i++) { |
| 1390 | msleep(200); |
| 1391 | |
| 1392 | count = qla8044_rd_direct(vha, |
| 1393 | QLA8044_PEG_ALIVE_COUNTER_INDEX); |
| 1394 | if (count != old_count) { |
| 1395 | rval = QLA_SUCCESS; |
| 1396 | goto dev_ready; |
| 1397 | } |
| 1398 | } |
| 1399 | qla8044_flash_lock_recovery(vha); |
| 1400 | } else { |
| 1401 | /* We are trying to perform a recovery here. */ |
| 1402 | if (ha->flags.isp82xx_fw_hung) |
| 1403 | qla8044_flash_lock_recovery(vha); |
| 1404 | } |
| 1405 | |
| 1406 | /* set to DEV_INITIALIZING */ |
| 1407 | ql_log(ql_log_info, vha, 0xb0b2, |
| 1408 | "%s: HW State: INITIALIZING\n", __func__); |
| 1409 | qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, |
| 1410 | QLA8XXX_DEV_INITIALIZING); |
| 1411 | |
| 1412 | qla8044_idc_unlock(ha); |
| 1413 | rval = qla8044_start_firmware(vha); |
| 1414 | qla8044_idc_lock(ha); |
| 1415 | |
| 1416 | if (rval != QLA_SUCCESS) { |
| 1417 | ql_log(ql_log_info, vha, 0xb0b3, |
| 1418 | "%s: HW State: FAILED\n", __func__); |
Saurav Kashyap | c41afc9 | 2013-11-07 02:54:56 -0500 | [diff] [blame] | 1419 | qla8044_clear_drv_active(ha); |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1420 | qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, |
| 1421 | QLA8XXX_DEV_FAILED); |
| 1422 | return rval; |
| 1423 | } |
| 1424 | |
| 1425 | /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after |
| 1426 | * device goes to INIT state. */ |
| 1427 | idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); |
| 1428 | if (idc_ctrl & GRACEFUL_RESET_BIT1) { |
| 1429 | qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, |
| 1430 | (idc_ctrl & ~GRACEFUL_RESET_BIT1)); |
| 1431 | ha->fw_dumped = 0; |
| 1432 | } |
| 1433 | |
| 1434 | dev_ready: |
| 1435 | ql_log(ql_log_info, vha, 0xb0b4, |
| 1436 | "%s: HW State: READY\n", __func__); |
| 1437 | qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY); |
| 1438 | |
| 1439 | return rval; |
| 1440 | } |
| 1441 | |
| 1442 | /*-------------------------Reset Sequence Functions-----------------------*/ |
| 1443 | static void |
| 1444 | qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha) |
| 1445 | { |
| 1446 | u8 *phdr; |
| 1447 | |
| 1448 | if (!vha->reset_tmplt.buff) { |
| 1449 | ql_log(ql_log_fatal, vha, 0xb0b5, |
| 1450 | "%s: Error Invalid reset_seq_template\n", __func__); |
| 1451 | return; |
| 1452 | } |
| 1453 | |
| 1454 | phdr = vha->reset_tmplt.buff; |
| 1455 | ql_dbg(ql_dbg_p3p, vha, 0xb0b6, |
| 1456 | "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X" |
| 1457 | "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n" |
| 1458 | "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n", |
| 1459 | *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4), |
| 1460 | *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8), |
| 1461 | *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12), |
| 1462 | *(phdr+13), *(phdr+14), *(phdr+15)); |
| 1463 | } |
| 1464 | |
| 1465 | /* |
| 1466 | * qla8044_reset_seq_checksum_test - Validate Reset Sequence template. |
| 1467 | * |
| 1468 | * @ha : Pointer to adapter structure |
| 1469 | * |
| 1470 | * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED |
| 1471 | */ |
| 1472 | static int |
| 1473 | qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha) |
| 1474 | { |
| 1475 | uint32_t sum = 0; |
| 1476 | uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff; |
| 1477 | int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t); |
| 1478 | |
| 1479 | while (u16_count-- > 0) |
| 1480 | sum += *buff++; |
| 1481 | |
| 1482 | while (sum >> 16) |
| 1483 | sum = (sum & 0xFFFF) + (sum >> 16); |
| 1484 | |
| 1485 | /* checksum of 0 indicates a valid template */ |
| 1486 | if (~sum) { |
| 1487 | return QLA_SUCCESS; |
| 1488 | } else { |
| 1489 | ql_log(ql_log_fatal, vha, 0xb0b7, |
| 1490 | "%s: Reset seq checksum failed\n", __func__); |
| 1491 | return QLA_FUNCTION_FAILED; |
| 1492 | } |
| 1493 | } |
| 1494 | |
| 1495 | /* |
| 1496 | * qla8044_read_reset_template - Read Reset Template from Flash, validate |
| 1497 | * the template and store offsets of stop/start/init offsets in ha->reset_tmplt. |
| 1498 | * |
| 1499 | * @ha : Pointer to adapter structure |
| 1500 | */ |
| 1501 | void |
| 1502 | qla8044_read_reset_template(struct scsi_qla_host *vha) |
| 1503 | { |
| 1504 | uint8_t *p_buff; |
| 1505 | uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size; |
| 1506 | |
| 1507 | vha->reset_tmplt.seq_error = 0; |
| 1508 | vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE); |
| 1509 | if (vha->reset_tmplt.buff == NULL) { |
| 1510 | ql_log(ql_log_fatal, vha, 0xb0b8, |
| 1511 | "%s: Failed to allocate reset template resources\n", |
| 1512 | __func__); |
| 1513 | goto exit_read_reset_template; |
| 1514 | } |
| 1515 | |
| 1516 | p_buff = vha->reset_tmplt.buff; |
| 1517 | addr = QLA8044_RESET_TEMPLATE_ADDR; |
| 1518 | |
| 1519 | tmplt_hdr_def_size = |
| 1520 | sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t); |
| 1521 | |
| 1522 | ql_dbg(ql_dbg_p3p, vha, 0xb0b9, |
| 1523 | "%s: Read template hdr size %d from Flash\n", |
| 1524 | __func__, tmplt_hdr_def_size); |
| 1525 | |
| 1526 | /* Copy template header from flash */ |
| 1527 | if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) { |
| 1528 | ql_log(ql_log_fatal, vha, 0xb0ba, |
| 1529 | "%s: Failed to read reset template\n", __func__); |
| 1530 | goto exit_read_template_error; |
| 1531 | } |
| 1532 | |
| 1533 | vha->reset_tmplt.hdr = |
| 1534 | (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff; |
| 1535 | |
| 1536 | /* Validate the template header size and signature */ |
| 1537 | tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); |
| 1538 | if ((tmplt_hdr_size != tmplt_hdr_def_size) || |
| 1539 | (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) { |
| 1540 | ql_log(ql_log_fatal, vha, 0xb0bb, |
| 1541 | "%s: Template Header size invalid %d " |
| 1542 | "tmplt_hdr_def_size %d!!!\n", __func__, |
| 1543 | tmplt_hdr_size, tmplt_hdr_def_size); |
| 1544 | goto exit_read_template_error; |
| 1545 | } |
| 1546 | |
| 1547 | addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size; |
| 1548 | p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size; |
| 1549 | tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size - |
| 1550 | vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t); |
| 1551 | |
| 1552 | ql_dbg(ql_dbg_p3p, vha, 0xb0bc, |
| 1553 | "%s: Read rest of the template size %d\n", |
| 1554 | __func__, vha->reset_tmplt.hdr->size); |
| 1555 | |
| 1556 | /* Copy rest of the template */ |
| 1557 | if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) { |
| 1558 | ql_log(ql_log_fatal, vha, 0xb0bd, |
| 1559 | "%s: Failed to read reset tempelate\n", __func__); |
| 1560 | goto exit_read_template_error; |
| 1561 | } |
| 1562 | |
| 1563 | /* Integrity check */ |
| 1564 | if (qla8044_reset_seq_checksum_test(vha)) { |
| 1565 | ql_log(ql_log_fatal, vha, 0xb0be, |
| 1566 | "%s: Reset Seq checksum failed!\n", __func__); |
| 1567 | goto exit_read_template_error; |
| 1568 | } |
| 1569 | |
| 1570 | ql_dbg(ql_dbg_p3p, vha, 0xb0bf, |
| 1571 | "%s: Reset Seq checksum passed! Get stop, " |
| 1572 | "start and init seq offsets\n", __func__); |
| 1573 | |
| 1574 | /* Get STOP, START, INIT sequence offsets */ |
| 1575 | vha->reset_tmplt.init_offset = vha->reset_tmplt.buff + |
| 1576 | vha->reset_tmplt.hdr->init_seq_offset; |
| 1577 | |
| 1578 | vha->reset_tmplt.start_offset = vha->reset_tmplt.buff + |
| 1579 | vha->reset_tmplt.hdr->start_seq_offset; |
| 1580 | |
| 1581 | vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff + |
| 1582 | vha->reset_tmplt.hdr->hdr_size; |
| 1583 | |
| 1584 | qla8044_dump_reset_seq_hdr(vha); |
| 1585 | |
| 1586 | goto exit_read_reset_template; |
| 1587 | |
| 1588 | exit_read_template_error: |
| 1589 | vfree(vha->reset_tmplt.buff); |
| 1590 | |
| 1591 | exit_read_reset_template: |
| 1592 | return; |
| 1593 | } |
| 1594 | |
| 1595 | void |
| 1596 | qla8044_set_idc_dontreset(struct scsi_qla_host *vha) |
| 1597 | { |
| 1598 | uint32_t idc_ctrl; |
| 1599 | struct qla_hw_data *ha = vha->hw; |
| 1600 | |
| 1601 | idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); |
| 1602 | idc_ctrl |= DONTRESET_BIT0; |
| 1603 | ql_dbg(ql_dbg_p3p, vha, 0xb0c0, |
| 1604 | "%s: idc_ctrl = %d\n", __func__, idc_ctrl); |
| 1605 | qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl); |
| 1606 | } |
| 1607 | |
| 1608 | inline void |
| 1609 | qla8044_set_rst_ready(struct scsi_qla_host *vha) |
| 1610 | { |
| 1611 | uint32_t drv_state; |
| 1612 | struct qla_hw_data *ha = vha->hw; |
| 1613 | |
| 1614 | drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); |
| 1615 | |
| 1616 | /* For ISP8044, drv_active register has 1 bit per function, |
| 1617 | * shift 1 by func_num to set a bit for the function.*/ |
| 1618 | drv_state |= (1 << ha->portnum); |
| 1619 | |
| 1620 | ql_log(ql_log_info, vha, 0xb0c1, |
| 1621 | "%s(%ld): drv_state: 0x%08x\n", |
| 1622 | __func__, vha->host_no, drv_state); |
| 1623 | qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state); |
| 1624 | } |
| 1625 | |
| 1626 | /** |
| 1627 | * qla8044_need_reset_handler - Code to start reset sequence |
| 1628 | * @ha: pointer to adapter structure |
| 1629 | * |
| 1630 | * Note: IDC lock must be held upon entry |
| 1631 | **/ |
| 1632 | static void |
| 1633 | qla8044_need_reset_handler(struct scsi_qla_host *vha) |
| 1634 | { |
| 1635 | uint32_t dev_state = 0, drv_state, drv_active; |
| 1636 | unsigned long reset_timeout, dev_init_timeout; |
| 1637 | struct qla_hw_data *ha = vha->hw; |
| 1638 | |
| 1639 | ql_log(ql_log_fatal, vha, 0xb0c2, |
| 1640 | "%s: Performing ISP error recovery\n", __func__); |
| 1641 | |
| 1642 | if (vha->flags.online) { |
| 1643 | qla8044_idc_unlock(ha); |
| 1644 | qla2x00_abort_isp_cleanup(vha); |
| 1645 | ha->isp_ops->get_flash_version(vha, vha->req->ring); |
| 1646 | ha->isp_ops->nvram_config(vha); |
| 1647 | qla8044_idc_lock(ha); |
| 1648 | } |
| 1649 | |
Saurav Kashyap | 8f47611 | 2013-10-30 03:38:13 -0400 | [diff] [blame] | 1650 | drv_state = qla8044_rd_direct(vha, |
| 1651 | QLA8044_CRB_DRV_STATE_INDEX); |
| 1652 | drv_active = qla8044_rd_direct(vha, |
| 1653 | QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1654 | |
| 1655 | ql_log(ql_log_info, vha, 0xb0c5, |
| 1656 | "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", |
| 1657 | __func__, vha->host_no, drv_state, drv_active); |
| 1658 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1659 | if (!ha->flags.nic_core_reset_owner) { |
| 1660 | ql_dbg(ql_dbg_p3p, vha, 0xb0c3, |
| 1661 | "%s(%ld): reset acknowledged\n", |
| 1662 | __func__, vha->host_no); |
| 1663 | qla8044_set_rst_ready(vha); |
| 1664 | |
| 1665 | /* Non-reset owners ACK Reset and wait for device INIT state |
| 1666 | * as part of Reset Recovery by Reset Owner |
| 1667 | */ |
| 1668 | dev_init_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); |
| 1669 | |
| 1670 | do { |
| 1671 | if (time_after_eq(jiffies, dev_init_timeout)) { |
| 1672 | ql_log(ql_log_info, vha, 0xb0c4, |
Atul Deshmukh | 145083e | 2014-02-26 04:14:59 -0500 | [diff] [blame] | 1673 | "%s: Non Reset owner: Reset Ack Timeout!\n", |
| 1674 | __func__); |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1675 | break; |
| 1676 | } |
| 1677 | |
| 1678 | qla8044_idc_unlock(ha); |
| 1679 | msleep(1000); |
| 1680 | qla8044_idc_lock(ha); |
| 1681 | |
| 1682 | dev_state = qla8044_rd_direct(vha, |
| 1683 | QLA8044_CRB_DEV_STATE_INDEX); |
Saurav Kashyap | 8f47611 | 2013-10-30 03:38:13 -0400 | [diff] [blame] | 1684 | } while (((drv_state & drv_active) != drv_active) && |
| 1685 | (dev_state == QLA8XXX_DEV_NEED_RESET)); |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1686 | } else { |
| 1687 | qla8044_set_rst_ready(vha); |
| 1688 | |
| 1689 | /* wait for 10 seconds for reset ack from all functions */ |
| 1690 | reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); |
| 1691 | |
Saurav Kashyap | 8f47611 | 2013-10-30 03:38:13 -0400 | [diff] [blame] | 1692 | while ((drv_state & drv_active) != drv_active) { |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1693 | if (time_after_eq(jiffies, reset_timeout)) { |
| 1694 | ql_log(ql_log_info, vha, 0xb0c6, |
| 1695 | "%s: RESET TIMEOUT!" |
| 1696 | "drv_state: 0x%08x, drv_active: 0x%08x\n", |
| 1697 | QLA2XXX_DRIVER_NAME, drv_state, drv_active); |
| 1698 | break; |
| 1699 | } |
| 1700 | |
| 1701 | qla8044_idc_unlock(ha); |
| 1702 | msleep(1000); |
| 1703 | qla8044_idc_lock(ha); |
| 1704 | |
| 1705 | drv_state = qla8044_rd_direct(vha, |
| 1706 | QLA8044_CRB_DRV_STATE_INDEX); |
| 1707 | drv_active = qla8044_rd_direct(vha, |
| 1708 | QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1709 | } |
| 1710 | |
| 1711 | if (drv_state != drv_active) { |
| 1712 | ql_log(ql_log_info, vha, 0xb0c7, |
| 1713 | "%s(%ld): Reset_owner turning off drv_active " |
| 1714 | "of non-acking function 0x%x\n", __func__, |
| 1715 | vha->host_no, (drv_active ^ drv_state)); |
| 1716 | drv_active = drv_active & drv_state; |
| 1717 | qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, |
| 1718 | drv_active); |
| 1719 | } |
| 1720 | |
| 1721 | /* |
| 1722 | * Clear RESET OWNER, will be set at next reset |
| 1723 | * by next RST_OWNER |
| 1724 | */ |
| 1725 | ha->flags.nic_core_reset_owner = 0; |
| 1726 | |
| 1727 | /* Start Reset Recovery */ |
| 1728 | qla8044_device_bootstrap(vha); |
| 1729 | } |
| 1730 | } |
| 1731 | |
| 1732 | static void |
| 1733 | qla8044_set_drv_active(struct scsi_qla_host *vha) |
| 1734 | { |
| 1735 | uint32_t drv_active; |
| 1736 | struct qla_hw_data *ha = vha->hw; |
| 1737 | |
| 1738 | drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1739 | |
| 1740 | /* For ISP8044, drv_active register has 1 bit per function, |
| 1741 | * shift 1 by func_num to set a bit for the function.*/ |
| 1742 | drv_active |= (1 << ha->portnum); |
| 1743 | |
| 1744 | ql_log(ql_log_info, vha, 0xb0c8, |
| 1745 | "%s(%ld): drv_active: 0x%08x\n", |
| 1746 | __func__, vha->host_no, drv_active); |
| 1747 | qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active); |
| 1748 | } |
| 1749 | |
Giridhar Malavali | 4fa0c66 | 2014-04-11 16:54:11 -0400 | [diff] [blame] | 1750 | static int |
| 1751 | qla8044_check_drv_active(struct scsi_qla_host *vha) |
| 1752 | { |
| 1753 | uint32_t drv_active; |
| 1754 | struct qla_hw_data *ha = vha->hw; |
| 1755 | |
| 1756 | drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1757 | if (drv_active & (1 << ha->portnum)) |
| 1758 | return QLA_SUCCESS; |
| 1759 | else |
| 1760 | return QLA_TEST_FAILED; |
| 1761 | } |
| 1762 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1763 | static void |
| 1764 | qla8044_clear_idc_dontreset(struct scsi_qla_host *vha) |
| 1765 | { |
| 1766 | uint32_t idc_ctrl; |
| 1767 | struct qla_hw_data *ha = vha->hw; |
| 1768 | |
| 1769 | idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); |
| 1770 | idc_ctrl &= ~DONTRESET_BIT0; |
| 1771 | ql_log(ql_log_info, vha, 0xb0c9, |
| 1772 | "%s: idc_ctrl = %d\n", __func__, |
| 1773 | idc_ctrl); |
| 1774 | qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl); |
| 1775 | } |
| 1776 | |
| 1777 | static int |
| 1778 | qla8044_set_idc_ver(struct scsi_qla_host *vha) |
| 1779 | { |
| 1780 | int idc_ver; |
| 1781 | uint32_t drv_active; |
| 1782 | int rval = QLA_SUCCESS; |
| 1783 | struct qla_hw_data *ha = vha->hw; |
| 1784 | |
| 1785 | drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1786 | if (drv_active == (1 << ha->portnum)) { |
| 1787 | idc_ver = qla8044_rd_direct(vha, |
| 1788 | QLA8044_CRB_DRV_IDC_VERSION_INDEX); |
| 1789 | idc_ver &= (~0xFF); |
| 1790 | idc_ver |= QLA8044_IDC_VER_MAJ_VALUE; |
| 1791 | qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX, |
| 1792 | idc_ver); |
| 1793 | ql_log(ql_log_info, vha, 0xb0ca, |
| 1794 | "%s: IDC version updated to %d\n", |
| 1795 | __func__, idc_ver); |
| 1796 | } else { |
| 1797 | idc_ver = qla8044_rd_direct(vha, |
| 1798 | QLA8044_CRB_DRV_IDC_VERSION_INDEX); |
| 1799 | idc_ver &= 0xFF; |
| 1800 | if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) { |
| 1801 | ql_log(ql_log_info, vha, 0xb0cb, |
| 1802 | "%s: qla4xxx driver IDC version %d " |
| 1803 | "is not compatible with IDC version %d " |
| 1804 | "of other drivers!\n", |
| 1805 | __func__, QLA8044_IDC_VER_MAJ_VALUE, |
| 1806 | idc_ver); |
| 1807 | rval = QLA_FUNCTION_FAILED; |
| 1808 | goto exit_set_idc_ver; |
| 1809 | } |
| 1810 | } |
| 1811 | |
| 1812 | /* Update IDC_MINOR_VERSION */ |
| 1813 | idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR); |
| 1814 | idc_ver &= ~(0x03 << (ha->portnum * 2)); |
| 1815 | idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2)); |
| 1816 | qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver); |
| 1817 | |
| 1818 | exit_set_idc_ver: |
| 1819 | return rval; |
| 1820 | } |
| 1821 | |
| 1822 | static int |
| 1823 | qla8044_update_idc_reg(struct scsi_qla_host *vha) |
| 1824 | { |
| 1825 | uint32_t drv_active; |
| 1826 | int rval = QLA_SUCCESS; |
| 1827 | struct qla_hw_data *ha = vha->hw; |
| 1828 | |
| 1829 | if (vha->flags.init_done) |
| 1830 | goto exit_update_idc_reg; |
| 1831 | |
| 1832 | qla8044_idc_lock(ha); |
| 1833 | qla8044_set_drv_active(vha); |
| 1834 | |
| 1835 | drv_active = qla8044_rd_direct(vha, |
| 1836 | QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1837 | |
| 1838 | /* If we are the first driver to load and |
| 1839 | * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */ |
| 1840 | if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba) |
| 1841 | qla8044_clear_idc_dontreset(vha); |
| 1842 | |
| 1843 | rval = qla8044_set_idc_ver(vha); |
| 1844 | if (rval == QLA_FUNCTION_FAILED) |
Saurav Kashyap | c41afc9 | 2013-11-07 02:54:56 -0500 | [diff] [blame] | 1845 | qla8044_clear_drv_active(ha); |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1846 | qla8044_idc_unlock(ha); |
| 1847 | |
| 1848 | exit_update_idc_reg: |
| 1849 | return rval; |
| 1850 | } |
| 1851 | |
| 1852 | /** |
| 1853 | * qla8044_need_qsnt_handler - Code to start qsnt |
| 1854 | * @ha: pointer to adapter structure |
| 1855 | **/ |
| 1856 | static void |
| 1857 | qla8044_need_qsnt_handler(struct scsi_qla_host *vha) |
| 1858 | { |
| 1859 | unsigned long qsnt_timeout; |
| 1860 | uint32_t drv_state, drv_active, dev_state; |
| 1861 | struct qla_hw_data *ha = vha->hw; |
| 1862 | |
| 1863 | if (vha->flags.online) |
| 1864 | qla2x00_quiesce_io(vha); |
| 1865 | else |
| 1866 | return; |
| 1867 | |
| 1868 | qla8044_set_qsnt_ready(vha); |
| 1869 | |
| 1870 | /* Wait for 30 secs for all functions to ack qsnt mode */ |
| 1871 | qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ); |
| 1872 | drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); |
| 1873 | drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1874 | |
| 1875 | /* Shift drv_active by 1 to match drv_state. As quiescent ready bit |
| 1876 | position is at bit 1 and drv active is at bit 0 */ |
| 1877 | drv_active = drv_active << 1; |
| 1878 | |
| 1879 | while (drv_state != drv_active) { |
| 1880 | if (time_after_eq(jiffies, qsnt_timeout)) { |
| 1881 | /* Other functions did not ack, changing state to |
| 1882 | * DEV_READY |
| 1883 | */ |
| 1884 | clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); |
| 1885 | qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, |
| 1886 | QLA8XXX_DEV_READY); |
| 1887 | qla8044_clear_qsnt_ready(vha); |
| 1888 | ql_log(ql_log_info, vha, 0xb0cc, |
| 1889 | "Timeout waiting for quiescent ack!!!\n"); |
| 1890 | return; |
| 1891 | } |
| 1892 | qla8044_idc_unlock(ha); |
| 1893 | msleep(1000); |
| 1894 | qla8044_idc_lock(ha); |
| 1895 | |
| 1896 | drv_state = qla8044_rd_direct(vha, |
| 1897 | QLA8044_CRB_DRV_STATE_INDEX); |
| 1898 | drv_active = qla8044_rd_direct(vha, |
| 1899 | QLA8044_CRB_DRV_ACTIVE_INDEX); |
| 1900 | drv_active = drv_active << 1; |
| 1901 | } |
| 1902 | |
| 1903 | /* All functions have Acked. Set quiescent state */ |
| 1904 | dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); |
| 1905 | |
| 1906 | if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { |
| 1907 | qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, |
| 1908 | QLA8XXX_DEV_QUIESCENT); |
| 1909 | ql_log(ql_log_info, vha, 0xb0cd, |
| 1910 | "%s: HW State: QUIESCENT\n", __func__); |
| 1911 | } |
| 1912 | } |
| 1913 | |
| 1914 | /* |
| 1915 | * qla8044_device_state_handler - Adapter state machine |
| 1916 | * @ha: pointer to host adapter structure. |
| 1917 | * |
| 1918 | * Note: IDC lock must be UNLOCKED upon entry |
| 1919 | **/ |
| 1920 | int |
| 1921 | qla8044_device_state_handler(struct scsi_qla_host *vha) |
| 1922 | { |
| 1923 | uint32_t dev_state; |
| 1924 | int rval = QLA_SUCCESS; |
| 1925 | unsigned long dev_init_timeout; |
| 1926 | struct qla_hw_data *ha = vha->hw; |
| 1927 | |
| 1928 | rval = qla8044_update_idc_reg(vha); |
| 1929 | if (rval == QLA_FUNCTION_FAILED) |
| 1930 | goto exit_error; |
| 1931 | |
| 1932 | dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); |
| 1933 | ql_dbg(ql_dbg_p3p, vha, 0xb0ce, |
| 1934 | "Device state is 0x%x = %s\n", |
| 1935 | dev_state, dev_state < MAX_STATES ? |
| 1936 | qdev_state(dev_state) : "Unknown"); |
| 1937 | |
| 1938 | /* wait for 30 seconds for device to go ready */ |
| 1939 | dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); |
| 1940 | |
| 1941 | qla8044_idc_lock(ha); |
| 1942 | |
| 1943 | while (1) { |
| 1944 | if (time_after_eq(jiffies, dev_init_timeout)) { |
Giridhar Malavali | 4fa0c66 | 2014-04-11 16:54:11 -0400 | [diff] [blame] | 1945 | if (qla8044_check_drv_active(vha) == QLA_SUCCESS) { |
| 1946 | ql_log(ql_log_warn, vha, 0xb0cf, |
| 1947 | "%s: Device Init Failed 0x%x = %s\n", |
| 1948 | QLA2XXX_DRIVER_NAME, dev_state, |
| 1949 | dev_state < MAX_STATES ? |
| 1950 | qdev_state(dev_state) : "Unknown"); |
| 1951 | qla8044_wr_direct(vha, |
| 1952 | QLA8044_CRB_DEV_STATE_INDEX, |
| 1953 | QLA8XXX_DEV_FAILED); |
| 1954 | } |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1955 | } |
| 1956 | |
| 1957 | dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); |
| 1958 | ql_log(ql_log_info, vha, 0xb0d0, |
| 1959 | "Device state is 0x%x = %s\n", |
| 1960 | dev_state, dev_state < MAX_STATES ? |
| 1961 | qdev_state(dev_state) : "Unknown"); |
| 1962 | |
| 1963 | /* NOTE: Make sure idc unlocked upon exit of switch statement */ |
| 1964 | switch (dev_state) { |
| 1965 | case QLA8XXX_DEV_READY: |
| 1966 | ha->flags.nic_core_reset_owner = 0; |
| 1967 | goto exit; |
| 1968 | case QLA8XXX_DEV_COLD: |
| 1969 | rval = qla8044_device_bootstrap(vha); |
Sawan Chandak | 3746078 | 2013-10-30 03:38:26 -0400 | [diff] [blame] | 1970 | break; |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1971 | case QLA8XXX_DEV_INITIALIZING: |
| 1972 | qla8044_idc_unlock(ha); |
| 1973 | msleep(1000); |
| 1974 | qla8044_idc_lock(ha); |
| 1975 | break; |
| 1976 | case QLA8XXX_DEV_NEED_RESET: |
| 1977 | /* For ISP8044, if NEED_RESET is set by any driver, |
| 1978 | * it should be honored, irrespective of IDC_CTRL |
| 1979 | * DONTRESET_BIT0 */ |
| 1980 | qla8044_need_reset_handler(vha); |
| 1981 | break; |
| 1982 | case QLA8XXX_DEV_NEED_QUIESCENT: |
| 1983 | /* idc locked/unlocked in handler */ |
| 1984 | qla8044_need_qsnt_handler(vha); |
| 1985 | |
| 1986 | /* Reset the init timeout after qsnt handler */ |
| 1987 | dev_init_timeout = jiffies + |
| 1988 | (ha->fcoe_reset_timeout * HZ); |
| 1989 | break; |
| 1990 | case QLA8XXX_DEV_QUIESCENT: |
| 1991 | ql_log(ql_log_info, vha, 0xb0d1, |
| 1992 | "HW State: QUIESCENT\n"); |
| 1993 | |
| 1994 | qla8044_idc_unlock(ha); |
| 1995 | msleep(1000); |
| 1996 | qla8044_idc_lock(ha); |
| 1997 | |
| 1998 | /* Reset the init timeout after qsnt handler */ |
| 1999 | dev_init_timeout = jiffies + |
| 2000 | (ha->fcoe_reset_timeout * HZ); |
| 2001 | break; |
| 2002 | case QLA8XXX_DEV_FAILED: |
| 2003 | ha->flags.nic_core_reset_owner = 0; |
| 2004 | qla8044_idc_unlock(ha); |
| 2005 | qla8xxx_dev_failed_handler(vha); |
| 2006 | rval = QLA_FUNCTION_FAILED; |
| 2007 | qla8044_idc_lock(ha); |
| 2008 | goto exit; |
| 2009 | default: |
| 2010 | qla8044_idc_unlock(ha); |
| 2011 | qla8xxx_dev_failed_handler(vha); |
| 2012 | rval = QLA_FUNCTION_FAILED; |
| 2013 | qla8044_idc_lock(ha); |
| 2014 | goto exit; |
| 2015 | } |
| 2016 | } |
| 2017 | exit: |
| 2018 | qla8044_idc_unlock(ha); |
| 2019 | |
| 2020 | exit_error: |
| 2021 | return rval; |
| 2022 | } |
| 2023 | |
| 2024 | /** |
| 2025 | * qla4_8xxx_check_temp - Check the ISP82XX temperature. |
| 2026 | * @ha: adapter block pointer. |
| 2027 | * |
| 2028 | * Note: The caller should not hold the idc lock. |
| 2029 | **/ |
| 2030 | static int |
| 2031 | qla8044_check_temp(struct scsi_qla_host *vha) |
| 2032 | { |
| 2033 | uint32_t temp, temp_state, temp_val; |
| 2034 | int status = QLA_SUCCESS; |
| 2035 | |
| 2036 | temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX); |
| 2037 | temp_state = qla82xx_get_temp_state(temp); |
| 2038 | temp_val = qla82xx_get_temp_val(temp); |
| 2039 | |
| 2040 | if (temp_state == QLA82XX_TEMP_PANIC) { |
| 2041 | ql_log(ql_log_warn, vha, 0xb0d2, |
| 2042 | "Device temperature %d degrees C" |
| 2043 | " exceeds maximum allowed. Hardware has been shut" |
| 2044 | " down\n", temp_val); |
| 2045 | status = QLA_FUNCTION_FAILED; |
| 2046 | return status; |
| 2047 | } else if (temp_state == QLA82XX_TEMP_WARN) { |
| 2048 | ql_log(ql_log_warn, vha, 0xb0d3, |
| 2049 | "Device temperature %d" |
| 2050 | " degrees C exceeds operating range." |
| 2051 | " Immediate action needed.\n", temp_val); |
| 2052 | } |
| 2053 | return 0; |
| 2054 | } |
| 2055 | |
Joe Carnuccio | 1ae47cf | 2013-08-27 01:37:36 -0400 | [diff] [blame] | 2056 | int qla8044_read_temperature(scsi_qla_host_t *vha) |
| 2057 | { |
| 2058 | uint32_t temp; |
| 2059 | |
| 2060 | temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX); |
| 2061 | return qla82xx_get_temp_val(temp); |
| 2062 | } |
| 2063 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 2064 | /** |
| 2065 | * qla8044_check_fw_alive - Check firmware health |
| 2066 | * @ha: Pointer to host adapter structure. |
| 2067 | * |
| 2068 | * Context: Interrupt |
| 2069 | **/ |
| 2070 | int |
| 2071 | qla8044_check_fw_alive(struct scsi_qla_host *vha) |
| 2072 | { |
| 2073 | uint32_t fw_heartbeat_counter; |
| 2074 | uint32_t halt_status1, halt_status2; |
| 2075 | int status = QLA_SUCCESS; |
| 2076 | |
| 2077 | fw_heartbeat_counter = qla8044_rd_direct(vha, |
| 2078 | QLA8044_PEG_ALIVE_COUNTER_INDEX); |
| 2079 | |
| 2080 | /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */ |
| 2081 | if (fw_heartbeat_counter == 0xffffffff) { |
| 2082 | ql_dbg(ql_dbg_p3p, vha, 0xb0d4, |
| 2083 | "scsi%ld: %s: Device in frozen " |
| 2084 | "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n", |
| 2085 | vha->host_no, __func__); |
| 2086 | return status; |
| 2087 | } |
| 2088 | |
| 2089 | if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { |
| 2090 | vha->seconds_since_last_heartbeat++; |
| 2091 | /* FW not alive after 2 seconds */ |
| 2092 | if (vha->seconds_since_last_heartbeat == 2) { |
| 2093 | vha->seconds_since_last_heartbeat = 0; |
| 2094 | halt_status1 = qla8044_rd_direct(vha, |
| 2095 | QLA8044_PEG_HALT_STATUS1_INDEX); |
| 2096 | halt_status2 = qla8044_rd_direct(vha, |
| 2097 | QLA8044_PEG_HALT_STATUS2_INDEX); |
| 2098 | |
| 2099 | ql_log(ql_log_info, vha, 0xb0d5, |
| 2100 | "scsi(%ld): %s, ISP8044 " |
| 2101 | "Dumping hw/fw registers:\n" |
| 2102 | " PEG_HALT_STATUS1: 0x%x, " |
| 2103 | "PEG_HALT_STATUS2: 0x%x,\n", |
| 2104 | vha->host_no, __func__, halt_status1, |
| 2105 | halt_status2); |
| 2106 | status = QLA_FUNCTION_FAILED; |
| 2107 | } |
| 2108 | } else |
| 2109 | vha->seconds_since_last_heartbeat = 0; |
| 2110 | |
| 2111 | vha->fw_heartbeat_counter = fw_heartbeat_counter; |
| 2112 | return status; |
| 2113 | } |
| 2114 | |
| 2115 | void |
| 2116 | qla8044_watchdog(struct scsi_qla_host *vha) |
| 2117 | { |
| 2118 | uint32_t dev_state, halt_status; |
| 2119 | int halt_status_unrecoverable = 0; |
| 2120 | struct qla_hw_data *ha = vha->hw; |
| 2121 | |
| 2122 | /* don't poll if reset is going on or FW hang in quiescent state */ |
| 2123 | if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 2124 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) { |
| 2125 | dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); |
| 2126 | |
Giridhar Malavali | 7012532 | 2014-04-11 16:54:16 -0400 | [diff] [blame^] | 2127 | if (qla8044_check_fw_alive(vha)) { |
| 2128 | ha->flags.isp82xx_fw_hung = 1; |
| 2129 | ql_log(ql_log_warn, vha, 0xb10a, |
| 2130 | "Firmware hung.\n"); |
| 2131 | qla82xx_clear_pending_mbx(vha); |
| 2132 | } |
| 2133 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 2134 | if (qla8044_check_temp(vha)) { |
| 2135 | set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); |
| 2136 | ha->flags.isp82xx_fw_hung = 1; |
| 2137 | qla2xxx_wake_dpc(vha); |
| 2138 | } else if (dev_state == QLA8XXX_DEV_NEED_RESET && |
| 2139 | !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { |
| 2140 | ql_log(ql_log_info, vha, 0xb0d6, |
| 2141 | "%s: HW State: NEED RESET!\n", |
| 2142 | __func__); |
| 2143 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); |
| 2144 | qla2xxx_wake_dpc(vha); |
| 2145 | } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && |
| 2146 | !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { |
| 2147 | ql_log(ql_log_info, vha, 0xb0d7, |
| 2148 | "%s: HW State: NEED QUIES detected!\n", |
| 2149 | __func__); |
| 2150 | set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); |
| 2151 | qla2xxx_wake_dpc(vha); |
| 2152 | } else { |
| 2153 | /* Check firmware health */ |
Giridhar Malavali | 7012532 | 2014-04-11 16:54:16 -0400 | [diff] [blame^] | 2154 | if (ha->flags.isp82xx_fw_hung) { |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 2155 | halt_status = qla8044_rd_direct(vha, |
| 2156 | QLA8044_PEG_HALT_STATUS1_INDEX); |
| 2157 | if (halt_status & |
| 2158 | QLA8044_HALT_STATUS_FW_RESET) { |
| 2159 | ql_log(ql_log_fatal, vha, |
| 2160 | 0xb0d8, "%s: Firmware " |
| 2161 | "error detected device " |
| 2162 | "is being reset\n", |
| 2163 | __func__); |
| 2164 | } else if (halt_status & |
| 2165 | QLA8044_HALT_STATUS_UNRECOVERABLE) { |
| 2166 | halt_status_unrecoverable = 1; |
| 2167 | } |
| 2168 | |
| 2169 | /* Since we cannot change dev_state in interrupt |
| 2170 | * context, set appropriate DPC flag then wakeup |
| 2171 | * DPC */ |
| 2172 | if (halt_status_unrecoverable) { |
| 2173 | set_bit(ISP_UNRECOVERABLE, |
| 2174 | &vha->dpc_flags); |
| 2175 | } else { |
| 2176 | if (dev_state == |
| 2177 | QLA8XXX_DEV_QUIESCENT) { |
| 2178 | set_bit(FCOE_CTX_RESET_NEEDED, |
| 2179 | &vha->dpc_flags); |
| 2180 | ql_log(ql_log_info, vha, 0xb0d9, |
| 2181 | "%s: FW CONTEXT Reset " |
| 2182 | "needed!\n", __func__); |
| 2183 | } else { |
| 2184 | ql_log(ql_log_info, vha, |
| 2185 | 0xb0da, "%s: " |
| 2186 | "detect abort needed\n", |
| 2187 | __func__); |
| 2188 | set_bit(ISP_ABORT_NEEDED, |
| 2189 | &vha->dpc_flags); |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 2190 | } |
| 2191 | } |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 2192 | qla2xxx_wake_dpc(vha); |
| 2193 | } |
| 2194 | } |
| 2195 | |
| 2196 | } |
| 2197 | } |
| 2198 | |
| 2199 | static int |
| 2200 | qla8044_minidump_process_control(struct scsi_qla_host *vha, |
| 2201 | struct qla8044_minidump_entry_hdr *entry_hdr) |
| 2202 | { |
| 2203 | struct qla8044_minidump_entry_crb *crb_entry; |
| 2204 | uint32_t read_value, opcode, poll_time, addr, index; |
| 2205 | uint32_t crb_addr, rval = QLA_SUCCESS; |
| 2206 | unsigned long wtime; |
| 2207 | struct qla8044_minidump_template_hdr *tmplt_hdr; |
| 2208 | int i; |
| 2209 | struct qla_hw_data *ha = vha->hw; |
| 2210 | |
| 2211 | ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__); |
| 2212 | tmplt_hdr = (struct qla8044_minidump_template_hdr *) |
| 2213 | ha->md_tmplt_hdr; |
| 2214 | crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr; |
| 2215 | |
| 2216 | crb_addr = crb_entry->addr; |
| 2217 | for (i = 0; i < crb_entry->op_count; i++) { |
| 2218 | opcode = crb_entry->crb_ctrl.opcode; |
| 2219 | |
| 2220 | if (opcode & QLA82XX_DBG_OPCODE_WR) { |
| 2221 | qla8044_wr_reg_indirect(vha, crb_addr, |
| 2222 | crb_entry->value_1); |
| 2223 | opcode &= ~QLA82XX_DBG_OPCODE_WR; |
| 2224 | } |
| 2225 | |
| 2226 | if (opcode & QLA82XX_DBG_OPCODE_RW) { |
| 2227 | qla8044_rd_reg_indirect(vha, crb_addr, &read_value); |
| 2228 | qla8044_wr_reg_indirect(vha, crb_addr, read_value); |
| 2229 | opcode &= ~QLA82XX_DBG_OPCODE_RW; |
| 2230 | } |
| 2231 | |
| 2232 | if (opcode & QLA82XX_DBG_OPCODE_AND) { |
| 2233 | qla8044_rd_reg_indirect(vha, crb_addr, &read_value); |
| 2234 | read_value &= crb_entry->value_2; |
| 2235 | opcode &= ~QLA82XX_DBG_OPCODE_AND; |
| 2236 | if (opcode & QLA82XX_DBG_OPCODE_OR) { |
| 2237 | read_value |= crb_entry->value_3; |
| 2238 | opcode &= ~QLA82XX_DBG_OPCODE_OR; |
| 2239 | } |
| 2240 | qla8044_wr_reg_indirect(vha, crb_addr, read_value); |
| 2241 | } |
| 2242 | if (opcode & QLA82XX_DBG_OPCODE_OR) { |
| 2243 | qla8044_rd_reg_indirect(vha, crb_addr, &read_value); |
| 2244 | read_value |= crb_entry->value_3; |
| 2245 | qla8044_wr_reg_indirect(vha, crb_addr, read_value); |
| 2246 | opcode &= ~QLA82XX_DBG_OPCODE_OR; |
| 2247 | } |
| 2248 | if (opcode & QLA82XX_DBG_OPCODE_POLL) { |
| 2249 | poll_time = crb_entry->crb_strd.poll_timeout; |
| 2250 | wtime = jiffies + poll_time; |
| 2251 | qla8044_rd_reg_indirect(vha, crb_addr, &read_value); |
| 2252 | |
| 2253 | do { |
| 2254 | if ((read_value & crb_entry->value_2) == |
| 2255 | crb_entry->value_1) { |
| 2256 | break; |
| 2257 | } else if (time_after_eq(jiffies, wtime)) { |
| 2258 | /* capturing dump failed */ |
| 2259 | rval = QLA_FUNCTION_FAILED; |
| 2260 | break; |
| 2261 | } else { |
| 2262 | qla8044_rd_reg_indirect(vha, |
| 2263 | crb_addr, &read_value); |
| 2264 | } |
| 2265 | } while (1); |
| 2266 | opcode &= ~QLA82XX_DBG_OPCODE_POLL; |
| 2267 | } |
| 2268 | |
| 2269 | if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { |
| 2270 | if (crb_entry->crb_strd.state_index_a) { |
| 2271 | index = crb_entry->crb_strd.state_index_a; |
| 2272 | addr = tmplt_hdr->saved_state_array[index]; |
| 2273 | } else { |
| 2274 | addr = crb_addr; |
| 2275 | } |
| 2276 | |
| 2277 | qla8044_rd_reg_indirect(vha, addr, &read_value); |
| 2278 | index = crb_entry->crb_ctrl.state_index_v; |
| 2279 | tmplt_hdr->saved_state_array[index] = read_value; |
| 2280 | opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; |
| 2281 | } |
| 2282 | |
| 2283 | if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { |
| 2284 | if (crb_entry->crb_strd.state_index_a) { |
| 2285 | index = crb_entry->crb_strd.state_index_a; |
| 2286 | addr = tmplt_hdr->saved_state_array[index]; |
| 2287 | } else { |
| 2288 | addr = crb_addr; |
| 2289 | } |
| 2290 | |
| 2291 | if (crb_entry->crb_ctrl.state_index_v) { |
| 2292 | index = crb_entry->crb_ctrl.state_index_v; |
| 2293 | read_value = |
| 2294 | tmplt_hdr->saved_state_array[index]; |
| 2295 | } else { |
| 2296 | read_value = crb_entry->value_1; |
| 2297 | } |
| 2298 | |
| 2299 | qla8044_wr_reg_indirect(vha, addr, read_value); |
| 2300 | opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; |
| 2301 | } |
| 2302 | |
| 2303 | if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { |
| 2304 | index = crb_entry->crb_ctrl.state_index_v; |
| 2305 | read_value = tmplt_hdr->saved_state_array[index]; |
| 2306 | read_value <<= crb_entry->crb_ctrl.shl; |
| 2307 | read_value >>= crb_entry->crb_ctrl.shr; |
| 2308 | if (crb_entry->value_2) |
| 2309 | read_value &= crb_entry->value_2; |
| 2310 | read_value |= crb_entry->value_3; |
| 2311 | read_value += crb_entry->value_1; |
| 2312 | tmplt_hdr->saved_state_array[index] = read_value; |
| 2313 | opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; |
| 2314 | } |
| 2315 | crb_addr += crb_entry->crb_strd.addr_stride; |
| 2316 | } |
| 2317 | return rval; |
| 2318 | } |
| 2319 | |
| 2320 | static void |
| 2321 | qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha, |
| 2322 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 2323 | { |
| 2324 | uint32_t r_addr, r_stride, loop_cnt, i, r_value; |
| 2325 | struct qla8044_minidump_entry_crb *crb_hdr; |
| 2326 | uint32_t *data_ptr = *d_ptr; |
| 2327 | |
| 2328 | ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__); |
| 2329 | crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr; |
| 2330 | r_addr = crb_hdr->addr; |
| 2331 | r_stride = crb_hdr->crb_strd.addr_stride; |
| 2332 | loop_cnt = crb_hdr->op_count; |
| 2333 | |
| 2334 | for (i = 0; i < loop_cnt; i++) { |
| 2335 | qla8044_rd_reg_indirect(vha, r_addr, &r_value); |
| 2336 | *data_ptr++ = r_addr; |
| 2337 | *data_ptr++ = r_value; |
| 2338 | r_addr += r_stride; |
| 2339 | } |
| 2340 | *d_ptr = data_ptr; |
| 2341 | } |
| 2342 | |
| 2343 | static int |
| 2344 | qla8044_minidump_process_rdmem(struct scsi_qla_host *vha, |
| 2345 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 2346 | { |
| 2347 | uint32_t r_addr, r_value, r_data; |
| 2348 | uint32_t i, j, loop_cnt; |
| 2349 | struct qla8044_minidump_entry_rdmem *m_hdr; |
| 2350 | unsigned long flags; |
| 2351 | uint32_t *data_ptr = *d_ptr; |
| 2352 | struct qla_hw_data *ha = vha->hw; |
| 2353 | |
| 2354 | ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__); |
| 2355 | m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr; |
| 2356 | r_addr = m_hdr->read_addr; |
| 2357 | loop_cnt = m_hdr->read_data_size/16; |
| 2358 | |
| 2359 | ql_dbg(ql_dbg_p3p, vha, 0xb0f0, |
| 2360 | "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", |
| 2361 | __func__, r_addr, m_hdr->read_data_size); |
| 2362 | |
| 2363 | if (r_addr & 0xf) { |
| 2364 | ql_dbg(ql_dbg_p3p, vha, 0xb0f1, |
Masanari Iida | 8faaaea | 2014-01-07 21:58:06 +0900 | [diff] [blame] | 2365 | "[%s]: Read addr 0x%x not 16 bytes aligned\n", |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 2366 | __func__, r_addr); |
| 2367 | return QLA_FUNCTION_FAILED; |
| 2368 | } |
| 2369 | |
| 2370 | if (m_hdr->read_data_size % 16) { |
| 2371 | ql_dbg(ql_dbg_p3p, vha, 0xb0f2, |
| 2372 | "[%s]: Read data[0x%x] not multiple of 16 bytes\n", |
| 2373 | __func__, m_hdr->read_data_size); |
| 2374 | return QLA_FUNCTION_FAILED; |
| 2375 | } |
| 2376 | |
| 2377 | ql_dbg(ql_dbg_p3p, vha, 0xb0f3, |
| 2378 | "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", |
| 2379 | __func__, r_addr, m_hdr->read_data_size, loop_cnt); |
| 2380 | |
| 2381 | write_lock_irqsave(&ha->hw_lock, flags); |
| 2382 | for (i = 0; i < loop_cnt; i++) { |
| 2383 | qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr); |
| 2384 | r_value = 0; |
| 2385 | qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value); |
| 2386 | r_value = MIU_TA_CTL_ENABLE; |
| 2387 | qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value); |
| 2388 | r_value = MIU_TA_CTL_START_ENABLE; |
| 2389 | qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value); |
| 2390 | |
| 2391 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 2392 | qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, |
| 2393 | &r_value); |
| 2394 | if ((r_value & MIU_TA_CTL_BUSY) == 0) |
| 2395 | break; |
| 2396 | } |
| 2397 | |
| 2398 | if (j >= MAX_CTL_CHECK) { |
| 2399 | printk_ratelimited(KERN_ERR |
| 2400 | "%s: failed to read through agent\n", __func__); |
| 2401 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 2402 | return QLA_SUCCESS; |
| 2403 | } |
| 2404 | |
| 2405 | for (j = 0; j < 4; j++) { |
| 2406 | qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j], |
| 2407 | &r_data); |
| 2408 | *data_ptr++ = r_data; |
| 2409 | } |
| 2410 | |
| 2411 | r_addr += 16; |
| 2412 | } |
| 2413 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 2414 | |
| 2415 | ql_dbg(ql_dbg_p3p, vha, 0xb0f4, |
| 2416 | "Leaving fn: %s datacount: 0x%x\n", |
| 2417 | __func__, (loop_cnt * 16)); |
| 2418 | |
| 2419 | *d_ptr = data_ptr; |
| 2420 | return QLA_SUCCESS; |
| 2421 | } |
| 2422 | |
| 2423 | /* ISP83xx flash read for _RDROM _BOARD */ |
| 2424 | static uint32_t |
| 2425 | qla8044_minidump_process_rdrom(struct scsi_qla_host *vha, |
| 2426 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 2427 | { |
| 2428 | uint32_t fl_addr, u32_count, rval; |
| 2429 | struct qla8044_minidump_entry_rdrom *rom_hdr; |
| 2430 | uint32_t *data_ptr = *d_ptr; |
| 2431 | |
| 2432 | rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr; |
| 2433 | fl_addr = rom_hdr->read_addr; |
| 2434 | u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t); |
| 2435 | |
| 2436 | ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n", |
| 2437 | __func__, fl_addr, u32_count); |
| 2438 | |
| 2439 | rval = qla8044_lockless_flash_read_u32(vha, fl_addr, |
| 2440 | (u8 *)(data_ptr), u32_count); |
| 2441 | |
| 2442 | if (rval != QLA_SUCCESS) { |
| 2443 | ql_log(ql_log_fatal, vha, 0xb0f6, |
| 2444 | "%s: Flash Read Error,Count=%d\n", __func__, u32_count); |
| 2445 | return QLA_FUNCTION_FAILED; |
| 2446 | } else { |
| 2447 | data_ptr += u32_count; |
| 2448 | *d_ptr = data_ptr; |
| 2449 | return QLA_SUCCESS; |
| 2450 | } |
| 2451 | } |
| 2452 | |
| 2453 | static void |
| 2454 | qla8044_mark_entry_skipped(struct scsi_qla_host *vha, |
| 2455 | struct qla8044_minidump_entry_hdr *entry_hdr, int index) |
| 2456 | { |
| 2457 | entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; |
| 2458 | |
| 2459 | ql_log(ql_log_info, vha, 0xb0f7, |
| 2460 | "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", |
| 2461 | vha->host_no, index, entry_hdr->entry_type, |
| 2462 | entry_hdr->d_ctrl.entry_capture_mask); |
| 2463 | } |
| 2464 | |
| 2465 | static int |
| 2466 | qla8044_minidump_process_l2tag(struct scsi_qla_host *vha, |
| 2467 | struct qla8044_minidump_entry_hdr *entry_hdr, |
| 2468 | uint32_t **d_ptr) |
| 2469 | { |
| 2470 | uint32_t addr, r_addr, c_addr, t_r_addr; |
| 2471 | uint32_t i, k, loop_count, t_value, r_cnt, r_value; |
| 2472 | unsigned long p_wait, w_time, p_mask; |
| 2473 | uint32_t c_value_w, c_value_r; |
| 2474 | struct qla8044_minidump_entry_cache *cache_hdr; |
| 2475 | int rval = QLA_FUNCTION_FAILED; |
| 2476 | uint32_t *data_ptr = *d_ptr; |
| 2477 | |
| 2478 | ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__); |
| 2479 | cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr; |
| 2480 | |
| 2481 | loop_count = cache_hdr->op_count; |
| 2482 | r_addr = cache_hdr->read_addr; |
| 2483 | c_addr = cache_hdr->control_addr; |
| 2484 | c_value_w = cache_hdr->cache_ctrl.write_value; |
| 2485 | |
| 2486 | t_r_addr = cache_hdr->tag_reg_addr; |
| 2487 | t_value = cache_hdr->addr_ctrl.init_tag_value; |
| 2488 | r_cnt = cache_hdr->read_ctrl.read_addr_cnt; |
| 2489 | p_wait = cache_hdr->cache_ctrl.poll_wait; |
| 2490 | p_mask = cache_hdr->cache_ctrl.poll_mask; |
| 2491 | |
| 2492 | for (i = 0; i < loop_count; i++) { |
| 2493 | qla8044_wr_reg_indirect(vha, t_r_addr, t_value); |
| 2494 | if (c_value_w) |
| 2495 | qla8044_wr_reg_indirect(vha, c_addr, c_value_w); |
| 2496 | |
| 2497 | if (p_mask) { |
| 2498 | w_time = jiffies + p_wait; |
| 2499 | do { |
| 2500 | qla8044_rd_reg_indirect(vha, c_addr, |
| 2501 | &c_value_r); |
| 2502 | if ((c_value_r & p_mask) == 0) { |
| 2503 | break; |
| 2504 | } else if (time_after_eq(jiffies, w_time)) { |
| 2505 | /* capturing dump failed */ |
| 2506 | return rval; |
| 2507 | } |
| 2508 | } while (1); |
| 2509 | } |
| 2510 | |
| 2511 | addr = r_addr; |
| 2512 | for (k = 0; k < r_cnt; k++) { |
| 2513 | qla8044_rd_reg_indirect(vha, addr, &r_value); |
| 2514 | *data_ptr++ = r_value; |
| 2515 | addr += cache_hdr->read_ctrl.read_addr_stride; |
| 2516 | } |
| 2517 | t_value += cache_hdr->addr_ctrl.tag_value_stride; |
| 2518 | } |
| 2519 | *d_ptr = data_ptr; |
| 2520 | return QLA_SUCCESS; |
| 2521 | } |
| 2522 | |
| 2523 | static void |
| 2524 | qla8044_minidump_process_l1cache(struct scsi_qla_host *vha, |
| 2525 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 2526 | { |
| 2527 | uint32_t addr, r_addr, c_addr, t_r_addr; |
| 2528 | uint32_t i, k, loop_count, t_value, r_cnt, r_value; |
| 2529 | uint32_t c_value_w; |
| 2530 | struct qla8044_minidump_entry_cache *cache_hdr; |
| 2531 | uint32_t *data_ptr = *d_ptr; |
| 2532 | |
| 2533 | cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr; |
| 2534 | loop_count = cache_hdr->op_count; |
| 2535 | r_addr = cache_hdr->read_addr; |
| 2536 | c_addr = cache_hdr->control_addr; |
| 2537 | c_value_w = cache_hdr->cache_ctrl.write_value; |
| 2538 | |
| 2539 | t_r_addr = cache_hdr->tag_reg_addr; |
| 2540 | t_value = cache_hdr->addr_ctrl.init_tag_value; |
| 2541 | r_cnt = cache_hdr->read_ctrl.read_addr_cnt; |
| 2542 | |
| 2543 | for (i = 0; i < loop_count; i++) { |
| 2544 | qla8044_wr_reg_indirect(vha, t_r_addr, t_value); |
| 2545 | qla8044_wr_reg_indirect(vha, c_addr, c_value_w); |
| 2546 | addr = r_addr; |
| 2547 | for (k = 0; k < r_cnt; k++) { |
| 2548 | qla8044_rd_reg_indirect(vha, addr, &r_value); |
| 2549 | *data_ptr++ = r_value; |
| 2550 | addr += cache_hdr->read_ctrl.read_addr_stride; |
| 2551 | } |
| 2552 | t_value += cache_hdr->addr_ctrl.tag_value_stride; |
| 2553 | } |
| 2554 | *d_ptr = data_ptr; |
| 2555 | } |
| 2556 | |
| 2557 | static void |
| 2558 | qla8044_minidump_process_rdocm(struct scsi_qla_host *vha, |
| 2559 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 2560 | { |
| 2561 | uint32_t r_addr, r_stride, loop_cnt, i, r_value; |
| 2562 | struct qla8044_minidump_entry_rdocm *ocm_hdr; |
| 2563 | uint32_t *data_ptr = *d_ptr; |
| 2564 | struct qla_hw_data *ha = vha->hw; |
| 2565 | |
| 2566 | ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__); |
| 2567 | |
| 2568 | ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr; |
| 2569 | r_addr = ocm_hdr->read_addr; |
| 2570 | r_stride = ocm_hdr->read_addr_stride; |
| 2571 | loop_cnt = ocm_hdr->op_count; |
| 2572 | |
| 2573 | ql_dbg(ql_dbg_p3p, vha, 0xb0fa, |
| 2574 | "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", |
| 2575 | __func__, r_addr, r_stride, loop_cnt); |
| 2576 | |
| 2577 | for (i = 0; i < loop_cnt; i++) { |
| 2578 | r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); |
| 2579 | *data_ptr++ = r_value; |
| 2580 | r_addr += r_stride; |
| 2581 | } |
| 2582 | ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n", |
| 2583 | __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))); |
| 2584 | |
| 2585 | *d_ptr = data_ptr; |
| 2586 | } |
| 2587 | |
| 2588 | static void |
| 2589 | qla8044_minidump_process_rdmux(struct scsi_qla_host *vha, |
| 2590 | struct qla8044_minidump_entry_hdr *entry_hdr, |
| 2591 | uint32_t **d_ptr) |
| 2592 | { |
| 2593 | uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; |
| 2594 | struct qla8044_minidump_entry_mux *mux_hdr; |
| 2595 | uint32_t *data_ptr = *d_ptr; |
| 2596 | |
| 2597 | ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__); |
| 2598 | |
| 2599 | mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr; |
| 2600 | r_addr = mux_hdr->read_addr; |
| 2601 | s_addr = mux_hdr->select_addr; |
| 2602 | s_stride = mux_hdr->select_value_stride; |
| 2603 | s_value = mux_hdr->select_value; |
| 2604 | loop_cnt = mux_hdr->op_count; |
| 2605 | |
| 2606 | for (i = 0; i < loop_cnt; i++) { |
| 2607 | qla8044_wr_reg_indirect(vha, s_addr, s_value); |
| 2608 | qla8044_rd_reg_indirect(vha, r_addr, &r_value); |
| 2609 | *data_ptr++ = s_value; |
| 2610 | *data_ptr++ = r_value; |
| 2611 | s_value += s_stride; |
| 2612 | } |
| 2613 | *d_ptr = data_ptr; |
| 2614 | } |
| 2615 | |
| 2616 | static void |
| 2617 | qla8044_minidump_process_queue(struct scsi_qla_host *vha, |
| 2618 | struct qla8044_minidump_entry_hdr *entry_hdr, |
| 2619 | uint32_t **d_ptr) |
| 2620 | { |
| 2621 | uint32_t s_addr, r_addr; |
| 2622 | uint32_t r_stride, r_value, r_cnt, qid = 0; |
| 2623 | uint32_t i, k, loop_cnt; |
| 2624 | struct qla8044_minidump_entry_queue *q_hdr; |
| 2625 | uint32_t *data_ptr = *d_ptr; |
| 2626 | |
| 2627 | ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__); |
| 2628 | q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr; |
| 2629 | s_addr = q_hdr->select_addr; |
| 2630 | r_cnt = q_hdr->rd_strd.read_addr_cnt; |
| 2631 | r_stride = q_hdr->rd_strd.read_addr_stride; |
| 2632 | loop_cnt = q_hdr->op_count; |
| 2633 | |
| 2634 | for (i = 0; i < loop_cnt; i++) { |
| 2635 | qla8044_wr_reg_indirect(vha, s_addr, qid); |
| 2636 | r_addr = q_hdr->read_addr; |
| 2637 | for (k = 0; k < r_cnt; k++) { |
| 2638 | qla8044_rd_reg_indirect(vha, r_addr, &r_value); |
| 2639 | *data_ptr++ = r_value; |
| 2640 | r_addr += r_stride; |
| 2641 | } |
| 2642 | qid += q_hdr->q_strd.queue_id_stride; |
| 2643 | } |
| 2644 | *d_ptr = data_ptr; |
| 2645 | } |
| 2646 | |
| 2647 | /* ISP83xx functions to process new minidump entries... */ |
| 2648 | static uint32_t |
| 2649 | qla8044_minidump_process_pollrd(struct scsi_qla_host *vha, |
| 2650 | struct qla8044_minidump_entry_hdr *entry_hdr, |
| 2651 | uint32_t **d_ptr) |
| 2652 | { |
| 2653 | uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; |
| 2654 | uint16_t s_stride, i; |
| 2655 | struct qla8044_minidump_entry_pollrd *pollrd_hdr; |
| 2656 | uint32_t *data_ptr = *d_ptr; |
| 2657 | |
| 2658 | pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr; |
| 2659 | s_addr = pollrd_hdr->select_addr; |
| 2660 | r_addr = pollrd_hdr->read_addr; |
| 2661 | s_value = pollrd_hdr->select_value; |
| 2662 | s_stride = pollrd_hdr->select_value_stride; |
| 2663 | |
| 2664 | poll_wait = pollrd_hdr->poll_wait; |
| 2665 | poll_mask = pollrd_hdr->poll_mask; |
| 2666 | |
| 2667 | for (i = 0; i < pollrd_hdr->op_count; i++) { |
| 2668 | qla8044_wr_reg_indirect(vha, s_addr, s_value); |
| 2669 | poll_wait = pollrd_hdr->poll_wait; |
| 2670 | while (1) { |
| 2671 | qla8044_rd_reg_indirect(vha, s_addr, &r_value); |
| 2672 | if ((r_value & poll_mask) != 0) { |
| 2673 | break; |
| 2674 | } else { |
| 2675 | usleep_range(1000, 1100); |
| 2676 | if (--poll_wait == 0) { |
| 2677 | ql_log(ql_log_fatal, vha, 0xb0fe, |
| 2678 | "%s: TIMEOUT\n", __func__); |
| 2679 | goto error; |
| 2680 | } |
| 2681 | } |
| 2682 | } |
| 2683 | qla8044_rd_reg_indirect(vha, r_addr, &r_value); |
| 2684 | *data_ptr++ = s_value; |
| 2685 | *data_ptr++ = r_value; |
| 2686 | |
| 2687 | s_value += s_stride; |
| 2688 | } |
| 2689 | *d_ptr = data_ptr; |
| 2690 | return QLA_SUCCESS; |
| 2691 | |
| 2692 | error: |
| 2693 | return QLA_FUNCTION_FAILED; |
| 2694 | } |
| 2695 | |
| 2696 | static void |
| 2697 | qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha, |
| 2698 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 2699 | { |
| 2700 | uint32_t sel_val1, sel_val2, t_sel_val, data, i; |
| 2701 | uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; |
| 2702 | struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr; |
| 2703 | uint32_t *data_ptr = *d_ptr; |
| 2704 | |
| 2705 | rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr; |
| 2706 | sel_val1 = rdmux2_hdr->select_value_1; |
| 2707 | sel_val2 = rdmux2_hdr->select_value_2; |
| 2708 | sel_addr1 = rdmux2_hdr->select_addr_1; |
| 2709 | sel_addr2 = rdmux2_hdr->select_addr_2; |
| 2710 | sel_val_mask = rdmux2_hdr->select_value_mask; |
| 2711 | read_addr = rdmux2_hdr->read_addr; |
| 2712 | |
| 2713 | for (i = 0; i < rdmux2_hdr->op_count; i++) { |
| 2714 | qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1); |
| 2715 | t_sel_val = sel_val1 & sel_val_mask; |
| 2716 | *data_ptr++ = t_sel_val; |
| 2717 | |
| 2718 | qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val); |
| 2719 | qla8044_rd_reg_indirect(vha, read_addr, &data); |
| 2720 | |
| 2721 | *data_ptr++ = data; |
| 2722 | |
| 2723 | qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2); |
| 2724 | t_sel_val = sel_val2 & sel_val_mask; |
| 2725 | *data_ptr++ = t_sel_val; |
| 2726 | |
| 2727 | qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val); |
| 2728 | qla8044_rd_reg_indirect(vha, read_addr, &data); |
| 2729 | |
| 2730 | *data_ptr++ = data; |
| 2731 | |
| 2732 | sel_val1 += rdmux2_hdr->select_value_stride; |
| 2733 | sel_val2 += rdmux2_hdr->select_value_stride; |
| 2734 | } |
| 2735 | |
| 2736 | *d_ptr = data_ptr; |
| 2737 | } |
| 2738 | |
| 2739 | static uint32_t |
| 2740 | qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha, |
| 2741 | struct qla8044_minidump_entry_hdr *entry_hdr, |
| 2742 | uint32_t **d_ptr) |
| 2743 | { |
| 2744 | uint32_t poll_wait, poll_mask, r_value, data; |
| 2745 | uint32_t addr_1, addr_2, value_1, value_2; |
| 2746 | struct qla8044_minidump_entry_pollrdmwr *poll_hdr; |
| 2747 | uint32_t *data_ptr = *d_ptr; |
| 2748 | |
| 2749 | poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr; |
| 2750 | addr_1 = poll_hdr->addr_1; |
| 2751 | addr_2 = poll_hdr->addr_2; |
| 2752 | value_1 = poll_hdr->value_1; |
| 2753 | value_2 = poll_hdr->value_2; |
| 2754 | poll_mask = poll_hdr->poll_mask; |
| 2755 | |
| 2756 | qla8044_wr_reg_indirect(vha, addr_1, value_1); |
| 2757 | |
| 2758 | poll_wait = poll_hdr->poll_wait; |
| 2759 | while (1) { |
| 2760 | qla8044_rd_reg_indirect(vha, addr_1, &r_value); |
| 2761 | |
| 2762 | if ((r_value & poll_mask) != 0) { |
| 2763 | break; |
| 2764 | } else { |
| 2765 | usleep_range(1000, 1100); |
| 2766 | if (--poll_wait == 0) { |
| 2767 | ql_log(ql_log_fatal, vha, 0xb0ff, |
| 2768 | "%s: TIMEOUT\n", __func__); |
| 2769 | goto error; |
| 2770 | } |
| 2771 | } |
| 2772 | } |
| 2773 | |
| 2774 | qla8044_rd_reg_indirect(vha, addr_2, &data); |
| 2775 | data &= poll_hdr->modify_mask; |
| 2776 | qla8044_wr_reg_indirect(vha, addr_2, data); |
| 2777 | qla8044_wr_reg_indirect(vha, addr_1, value_2); |
| 2778 | |
| 2779 | poll_wait = poll_hdr->poll_wait; |
| 2780 | while (1) { |
| 2781 | qla8044_rd_reg_indirect(vha, addr_1, &r_value); |
| 2782 | |
| 2783 | if ((r_value & poll_mask) != 0) { |
| 2784 | break; |
| 2785 | } else { |
| 2786 | usleep_range(1000, 1100); |
| 2787 | if (--poll_wait == 0) { |
| 2788 | ql_log(ql_log_fatal, vha, 0xb100, |
| 2789 | "%s: TIMEOUT2\n", __func__); |
| 2790 | goto error; |
| 2791 | } |
| 2792 | } |
| 2793 | } |
| 2794 | |
| 2795 | *data_ptr++ = addr_2; |
| 2796 | *data_ptr++ = data; |
| 2797 | |
| 2798 | *d_ptr = data_ptr; |
| 2799 | |
| 2800 | return QLA_SUCCESS; |
| 2801 | |
| 2802 | error: |
| 2803 | return QLA_FUNCTION_FAILED; |
| 2804 | } |
| 2805 | |
| 2806 | #define ISP8044_PEX_DMA_ENGINE_INDEX 8 |
| 2807 | #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000 |
| 2808 | #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000 |
| 2809 | #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0 |
| 2810 | #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04 |
| 2811 | #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08 |
| 2812 | |
| 2813 | #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024) |
| 2814 | #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */ |
| 2815 | |
| 2816 | static int |
| 2817 | qla8044_check_dma_engine_state(struct scsi_qla_host *vha) |
| 2818 | { |
| 2819 | struct qla_hw_data *ha = vha->hw; |
| 2820 | int rval = QLA_SUCCESS; |
| 2821 | uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; |
| 2822 | uint64_t dma_base_addr = 0; |
| 2823 | struct qla8044_minidump_template_hdr *tmplt_hdr = NULL; |
| 2824 | |
| 2825 | tmplt_hdr = ha->md_tmplt_hdr; |
| 2826 | dma_eng_num = |
| 2827 | tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; |
| 2828 | dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS + |
| 2829 | (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET); |
| 2830 | |
| 2831 | /* Read the pex-dma's command-status-and-control register. */ |
| 2832 | rval = qla8044_rd_reg_indirect(vha, |
| 2833 | (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL), |
| 2834 | &cmd_sts_and_cntrl); |
| 2835 | if (rval) |
| 2836 | return QLA_FUNCTION_FAILED; |
| 2837 | |
| 2838 | /* Check if requested pex-dma engine is available. */ |
| 2839 | if (cmd_sts_and_cntrl & BIT_31) |
| 2840 | return QLA_SUCCESS; |
| 2841 | |
| 2842 | return QLA_FUNCTION_FAILED; |
| 2843 | } |
| 2844 | |
| 2845 | static int |
| 2846 | qla8044_start_pex_dma(struct scsi_qla_host *vha, |
| 2847 | struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr) |
| 2848 | { |
| 2849 | struct qla_hw_data *ha = vha->hw; |
| 2850 | int rval = QLA_SUCCESS, wait = 0; |
| 2851 | uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; |
| 2852 | uint64_t dma_base_addr = 0; |
| 2853 | struct qla8044_minidump_template_hdr *tmplt_hdr = NULL; |
| 2854 | |
| 2855 | tmplt_hdr = ha->md_tmplt_hdr; |
| 2856 | dma_eng_num = |
| 2857 | tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; |
| 2858 | dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS + |
| 2859 | (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET); |
| 2860 | |
| 2861 | rval = qla8044_wr_reg_indirect(vha, |
| 2862 | dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW, |
| 2863 | m_hdr->desc_card_addr); |
| 2864 | if (rval) |
| 2865 | goto error_exit; |
| 2866 | |
| 2867 | rval = qla8044_wr_reg_indirect(vha, |
| 2868 | dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0); |
| 2869 | if (rval) |
| 2870 | goto error_exit; |
| 2871 | |
| 2872 | rval = qla8044_wr_reg_indirect(vha, |
| 2873 | dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL, |
| 2874 | m_hdr->start_dma_cmd); |
| 2875 | if (rval) |
| 2876 | goto error_exit; |
| 2877 | |
| 2878 | /* Wait for dma operation to complete. */ |
| 2879 | for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) { |
| 2880 | rval = qla8044_rd_reg_indirect(vha, |
| 2881 | (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL), |
| 2882 | &cmd_sts_and_cntrl); |
| 2883 | if (rval) |
| 2884 | goto error_exit; |
| 2885 | |
| 2886 | if ((cmd_sts_and_cntrl & BIT_1) == 0) |
| 2887 | break; |
| 2888 | |
| 2889 | udelay(10); |
| 2890 | } |
| 2891 | |
| 2892 | /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ |
| 2893 | if (wait >= ISP8044_PEX_DMA_MAX_WAIT) { |
| 2894 | rval = QLA_FUNCTION_FAILED; |
| 2895 | goto error_exit; |
| 2896 | } |
| 2897 | |
| 2898 | error_exit: |
| 2899 | return rval; |
| 2900 | } |
| 2901 | |
| 2902 | static int |
| 2903 | qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha, |
| 2904 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 2905 | { |
| 2906 | struct qla_hw_data *ha = vha->hw; |
| 2907 | int rval = QLA_SUCCESS; |
| 2908 | struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL; |
| 2909 | uint32_t chunk_size, read_size; |
| 2910 | uint8_t *data_ptr = (uint8_t *)*d_ptr; |
| 2911 | void *rdmem_buffer = NULL; |
| 2912 | dma_addr_t rdmem_dma; |
| 2913 | struct qla8044_pex_dma_descriptor dma_desc; |
| 2914 | |
| 2915 | rval = qla8044_check_dma_engine_state(vha); |
| 2916 | if (rval != QLA_SUCCESS) { |
| 2917 | ql_dbg(ql_dbg_p3p, vha, 0xb147, |
| 2918 | "DMA engine not available. Fallback to rdmem-read.\n"); |
| 2919 | return QLA_FUNCTION_FAILED; |
| 2920 | } |
| 2921 | |
| 2922 | m_hdr = (void *)entry_hdr; |
| 2923 | |
| 2924 | rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, |
| 2925 | ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL); |
| 2926 | if (!rdmem_buffer) { |
| 2927 | ql_dbg(ql_dbg_p3p, vha, 0xb148, |
| 2928 | "Unable to allocate rdmem dma buffer\n"); |
| 2929 | return QLA_FUNCTION_FAILED; |
| 2930 | } |
| 2931 | |
| 2932 | /* Prepare pex-dma descriptor to be written to MS memory. */ |
| 2933 | /* dma-desc-cmd layout: |
| 2934 | * 0-3: dma-desc-cmd 0-3 |
| 2935 | * 4-7: pcid function number |
| 2936 | * 8-15: dma-desc-cmd 8-15 |
| 2937 | * dma_bus_addr: dma buffer address |
| 2938 | * cmd.read_data_size: amount of data-chunk to be read. |
| 2939 | */ |
| 2940 | dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); |
| 2941 | dma_desc.cmd.dma_desc_cmd |= |
| 2942 | ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); |
| 2943 | |
| 2944 | dma_desc.dma_bus_addr = rdmem_dma; |
| 2945 | dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE; |
| 2946 | read_size = 0; |
| 2947 | |
| 2948 | /* |
| 2949 | * Perform rdmem operation using pex-dma. |
| 2950 | * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE. |
| 2951 | */ |
| 2952 | while (read_size < m_hdr->read_data_size) { |
| 2953 | if (m_hdr->read_data_size - read_size < |
| 2954 | ISP8044_PEX_DMA_READ_SIZE) { |
| 2955 | chunk_size = (m_hdr->read_data_size - read_size); |
| 2956 | dma_desc.cmd.read_data_size = chunk_size; |
| 2957 | } |
| 2958 | |
| 2959 | dma_desc.src_addr = m_hdr->read_addr + read_size; |
| 2960 | |
| 2961 | /* Prepare: Write pex-dma descriptor to MS memory. */ |
| 2962 | rval = qla8044_ms_mem_write_128b(vha, |
| 2963 | m_hdr->desc_card_addr, (void *)&dma_desc, |
| 2964 | (sizeof(struct qla8044_pex_dma_descriptor)/16)); |
| 2965 | if (rval) { |
| 2966 | ql_log(ql_log_warn, vha, 0xb14a, |
| 2967 | "%s: Error writing rdmem-dma-init to MS !!!\n", |
| 2968 | __func__); |
| 2969 | goto error_exit; |
| 2970 | } |
| 2971 | ql_dbg(ql_dbg_p3p, vha, 0xb14b, |
| 2972 | "%s: Dma-descriptor: Instruct for rdmem dma " |
| 2973 | "(chunk_size 0x%x).\n", __func__, chunk_size); |
| 2974 | |
| 2975 | /* Execute: Start pex-dma operation. */ |
| 2976 | rval = qla8044_start_pex_dma(vha, m_hdr); |
| 2977 | if (rval) |
| 2978 | goto error_exit; |
| 2979 | |
| 2980 | memcpy(data_ptr, rdmem_buffer, chunk_size); |
| 2981 | data_ptr += chunk_size; |
| 2982 | read_size += chunk_size; |
| 2983 | } |
| 2984 | |
| 2985 | *d_ptr = (void *)data_ptr; |
| 2986 | |
| 2987 | error_exit: |
| 2988 | if (rdmem_buffer) |
| 2989 | dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE, |
| 2990 | rdmem_buffer, rdmem_dma); |
| 2991 | |
| 2992 | return rval; |
| 2993 | } |
| 2994 | |
Pratik Mohanty | 804df80 | 2014-04-11 16:54:15 -0400 | [diff] [blame] | 2995 | static uint32_t |
| 2996 | qla8044_minidump_process_rddfe(struct scsi_qla_host *vha, |
| 2997 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 2998 | { |
| 2999 | int loop_cnt; |
| 3000 | uint32_t addr1, addr2, value, data, temp, wrVal; |
| 3001 | uint8_t stride, stride2; |
| 3002 | uint16_t count; |
| 3003 | uint32_t poll, mask, data_size, modify_mask; |
| 3004 | uint32_t wait_count = 0; |
| 3005 | |
| 3006 | uint32_t *data_ptr = *d_ptr; |
| 3007 | |
| 3008 | struct qla8044_minidump_entry_rddfe *rddfe; |
| 3009 | rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr; |
| 3010 | |
| 3011 | addr1 = rddfe->addr_1; |
| 3012 | value = rddfe->value; |
| 3013 | stride = rddfe->stride; |
| 3014 | stride2 = rddfe->stride2; |
| 3015 | count = rddfe->count; |
| 3016 | |
| 3017 | poll = rddfe->poll; |
| 3018 | mask = rddfe->mask; |
| 3019 | modify_mask = rddfe->modify_mask; |
| 3020 | data_size = rddfe->data_size; |
| 3021 | |
| 3022 | addr2 = addr1 + stride; |
| 3023 | |
| 3024 | for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) { |
| 3025 | qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value)); |
| 3026 | |
| 3027 | wait_count = 0; |
| 3028 | while (wait_count < poll) { |
| 3029 | qla8044_rd_reg_indirect(vha, addr1, &temp); |
| 3030 | if ((temp & mask) != 0) |
| 3031 | break; |
| 3032 | wait_count++; |
| 3033 | } |
| 3034 | |
| 3035 | if (wait_count == poll) { |
| 3036 | ql_log(ql_log_warn, vha, 0xb153, |
| 3037 | "%s: TIMEOUT\n", __func__); |
| 3038 | goto error; |
| 3039 | } else { |
| 3040 | qla8044_rd_reg_indirect(vha, addr2, &temp); |
| 3041 | temp = temp & modify_mask; |
| 3042 | temp = (temp | ((loop_cnt << 16) | loop_cnt)); |
| 3043 | wrVal = ((temp << 16) | temp); |
| 3044 | |
| 3045 | qla8044_wr_reg_indirect(vha, addr2, wrVal); |
| 3046 | qla8044_wr_reg_indirect(vha, addr1, value); |
| 3047 | |
| 3048 | wait_count = 0; |
| 3049 | while (wait_count < poll) { |
| 3050 | qla8044_rd_reg_indirect(vha, addr1, &temp); |
| 3051 | if ((temp & mask) != 0) |
| 3052 | break; |
| 3053 | wait_count++; |
| 3054 | } |
| 3055 | if (wait_count == poll) { |
| 3056 | ql_log(ql_log_warn, vha, 0xb154, |
| 3057 | "%s: TIMEOUT\n", __func__); |
| 3058 | goto error; |
| 3059 | } |
| 3060 | |
| 3061 | qla8044_wr_reg_indirect(vha, addr1, |
| 3062 | ((0x40000000 | value) + stride2)); |
| 3063 | wait_count = 0; |
| 3064 | while (wait_count < poll) { |
| 3065 | qla8044_rd_reg_indirect(vha, addr1, &temp); |
| 3066 | if ((temp & mask) != 0) |
| 3067 | break; |
| 3068 | wait_count++; |
| 3069 | } |
| 3070 | |
| 3071 | if (wait_count == poll) { |
| 3072 | ql_log(ql_log_warn, vha, 0xb155, |
| 3073 | "%s: TIMEOUT\n", __func__); |
| 3074 | goto error; |
| 3075 | } |
| 3076 | |
| 3077 | qla8044_rd_reg_indirect(vha, addr2, &data); |
| 3078 | |
| 3079 | *data_ptr++ = wrVal; |
| 3080 | *data_ptr++ = data; |
| 3081 | } |
| 3082 | |
| 3083 | } |
| 3084 | |
| 3085 | *d_ptr = data_ptr; |
| 3086 | return QLA_SUCCESS; |
| 3087 | |
| 3088 | error: |
| 3089 | return -1; |
| 3090 | |
| 3091 | } |
| 3092 | |
| 3093 | static uint32_t |
| 3094 | qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha, |
| 3095 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 3096 | { |
| 3097 | int ret = 0; |
| 3098 | uint32_t addr1, addr2, value1, value2, data, selVal; |
| 3099 | uint8_t stride1, stride2; |
| 3100 | uint32_t addr3, addr4, addr5, addr6, addr7; |
| 3101 | uint16_t count, loop_cnt; |
| 3102 | uint32_t poll, mask; |
| 3103 | uint32_t *data_ptr = *d_ptr; |
| 3104 | |
| 3105 | struct qla8044_minidump_entry_rdmdio *rdmdio; |
| 3106 | |
| 3107 | rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr; |
| 3108 | |
| 3109 | addr1 = rdmdio->addr_1; |
| 3110 | addr2 = rdmdio->addr_2; |
| 3111 | value1 = rdmdio->value_1; |
| 3112 | stride1 = rdmdio->stride_1; |
| 3113 | stride2 = rdmdio->stride_2; |
| 3114 | count = rdmdio->count; |
| 3115 | |
| 3116 | poll = rdmdio->poll; |
| 3117 | mask = rdmdio->mask; |
| 3118 | value2 = rdmdio->value_2; |
| 3119 | |
| 3120 | addr3 = addr1 + stride1; |
| 3121 | |
| 3122 | for (loop_cnt = 0; loop_cnt < count; loop_cnt++) { |
| 3123 | ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2, |
| 3124 | addr3, mask); |
| 3125 | if (ret == -1) |
| 3126 | goto error; |
| 3127 | |
| 3128 | addr4 = addr2 - stride1; |
| 3129 | ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4, |
| 3130 | value2); |
| 3131 | if (ret == -1) |
| 3132 | goto error; |
| 3133 | |
| 3134 | addr5 = addr2 - (2 * stride1); |
| 3135 | ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5, |
| 3136 | value1); |
| 3137 | if (ret == -1) |
| 3138 | goto error; |
| 3139 | |
| 3140 | addr6 = addr2 - (3 * stride1); |
| 3141 | ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, |
| 3142 | addr6, 0x2); |
| 3143 | if (ret == -1) |
| 3144 | goto error; |
| 3145 | |
| 3146 | ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2, |
| 3147 | addr3, mask); |
| 3148 | if (ret == -1) |
| 3149 | goto error; |
| 3150 | |
| 3151 | addr7 = addr2 - (4 * stride1); |
| 3152 | data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, |
| 3153 | mask, addr7); |
| 3154 | if (data == -1) |
| 3155 | goto error; |
| 3156 | |
| 3157 | selVal = (value2 << 18) | (value1 << 2) | 2; |
| 3158 | |
| 3159 | stride2 = rdmdio->stride_2; |
| 3160 | *data_ptr++ = selVal; |
| 3161 | *data_ptr++ = data; |
| 3162 | |
| 3163 | value1 = value1 + stride2; |
| 3164 | *d_ptr = data_ptr; |
| 3165 | } |
| 3166 | |
| 3167 | return 0; |
| 3168 | |
| 3169 | error: |
| 3170 | return -1; |
| 3171 | } |
| 3172 | |
| 3173 | static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha, |
| 3174 | struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) |
| 3175 | { |
| 3176 | uint32_t addr1, addr2, value1, value2, poll, mask, r_value; |
| 3177 | uint32_t wait_count = 0; |
| 3178 | struct qla8044_minidump_entry_pollwr *pollwr_hdr; |
| 3179 | |
| 3180 | pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr; |
| 3181 | addr1 = pollwr_hdr->addr_1; |
| 3182 | addr2 = pollwr_hdr->addr_2; |
| 3183 | value1 = pollwr_hdr->value_1; |
| 3184 | value2 = pollwr_hdr->value_2; |
| 3185 | |
| 3186 | poll = pollwr_hdr->poll; |
| 3187 | mask = pollwr_hdr->mask; |
| 3188 | |
| 3189 | while (wait_count < poll) { |
| 3190 | qla8044_rd_reg_indirect(vha, addr1, &r_value); |
| 3191 | |
| 3192 | if ((r_value & poll) != 0) |
| 3193 | break; |
| 3194 | wait_count++; |
| 3195 | } |
| 3196 | |
| 3197 | if (wait_count == poll) { |
| 3198 | ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__); |
| 3199 | goto error; |
| 3200 | } |
| 3201 | |
| 3202 | qla8044_wr_reg_indirect(vha, addr2, value2); |
| 3203 | qla8044_wr_reg_indirect(vha, addr1, value1); |
| 3204 | |
| 3205 | wait_count = 0; |
| 3206 | while (wait_count < poll) { |
| 3207 | qla8044_rd_reg_indirect(vha, addr1, &r_value); |
| 3208 | |
| 3209 | if ((r_value & poll) != 0) |
| 3210 | break; |
| 3211 | wait_count++; |
| 3212 | } |
| 3213 | |
| 3214 | return QLA_SUCCESS; |
| 3215 | |
| 3216 | error: |
| 3217 | return -1; |
| 3218 | } |
| 3219 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 3220 | /* |
| 3221 | * |
| 3222 | * qla8044_collect_md_data - Retrieve firmware minidump data. |
| 3223 | * @ha: pointer to adapter structure |
| 3224 | **/ |
| 3225 | int |
| 3226 | qla8044_collect_md_data(struct scsi_qla_host *vha) |
| 3227 | { |
| 3228 | int num_entry_hdr = 0; |
| 3229 | struct qla8044_minidump_entry_hdr *entry_hdr; |
| 3230 | struct qla8044_minidump_template_hdr *tmplt_hdr; |
| 3231 | uint32_t *data_ptr; |
| 3232 | uint32_t data_collected = 0, f_capture_mask; |
| 3233 | int i, rval = QLA_FUNCTION_FAILED; |
| 3234 | uint64_t now; |
| 3235 | uint32_t timestamp, idc_control; |
| 3236 | struct qla_hw_data *ha = vha->hw; |
| 3237 | |
| 3238 | if (!ha->md_dump) { |
| 3239 | ql_log(ql_log_info, vha, 0xb101, |
| 3240 | "%s(%ld) No buffer to dump\n", |
| 3241 | __func__, vha->host_no); |
| 3242 | return rval; |
| 3243 | } |
| 3244 | |
| 3245 | if (ha->fw_dumped) { |
| 3246 | ql_log(ql_log_warn, vha, 0xb10d, |
| 3247 | "Firmware has been previously dumped (%p) " |
| 3248 | "-- ignoring request.\n", ha->fw_dump); |
| 3249 | goto md_failed; |
| 3250 | } |
| 3251 | |
| 3252 | ha->fw_dumped = 0; |
| 3253 | |
| 3254 | if (!ha->md_tmplt_hdr || !ha->md_dump) { |
| 3255 | ql_log(ql_log_warn, vha, 0xb10e, |
| 3256 | "Memory not allocated for minidump capture\n"); |
| 3257 | goto md_failed; |
| 3258 | } |
| 3259 | |
| 3260 | qla8044_idc_lock(ha); |
| 3261 | idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); |
| 3262 | if (idc_control & GRACEFUL_RESET_BIT1) { |
| 3263 | ql_log(ql_log_warn, vha, 0xb112, |
| 3264 | "Forced reset from application, " |
| 3265 | "ignore minidump capture\n"); |
| 3266 | qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, |
| 3267 | (idc_control & ~GRACEFUL_RESET_BIT1)); |
| 3268 | qla8044_idc_unlock(ha); |
| 3269 | |
| 3270 | goto md_failed; |
| 3271 | } |
| 3272 | qla8044_idc_unlock(ha); |
| 3273 | |
| 3274 | if (qla82xx_validate_template_chksum(vha)) { |
| 3275 | ql_log(ql_log_info, vha, 0xb109, |
| 3276 | "Template checksum validation error\n"); |
| 3277 | goto md_failed; |
| 3278 | } |
| 3279 | |
| 3280 | tmplt_hdr = (struct qla8044_minidump_template_hdr *) |
| 3281 | ha->md_tmplt_hdr; |
| 3282 | data_ptr = (uint32_t *)((uint8_t *)ha->md_dump); |
| 3283 | num_entry_hdr = tmplt_hdr->num_of_entries; |
| 3284 | |
| 3285 | ql_dbg(ql_dbg_p3p, vha, 0xb11a, |
| 3286 | "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); |
| 3287 | |
| 3288 | f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; |
| 3289 | |
| 3290 | /* Validate whether required debug level is set */ |
| 3291 | if ((f_capture_mask & 0x3) != 0x3) { |
| 3292 | ql_log(ql_log_warn, vha, 0xb10f, |
| 3293 | "Minimum required capture mask[0x%x] level not set\n", |
| 3294 | f_capture_mask); |
| 3295 | |
| 3296 | } |
| 3297 | tmplt_hdr->driver_capture_mask = ql2xmdcapmask; |
| 3298 | ql_log(ql_log_info, vha, 0xb102, |
| 3299 | "[%s]: starting data ptr: %p\n", |
| 3300 | __func__, data_ptr); |
| 3301 | ql_log(ql_log_info, vha, 0xb10b, |
| 3302 | "[%s]: no of entry headers in Template: 0x%x\n", |
| 3303 | __func__, num_entry_hdr); |
| 3304 | ql_log(ql_log_info, vha, 0xb10c, |
| 3305 | "[%s]: Total_data_size 0x%x, %d obtained\n", |
| 3306 | __func__, ha->md_dump_size, ha->md_dump_size); |
| 3307 | |
| 3308 | /* Update current timestamp before taking dump */ |
| 3309 | now = get_jiffies_64(); |
| 3310 | timestamp = (u32)(jiffies_to_msecs(now) / 1000); |
| 3311 | tmplt_hdr->driver_timestamp = timestamp; |
| 3312 | |
| 3313 | entry_hdr = (struct qla8044_minidump_entry_hdr *) |
| 3314 | (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); |
| 3315 | tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] = |
| 3316 | tmplt_hdr->ocm_window_reg[ha->portnum]; |
| 3317 | |
| 3318 | /* Walk through the entry headers - validate/perform required action */ |
| 3319 | for (i = 0; i < num_entry_hdr; i++) { |
| 3320 | if (data_collected > ha->md_dump_size) { |
| 3321 | ql_log(ql_log_info, vha, 0xb103, |
| 3322 | "Data collected: [0x%x], " |
| 3323 | "Total Dump size: [0x%x]\n", |
| 3324 | data_collected, ha->md_dump_size); |
| 3325 | return rval; |
| 3326 | } |
| 3327 | |
| 3328 | if (!(entry_hdr->d_ctrl.entry_capture_mask & |
| 3329 | ql2xmdcapmask)) { |
| 3330 | entry_hdr->d_ctrl.driver_flags |= |
| 3331 | QLA82XX_DBG_SKIPPED_FLAG; |
| 3332 | goto skip_nxt_entry; |
| 3333 | } |
| 3334 | |
| 3335 | ql_dbg(ql_dbg_p3p, vha, 0xb104, |
| 3336 | "Data collected: [0x%x], Dump size left:[0x%x]\n", |
| 3337 | data_collected, |
| 3338 | (ha->md_dump_size - data_collected)); |
| 3339 | |
| 3340 | /* Decode the entry type and take required action to capture |
| 3341 | * debug data |
| 3342 | */ |
| 3343 | switch (entry_hdr->entry_type) { |
| 3344 | case QLA82XX_RDEND: |
| 3345 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3346 | break; |
| 3347 | case QLA82XX_CNTRL: |
| 3348 | rval = qla8044_minidump_process_control(vha, |
| 3349 | entry_hdr); |
| 3350 | if (rval != QLA_SUCCESS) { |
| 3351 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3352 | goto md_failed; |
| 3353 | } |
| 3354 | break; |
| 3355 | case QLA82XX_RDCRB: |
| 3356 | qla8044_minidump_process_rdcrb(vha, |
| 3357 | entry_hdr, &data_ptr); |
| 3358 | break; |
| 3359 | case QLA82XX_RDMEM: |
| 3360 | rval = qla8044_minidump_pex_dma_read(vha, |
| 3361 | entry_hdr, &data_ptr); |
| 3362 | if (rval != QLA_SUCCESS) { |
| 3363 | rval = qla8044_minidump_process_rdmem(vha, |
| 3364 | entry_hdr, &data_ptr); |
| 3365 | if (rval != QLA_SUCCESS) { |
| 3366 | qla8044_mark_entry_skipped(vha, |
| 3367 | entry_hdr, i); |
| 3368 | goto md_failed; |
| 3369 | } |
| 3370 | } |
| 3371 | break; |
| 3372 | case QLA82XX_BOARD: |
| 3373 | case QLA82XX_RDROM: |
| 3374 | rval = qla8044_minidump_process_rdrom(vha, |
| 3375 | entry_hdr, &data_ptr); |
| 3376 | if (rval != QLA_SUCCESS) { |
| 3377 | qla8044_mark_entry_skipped(vha, |
| 3378 | entry_hdr, i); |
| 3379 | } |
| 3380 | break; |
| 3381 | case QLA82XX_L2DTG: |
| 3382 | case QLA82XX_L2ITG: |
| 3383 | case QLA82XX_L2DAT: |
| 3384 | case QLA82XX_L2INS: |
| 3385 | rval = qla8044_minidump_process_l2tag(vha, |
| 3386 | entry_hdr, &data_ptr); |
| 3387 | if (rval != QLA_SUCCESS) { |
| 3388 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3389 | goto md_failed; |
| 3390 | } |
| 3391 | break; |
| 3392 | case QLA8044_L1DTG: |
| 3393 | case QLA8044_L1ITG: |
| 3394 | case QLA82XX_L1DAT: |
| 3395 | case QLA82XX_L1INS: |
| 3396 | qla8044_minidump_process_l1cache(vha, |
| 3397 | entry_hdr, &data_ptr); |
| 3398 | break; |
| 3399 | case QLA82XX_RDOCM: |
| 3400 | qla8044_minidump_process_rdocm(vha, |
| 3401 | entry_hdr, &data_ptr); |
| 3402 | break; |
| 3403 | case QLA82XX_RDMUX: |
| 3404 | qla8044_minidump_process_rdmux(vha, |
| 3405 | entry_hdr, &data_ptr); |
| 3406 | break; |
| 3407 | case QLA82XX_QUEUE: |
| 3408 | qla8044_minidump_process_queue(vha, |
| 3409 | entry_hdr, &data_ptr); |
| 3410 | break; |
| 3411 | case QLA8044_POLLRD: |
| 3412 | rval = qla8044_minidump_process_pollrd(vha, |
| 3413 | entry_hdr, &data_ptr); |
| 3414 | if (rval != QLA_SUCCESS) |
| 3415 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3416 | break; |
| 3417 | case QLA8044_RDMUX2: |
| 3418 | qla8044_minidump_process_rdmux2(vha, |
| 3419 | entry_hdr, &data_ptr); |
| 3420 | break; |
| 3421 | case QLA8044_POLLRDMWR: |
| 3422 | rval = qla8044_minidump_process_pollrdmwr(vha, |
| 3423 | entry_hdr, &data_ptr); |
| 3424 | if (rval != QLA_SUCCESS) |
| 3425 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3426 | break; |
Pratik Mohanty | 804df80 | 2014-04-11 16:54:15 -0400 | [diff] [blame] | 3427 | case QLA8044_RDDFE: |
| 3428 | rval = qla8044_minidump_process_rddfe(vha, entry_hdr, |
| 3429 | &data_ptr); |
| 3430 | if (rval != QLA_SUCCESS) |
| 3431 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3432 | break; |
| 3433 | case QLA8044_RDMDIO: |
| 3434 | rval = qla8044_minidump_process_rdmdio(vha, entry_hdr, |
| 3435 | &data_ptr); |
| 3436 | if (rval != QLA_SUCCESS) |
| 3437 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3438 | break; |
| 3439 | case QLA8044_POLLWR: |
| 3440 | rval = qla8044_minidump_process_pollwr(vha, entry_hdr, |
| 3441 | &data_ptr); |
| 3442 | if (rval != QLA_SUCCESS) |
| 3443 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3444 | break; |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 3445 | case QLA82XX_RDNOP: |
| 3446 | default: |
| 3447 | qla8044_mark_entry_skipped(vha, entry_hdr, i); |
| 3448 | break; |
| 3449 | } |
| 3450 | |
| 3451 | data_collected = (uint8_t *)data_ptr - |
| 3452 | (uint8_t *)((uint8_t *)ha->md_dump); |
| 3453 | skip_nxt_entry: |
| 3454 | /* |
| 3455 | * next entry in the template |
| 3456 | */ |
| 3457 | entry_hdr = (struct qla8044_minidump_entry_hdr *) |
| 3458 | (((uint8_t *)entry_hdr) + entry_hdr->entry_size); |
| 3459 | } |
| 3460 | |
| 3461 | if (data_collected != ha->md_dump_size) { |
| 3462 | ql_log(ql_log_info, vha, 0xb105, |
| 3463 | "Dump data mismatch: Data collected: " |
| 3464 | "[0x%x], total_data_size:[0x%x]\n", |
| 3465 | data_collected, ha->md_dump_size); |
Saurav Kashyap | edaa5c7 | 2014-04-11 16:54:14 -0400 | [diff] [blame] | 3466 | rval = QLA_FUNCTION_FAILED; |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 3467 | goto md_failed; |
| 3468 | } |
| 3469 | |
| 3470 | ql_log(ql_log_info, vha, 0xb110, |
| 3471 | "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", |
| 3472 | vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); |
| 3473 | ha->fw_dumped = 1; |
| 3474 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); |
| 3475 | |
| 3476 | |
| 3477 | ql_log(ql_log_info, vha, 0xb106, |
| 3478 | "Leaving fn: %s Last entry: 0x%x\n", |
| 3479 | __func__, i); |
| 3480 | md_failed: |
| 3481 | return rval; |
| 3482 | } |
| 3483 | |
| 3484 | void |
| 3485 | qla8044_get_minidump(struct scsi_qla_host *vha) |
| 3486 | { |
| 3487 | struct qla_hw_data *ha = vha->hw; |
| 3488 | |
| 3489 | if (!qla8044_collect_md_data(vha)) { |
| 3490 | ha->fw_dumped = 1; |
Saurav Kashyap | edaa5c7 | 2014-04-11 16:54:14 -0400 | [diff] [blame] | 3491 | ha->prev_minidump_failed = 0; |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 3492 | } else { |
| 3493 | ql_log(ql_log_fatal, vha, 0xb0db, |
| 3494 | "%s: Unable to collect minidump\n", |
| 3495 | __func__); |
Saurav Kashyap | edaa5c7 | 2014-04-11 16:54:14 -0400 | [diff] [blame] | 3496 | ha->prev_minidump_failed = 1; |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 3497 | } |
| 3498 | } |
| 3499 | |
| 3500 | static int |
| 3501 | qla8044_poll_flash_status_reg(struct scsi_qla_host *vha) |
| 3502 | { |
| 3503 | uint32_t flash_status; |
| 3504 | int retries = QLA8044_FLASH_READ_RETRY_COUNT; |
| 3505 | int ret_val = QLA_SUCCESS; |
| 3506 | |
| 3507 | while (retries--) { |
| 3508 | ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS, |
| 3509 | &flash_status); |
| 3510 | if (ret_val) { |
Saurav Kashyap | 6ddcfef | 2013-08-27 01:37:53 -0400 | [diff] [blame] | 3511 | ql_log(ql_log_warn, vha, 0xb13c, |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 3512 | "%s: Failed to read FLASH_STATUS reg.\n", |
| 3513 | __func__); |
| 3514 | break; |
| 3515 | } |
| 3516 | if ((flash_status & QLA8044_FLASH_STATUS_READY) == |
| 3517 | QLA8044_FLASH_STATUS_READY) |
| 3518 | break; |
| 3519 | msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY); |
| 3520 | } |
| 3521 | |
| 3522 | if (!retries) |
| 3523 | ret_val = QLA_FUNCTION_FAILED; |
| 3524 | |
| 3525 | return ret_val; |
| 3526 | } |
| 3527 | |
| 3528 | static int |
| 3529 | qla8044_write_flash_status_reg(struct scsi_qla_host *vha, |
| 3530 | uint32_t data) |
| 3531 | { |
| 3532 | int ret_val = QLA_SUCCESS; |
| 3533 | uint32_t cmd; |
| 3534 | |
| 3535 | cmd = vha->hw->fdt_wrt_sts_reg_cmd; |
| 3536 | |
| 3537 | ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, |
| 3538 | QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd); |
| 3539 | if (ret_val) { |
| 3540 | ql_log(ql_log_warn, vha, 0xb125, |
| 3541 | "%s: Failed to write to FLASH_ADDR.\n", __func__); |
| 3542 | goto exit_func; |
| 3543 | } |
| 3544 | |
| 3545 | ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data); |
| 3546 | if (ret_val) { |
| 3547 | ql_log(ql_log_warn, vha, 0xb126, |
| 3548 | "%s: Failed to write to FLASH_WRDATA.\n", __func__); |
| 3549 | goto exit_func; |
| 3550 | } |
| 3551 | |
| 3552 | ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, |
| 3553 | QLA8044_FLASH_SECOND_ERASE_MS_VAL); |
| 3554 | if (ret_val) { |
| 3555 | ql_log(ql_log_warn, vha, 0xb127, |
| 3556 | "%s: Failed to write to FLASH_CONTROL.\n", __func__); |
| 3557 | goto exit_func; |
| 3558 | } |
| 3559 | |
| 3560 | ret_val = qla8044_poll_flash_status_reg(vha); |
| 3561 | if (ret_val) |
| 3562 | ql_log(ql_log_warn, vha, 0xb128, |
| 3563 | "%s: Error polling flash status reg.\n", __func__); |
| 3564 | |
| 3565 | exit_func: |
| 3566 | return ret_val; |
| 3567 | } |
| 3568 | |
| 3569 | /* |
| 3570 | * This function assumes that the flash lock is held. |
| 3571 | */ |
| 3572 | static int |
| 3573 | qla8044_unprotect_flash(scsi_qla_host_t *vha) |
| 3574 | { |
| 3575 | int ret_val; |
| 3576 | struct qla_hw_data *ha = vha->hw; |
| 3577 | |
| 3578 | ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable); |
| 3579 | if (ret_val) |
| 3580 | ql_log(ql_log_warn, vha, 0xb139, |
| 3581 | "%s: Write flash status failed.\n", __func__); |
| 3582 | |
| 3583 | return ret_val; |
| 3584 | } |
| 3585 | |
| 3586 | /* |
| 3587 | * This function assumes that the flash lock is held. |
| 3588 | */ |
| 3589 | static int |
| 3590 | qla8044_protect_flash(scsi_qla_host_t *vha) |
| 3591 | { |
| 3592 | int ret_val; |
| 3593 | struct qla_hw_data *ha = vha->hw; |
| 3594 | |
| 3595 | ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable); |
| 3596 | if (ret_val) |
| 3597 | ql_log(ql_log_warn, vha, 0xb13b, |
| 3598 | "%s: Write flash status failed.\n", __func__); |
| 3599 | |
| 3600 | return ret_val; |
| 3601 | } |
| 3602 | |
| 3603 | |
| 3604 | static int |
| 3605 | qla8044_erase_flash_sector(struct scsi_qla_host *vha, |
| 3606 | uint32_t sector_start_addr) |
| 3607 | { |
| 3608 | uint32_t reversed_addr; |
| 3609 | int ret_val = QLA_SUCCESS; |
| 3610 | |
| 3611 | ret_val = qla8044_poll_flash_status_reg(vha); |
| 3612 | if (ret_val) { |
| 3613 | ql_log(ql_log_warn, vha, 0xb12e, |
| 3614 | "%s: Poll flash status after erase failed..\n", __func__); |
| 3615 | } |
| 3616 | |
| 3617 | reversed_addr = (((sector_start_addr & 0xFF) << 16) | |
| 3618 | (sector_start_addr & 0xFF00) | |
| 3619 | ((sector_start_addr & 0xFF0000) >> 16)); |
| 3620 | |
| 3621 | ret_val = qla8044_wr_reg_indirect(vha, |
| 3622 | QLA8044_FLASH_WRDATA, reversed_addr); |
| 3623 | if (ret_val) { |
| 3624 | ql_log(ql_log_warn, vha, 0xb12f, |
| 3625 | "%s: Failed to write to FLASH_WRDATA.\n", __func__); |
| 3626 | } |
| 3627 | ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, |
| 3628 | QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd); |
| 3629 | if (ret_val) { |
| 3630 | ql_log(ql_log_warn, vha, 0xb130, |
| 3631 | "%s: Failed to write to FLASH_ADDR.\n", __func__); |
| 3632 | } |
| 3633 | ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, |
| 3634 | QLA8044_FLASH_LAST_ERASE_MS_VAL); |
| 3635 | if (ret_val) { |
| 3636 | ql_log(ql_log_warn, vha, 0xb131, |
| 3637 | "%s: Failed write to FLASH_CONTROL.\n", __func__); |
| 3638 | } |
| 3639 | ret_val = qla8044_poll_flash_status_reg(vha); |
| 3640 | if (ret_val) { |
| 3641 | ql_log(ql_log_warn, vha, 0xb132, |
| 3642 | "%s: Poll flash status failed.\n", __func__); |
| 3643 | } |
| 3644 | |
| 3645 | |
| 3646 | return ret_val; |
| 3647 | } |
| 3648 | |
| 3649 | /* |
| 3650 | * qla8044_flash_write_u32 - Write data to flash |
| 3651 | * |
| 3652 | * @ha : Pointer to adapter structure |
| 3653 | * addr : Flash address to write to |
| 3654 | * p_data : Data to be written |
| 3655 | * |
| 3656 | * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED |
| 3657 | * |
| 3658 | * NOTE: Lock should be held on entry |
| 3659 | */ |
| 3660 | static int |
| 3661 | qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr, |
| 3662 | uint32_t *p_data) |
| 3663 | { |
| 3664 | int ret_val = QLA_SUCCESS; |
| 3665 | |
| 3666 | ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, |
| 3667 | 0x00800000 | (addr >> 2)); |
| 3668 | if (ret_val) { |
| 3669 | ql_log(ql_log_warn, vha, 0xb134, |
| 3670 | "%s: Failed write to FLASH_ADDR.\n", __func__); |
| 3671 | goto exit_func; |
| 3672 | } |
| 3673 | ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data); |
| 3674 | if (ret_val) { |
| 3675 | ql_log(ql_log_warn, vha, 0xb135, |
| 3676 | "%s: Failed write to FLASH_WRDATA.\n", __func__); |
| 3677 | goto exit_func; |
| 3678 | } |
| 3679 | ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D); |
| 3680 | if (ret_val) { |
| 3681 | ql_log(ql_log_warn, vha, 0xb136, |
| 3682 | "%s: Failed write to FLASH_CONTROL.\n", __func__); |
| 3683 | goto exit_func; |
| 3684 | } |
| 3685 | ret_val = qla8044_poll_flash_status_reg(vha); |
| 3686 | if (ret_val) { |
| 3687 | ql_log(ql_log_warn, vha, 0xb137, |
| 3688 | "%s: Poll flash status failed.\n", __func__); |
| 3689 | } |
| 3690 | |
| 3691 | exit_func: |
| 3692 | return ret_val; |
| 3693 | } |
| 3694 | |
| 3695 | static int |
| 3696 | qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr, |
| 3697 | uint32_t faddr, uint32_t dwords) |
| 3698 | { |
| 3699 | int ret = QLA_FUNCTION_FAILED; |
| 3700 | uint32_t spi_val; |
| 3701 | |
| 3702 | if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS || |
| 3703 | dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) { |
| 3704 | ql_dbg(ql_dbg_user, vha, 0xb123, |
| 3705 | "Got unsupported dwords = 0x%x.\n", |
| 3706 | dwords); |
| 3707 | return QLA_FUNCTION_FAILED; |
| 3708 | } |
| 3709 | |
| 3710 | qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val); |
| 3711 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, |
| 3712 | spi_val | QLA8044_FLASH_SPI_CTL); |
| 3713 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, |
| 3714 | QLA8044_FLASH_FIRST_TEMP_VAL); |
| 3715 | |
| 3716 | /* First DWORD write to FLASH_WRDATA */ |
| 3717 | ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, |
| 3718 | *dwptr++); |
| 3719 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, |
| 3720 | QLA8044_FLASH_FIRST_MS_PATTERN); |
| 3721 | |
| 3722 | ret = qla8044_poll_flash_status_reg(vha); |
| 3723 | if (ret) { |
| 3724 | ql_log(ql_log_warn, vha, 0xb124, |
| 3725 | "%s: Failed.\n", __func__); |
| 3726 | goto exit_func; |
| 3727 | } |
| 3728 | |
| 3729 | dwords--; |
| 3730 | |
| 3731 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, |
| 3732 | QLA8044_FLASH_SECOND_TEMP_VAL); |
| 3733 | |
| 3734 | |
| 3735 | /* Second to N-1 DWORDS writes */ |
| 3736 | while (dwords != 1) { |
| 3737 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++); |
| 3738 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, |
| 3739 | QLA8044_FLASH_SECOND_MS_PATTERN); |
| 3740 | ret = qla8044_poll_flash_status_reg(vha); |
| 3741 | if (ret) { |
| 3742 | ql_log(ql_log_warn, vha, 0xb129, |
| 3743 | "%s: Failed.\n", __func__); |
| 3744 | goto exit_func; |
| 3745 | } |
| 3746 | dwords--; |
| 3747 | } |
| 3748 | |
| 3749 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, |
| 3750 | QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2)); |
| 3751 | |
| 3752 | /* Last DWORD write */ |
| 3753 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++); |
| 3754 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, |
| 3755 | QLA8044_FLASH_LAST_MS_PATTERN); |
| 3756 | ret = qla8044_poll_flash_status_reg(vha); |
| 3757 | if (ret) { |
| 3758 | ql_log(ql_log_warn, vha, 0xb12a, |
| 3759 | "%s: Failed.\n", __func__); |
| 3760 | goto exit_func; |
| 3761 | } |
| 3762 | qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val); |
| 3763 | |
| 3764 | if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) { |
| 3765 | ql_log(ql_log_warn, vha, 0xb12b, |
| 3766 | "%s: Failed.\n", __func__); |
| 3767 | spi_val = 0; |
| 3768 | /* Operation failed, clear error bit. */ |
| 3769 | qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, |
| 3770 | &spi_val); |
| 3771 | qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, |
| 3772 | spi_val | QLA8044_FLASH_SPI_CTL); |
| 3773 | } |
| 3774 | exit_func: |
| 3775 | return ret; |
| 3776 | } |
| 3777 | |
| 3778 | static int |
| 3779 | qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr, |
| 3780 | uint32_t faddr, uint32_t dwords) |
| 3781 | { |
| 3782 | int ret = QLA_FUNCTION_FAILED; |
| 3783 | uint32_t liter; |
| 3784 | |
| 3785 | for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { |
| 3786 | ret = qla8044_flash_write_u32(vha, faddr, dwptr); |
| 3787 | if (ret) { |
| 3788 | ql_dbg(ql_dbg_p3p, vha, 0xb141, |
| 3789 | "%s: flash address=%x data=%x.\n", __func__, |
| 3790 | faddr, *dwptr); |
| 3791 | break; |
| 3792 | } |
| 3793 | } |
| 3794 | |
| 3795 | return ret; |
| 3796 | } |
| 3797 | |
| 3798 | int |
| 3799 | qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
| 3800 | uint32_t offset, uint32_t length) |
| 3801 | { |
| 3802 | int rval = QLA_FUNCTION_FAILED, i, burst_iter_count; |
| 3803 | int dword_count, erase_sec_count; |
| 3804 | uint32_t erase_offset; |
| 3805 | uint8_t *p_cache, *p_src; |
| 3806 | |
| 3807 | erase_offset = offset; |
| 3808 | |
| 3809 | p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL); |
| 3810 | if (!p_cache) |
| 3811 | return QLA_FUNCTION_FAILED; |
| 3812 | |
| 3813 | memcpy(p_cache, buf, length); |
| 3814 | p_src = p_cache; |
| 3815 | dword_count = length / sizeof(uint32_t); |
| 3816 | /* Since the offset and legth are sector aligned, it will be always |
| 3817 | * multiple of burst_iter_count (64) |
| 3818 | */ |
| 3819 | burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS; |
| 3820 | erase_sec_count = length / QLA8044_SECTOR_SIZE; |
| 3821 | |
| 3822 | /* Suspend HBA. */ |
| 3823 | scsi_block_requests(vha->host); |
| 3824 | /* Lock and enable write for whole operation. */ |
| 3825 | qla8044_flash_lock(vha); |
| 3826 | qla8044_unprotect_flash(vha); |
| 3827 | |
| 3828 | /* Erasing the sectors */ |
| 3829 | for (i = 0; i < erase_sec_count; i++) { |
| 3830 | rval = qla8044_erase_flash_sector(vha, erase_offset); |
| 3831 | ql_dbg(ql_dbg_user, vha, 0xb138, |
| 3832 | "Done erase of sector=0x%x.\n", |
| 3833 | erase_offset); |
| 3834 | if (rval) { |
| 3835 | ql_log(ql_log_warn, vha, 0xb121, |
| 3836 | "Failed to erase the sector having address: " |
| 3837 | "0x%x.\n", erase_offset); |
| 3838 | goto out; |
| 3839 | } |
| 3840 | erase_offset += QLA8044_SECTOR_SIZE; |
| 3841 | } |
Saurav Kashyap | 6ddcfef | 2013-08-27 01:37:53 -0400 | [diff] [blame] | 3842 | ql_dbg(ql_dbg_user, vha, 0xb13f, |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 3843 | "Got write for addr = 0x%x length=0x%x.\n", |
| 3844 | offset, length); |
| 3845 | |
| 3846 | for (i = 0; i < burst_iter_count; i++) { |
| 3847 | |
| 3848 | /* Go with write. */ |
| 3849 | rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src, |
| 3850 | offset, QLA8044_MAX_OPTROM_BURST_DWORDS); |
| 3851 | if (rval) { |
| 3852 | /* Buffer Mode failed skip to dword mode */ |
| 3853 | ql_log(ql_log_warn, vha, 0xb122, |
| 3854 | "Failed to write flash in buffer mode, " |
| 3855 | "Reverting to slow-write.\n"); |
| 3856 | rval = qla8044_write_flash_dword_mode(vha, |
| 3857 | (uint32_t *)p_src, offset, |
| 3858 | QLA8044_MAX_OPTROM_BURST_DWORDS); |
| 3859 | } |
| 3860 | p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; |
| 3861 | offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; |
| 3862 | } |
| 3863 | ql_dbg(ql_dbg_user, vha, 0xb133, |
| 3864 | "Done writing.\n"); |
| 3865 | |
| 3866 | out: |
| 3867 | qla8044_protect_flash(vha); |
| 3868 | qla8044_flash_unlock(vha); |
| 3869 | scsi_unblock_requests(vha->host); |
| 3870 | kfree(p_cache); |
| 3871 | |
| 3872 | return rval; |
| 3873 | } |
| 3874 | |
| 3875 | #define LEG_INT_PTR_B31 (1 << 31) |
| 3876 | #define LEG_INT_PTR_B30 (1 << 30) |
| 3877 | #define PF_BITS_MASK (0xF << 16) |
| 3878 | /** |
| 3879 | * qla8044_intr_handler() - Process interrupts for the ISP8044 |
| 3880 | * @irq: |
| 3881 | * @dev_id: SCSI driver HA context |
| 3882 | * |
| 3883 | * Called by system whenever the host adapter generates an interrupt. |
| 3884 | * |
| 3885 | * Returns handled flag. |
| 3886 | */ |
| 3887 | irqreturn_t |
| 3888 | qla8044_intr_handler(int irq, void *dev_id) |
| 3889 | { |
| 3890 | scsi_qla_host_t *vha; |
| 3891 | struct qla_hw_data *ha; |
| 3892 | struct rsp_que *rsp; |
| 3893 | struct device_reg_82xx __iomem *reg; |
| 3894 | int status = 0; |
| 3895 | unsigned long flags; |
| 3896 | unsigned long iter; |
| 3897 | uint32_t stat; |
| 3898 | uint16_t mb[4]; |
| 3899 | uint32_t leg_int_ptr = 0, pf_bit; |
| 3900 | |
| 3901 | rsp = (struct rsp_que *) dev_id; |
| 3902 | if (!rsp) { |
| 3903 | ql_log(ql_log_info, NULL, 0xb143, |
| 3904 | "%s(): NULL response queue pointer\n", __func__); |
| 3905 | return IRQ_NONE; |
| 3906 | } |
| 3907 | ha = rsp->hw; |
| 3908 | vha = pci_get_drvdata(ha->pdev); |
| 3909 | |
| 3910 | if (unlikely(pci_channel_offline(ha->pdev))) |
| 3911 | return IRQ_HANDLED; |
| 3912 | |
| 3913 | leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET); |
| 3914 | |
| 3915 | /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */ |
| 3916 | if (!(leg_int_ptr & (LEG_INT_PTR_B31))) { |
| 3917 | ql_dbg(ql_dbg_p3p, vha, 0xb144, |
| 3918 | "%s: Legacy Interrupt Bit 31 not set, " |
| 3919 | "spurious interrupt!\n", __func__); |
| 3920 | return IRQ_NONE; |
| 3921 | } |
| 3922 | |
| 3923 | pf_bit = ha->portnum << 16; |
| 3924 | /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */ |
| 3925 | if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) { |
| 3926 | ql_dbg(ql_dbg_p3p, vha, 0xb145, |
| 3927 | "%s: Incorrect function ID 0x%x in " |
| 3928 | "legacy interrupt register, " |
| 3929 | "ha->pf_bit = 0x%x\n", __func__, |
| 3930 | (leg_int_ptr & (PF_BITS_MASK)), pf_bit); |
| 3931 | return IRQ_NONE; |
| 3932 | } |
| 3933 | |
| 3934 | /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger |
| 3935 | * Control register and poll till Legacy Interrupt Pointer register |
| 3936 | * bit32 is 0. |
| 3937 | */ |
| 3938 | qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0); |
| 3939 | do { |
| 3940 | leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET); |
| 3941 | if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) |
| 3942 | break; |
| 3943 | } while (leg_int_ptr & (LEG_INT_PTR_B30)); |
| 3944 | |
| 3945 | reg = &ha->iobase->isp82; |
| 3946 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 3947 | for (iter = 1; iter--; ) { |
| 3948 | |
| 3949 | if (RD_REG_DWORD(®->host_int)) { |
| 3950 | stat = RD_REG_DWORD(®->host_status); |
| 3951 | if ((stat & HSRX_RISC_INT) == 0) |
| 3952 | break; |
| 3953 | |
| 3954 | switch (stat & 0xff) { |
| 3955 | case 0x1: |
| 3956 | case 0x2: |
| 3957 | case 0x10: |
| 3958 | case 0x11: |
| 3959 | qla82xx_mbx_completion(vha, MSW(stat)); |
| 3960 | status |= MBX_INTERRUPT; |
| 3961 | break; |
| 3962 | case 0x12: |
| 3963 | mb[0] = MSW(stat); |
| 3964 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); |
| 3965 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); |
| 3966 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); |
| 3967 | qla2x00_async_event(vha, rsp, mb); |
| 3968 | break; |
| 3969 | case 0x13: |
| 3970 | qla24xx_process_response_queue(vha, rsp); |
| 3971 | break; |
| 3972 | default: |
| 3973 | ql_dbg(ql_dbg_p3p, vha, 0xb146, |
| 3974 | "Unrecognized interrupt type " |
| 3975 | "(%d).\n", stat & 0xff); |
| 3976 | break; |
| 3977 | } |
| 3978 | } |
| 3979 | WRT_REG_DWORD(®->host_int, 0); |
| 3980 | } |
| 3981 | |
| 3982 | qla2x00_handle_mbx_completion(ha, status); |
| 3983 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 3984 | |
| 3985 | return IRQ_HANDLED; |
| 3986 | } |
| 3987 | |
| 3988 | static int |
| 3989 | qla8044_idc_dontreset(struct qla_hw_data *ha) |
| 3990 | { |
| 3991 | uint32_t idc_ctrl; |
| 3992 | |
| 3993 | idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); |
| 3994 | return idc_ctrl & DONTRESET_BIT0; |
| 3995 | } |
| 3996 | |
| 3997 | static void |
| 3998 | qla8044_clear_rst_ready(scsi_qla_host_t *vha) |
| 3999 | { |
| 4000 | uint32_t drv_state; |
| 4001 | |
| 4002 | drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); |
| 4003 | |
| 4004 | /* |
| 4005 | * For ISP8044, drv_active register has 1 bit per function, |
| 4006 | * shift 1 by func_num to set a bit for the function. |
| 4007 | * For ISP82xx, drv_active has 4 bits per function |
| 4008 | */ |
| 4009 | drv_state &= ~(1 << vha->hw->portnum); |
| 4010 | |
Saurav Kashyap | 6ddcfef | 2013-08-27 01:37:53 -0400 | [diff] [blame] | 4011 | ql_dbg(ql_dbg_p3p, vha, 0xb13d, |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 4012 | "drv_state: 0x%08x\n", drv_state); |
| 4013 | qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state); |
| 4014 | } |
| 4015 | |
| 4016 | int |
| 4017 | qla8044_abort_isp(scsi_qla_host_t *vha) |
| 4018 | { |
| 4019 | int rval; |
| 4020 | uint32_t dev_state; |
| 4021 | struct qla_hw_data *ha = vha->hw; |
| 4022 | |
| 4023 | qla8044_idc_lock(ha); |
| 4024 | dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); |
| 4025 | |
| 4026 | if (ql2xdontresethba) |
| 4027 | qla8044_set_idc_dontreset(vha); |
| 4028 | |
| 4029 | /* If device_state is NEED_RESET, go ahead with |
| 4030 | * Reset,irrespective of ql2xdontresethba. This is to allow a |
| 4031 | * non-reset-owner to force a reset. Non-reset-owner sets |
| 4032 | * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset |
| 4033 | * and then forces a Reset by setting device_state to |
| 4034 | * NEED_RESET. */ |
| 4035 | if (dev_state == QLA8XXX_DEV_READY) { |
| 4036 | /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset |
| 4037 | * recovery */ |
| 4038 | if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) { |
Saurav Kashyap | 6ddcfef | 2013-08-27 01:37:53 -0400 | [diff] [blame] | 4039 | ql_dbg(ql_dbg_p3p, vha, 0xb13e, |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 4040 | "Reset recovery disabled\n"); |
| 4041 | rval = QLA_FUNCTION_FAILED; |
| 4042 | goto exit_isp_reset; |
| 4043 | } |
| 4044 | |
Saurav Kashyap | 6ddcfef | 2013-08-27 01:37:53 -0400 | [diff] [blame] | 4045 | ql_dbg(ql_dbg_p3p, vha, 0xb140, |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 4046 | "HW State: NEED RESET\n"); |
| 4047 | qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, |
| 4048 | QLA8XXX_DEV_NEED_RESET); |
| 4049 | } |
| 4050 | |
| 4051 | /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority |
| 4052 | * and which drivers are present. Unlike ISP82XX, the function setting |
| 4053 | * NEED_RESET, may not be the Reset owner. */ |
| 4054 | qla83xx_reset_ownership(vha); |
| 4055 | |
| 4056 | qla8044_idc_unlock(ha); |
| 4057 | rval = qla8044_device_state_handler(vha); |
| 4058 | qla8044_idc_lock(ha); |
| 4059 | qla8044_clear_rst_ready(vha); |
| 4060 | |
| 4061 | exit_isp_reset: |
| 4062 | qla8044_idc_unlock(ha); |
| 4063 | if (rval == QLA_SUCCESS) { |
| 4064 | ha->flags.isp82xx_fw_hung = 0; |
| 4065 | ha->flags.nic_core_reset_hdlr_active = 0; |
| 4066 | rval = qla82xx_restart_isp(vha); |
| 4067 | } |
| 4068 | |
| 4069 | return rval; |
| 4070 | } |
| 4071 | |
Chad Dupuis | a1b23c5 | 2014-02-26 04:15:12 -0500 | [diff] [blame] | 4072 | void |
| 4073 | qla8044_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 4074 | { |
| 4075 | struct qla_hw_data *ha = vha->hw; |
| 4076 | |
| 4077 | if (!ha->allow_cna_fw_dump) |
| 4078 | return; |
| 4079 | |
| 4080 | scsi_block_requests(vha->host); |
| 4081 | ha->flags.isp82xx_no_md_cap = 1; |
| 4082 | qla8044_idc_lock(ha); |
| 4083 | qla82xx_set_reset_owner(vha); |
| 4084 | qla8044_idc_unlock(ha); |
| 4085 | qla2x00_wait_for_chip_reset(vha); |
| 4086 | scsi_unblock_requests(vha->host); |
| 4087 | } |