blob: fd60940e40636949aba4aa23e5ca5acd7efdf7ea [file] [log] [blame]
Marc Dietrichcc2afa42011-11-01 10:37:05 +00001/dts-v1/;
2
Marc Dietrichcc2afa42011-11-01 10:37:05 +00003/include/ "tegra20.dtsi"
4
5/ {
6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Marc Dietrichcc2afa42011-11-01 10:37:05 +000010 reg = <0x00000000 0x20000000>;
11 };
12
Stephen Warren11a3c862013-01-02 14:53:22 -070013 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060025 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060026 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata", "atc", "atd", "ate",
32 "dap2", "gmb", "gmc", "gmd", "spia",
33 "spib", "spic", "spid", "spie";
34 nvidia,function = "gmi";
35 };
36 atb {
37 nvidia,pins = "atb", "gma", "gme";
38 nvidia,function = "sdio4";
39 };
40 cdev1 {
41 nvidia,pins = "cdev1";
42 nvidia,function = "plla_out";
43 };
44 cdev2 {
45 nvidia,pins = "cdev2";
46 nvidia,function = "pllp_out4";
47 };
48 crtp {
49 nvidia,pins = "crtp";
50 nvidia,function = "crt";
51 };
52 csus {
53 nvidia,pins = "csus";
54 nvidia,function = "pllc_out1";
55 };
56 dap1 {
57 nvidia,pins = "dap1";
58 nvidia,function = "dap1";
59 };
60 dap3 {
61 nvidia,pins = "dap3";
62 nvidia,function = "dap3";
63 };
64 dap4 {
65 nvidia,pins = "dap4";
66 nvidia,function = "dap4";
67 };
68 ddc {
69 nvidia,pins = "ddc";
70 nvidia,function = "i2c2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "rsvd1";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gpu {
81 nvidia,pins = "gpu", "sdb", "sdd";
82 nvidia,function = "pwm";
83 };
84 gpu7 {
85 nvidia,pins = "gpu7";
86 nvidia,function = "rtck";
87 };
88 gpv {
89 nvidia,pins = "gpv", "slxa", "slxk";
90 nvidia,function = "pcie";
91 };
92 hdint {
93 nvidia,pins = "hdint", "pta";
94 nvidia,function = "hdmi";
95 };
96 i2cp {
97 nvidia,pins = "i2cp";
98 nvidia,function = "i2cp";
99 };
100 irrx {
101 nvidia,pins = "irrx", "irtx";
102 nvidia,function = "uarta";
103 };
104 kbca {
105 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
106 nvidia,function = "kbc";
107 };
108 kbcb {
109 nvidia,pins = "kbcb", "kbcd";
110 nvidia,function = "sdio2";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
114 "ld3", "ld4", "ld5", "ld6", "ld7",
115 "ld8", "ld9", "ld10", "ld11", "ld12",
116 "ld13", "ld14", "ld15", "ld16", "ld17",
117 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
118 "lhs", "lm0", "lm1", "lpp", "lpw0",
119 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
120 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
121 "lvs";
122 nvidia,function = "displaya";
123 };
124 owc {
125 nvidia,pins = "owc";
126 nvidia,function = "owr";
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 };
132 rm {
133 nvidia,pins = "rm";
134 nvidia,function = "i2c1";
135 };
136 sdc {
137 nvidia,pins = "sdc";
138 nvidia,function = "twc";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 slxc {
145 nvidia,pins = "slxc", "slxd";
146 nvidia,function = "spi4";
147 };
148 spdi {
149 nvidia,pins = "spdi", "spdo";
150 nvidia,function = "rsvd2";
151 };
152 spif {
153 nvidia,pins = "spif", "uac";
154 nvidia,function = "rsvd4";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "spdif";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600174 "cdev1", "cdev2", "dap1", "dap2", "dtf",
175 "gma", "gmb", "gmc", "gmd", "gme",
176 "gpu", "gpu7", "gpv", "i2cp", "pta",
177 "rm", "sdio1", "slxk", "spdo", "uac",
178 "uda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600179 nvidia,pull = <0>;
180 nvidia,tristate = <0>;
181 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600182 conf_ck32 {
183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
184 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
185 nvidia,pull = <0>;
186 };
187 conf_crtp {
188 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
189 "dtc", "dte", "slxa", "slxc", "slxd",
190 "spdi";
191 nvidia,pull = <0>;
192 nvidia,tristate = <1>;
193 };
194 conf_csus {
195 nvidia,pins = "csus", "spia", "spib", "spid",
196 "spif";
197 nvidia,pull = <1>;
198 nvidia,tristate = <1>;
199 };
200 conf_ddc {
201 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
202 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
203 "spic", "spig", "uaa", "uab";
204 nvidia,pull = <2>;
205 nvidia,tristate = <0>;
206 };
207 conf_dta {
208 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
209 "spie", "spih", "uad", "uca", "ucb";
210 nvidia,pull = <2>;
211 nvidia,tristate = <1>;
212 };
213 conf_hdint {
214 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
215 "ld3", "ld4", "ld5", "ld6", "ld7",
216 "ld8", "ld9", "ld10", "ld11", "ld12",
217 "ld13", "ld14", "ld15", "ld16", "ld17",
218 "ldc", "ldi", "lhs", "lsc0", "lspi",
219 "lvs", "pmc";
220 nvidia,tristate = <0>;
221 };
222 conf_lc {
223 nvidia,pins = "lc", "ls";
224 nvidia,pull = <2>;
225 };
226 conf_lcsn {
227 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
228 "lm0", "lm1", "lpp", "lpw0", "lpw1",
229 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
230 "lvp0", "lvp1", "sdb";
231 nvidia,tristate = <1>;
232 };
233 conf_ld17_0 {
234 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
235 "ld23_22";
236 nvidia,pull = <1>;
237 };
238 };
239 };
240
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600241 i2s@70002800 {
242 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600243 };
244
245 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600246 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600247 };
248
Stephen Warrenc04abb32012-05-11 17:03:26 -0600249 serial@70006200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600250 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600251 };
252
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000253 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600254 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000255 clock-frequency = <400000>;
Leon Romanovsky613e9652012-02-02 22:13:35 +0200256
257 alc5632: alc5632@1e {
258 compatible = "realtek,alc5632";
259 reg = <0x1e>;
260 gpio-controller;
261 #gpio-cells = <2>;
262 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000263 };
264
Stephen Warren11a3c862013-01-02 14:53:22 -0700265 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600266 status = "okay";
Stephen Warren11a3c862013-01-02 14:53:22 -0700267 clock-frequency = <100000>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000268 };
269
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600270 nvec {
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000271 compatible = "nvidia,nvec";
Stephen Warrenba04c282012-05-11 16:28:59 -0600272 reg = <0x7000c500 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700273 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600274 #address-cells = <1>;
275 #size-cells = <0>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000276 clock-frequency = <80000>;
Stephen Warrenc44e4382012-05-11 16:21:10 -0600277 request-gpios = <&gpio 170 0>; /* gpio PV2 */
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000278 slave-addr = <138>;
Prashant Gaikwadd409b3a2013-01-11 13:31:23 +0530279 clocks = <&tegra_car 67>, <&tegra_car 124>;
280 clock-names = "div-clk", "fast-clk";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000281 };
282
283 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600284 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000285 clock-frequency = <400000>;
Marc Dietrich1266f892012-01-31 19:53:21 +0100286
Stephen Warren217b8f02012-06-21 14:24:57 -0600287 pmic: tps6586x@34 {
288 compatible = "ti,tps6586x";
289 reg = <0x34>;
290 interrupts = <0 86 0x4>;
291
292 #gpio-cells = <2>;
293 gpio-controller;
294
295 sys-supply = <&p5valw_reg>;
296 vin-sm0-supply = <&sys_reg>;
297 vin-sm1-supply = <&sys_reg>;
298 vin-sm2-supply = <&sys_reg>;
299 vinldo01-supply = <&sm2_reg>;
300 vinldo23-supply = <&sm2_reg>;
301 vinldo4-supply = <&sm2_reg>;
302 vinldo678-supply = <&sm2_reg>;
303 vinldo9-supply = <&sm2_reg>;
304
305 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600306 sys_reg: sys {
Stephen Warren217b8f02012-06-21 14:24:57 -0600307 regulator-name = "vdd_sys";
308 regulator-always-on;
309 };
310
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600311 sm0 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600312 regulator-name = "+1.2vs_sm0,vdd_core";
313 regulator-min-microvolt = <1200000>;
314 regulator-max-microvolt = <1200000>;
315 regulator-always-on;
316 };
317
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600318 sm1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600319 regulator-name = "+1.0vs_sm1,vdd_cpu";
320 regulator-min-microvolt = <1000000>;
321 regulator-max-microvolt = <1000000>;
322 regulator-always-on;
323 };
324
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600325 sm2_reg: sm2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600326 regulator-name = "+3.7vs_sm2,vin_ldo*";
327 regulator-min-microvolt = <3700000>;
328 regulator-max-microvolt = <3700000>;
329 regulator-always-on;
330 };
331
332 /* LDO0 is not connected to anything */
333
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600334 ldo1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600335 regulator-name = "+1.1vs_ldo1,avdd_pll*";
336 regulator-min-microvolt = <1100000>;
337 regulator-max-microvolt = <1100000>;
338 regulator-always-on;
339 };
340
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600341 ldo2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600342 regulator-name = "+1.2vs_ldo2,vdd_rtc";
343 regulator-min-microvolt = <1200000>;
344 regulator-max-microvolt = <1200000>;
345 };
346
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600347 ldo3 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600348 regulator-name = "+3.3vs_ldo3,avdd_usb*";
349 regulator-min-microvolt = <3300000>;
350 regulator-max-microvolt = <3300000>;
351 regulator-always-on;
352 };
353
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600354 ldo4 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600355 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
356 regulator-min-microvolt = <1800000>;
357 regulator-max-microvolt = <1800000>;
358 regulator-always-on;
359 };
360
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600361 ldo5 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600362 regulator-name = "+2.85vs_ldo5,vcore_mmc";
363 regulator-min-microvolt = <2850000>;
364 regulator-max-microvolt = <2850000>;
365 regulator-always-on;
366 };
367
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600368 ldo6 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600369 /*
370 * Research indicates this should be
371 * 1.8v; other boards that use this
372 * rail for the same purpose need it
373 * set to 1.8v. The schematic signal
374 * name is incorrect; perhaps copied
375 * from an incorrect NVIDIA reference.
376 */
377 regulator-name = "+2.85vs_ldo6,avdd_vdac";
378 regulator-min-microvolt = <1800000>;
379 regulator-max-microvolt = <1800000>;
380 };
381
Stephen Warren11a3c862013-01-02 14:53:22 -0700382 hdmi_vdd_reg: ldo7 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600383 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
384 regulator-min-microvolt = <3300000>;
385 regulator-max-microvolt = <3300000>;
386 };
387
Stephen Warren11a3c862013-01-02 14:53:22 -0700388 hdmi_pll_reg: ldo8 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600389 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <1800000>;
392 };
393
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600394 ldo9 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600395 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
396 regulator-min-microvolt = <2850000>;
397 regulator-max-microvolt = <2850000>;
398 regulator-always-on;
399 };
400
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600401 ldo_rtc {
Stephen Warren217b8f02012-06-21 14:24:57 -0600402 regulator-name = "+3.3vs_rtc";
403 regulator-min-microvolt = <3300000>;
404 regulator-max-microvolt = <3300000>;
405 regulator-always-on;
406 };
407 };
408 };
409
Marc Dietrich1266f892012-01-31 19:53:21 +0100410 adt7461@4c {
411 compatible = "adi,adt7461";
412 reg = <0x4c>;
413 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000414 };
415
Stephen Warren217b8f02012-06-21 14:24:57 -0600416 pmc {
417 nvidia,invert-interrupt;
418 };
419
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600420 usb@c5000000 {
421 status = "okay";
422 };
423
Stephen Warrenc04abb32012-05-11 17:03:26 -0600424 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600425 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600426 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000427 };
428
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600429 usb@c5008000 {
430 status = "okay";
431 };
432
Venu Byravarasu40e8b3a2013-01-24 15:46:46 +0530433 usb-phy@c5004400 {
434 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
435 };
436
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000437 sdhci@c8000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600438 status = "okay";
Joseph Lo908ab932013-02-22 11:23:39 +0800439 cd-gpios = <&gpio 173 1>; /* gpio PV5 */
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000440 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
Marc Dietrich5f21f122012-01-28 20:03:04 +0100441 power-gpios = <&gpio 169 0>; /* gpio PV1 */
Arnd Bergmann7f217792012-05-13 00:14:24 -0400442 bus-width = <4>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000443 };
444
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000445 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600446 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400447 bus-width = <8>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000448 };
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100449
Joseph Lo7021d122013-04-03 19:31:27 +0800450 clocks {
451 compatible = "simple-bus";
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 clk32k_in: clock {
456 compatible = "fixed-clock";
457 reg=<0>;
458 #clock-cells = <0>;
459 clock-frequency = <32768>;
460 };
461 };
462
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100463 gpio-keys {
464 compatible = "gpio-keys";
465
466 power {
467 label = "Power";
468 gpios = <&gpio 79 1>; /* gpio PJ7, active low */
469 linux,code = <116>; /* KEY_POWER */
470 gpio-key,wakeup;
471 };
472 };
Marc Dietrich80c94732012-01-28 20:03:08 +0100473
474 gpio-leds {
475 compatible = "gpio-leds";
476
477 wifi {
478 label = "wifi-led";
Stephen Warrenc44e4382012-05-11 16:21:10 -0600479 gpios = <&gpio 24 0>; /* gpio PD0 */
Marc Dietrich80c94732012-01-28 20:03:08 +0100480 linux,default-trigger = "rfkill0";
481 };
482 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600483
Stephen Warren217b8f02012-06-21 14:24:57 -0600484 regulators {
485 compatible = "simple-bus";
486 #address-cells = <1>;
487 #size-cells = <0>;
488
489 p5valw_reg: regulator@0 {
490 compatible = "regulator-fixed";
491 reg = <0>;
492 regulator-name = "+5valw";
493 regulator-min-microvolt = <5000000>;
494 regulator-max-microvolt = <5000000>;
495 regulator-always-on;
496 };
497 };
498
Stephen Warrenc04abb32012-05-11 17:03:26 -0600499 sound {
500 compatible = "nvidia,tegra-audio-alc5632-paz00",
501 "nvidia,tegra-audio-alc5632";
502
503 nvidia,model = "Compal PAZ00";
504
505 nvidia,audio-routing =
506 "Int Spk", "SPKOUT",
507 "Int Spk", "SPKOUTN",
508 "Headset Mic", "MICBIAS1",
509 "MIC1", "Headset Mic",
510 "Headset Stereophone", "HPR",
511 "Headset Stereophone", "HPL",
512 "DMICDAT", "Digital Mic";
513
514 nvidia,audio-codec = <&alc5632>;
515 nvidia,i2s-controller = <&tegra_i2s1>;
516 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600517 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000518};