blob: 1447d794c22ad21648408a390e4b78bc84493af0 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020029#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +000030#include "radeon_asic.h"
Jerome Glissec93bb852009-07-13 21:04:08 +020031#include "atom.h"
Jerome Glisse3bc68532009-10-01 09:39:24 +020032#include "rs690d.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020033
Alex Deucher89e51812012-02-23 17:53:38 -050034int rs690_mc_wait_for_idle(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020035{
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40 /* read MC_STATUS */
Jerome Glisse3bc68532009-10-01 09:39:24 +020041 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
Jerome Glisse771fe6b2009-06-05 14:42:42 +020043 return 0;
Jerome Glisse3bc68532009-10-01 09:39:24 +020044 udelay(1);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020045 }
46 return -1;
47}
48
Jerome Glisse3bc68532009-10-01 09:39:24 +020049static void rs690_gpu_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020050{
Jerome Glisse771fe6b2009-06-05 14:42:42 +020051 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57}
58
Alex Deuchera084e6e2010-03-18 01:04:01 -040059union igp_info {
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62};
63
Jerome Glissec93bb852009-07-13 21:04:08 +020064void rs690_pm_info(struct radeon_device *rdev)
65{
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
Alex Deuchera084e6e2010-03-18 01:04:01 -040067 union igp_info *info;
Jerome Glissec93bb852009-07-13 21:04:08 +020068 uint16_t data_offset;
69 uint8_t frev, crev;
70 fixed20_12 tmp;
71
Alex Deuchera084e6e2010-03-18 01:04:01 -040072 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76 /* Get various system informations from bios */
77 switch (crev) {
78 case 1:
Ben Skeggs68adac52010-04-28 11:46:42 +100079 tmp.full = dfixed_const(100);
Alex Deucher265aa6c2011-02-14 16:16:22 -050080 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
Ben Skeggs68adac52010-04-28 11:46:42 +100081 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
Alex Deucher265aa6c2011-02-14 16:16:22 -050082 if (le16_to_cpu(info->info.usK8MemoryClock))
Alex Deucherf8920342010-06-30 12:02:03 -040083 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
84 else if (rdev->clock.default_mclk) {
85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
87 } else
88 rdev->pm.igp_system_mclk.full = dfixed_const(400);
Ben Skeggs68adac52010-04-28 11:46:42 +100089 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
90 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
Alex Deuchera084e6e2010-03-18 01:04:01 -040091 break;
92 case 2:
Ben Skeggs68adac52010-04-28 11:46:42 +100093 tmp.full = dfixed_const(100);
Alex Deucher265aa6c2011-02-14 16:16:22 -050094 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
Ben Skeggs68adac52010-04-28 11:46:42 +100095 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
Alex Deucher265aa6c2011-02-14 16:16:22 -050096 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
97 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
Alex Deucherf8920342010-06-30 12:02:03 -040098 else if (rdev->clock.default_mclk)
99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
100 else
101 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
Ben Skeggs68adac52010-04-28 11:46:42 +1000102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
Alex Deucher265aa6c2011-02-14 16:16:22 -0500103 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
Ben Skeggs68adac52010-04-28 11:46:42 +1000104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
Alex Deuchera084e6e2010-03-18 01:04:01 -0400106 break;
107 default:
Alex Deuchera084e6e2010-03-18 01:04:01 -0400108 /* We assume the slower possible clock ie worst case */
Alex Deucherf8920342010-06-30 12:02:03 -0400109 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
110 rdev->pm.igp_system_mclk.full = dfixed_const(200);
111 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
Ben Skeggs68adac52010-04-28 11:46:42 +1000112 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
Alex Deuchera084e6e2010-03-18 01:04:01 -0400113 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
114 break;
115 }
116 } else {
Jerome Glissec93bb852009-07-13 21:04:08 +0200117 /* We assume the slower possible clock ie worst case */
Alex Deucherf8920342010-06-30 12:02:03 -0400118 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
119 rdev->pm.igp_system_mclk.full = dfixed_const(200);
120 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
Ben Skeggs68adac52010-04-28 11:46:42 +1000121 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
Jerome Glissec93bb852009-07-13 21:04:08 +0200122 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
Jerome Glissec93bb852009-07-13 21:04:08 +0200123 }
124 /* Compute various bandwidth */
125 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000126 tmp.full = dfixed_const(4);
127 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200128 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
129 * = ht_clk * ht_width / 5
130 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000131 tmp.full = dfixed_const(5);
132 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
Jerome Glissec93bb852009-07-13 21:04:08 +0200133 rdev->pm.igp_ht_link_width);
Ben Skeggs68adac52010-04-28 11:46:42 +1000134 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200135 if (tmp.full < rdev->pm.max_bandwidth.full) {
136 /* HT link is a limiting factor */
137 rdev->pm.max_bandwidth.full = tmp.full;
138 }
139 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
140 * = (sideport_clk * 14) / 10
141 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000142 tmp.full = dfixed_const(14);
143 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
144 tmp.full = dfixed_const(10);
145 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200146}
147
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400148static void rs690_mc_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200149{
Jerome Glissed594e462010-02-17 21:54:29 +0000150 u64 base;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400151 uint32_t h_addr, l_addr;
152 unsigned long long k8_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200153
154 rs400_gart_adjust_size(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200155 rdev->mc.vram_is_ddr = true;
Alex Deucher722f2942009-12-03 16:18:19 -0500156 rdev->mc.vram_width = 128;
Dave Airlie7a50f012009-07-21 20:39:30 +1000157 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
158 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
Jordan Crouse01d73a62010-05-27 13:40:24 -0600159 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
160 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
Jerome Glisse51e5fcd2010-02-19 14:33:54 +0000161 rdev->mc.visible_vram_size = rdev->mc.aper_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
163 base = G_000100_MC_FB_START(base) << 16;
Alex Deucher06b64762010-01-05 11:27:29 -0500164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
Samuel Lia0a53aa2013-04-08 17:25:47 -0400165
166 /* Use K8 direct mapping for fast fb access. */
167 rdev->fastfb_working = false;
168 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
169 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
170 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
171#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
172 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
173#endif
174 {
175 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
176 * memory is present.
177 */
178 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
179 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
180 (unsigned long long)rdev->mc.aper_base, k8_addr);
181 rdev->mc.aper_base = (resource_size_t)k8_addr;
182 rdev->fastfb_working = true;
183 }
184 }
185
Alex Deucher4c70b2e2010-08-02 19:39:15 -0400186 rs690_pm_info(rdev);
Jerome Glissed594e462010-02-17 21:54:29 +0000187 radeon_vram_location(rdev, &rdev->mc, base);
Alex Deucher8d369bb2010-07-15 10:51:10 -0400188 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
Jerome Glissed594e462010-02-17 21:54:29 +0000189 radeon_gtt_location(rdev, &rdev->mc);
Alex Deucherf47299c2010-03-16 20:54:38 -0400190 radeon_update_bandwidth_info(rdev);
Alex Deucher22dd5012009-12-06 19:45:17 -0500191}
192
Jerome Glissec93bb852009-07-13 21:04:08 +0200193void rs690_line_buffer_adjust(struct radeon_device *rdev,
194 struct drm_display_mode *mode1,
195 struct drm_display_mode *mode2)
196{
197 u32 tmp;
198
199 /*
200 * Line Buffer Setup
201 * There is a single line buffer shared by both display controllers.
Jerome Glisse3bc68532009-10-01 09:39:24 +0200202 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
Jerome Glissec93bb852009-07-13 21:04:08 +0200203 * the display controllers. The paritioning can either be done
204 * manually or via one of four preset allocations specified in bits 1:0:
205 * 0 - line buffer is divided in half and shared between crtc
206 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
207 * 2 - D1 gets the whole buffer
208 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
Jerome Glisse3bc68532009-10-01 09:39:24 +0200209 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
Jerome Glissec93bb852009-07-13 21:04:08 +0200210 * allocation mode. In manual allocation mode, D1 always starts at 0,
211 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
212 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200213 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
214 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
Jerome Glissec93bb852009-07-13 21:04:08 +0200215 /* auto */
216 if (mode1 && mode2) {
217 if (mode1->hdisplay > mode2->hdisplay) {
218 if (mode1->hdisplay > 2560)
Jerome Glisse3bc68532009-10-01 09:39:24 +0200219 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
Jerome Glissec93bb852009-07-13 21:04:08 +0200220 else
Jerome Glisse3bc68532009-10-01 09:39:24 +0200221 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
Jerome Glissec93bb852009-07-13 21:04:08 +0200222 } else if (mode2->hdisplay > mode1->hdisplay) {
223 if (mode2->hdisplay > 2560)
Jerome Glisse3bc68532009-10-01 09:39:24 +0200224 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
Jerome Glissec93bb852009-07-13 21:04:08 +0200225 else
Jerome Glisse3bc68532009-10-01 09:39:24 +0200226 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
Jerome Glissec93bb852009-07-13 21:04:08 +0200227 } else
Jerome Glisse3bc68532009-10-01 09:39:24 +0200228 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
Jerome Glissec93bb852009-07-13 21:04:08 +0200229 } else if (mode1) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200230 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
Jerome Glissec93bb852009-07-13 21:04:08 +0200231 } else if (mode2) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200232 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
Jerome Glissec93bb852009-07-13 21:04:08 +0200233 }
Jerome Glisse3bc68532009-10-01 09:39:24 +0200234 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200235}
236
237struct rs690_watermark {
238 u32 lb_request_fifo_depth;
239 fixed20_12 num_line_pair;
240 fixed20_12 estimated_width;
241 fixed20_12 worst_case_latency;
242 fixed20_12 consumption_rate;
243 fixed20_12 active_time;
244 fixed20_12 dbpp;
245 fixed20_12 priority_mark_max;
246 fixed20_12 priority_mark;
247 fixed20_12 sclk;
248};
249
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400250static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400251 struct radeon_crtc *crtc,
252 struct rs690_watermark *wm,
253 bool low)
Jerome Glissec93bb852009-07-13 21:04:08 +0200254{
255 struct drm_display_mode *mode = &crtc->base.mode;
256 fixed20_12 a, b, c;
257 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
258 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400259 fixed20_12 sclk, core_bandwidth, max_bandwidth;
260 u32 selected_sclk;
Jerome Glissec93bb852009-07-13 21:04:08 +0200261
262 if (!crtc->base.enabled) {
263 /* FIXME: wouldn't it better to set priority mark to maximum */
264 wm->lb_request_fifo_depth = 4;
265 return;
266 }
267
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400268 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
269 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
270 selected_sclk = radeon_dpm_get_sclk(rdev, low);
271 else
272 selected_sclk = rdev->pm.current_sclk;
273
274 /* sclk in Mhz */
275 a.full = dfixed_const(100);
276 sclk.full = dfixed_const(selected_sclk);
277 sclk.full = dfixed_div(sclk, a);
278
279 /* core_bandwidth = sclk(Mhz) * 16 */
280 a.full = dfixed_const(16);
281 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
282
Ben Skeggs68adac52010-04-28 11:46:42 +1000283 if (crtc->vsc.full > dfixed_const(2))
284 wm->num_line_pair.full = dfixed_const(2);
Jerome Glissec93bb852009-07-13 21:04:08 +0200285 else
Ben Skeggs68adac52010-04-28 11:46:42 +1000286 wm->num_line_pair.full = dfixed_const(1);
Jerome Glissec93bb852009-07-13 21:04:08 +0200287
Ben Skeggs68adac52010-04-28 11:46:42 +1000288 b.full = dfixed_const(mode->crtc_hdisplay);
289 c.full = dfixed_const(256);
290 a.full = dfixed_div(b, c);
291 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
292 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
293 if (a.full < dfixed_const(4)) {
Jerome Glissec93bb852009-07-13 21:04:08 +0200294 wm->lb_request_fifo_depth = 4;
295 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000296 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
Jerome Glissec93bb852009-07-13 21:04:08 +0200297 }
298
299 /* Determine consumption rate
300 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
301 * vtaps = number of vertical taps,
302 * vsc = vertical scaling ratio, defined as source/destination
303 * hsc = horizontal scaling ration, defined as source/destination
304 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000305 a.full = dfixed_const(mode->clock);
306 b.full = dfixed_const(1000);
307 a.full = dfixed_div(a, b);
308 pclk.full = dfixed_div(b, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200309 if (crtc->rmx_type != RMX_OFF) {
Ben Skeggs68adac52010-04-28 11:46:42 +1000310 b.full = dfixed_const(2);
Jerome Glissec93bb852009-07-13 21:04:08 +0200311 if (crtc->vsc.full > b.full)
312 b.full = crtc->vsc.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000313 b.full = dfixed_mul(b, crtc->hsc);
314 c.full = dfixed_const(2);
315 b.full = dfixed_div(b, c);
316 consumption_time.full = dfixed_div(pclk, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200317 } else {
318 consumption_time.full = pclk.full;
319 }
Ben Skeggs68adac52010-04-28 11:46:42 +1000320 a.full = dfixed_const(1);
321 wm->consumption_rate.full = dfixed_div(a, consumption_time);
Jerome Glissec93bb852009-07-13 21:04:08 +0200322
323
324 /* Determine line time
325 * LineTime = total time for one line of displayhtotal
326 * LineTime = total number of horizontal pixels
327 * pclk = pixel clock period(ns)
328 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000329 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
330 line_time.full = dfixed_mul(a, pclk);
Jerome Glissec93bb852009-07-13 21:04:08 +0200331
332 /* Determine active time
333 * ActiveTime = time of active region of display within one line,
334 * hactive = total number of horizontal active pixels
335 * htotal = total number of horizontal pixels
336 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000337 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
338 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
339 wm->active_time.full = dfixed_mul(line_time, b);
340 wm->active_time.full = dfixed_div(wm->active_time, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200341
342 /* Maximun bandwidth is the minimun bandwidth of all component */
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400343 max_bandwidth = core_bandwidth;
Alex Deucher0888e882010-06-12 11:50:13 -0400344 if (rdev->mc.igp_sideport_enabled) {
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400345 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
Jerome Glissec93bb852009-07-13 21:04:08 +0200346 rdev->pm.sideport_bandwidth.full)
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400347 max_bandwidth = rdev->pm.sideport_bandwidth;
Ben Skeggs68adac52010-04-28 11:46:42 +1000348 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
349 read_delay_latency.full = dfixed_div(read_delay_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200350 rdev->pm.igp_sideport_mclk);
351 } else {
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400352 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
Jerome Glissec93bb852009-07-13 21:04:08 +0200353 rdev->pm.k8_bandwidth.full)
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400354 max_bandwidth = rdev->pm.k8_bandwidth;
355 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
Jerome Glissec93bb852009-07-13 21:04:08 +0200356 rdev->pm.ht_bandwidth.full)
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400357 max_bandwidth = rdev->pm.ht_bandwidth;
Ben Skeggs68adac52010-04-28 11:46:42 +1000358 read_delay_latency.full = dfixed_const(5000);
Jerome Glissec93bb852009-07-13 21:04:08 +0200359 }
360
361 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000362 a.full = dfixed_const(16);
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400363 sclk.full = dfixed_mul(max_bandwidth, a);
Ben Skeggs68adac52010-04-28 11:46:42 +1000364 a.full = dfixed_const(1000);
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400365 sclk.full = dfixed_div(a, sclk);
Jerome Glissec93bb852009-07-13 21:04:08 +0200366 /* Determine chunk time
367 * ChunkTime = the time it takes the DCP to send one chunk of data
368 * to the LB which consists of pipeline delay and inter chunk gap
369 * sclk = system clock(ns)
370 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000371 a.full = dfixed_const(256 * 13);
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400372 chunk_time.full = dfixed_mul(sclk, a);
Ben Skeggs68adac52010-04-28 11:46:42 +1000373 a.full = dfixed_const(10);
374 chunk_time.full = dfixed_div(chunk_time, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200375
376 /* Determine the worst case latency
377 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
378 * WorstCaseLatency = worst case time from urgent to when the MC starts
379 * to return data
380 * READ_DELAY_IDLE_MAX = constant of 1us
381 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
382 * which consists of pipeline delay and inter chunk gap
383 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000384 if (dfixed_trunc(wm->num_line_pair) > 1) {
385 a.full = dfixed_const(3);
386 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
Jerome Glissec93bb852009-07-13 21:04:08 +0200387 wm->worst_case_latency.full += read_delay_latency.full;
388 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000389 a.full = dfixed_const(2);
390 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
Jerome Glissec93bb852009-07-13 21:04:08 +0200391 wm->worst_case_latency.full += read_delay_latency.full;
392 }
393
394 /* Determine the tolerable latency
395 * TolerableLatency = Any given request has only 1 line time
396 * for the data to be returned
397 * LBRequestFifoDepth = Number of chunk requests the LB can
398 * put into the request FIFO for a display
399 * LineTime = total time for one line of display
400 * ChunkTime = the time it takes the DCP to send one chunk
401 * of data to the LB which consists of
402 * pipeline delay and inter chunk gap
403 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000404 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
Jerome Glissec93bb852009-07-13 21:04:08 +0200405 tolerable_latency.full = line_time.full;
406 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000407 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
Jerome Glissec93bb852009-07-13 21:04:08 +0200408 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000409 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
Jerome Glissec93bb852009-07-13 21:04:08 +0200410 tolerable_latency.full = line_time.full - tolerable_latency.full;
411 }
412 /* We assume worst case 32bits (4 bytes) */
Ben Skeggs68adac52010-04-28 11:46:42 +1000413 wm->dbpp.full = dfixed_const(4 * 8);
Jerome Glissec93bb852009-07-13 21:04:08 +0200414
415 /* Determine the maximum priority mark
416 * width = viewport width in pixels
417 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000418 a.full = dfixed_const(16);
419 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
420 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
421 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
Jerome Glissec93bb852009-07-13 21:04:08 +0200422
423 /* Determine estimated width */
424 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000425 estimated_width.full = dfixed_div(estimated_width, consumption_time);
426 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
427 wm->priority_mark.full = dfixed_const(10);
Jerome Glissec93bb852009-07-13 21:04:08 +0200428 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000429 a.full = dfixed_const(16);
430 wm->priority_mark.full = dfixed_div(estimated_width, a);
431 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
Jerome Glissec93bb852009-07-13 21:04:08 +0200432 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
433 }
434}
435
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400436static void rs690_compute_mode_priority(struct radeon_device *rdev,
437 struct rs690_watermark *wm0,
438 struct rs690_watermark *wm1,
439 struct drm_display_mode *mode0,
440 struct drm_display_mode *mode1,
441 u32 *d1mode_priority_a_cnt,
442 u32 *d2mode_priority_a_cnt)
443{
444 fixed20_12 priority_mark02, priority_mark12, fill_rate;
445 fixed20_12 a, b;
446
447 *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
448 *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
449
450 if (mode0 && mode1) {
451 if (dfixed_trunc(wm0->dbpp) > 64)
452 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
453 else
454 a.full = wm0->num_line_pair.full;
455 if (dfixed_trunc(wm1->dbpp) > 64)
456 b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
457 else
458 b.full = wm1->num_line_pair.full;
459 a.full += b.full;
460 fill_rate.full = dfixed_div(wm0->sclk, a);
461 if (wm0->consumption_rate.full > fill_rate.full) {
462 b.full = wm0->consumption_rate.full - fill_rate.full;
463 b.full = dfixed_mul(b, wm0->active_time);
464 a.full = dfixed_mul(wm0->worst_case_latency,
465 wm0->consumption_rate);
466 a.full = a.full + b.full;
467 b.full = dfixed_const(16 * 1000);
468 priority_mark02.full = dfixed_div(a, b);
469 } else {
470 a.full = dfixed_mul(wm0->worst_case_latency,
471 wm0->consumption_rate);
472 b.full = dfixed_const(16 * 1000);
473 priority_mark02.full = dfixed_div(a, b);
474 }
475 if (wm1->consumption_rate.full > fill_rate.full) {
476 b.full = wm1->consumption_rate.full - fill_rate.full;
477 b.full = dfixed_mul(b, wm1->active_time);
478 a.full = dfixed_mul(wm1->worst_case_latency,
479 wm1->consumption_rate);
480 a.full = a.full + b.full;
481 b.full = dfixed_const(16 * 1000);
482 priority_mark12.full = dfixed_div(a, b);
483 } else {
484 a.full = dfixed_mul(wm1->worst_case_latency,
485 wm1->consumption_rate);
486 b.full = dfixed_const(16 * 1000);
487 priority_mark12.full = dfixed_div(a, b);
488 }
489 if (wm0->priority_mark.full > priority_mark02.full)
490 priority_mark02.full = wm0->priority_mark.full;
491 if (dfixed_trunc(priority_mark02) < 0)
492 priority_mark02.full = 0;
493 if (wm0->priority_mark_max.full > priority_mark02.full)
494 priority_mark02.full = wm0->priority_mark_max.full;
495 if (wm1->priority_mark.full > priority_mark12.full)
496 priority_mark12.full = wm1->priority_mark.full;
497 if (dfixed_trunc(priority_mark12) < 0)
498 priority_mark12.full = 0;
499 if (wm1->priority_mark_max.full > priority_mark12.full)
500 priority_mark12.full = wm1->priority_mark_max.full;
501 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
502 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
503 if (rdev->disp_priority == 2) {
504 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
505 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
506 }
507 } else if (mode0) {
508 if (dfixed_trunc(wm0->dbpp) > 64)
509 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
510 else
511 a.full = wm0->num_line_pair.full;
512 fill_rate.full = dfixed_div(wm0->sclk, a);
513 if (wm0->consumption_rate.full > fill_rate.full) {
514 b.full = wm0->consumption_rate.full - fill_rate.full;
515 b.full = dfixed_mul(b, wm0->active_time);
516 a.full = dfixed_mul(wm0->worst_case_latency,
517 wm0->consumption_rate);
518 a.full = a.full + b.full;
519 b.full = dfixed_const(16 * 1000);
520 priority_mark02.full = dfixed_div(a, b);
521 } else {
522 a.full = dfixed_mul(wm0->worst_case_latency,
523 wm0->consumption_rate);
524 b.full = dfixed_const(16 * 1000);
525 priority_mark02.full = dfixed_div(a, b);
526 }
527 if (wm0->priority_mark.full > priority_mark02.full)
528 priority_mark02.full = wm0->priority_mark.full;
529 if (dfixed_trunc(priority_mark02) < 0)
530 priority_mark02.full = 0;
531 if (wm0->priority_mark_max.full > priority_mark02.full)
532 priority_mark02.full = wm0->priority_mark_max.full;
533 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
534 if (rdev->disp_priority == 2)
535 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
536 } else if (mode1) {
537 if (dfixed_trunc(wm1->dbpp) > 64)
538 a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
539 else
540 a.full = wm1->num_line_pair.full;
541 fill_rate.full = dfixed_div(wm1->sclk, a);
542 if (wm1->consumption_rate.full > fill_rate.full) {
543 b.full = wm1->consumption_rate.full - fill_rate.full;
544 b.full = dfixed_mul(b, wm1->active_time);
545 a.full = dfixed_mul(wm1->worst_case_latency,
546 wm1->consumption_rate);
547 a.full = a.full + b.full;
548 b.full = dfixed_const(16 * 1000);
549 priority_mark12.full = dfixed_div(a, b);
550 } else {
551 a.full = dfixed_mul(wm1->worst_case_latency,
552 wm1->consumption_rate);
553 b.full = dfixed_const(16 * 1000);
554 priority_mark12.full = dfixed_div(a, b);
555 }
556 if (wm1->priority_mark.full > priority_mark12.full)
557 priority_mark12.full = wm1->priority_mark.full;
558 if (dfixed_trunc(priority_mark12) < 0)
559 priority_mark12.full = 0;
560 if (wm1->priority_mark_max.full > priority_mark12.full)
561 priority_mark12.full = wm1->priority_mark_max.full;
562 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
563 if (rdev->disp_priority == 2)
564 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
565 }
566}
567
Jerome Glissec93bb852009-07-13 21:04:08 +0200568void rs690_bandwidth_update(struct radeon_device *rdev)
569{
570 struct drm_display_mode *mode0 = NULL;
571 struct drm_display_mode *mode1 = NULL;
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400572 struct rs690_watermark wm0_high, wm0_low;
573 struct rs690_watermark wm1_high, wm1_low;
Alex Deuchere06b14e2010-08-02 12:13:46 -0400574 u32 tmp;
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400575 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
576 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
Jerome Glissec93bb852009-07-13 21:04:08 +0200577
Alex Deucherf46c0122010-03-31 00:33:27 -0400578 radeon_update_display_priority(rdev);
579
Jerome Glissec93bb852009-07-13 21:04:08 +0200580 if (rdev->mode_info.crtcs[0]->base.enabled)
581 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
582 if (rdev->mode_info.crtcs[1]->base.enabled)
583 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
584 /*
585 * Set display0/1 priority up in the memory controller for
586 * modes if the user specifies HIGH for displaypriority
587 * option.
588 */
Alex Deucherf46c0122010-03-31 00:33:27 -0400589 if ((rdev->disp_priority == 2) &&
590 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200591 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
592 tmp &= C_000104_MC_DISP0R_INIT_LAT;
593 tmp &= C_000104_MC_DISP1R_INIT_LAT;
Jerome Glissec93bb852009-07-13 21:04:08 +0200594 if (mode0)
Jerome Glisse3bc68532009-10-01 09:39:24 +0200595 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
596 if (mode1)
597 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
598 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200599 }
600 rs690_line_buffer_adjust(rdev, mode0, mode1);
601
602 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
Jerome Glisse3bc68532009-10-01 09:39:24 +0200603 WREG32(R_006C9C_DCP_CONTROL, 0);
Jerome Glissec93bb852009-07-13 21:04:08 +0200604 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
Jerome Glisse3bc68532009-10-01 09:39:24 +0200605 WREG32(R_006C9C_DCP_CONTROL, 2);
Jerome Glissec93bb852009-07-13 21:04:08 +0200606
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400607 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
608 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
Jerome Glissec93bb852009-07-13 21:04:08 +0200609
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400610 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
611 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
612
613 tmp = (wm0_high.lb_request_fifo_depth - 1);
614 tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
Jerome Glisse3bc68532009-10-01 09:39:24 +0200615 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200616
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400617 rs690_compute_mode_priority(rdev,
618 &wm0_high, &wm1_high,
619 mode0, mode1,
620 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
621 rs690_compute_mode_priority(rdev,
622 &wm0_low, &wm1_low,
623 mode0, mode1,
624 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
Alex Deuchere06b14e2010-08-02 12:13:46 -0400625
626 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400627 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
Alex Deuchere06b14e2010-08-02 12:13:46 -0400628 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
Alex Deucher3a4d8f72012-10-25 16:58:55 -0400629 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
Jerome Glissec93bb852009-07-13 21:04:08 +0200630}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200631
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200632uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
633{
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400634 unsigned long flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200635 uint32_t r;
636
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400637 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200638 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
639 r = RREG32(R_00007C_MC_DATA);
640 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400641 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200642 return r;
643}
644
645void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
646{
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400647 unsigned long flags;
648
649 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200650 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
651 S_000078_MC_IND_WR_EN(1));
652 WREG32(R_00007C_MC_DATA, v);
653 WREG32(R_000078_MC_INDEX, 0x7F);
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400654 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200655}
656
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400657static void rs690_mc_program(struct radeon_device *rdev)
Jerome Glisse3bc68532009-10-01 09:39:24 +0200658{
659 struct rv515_mc_save save;
660
661 /* Stops all mc clients */
662 rv515_mc_stop(rdev, &save);
663
664 /* Wait for mc idle */
665 if (rs690_mc_wait_for_idle(rdev))
666 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
667 /* Program MC, should be a 32bits limited address space */
668 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
669 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
670 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
671 WREG32(R_000134_HDP_FB_LOCATION,
672 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
673
674 rv515_mc_resume(rdev, &save);
675}
676
677static int rs690_startup(struct radeon_device *rdev)
678{
679 int r;
680
681 rs690_mc_program(rdev);
682 /* Resume clock */
683 rv515_clock_startup(rdev);
684 /* Initialize GPU configuration (# pipes, ...) */
685 rs690_gpu_init(rdev);
686 /* Initialize GART (initialize after TTM so we can allocate
687 * memory through TTM but finalize after TTM) */
688 r = rs400_gart_enable(rdev);
689 if (r)
690 return r;
Alex Deucher724c80e2010-08-27 18:25:25 -0400691
692 /* allocate wb buffer */
693 r = radeon_wb_init(rdev);
694 if (r)
695 return r;
696
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000697 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
698 if (r) {
699 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
700 return r;
701 }
702
Jerome Glisse3bc68532009-10-01 09:39:24 +0200703 /* Enable IRQ */
Adis Hamziće49f3952013-06-02 16:47:54 +0200704 if (!rdev->irq.installed) {
705 r = radeon_irq_kms_init(rdev);
706 if (r)
707 return r;
708 }
709
Jerome Glisseac447df2009-09-30 22:18:43 +0200710 rs600_irq_set(rdev);
Jerome Glissecafe6602010-01-07 12:39:21 +0100711 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200712 /* 1M ring buffer */
713 r = r100_cp_init(rdev, 1024 * 1024);
714 if (r) {
Paul Bolleec4f2ac2011-01-28 23:32:04 +0100715 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200716 return r;
717 }
Rafał Miłeckife50ac72010-06-19 12:24:57 +0200718
Christian König2898c342012-07-05 11:55:34 +0200719 r = radeon_ib_pool_init(rdev);
720 if (r) {
721 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500722 return r;
Christian König2898c342012-07-05 11:55:34 +0200723 }
Jerome Glisseb15ba512011-11-15 11:48:34 -0500724
Alex Deucherd4e30ef2012-06-04 17:18:51 -0400725 r = r600_audio_init(rdev);
726 if (r) {
727 dev_err(rdev->dev, "failed initializing audio\n");
728 return r;
729 }
730
Jerome Glisse3bc68532009-10-01 09:39:24 +0200731 return 0;
732}
733
734int rs690_resume(struct radeon_device *rdev)
735{
Jerome Glisse6b7746e2012-02-20 17:57:20 -0500736 int r;
737
Jerome Glisse3bc68532009-10-01 09:39:24 +0200738 /* Make sur GART are not working */
739 rs400_gart_disable(rdev);
740 /* Resume clock before doing reset */
741 rv515_clock_startup(rdev);
742 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
Jerome Glissea2d07b72010-03-09 14:45:11 +0000743 if (radeon_asic_reset(rdev)) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200744 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
745 RREG32(R_000E40_RBBM_STATUS),
746 RREG32(R_0007C0_CP_STAT));
747 }
748 /* post */
749 atom_asic_init(rdev->mode_info.atom_context);
750 /* Resume clock after posting */
751 rv515_clock_startup(rdev);
Dave Airlie550e2d92009-12-09 14:15:38 +1000752 /* Initialize surface registers */
753 radeon_surface_init(rdev);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500754
755 rdev->accel_working = true;
Jerome Glisse6b7746e2012-02-20 17:57:20 -0500756 r = rs690_startup(rdev);
757 if (r) {
758 rdev->accel_working = false;
759 }
760 return r;
Jerome Glisse3bc68532009-10-01 09:39:24 +0200761}
762
763int rs690_suspend(struct radeon_device *rdev)
764{
Rafał Miłeckife50ac72010-06-19 12:24:57 +0200765 r600_audio_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200766 r100_cp_disable(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400767 radeon_wb_disable(rdev);
Jerome Glisseac447df2009-09-30 22:18:43 +0200768 rs600_irq_disable(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200769 rs400_gart_disable(rdev);
770 return 0;
771}
772
773void rs690_fini(struct radeon_device *rdev)
774{
Rafał Miłeckife50ac72010-06-19 12:24:57 +0200775 r600_audio_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200776 r100_cp_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400777 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +0200778 radeon_ib_pool_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200779 radeon_gem_fini(rdev);
780 rs400_gart_fini(rdev);
781 radeon_irq_kms_fini(rdev);
782 radeon_fence_driver_fini(rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +0100783 radeon_bo_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200784 radeon_atombios_fini(rdev);
785 kfree(rdev->bios);
786 rdev->bios = NULL;
787}
788
789int rs690_init(struct radeon_device *rdev)
790{
791 int r;
792
Jerome Glisse3bc68532009-10-01 09:39:24 +0200793 /* Disable VGA */
794 rv515_vga_render_disable(rdev);
795 /* Initialize scratch registers */
796 radeon_scratch_init(rdev);
797 /* Initialize surface registers */
798 radeon_surface_init(rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000799 /* restore some register to sane defaults */
800 r100_restore_sanity(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200801 /* TODO: disable VGA need to use VGA request */
802 /* BIOS*/
803 if (!radeon_get_bios(rdev)) {
804 if (ASIC_IS_AVIVO(rdev))
805 return -EINVAL;
806 }
807 if (rdev->is_atom_bios) {
808 r = radeon_atombios_init(rdev);
809 if (r)
810 return r;
811 } else {
812 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
813 return -EINVAL;
814 }
815 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
Jerome Glissea2d07b72010-03-09 14:45:11 +0000816 if (radeon_asic_reset(rdev)) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200817 dev_warn(rdev->dev,
818 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
819 RREG32(R_000E40_RBBM_STATUS),
820 RREG32(R_0007C0_CP_STAT));
821 }
822 /* check if cards are posted or not */
Dave Airlie72542d72009-12-01 14:06:31 +1000823 if (radeon_boot_test_post_card(rdev) == false)
824 return -EINVAL;
825
Jerome Glisse3bc68532009-10-01 09:39:24 +0200826 /* Initialize clocks */
827 radeon_get_clock_info(rdev->ddev);
Jerome Glissed594e462010-02-17 21:54:29 +0000828 /* initialize memory controller */
829 rs690_mc_init(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200830 rv515_debugfs(rdev);
831 /* Fence driver */
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000832 r = radeon_fence_driver_init(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200833 if (r)
834 return r;
Jerome Glisse3bc68532009-10-01 09:39:24 +0200835 /* Memory manager */
Jerome Glisse4c788672009-11-20 14:29:23 +0100836 r = radeon_bo_init(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200837 if (r)
838 return r;
839 r = rs400_gart_init(rdev);
840 if (r)
841 return r;
842 rs600_set_safe_registers(rdev);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500843
Jerome Glisse3bc68532009-10-01 09:39:24 +0200844 rdev->accel_working = true;
845 r = rs690_startup(rdev);
846 if (r) {
847 /* Somethings want wront with the accel init stop accel */
848 dev_err(rdev->dev, "Disabling GPU acceleration\n");
Jerome Glisse3bc68532009-10-01 09:39:24 +0200849 r100_cp_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400850 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +0200851 radeon_ib_pool_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200852 rs400_gart_fini(rdev);
853 radeon_irq_kms_fini(rdev);
854 rdev->accel_working = false;
855 }
856 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200857}