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eric miao2c8086a2007-09-11 19:13:17 -07001/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
eric miaoe9bba8e2007-10-30 08:01:38 +01008 * 2007-09-02: eric miao <eric.miao@marvell.com>
eric miao2c8086a2007-09-11 19:13:17 -07009 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/pm.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
Russell King7b5dea12008-01-07 22:18:30 +000022#include <linux/io.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020023#include <linux/syscore_ops.h>
Sebastian Andrzej Siewiorb4593962011-02-23 12:38:16 +010024#include <linux/i2c/pxa-i2c.h>
eric miao2c8086a2007-09-11 19:13:17 -070025
Marek Vasut851982c2010-10-11 02:20:19 +020026#include <asm/mach/map.h>
Russell King2c74a0c2011-06-22 17:41:48 +010027#include <asm/suspend.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010028#include <mach/hardware.h>
Eric Miaoa58fbcd2009-01-06 17:37:37 +080029#include <mach/gpio.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010030#include <mach/pxa3xx-regs.h>
Russell Kingafd2fc02008-08-07 11:05:25 +010031#include <mach/reset.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010032#include <mach/ohci.h>
33#include <mach/pm.h>
34#include <mach/dma.h>
Marek Vasutad68bb92010-11-03 16:29:35 +010035#include <mach/smemc.h>
eric miao2c8086a2007-09-11 19:13:17 -070036
37#include "generic.h"
38#include "devices.h"
39#include "clock.h"
40
Mike Rapoportbf293ae2009-11-11 11:36:59 +020041#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
42#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
43
Russell King8c3abc72008-11-08 20:25:21 +000044static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
45static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
46static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
47static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
48static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
49static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
Igor Grinberge68750a2009-11-04 14:14:39 +020050static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
Russell King8c3abc72008-11-08 20:25:21 +000051static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
52static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
53static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
54static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
55static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
56static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
57static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
58static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
59static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
60
Eric Miao2e8581e2010-11-22 09:41:39 +080061static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
Eric Miaoc0850522010-11-29 22:56:00 +080062static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
Eric Miao2e8581e2010-11-22 09:41:39 +080063static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
64static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
Eric Miao40298132010-11-22 10:49:55 +080065static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
Eric Miao2e8581e2010-11-22 09:41:39 +080066
Russell King8c3abc72008-11-08 20:25:21 +000067static struct clk_lookup pxa3xx_clkregs[] = {
68 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
Mike Rapoport9ba63c42008-08-17 06:23:05 +010069 /* Power I2C clock is always on */
Daniel Mack5c68b092009-06-22 21:01:58 +020070 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
Russell King8c3abc72008-11-08 20:25:21 +000071 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
72 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
73 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
74 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
75 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
76 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
77 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
78 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
79 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
80 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
Igor Grinberg69f22be2010-07-27 15:06:58 +030081 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
Russell King8c3abc72008-11-08 20:25:21 +000082 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
83 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
84 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
85 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
86 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
87 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
88 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
89 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
90 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
Eric Miaoc0850522010-11-29 22:56:00 +080091 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
eric miao2c8086a2007-09-11 19:13:17 -070092};
93
Russell King7b5dea12008-01-07 22:18:30 +000094#ifdef CONFIG_PM
Russell King7b5dea12008-01-07 22:18:30 +000095
96#define ISRAM_START 0x5c000000
97#define ISRAM_SIZE SZ_256K
98
99static void __iomem *sram;
100static unsigned long wakeup_src;
101
Russell King7b5dea12008-01-07 22:18:30 +0000102/*
103 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
104 * memory controller has to be reinitialised, so we place some code
105 * in the SRAM to perform this function.
106 *
107 * We disable FIQs across the standby - otherwise, we might receive a
108 * FIQ while the SDRAM is unavailable.
109 */
110static void pxa3xx_cpu_standby(unsigned int pwrmode)
111{
112 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
113 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
114
115 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
116 pm_enter_standby_end - pm_enter_standby_start);
117
118 AD2D0SR = ~0;
119 AD2D1SR = ~0;
120 AD2D0ER = wakeup_src;
121 AD2D1ER = 0;
122 ASCR = ASCR;
123 ARSR = ARSR;
124
125 local_fiq_disable();
126 fn(pwrmode);
127 local_fiq_enable();
128
129 AD2D0ER = 0;
130 AD2D1ER = 0;
Russell King7b5dea12008-01-07 22:18:30 +0000131}
132
eric miaoc4d1fb62008-01-28 23:00:02 +0000133/*
134 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
135 * PXA3xx development kits assumes that the resuming process continues
136 * with the address stored within the first 4 bytes of SDRAM. The PSPR
137 * register is used privately by BootROM and OBM, and _must_ be set to
138 * 0x5c014000 for the moment.
139 */
140static void pxa3xx_cpu_pm_suspend(void)
141{
142 volatile unsigned long *p = (volatile void *)0xc0000000;
143 unsigned long saved_data = *p;
Russell Kinga9503d22011-06-21 16:29:30 +0100144#ifndef CONFIG_IWMMXT
145 u64 acc0;
eric miaoc4d1fb62008-01-28 23:00:02 +0000146
Russell Kinga9503d22011-06-21 16:29:30 +0100147 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
148#endif
149
Russell King29cb3cd2011-07-02 09:54:01 +0100150 extern int pxa3xx_finish_suspend(unsigned long);
eric miaoc4d1fb62008-01-28 23:00:02 +0000151
152 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
153 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
154 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
155
156 /* clear and setup wakeup source */
157 AD3SR = ~0;
158 AD3ER = wakeup_src;
159 ASCR = ASCR;
160 ARSR = ARSR;
161
162 PCFR |= (1u << 13); /* L1_DIS */
163 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
164
165 PSPR = 0x5c014000;
166
167 /* overwrite with the resume address */
Russell King4f5ad992011-02-06 17:41:26 +0000168 *p = virt_to_phys(cpu_resume);
eric miaoc4d1fb62008-01-28 23:00:02 +0000169
Russell King2c74a0c2011-06-22 17:41:48 +0100170 cpu_suspend(0, pxa3xx_finish_suspend);
eric miaoc4d1fb62008-01-28 23:00:02 +0000171
172 *p = saved_data;
173
174 AD3ER = 0;
Russell Kinga9503d22011-06-21 16:29:30 +0100175
176#ifndef CONFIG_IWMMXT
177 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
178#endif
eric miaoc4d1fb62008-01-28 23:00:02 +0000179}
180
Russell King7b5dea12008-01-07 22:18:30 +0000181static void pxa3xx_cpu_pm_enter(suspend_state_t state)
182{
183 /*
184 * Don't sleep if no wakeup sources are defined
185 */
Mark Brownb86a5da2008-04-09 11:32:21 +0100186 if (wakeup_src == 0) {
187 printk(KERN_ERR "Not suspending: no wakeup sources\n");
Russell King7b5dea12008-01-07 22:18:30 +0000188 return;
Mark Brownb86a5da2008-04-09 11:32:21 +0100189 }
Russell King7b5dea12008-01-07 22:18:30 +0000190
191 switch (state) {
192 case PM_SUSPEND_STANDBY:
193 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
194 break;
195
196 case PM_SUSPEND_MEM:
eric miaoc4d1fb62008-01-28 23:00:02 +0000197 pxa3xx_cpu_pm_suspend();
Russell King7b5dea12008-01-07 22:18:30 +0000198 break;
199 }
200}
201
202static int pxa3xx_cpu_pm_valid(suspend_state_t state)
203{
204 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
205}
206
207static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
Russell King7b5dea12008-01-07 22:18:30 +0000208 .valid = pxa3xx_cpu_pm_valid,
209 .enter = pxa3xx_cpu_pm_enter,
210};
211
212static void __init pxa3xx_init_pm(void)
213{
214 sram = ioremap(ISRAM_START, ISRAM_SIZE);
215 if (!sram) {
216 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
217 return;
218 }
219
220 /*
221 * Since we copy wakeup code into the SRAM, we need to ensure
222 * that it is preserved over the low power modes. Note: bit 8
223 * is undocumented in the developer manual, but must be set.
224 */
225 AD1R |= ADXR_L2 | ADXR_R0;
226 AD2R |= ADXR_L2 | ADXR_R0;
227 AD3R |= ADXR_L2 | ADXR_R0;
228
229 /*
230 * Clear the resume enable registers.
231 */
232 AD1D0ER = 0;
233 AD2D0ER = 0;
234 AD2D1ER = 0;
235 AD3ER = 0;
236
237 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
238}
239
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100240static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
Russell King7b5dea12008-01-07 22:18:30 +0000241{
242 unsigned long flags, mask = 0;
243
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100244 switch (d->irq) {
Russell King7b5dea12008-01-07 22:18:30 +0000245 case IRQ_SSP3:
246 mask = ADXER_MFP_WSSP3;
247 break;
248 case IRQ_MSL:
249 mask = ADXER_WMSL0;
250 break;
251 case IRQ_USBH2:
252 case IRQ_USBH1:
253 mask = ADXER_WUSBH;
254 break;
255 case IRQ_KEYPAD:
256 mask = ADXER_WKP;
257 break;
258 case IRQ_AC97:
259 mask = ADXER_MFP_WAC97;
260 break;
261 case IRQ_USIM:
262 mask = ADXER_WUSIM0;
263 break;
264 case IRQ_SSP2:
265 mask = ADXER_MFP_WSSP2;
266 break;
267 case IRQ_I2C:
268 mask = ADXER_MFP_WI2C;
269 break;
270 case IRQ_STUART:
271 mask = ADXER_MFP_WUART3;
272 break;
273 case IRQ_BTUART:
274 mask = ADXER_MFP_WUART2;
275 break;
276 case IRQ_FFUART:
277 mask = ADXER_MFP_WUART1;
278 break;
279 case IRQ_MMC:
280 mask = ADXER_MFP_WMMC1;
281 break;
282 case IRQ_SSP:
283 mask = ADXER_MFP_WSSP1;
284 break;
285 case IRQ_RTCAlrm:
286 mask = ADXER_WRTC;
287 break;
288 case IRQ_SSP4:
289 mask = ADXER_MFP_WSSP4;
290 break;
291 case IRQ_TSI:
292 mask = ADXER_WTSI;
293 break;
294 case IRQ_USIM2:
295 mask = ADXER_WUSIM1;
296 break;
297 case IRQ_MMC2:
298 mask = ADXER_MFP_WMMC2;
299 break;
300 case IRQ_NAND:
301 mask = ADXER_MFP_WFLASH;
302 break;
303 case IRQ_USB2:
304 mask = ADXER_WUSB2;
305 break;
306 case IRQ_WAKEUP0:
307 mask = ADXER_WEXTWAKE0;
308 break;
309 case IRQ_WAKEUP1:
310 mask = ADXER_WEXTWAKE1;
311 break;
312 case IRQ_MMC3:
313 mask = ADXER_MFP_GEN12;
314 break;
Mark Browne1217702008-04-23 10:28:18 +0100315 default:
316 return -EINVAL;
Russell King7b5dea12008-01-07 22:18:30 +0000317 }
318
319 local_irq_save(flags);
320 if (on)
321 wakeup_src |= mask;
322 else
323 wakeup_src &= ~mask;
324 local_irq_restore(flags);
325
326 return 0;
327}
Russell King7b5dea12008-01-07 22:18:30 +0000328#else
329static inline void pxa3xx_init_pm(void) {}
eric miaob9e25ac2008-03-04 14:19:58 +0800330#define pxa3xx_set_wake NULL
Russell King7b5dea12008-01-07 22:18:30 +0000331#endif
332
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100333static void pxa_ack_ext_wakeup(struct irq_data *d)
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200334{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100335 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200336}
337
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100338static void pxa_mask_ext_wakeup(struct irq_data *d)
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200339{
Eric Miao5d284e32011-04-27 22:48:04 +0800340 pxa_mask_irq(d);
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100341 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200342}
343
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100344static void pxa_unmask_ext_wakeup(struct irq_data *d)
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200345{
Eric Miao5d284e32011-04-27 22:48:04 +0800346 pxa_unmask_irq(d);
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100347 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200348}
349
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100350static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
Igor Grinberg12882092010-06-13 11:31:48 +0300351{
352 if (flow_type & IRQ_TYPE_EDGE_RISING)
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100353 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
Igor Grinberg12882092010-06-13 11:31:48 +0300354
355 if (flow_type & IRQ_TYPE_EDGE_FALLING)
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100356 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
Igor Grinberg12882092010-06-13 11:31:48 +0300357
358 return 0;
359}
360
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200361static struct irq_chip pxa_ext_wakeup_chip = {
362 .name = "WAKEUP",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100363 .irq_ack = pxa_ack_ext_wakeup,
364 .irq_mask = pxa_mask_ext_wakeup,
365 .irq_unmask = pxa_unmask_ext_wakeup,
366 .irq_set_type = pxa_set_ext_wakeup_type,
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200367};
368
369static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
370{
371 int irq;
372
373 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100374 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
375 handle_edge_irq);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200376 set_irq_flags(irq, IRQF_VALID);
377 }
378
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100379 pxa_ext_wakeup_chip.irq_set_wake = fn;
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200380}
381
eric miao2c8086a2007-09-11 19:13:17 -0700382void __init pxa3xx_init_irq(void)
383{
384 /* enable CP6 access */
385 u32 value;
386 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
387 value |= (1 << 6);
388 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
389
eric miaob9e25ac2008-03-04 14:19:58 +0800390 pxa_init_irq(56, pxa3xx_set_wake);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200391 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800392 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
eric miao2c8086a2007-09-11 19:13:17 -0700393}
394
Marek Vasut851982c2010-10-11 02:20:19 +0200395static struct map_desc pxa3xx_io_desc[] __initdata = {
396 { /* Mem Ctl */
Marek Vasutad68bb92010-11-03 16:29:35 +0100397 .virtual = SMEMC_VIRT,
398 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
Marek Vasut851982c2010-10-11 02:20:19 +0200399 .length = 0x00200000,
400 .type = MT_DEVICE
401 }
402};
403
404void __init pxa3xx_map_io(void)
405{
406 pxa_map_io();
407 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
408 pxa3xx_get_clk_frequency_khz(1);
409}
410
eric miao2c8086a2007-09-11 19:13:17 -0700411/*
412 * device registration specific to PXA3xx.
413 */
414
Mike Rapoport9ba63c42008-08-17 06:23:05 +0100415void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
416{
Eric Miao14758222008-11-28 15:24:12 +0800417 pxa_register_device(&pxa3xx_device_i2c_power, info);
Mike Rapoport9ba63c42008-08-17 06:23:05 +0100418}
419
eric miao2c8086a2007-09-11 19:13:17 -0700420static struct platform_device *devices[] __initdata = {
Robert Jarzmik94c35a62009-04-21 19:19:36 +0200421 &pxa27x_device_udc,
Eric Miao09a53582010-06-14 00:43:00 +0800422 &pxa_device_pmu,
eric miao2c8086a2007-09-11 19:13:17 -0700423 &pxa_device_i2s,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000424 &pxa_device_asoc_ssp1,
425 &pxa_device_asoc_ssp2,
426 &pxa_device_asoc_ssp3,
427 &pxa_device_asoc_ssp4,
428 &pxa_device_asoc_platform,
Robert Jarzmik72493142008-11-13 23:50:56 +0100429 &sa1100_device_rtc,
eric miao2c8086a2007-09-11 19:13:17 -0700430 &pxa_device_rtc,
eric miaod8e0db12007-12-10 17:54:36 +0800431 &pxa27x_device_ssp1,
432 &pxa27x_device_ssp2,
433 &pxa27x_device_ssp3,
434 &pxa3xx_device_ssp4,
eric miao75540c12008-04-13 21:44:04 +0100435 &pxa27x_device_pwm0,
436 &pxa27x_device_pwm1,
eric miao2c8086a2007-09-11 19:13:17 -0700437};
438
439static int __init pxa3xx_init(void)
440{
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200441 int ret = 0;
eric miao2c8086a2007-09-11 19:13:17 -0700442
443 if (cpu_is_pxa3xx()) {
Eric Miao04fef222008-07-29 14:26:00 +0800444
445 reset_status = ARSR;
446
Dmitry Krivoschekov86260f92008-02-08 15:02:03 +0100447 /*
448 * clear RDH bit every time after reset
449 *
450 * Note: the last 3 bits DxS are write-1-to-clear so carefully
451 * preserve them here in case they will be referenced later
452 */
453 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
454
Russell King0a0300d2010-01-12 12:28:00 +0000455 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
eric miao2c8086a2007-09-11 19:13:17 -0700456
Eric Miaofef1f992009-01-02 16:26:33 +0800457 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
eric miao2c8086a2007-09-11 19:13:17 -0700458 return ret;
459
Russell King7b5dea12008-01-07 22:18:30 +0000460 pxa3xx_init_pm();
461
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200462 register_syscore_ops(&pxa_irq_syscore_ops);
463 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
464 register_syscore_ops(&pxa_gpio_syscore_ops);
465 register_syscore_ops(&pxa3xx_clock_syscore_ops);
eric miaoc01655042008-01-28 23:00:02 +0000466
467 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
eric miao2c8086a2007-09-11 19:13:17 -0700468 }
eric miaoc01655042008-01-28 23:00:02 +0000469
470 return ret;
eric miao2c8086a2007-09-11 19:13:17 -0700471}
472
Russell King1c104e02008-04-19 10:59:24 +0100473postcore_initcall(pxa3xx_init);