blob: 4d90ac2dbb1be827aef1a633159ae835f701588d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02005 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Sergei Shtylyov59c8d042009-04-18 17:42:19 +02006 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
Alan Coxb39b01f2005-06-27 15:24:27 -070013 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080014 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
Alan Coxb39b01f2005-06-27 15:24:27 -070019 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
Alan Coxccd32e22008-11-02 21:40:08 +010055 * Alan Cox <alan@lxorguk.ukuu.org.uk>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080057 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010062 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -080066 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
Sergei Shtylyov26c068d2006-12-13 00:35:52 -080069 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
Sergei Shtylyov72931362007-09-11 22:28:35 +020070 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
Sergei Shtylyov33b18a62006-12-13 00:35:50 -080072 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -080074 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010076 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
Sergei Shtylyov90778572007-02-07 18:17:51 +010078 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +020080 * - optimize the UltraDMA filtering and the drive list lookup code
Sergei Shtylyovb4586712007-02-07 18:17:54 +010081 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010082 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +010086 * - rename all the register related variables consistently
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010087 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
Sergei Shtylyov866664d2008-01-25 22:17:05 +010089 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010090 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +010094 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010095 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
Sergei Shtylyov278978e2007-06-08 15:14:32 +0200109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
Sergei Shtylyov6273d262007-02-07 18:18:20 +0100111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200115 * - set the correct hwif->ultra_mask for each individual chip
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyovc018f1e2009-04-18 17:42:19 +0200117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 */
121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122#include <linux/types.h>
123#include <linux/module.h>
124#include <linux/kernel.h>
125#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126#include <linux/blkdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127#include <linux/interrupt.h>
128#include <linux/pci.h>
129#include <linux/init.h>
130#include <linux/ide.h>
131
132#include <asm/uaccess.h>
133#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200135#define DRV_NAME "hpt366"
136
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137/* various tuning parameters */
Sergei Shtylyovc018f1e2009-04-18 17:42:19 +0200138#undef HPT_RESET_STATE_ENGINE
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800139#undef HPT_DELAY_INTERRUPT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141static const char *bad_ata100_5[] = {
142 "IBM-DTLA-307075",
143 "IBM-DTLA-307060",
144 "IBM-DTLA-307045",
145 "IBM-DTLA-307030",
146 "IBM-DTLA-307020",
147 "IBM-DTLA-307015",
148 "IBM-DTLA-305040",
149 "IBM-DTLA-305030",
150 "IBM-DTLA-305020",
151 "IC35L010AVER07-0",
152 "IC35L020AVER07-0",
153 "IC35L030AVER07-0",
154 "IC35L040AVER07-0",
155 "IC35L060AVER07-0",
156 "WDC AC310200R",
157 NULL
158};
159
160static const char *bad_ata66_4[] = {
161 "IBM-DTLA-307075",
162 "IBM-DTLA-307060",
163 "IBM-DTLA-307045",
164 "IBM-DTLA-307030",
165 "IBM-DTLA-307020",
166 "IBM-DTLA-307015",
167 "IBM-DTLA-305040",
168 "IBM-DTLA-305030",
169 "IBM-DTLA-305020",
170 "IC35L010AVER07-0",
171 "IC35L020AVER07-0",
172 "IC35L030AVER07-0",
173 "IC35L040AVER07-0",
174 "IC35L060AVER07-0",
175 "WDC AC310200R",
Sergei Shtylyov783353b2007-07-03 22:28:35 +0200176 "MAXTOR STM3320620A",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 NULL
178};
179
180static const char *bad_ata66_3[] = {
181 "WDC AC310200R",
182 NULL
183};
184
185static const char *bad_ata33[] = {
186 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
187 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
188 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
189 "Maxtor 90510D4",
190 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
191 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
192 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
193 NULL
194};
195
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800196static u8 xfer_speeds[] = {
197 XFER_UDMA_6,
198 XFER_UDMA_5,
199 XFER_UDMA_4,
200 XFER_UDMA_3,
201 XFER_UDMA_2,
202 XFER_UDMA_1,
203 XFER_UDMA_0,
204
205 XFER_MW_DMA_2,
206 XFER_MW_DMA_1,
207 XFER_MW_DMA_0,
208
209 XFER_PIO_4,
210 XFER_PIO_3,
211 XFER_PIO_2,
212 XFER_PIO_1,
213 XFER_PIO_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214};
215
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800216/* Key for bus clock timings
217 * 36x 37x
218 * bits bits
219 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
220 * cycles = value + 1
221 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
222 * cycles = value + 1
223 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
224 * register access.
225 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
226 * register access.
227 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
228 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
229 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
230 * MW DMA xfer.
231 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
232 * task file register access.
233 * 28 28 UDMA enable.
234 * 29 29 DMA enable.
235 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
236 * PIO xfer.
237 * 31 31 FIFO enable.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800240static u32 forty_base_hpt36x[] = {
241 /* XFER_UDMA_6 */ 0x900fd943,
242 /* XFER_UDMA_5 */ 0x900fd943,
243 /* XFER_UDMA_4 */ 0x900fd943,
244 /* XFER_UDMA_3 */ 0x900ad943,
245 /* XFER_UDMA_2 */ 0x900bd943,
246 /* XFER_UDMA_1 */ 0x9008d943,
247 /* XFER_UDMA_0 */ 0x9008d943,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800249 /* XFER_MW_DMA_2 */ 0xa008d943,
250 /* XFER_MW_DMA_1 */ 0xa010d955,
251 /* XFER_MW_DMA_0 */ 0xa010d9fc,
252
253 /* XFER_PIO_4 */ 0xc008d963,
254 /* XFER_PIO_3 */ 0xc010d974,
255 /* XFER_PIO_2 */ 0xc010d997,
256 /* XFER_PIO_1 */ 0xc010d9c7,
257 /* XFER_PIO_0 */ 0xc018d9d9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258};
259
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800260static u32 thirty_three_base_hpt36x[] = {
261 /* XFER_UDMA_6 */ 0x90c9a731,
262 /* XFER_UDMA_5 */ 0x90c9a731,
263 /* XFER_UDMA_4 */ 0x90c9a731,
264 /* XFER_UDMA_3 */ 0x90cfa731,
265 /* XFER_UDMA_2 */ 0x90caa731,
266 /* XFER_UDMA_1 */ 0x90cba731,
267 /* XFER_UDMA_0 */ 0x90c8a731,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800269 /* XFER_MW_DMA_2 */ 0xa0c8a731,
270 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
271 /* XFER_MW_DMA_0 */ 0xa0c8a797,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800273 /* XFER_PIO_4 */ 0xc0c8a731,
274 /* XFER_PIO_3 */ 0xc0c8a742,
275 /* XFER_PIO_2 */ 0xc0d0a753,
276 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
277 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278};
279
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800280static u32 twenty_five_base_hpt36x[] = {
281 /* XFER_UDMA_6 */ 0x90c98521,
282 /* XFER_UDMA_5 */ 0x90c98521,
283 /* XFER_UDMA_4 */ 0x90c98521,
284 /* XFER_UDMA_3 */ 0x90cf8521,
285 /* XFER_UDMA_2 */ 0x90cf8521,
286 /* XFER_UDMA_1 */ 0x90cb8521,
287 /* XFER_UDMA_0 */ 0x90cb8521,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800289 /* XFER_MW_DMA_2 */ 0xa0ca8521,
290 /* XFER_MW_DMA_1 */ 0xa0ca8532,
291 /* XFER_MW_DMA_0 */ 0xa0ca8575,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800293 /* XFER_PIO_4 */ 0xc0ca8521,
294 /* XFER_PIO_3 */ 0xc0ca8532,
295 /* XFER_PIO_2 */ 0xc0ca8542,
296 /* XFER_PIO_1 */ 0xc0d08572,
297 /* XFER_PIO_0 */ 0xc0d08585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298};
299
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100300/*
301 * The following are the new timing tables with PIO mode data/taskfile transfer
302 * overclocking fixed...
303 */
304
305/* This table is taken from the HPT370 data manual rev. 1.02 */
306static u32 thirty_three_base_hpt37x[] = {
307 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
308 /* XFER_UDMA_5 */ 0x16455031,
309 /* XFER_UDMA_4 */ 0x16455031,
310 /* XFER_UDMA_3 */ 0x166d5031,
311 /* XFER_UDMA_2 */ 0x16495031,
312 /* XFER_UDMA_1 */ 0x164d5033,
313 /* XFER_UDMA_0 */ 0x16515097,
314
315 /* XFER_MW_DMA_2 */ 0x26515031,
316 /* XFER_MW_DMA_1 */ 0x26515033,
317 /* XFER_MW_DMA_0 */ 0x26515097,
318
319 /* XFER_PIO_4 */ 0x06515021,
320 /* XFER_PIO_3 */ 0x06515022,
321 /* XFER_PIO_2 */ 0x06515033,
322 /* XFER_PIO_1 */ 0x06915065,
323 /* XFER_PIO_0 */ 0x06d1508a
324};
325
326static u32 fifty_base_hpt37x[] = {
327 /* XFER_UDMA_6 */ 0x1a861842,
328 /* XFER_UDMA_5 */ 0x1a861842,
329 /* XFER_UDMA_4 */ 0x1aae1842,
330 /* XFER_UDMA_3 */ 0x1a8e1842,
331 /* XFER_UDMA_2 */ 0x1a0e1842,
332 /* XFER_UDMA_1 */ 0x1a161854,
333 /* XFER_UDMA_0 */ 0x1a1a18ea,
334
335 /* XFER_MW_DMA_2 */ 0x2a821842,
336 /* XFER_MW_DMA_1 */ 0x2a821854,
337 /* XFER_MW_DMA_0 */ 0x2a8218ea,
338
339 /* XFER_PIO_4 */ 0x0a821842,
340 /* XFER_PIO_3 */ 0x0a821843,
341 /* XFER_PIO_2 */ 0x0a821855,
342 /* XFER_PIO_1 */ 0x0ac218a8,
343 /* XFER_PIO_0 */ 0x0b02190c
344};
345
346static u32 sixty_six_base_hpt37x[] = {
347 /* XFER_UDMA_6 */ 0x1c86fe62,
348 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
349 /* XFER_UDMA_4 */ 0x1c8afe62,
350 /* XFER_UDMA_3 */ 0x1c8efe62,
351 /* XFER_UDMA_2 */ 0x1c92fe62,
352 /* XFER_UDMA_1 */ 0x1c9afe62,
353 /* XFER_UDMA_0 */ 0x1c82fe62,
354
355 /* XFER_MW_DMA_2 */ 0x2c82fe62,
356 /* XFER_MW_DMA_1 */ 0x2c82fe66,
357 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
358
359 /* XFER_PIO_4 */ 0x0c82fe62,
360 /* XFER_PIO_3 */ 0x0c82fe84,
361 /* XFER_PIO_2 */ 0x0c82fea6,
362 /* XFER_PIO_1 */ 0x0d02ff26,
363 /* XFER_PIO_0 */ 0x0d42ff7f
364};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100366#define HPT371_ALLOW_ATA133_6 1
367#define HPT302_ALLOW_ATA133_6 1
368#define HPT372_ALLOW_ATA133_6 1
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100369#define HPT370_ALLOW_ATA100_5 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370#define HPT366_ALLOW_ATA66_4 1
371#define HPT366_ALLOW_ATA66_3 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100373/* Supported ATA clock frequencies */
374enum ata_clock {
375 ATA_CLOCK_25MHZ,
376 ATA_CLOCK_33MHZ,
377 ATA_CLOCK_40MHZ,
378 ATA_CLOCK_50MHZ,
379 ATA_CLOCK_66MHZ,
380 NUM_ATA_CLOCKS
Alan Coxb39b01f2005-06-27 15:24:27 -0700381};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100383struct hpt_timings {
384 u32 pio_mask;
385 u32 dma_mask;
386 u32 ultra_mask;
387 u32 *clock_table[NUM_ATA_CLOCKS];
388};
389
Alan Coxb39b01f2005-06-27 15:24:27 -0700390/*
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100391 * Hold all the HighPoint chip information in one place.
Alan Coxb39b01f2005-06-27 15:24:27 -0700392 */
393
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100394struct hpt_info {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200395 char *chip_name; /* Chip name */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100396 u8 chip_type; /* Chip type */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200397 u8 udma_mask; /* Allowed UltraDMA modes mask. */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100398 u8 dpll_clk; /* DPLL clock in MHz */
399 u8 pci_clk; /* PCI clock in MHz */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100400 struct hpt_timings *timings; /* Chipset timing data */
401 u8 clock; /* ATA clock selected */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100402};
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100403
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100404/* Supported HighPoint chips */
405enum {
406 HPT36x,
407 HPT370,
408 HPT370A,
409 HPT374,
410 HPT372,
411 HPT372A,
412 HPT302,
413 HPT371,
414 HPT372N,
415 HPT302N,
416 HPT371N
417};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100419static struct hpt_timings hpt36x_timings = {
420 .pio_mask = 0xc1f8ffff,
421 .dma_mask = 0x303800ff,
422 .ultra_mask = 0x30070000,
423 .clock_table = {
424 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
425 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
426 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
427 [ATA_CLOCK_50MHZ] = NULL,
428 [ATA_CLOCK_66MHZ] = NULL
429 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100430};
431
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100432static struct hpt_timings hpt37x_timings = {
433 .pio_mask = 0xcfc3ffff,
434 .dma_mask = 0x31c001ff,
435 .ultra_mask = 0x303c0000,
436 .clock_table = {
437 [ATA_CLOCK_25MHZ] = NULL,
438 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
439 [ATA_CLOCK_40MHZ] = NULL,
440 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
441 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
442 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100443};
444
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200445static const struct hpt_info hpt36x __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200446 .chip_name = "HPT36x",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100447 .chip_type = HPT36x,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200448 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100449 .dpll_clk = 0, /* no DPLL */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100450 .timings = &hpt36x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100451};
452
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200453static const struct hpt_info hpt370 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200454 .chip_name = "HPT370",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100455 .chip_type = HPT370,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200456 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100457 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100458 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100459};
460
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200461static const struct hpt_info hpt370a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200462 .chip_name = "HPT370A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100463 .chip_type = HPT370A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200464 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100465 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100466 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100467};
468
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200469static const struct hpt_info hpt374 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200470 .chip_name = "HPT374",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100471 .chip_type = HPT374,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200472 .udma_mask = ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100473 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100474 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100475};
476
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200477static const struct hpt_info hpt372 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200478 .chip_name = "HPT372",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100479 .chip_type = HPT372,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200480 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100481 .dpll_clk = 55,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100482 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100483};
484
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200485static const struct hpt_info hpt372a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200486 .chip_name = "HPT372A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100487 .chip_type = HPT372A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200488 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100489 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100490 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100491};
492
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200493static const struct hpt_info hpt302 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200494 .chip_name = "HPT302",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100495 .chip_type = HPT302,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200496 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100497 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100498 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100499};
500
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200501static const struct hpt_info hpt371 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200502 .chip_name = "HPT371",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100503 .chip_type = HPT371,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200504 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100505 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100506 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100507};
508
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200509static const struct hpt_info hpt372n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200510 .chip_name = "HPT372N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100511 .chip_type = HPT372N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200512 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100513 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100514 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100515};
516
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200517static const struct hpt_info hpt302n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200518 .chip_name = "HPT302N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100519 .chip_type = HPT302N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200520 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100521 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100522 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100523};
524
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200525static const struct hpt_info hpt371n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200526 .chip_name = "HPT371N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100527 .chip_type = HPT371N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200528 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100529 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100530 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100531};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100533static int check_in_drive_list(ide_drive_t *drive, const char **list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534{
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200535 char *m = (char *)&drive->id[ATA_ID_PROD];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100537 while (*list)
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200538 if (!strcmp(*list++, m))
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100539 return 1;
540 return 0;
541}
Alan Coxb39b01f2005-06-27 15:24:27 -0700542
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200543static struct hpt_info *hpt3xx_get_info(struct device *dev)
544{
545 struct ide_host *host = dev_get_drvdata(dev);
546 struct hpt_info *info = (struct hpt_info *)host->host_priv;
547
548 return dev == host->dev[1] ? info + 1 : info;
549}
550
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551/*
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200552 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
553 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554 */
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200555
556static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100558 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200559 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200560 u8 mask = hwif->ultra_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200562 switch (info->chip_type) {
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200563 case HPT36x:
564 if (!HPT366_ALLOW_ATA66_4 ||
565 check_in_drive_list(drive, bad_ata66_4))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200566 mask = ATA_UDMA3;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100567
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200568 if (!HPT366_ALLOW_ATA66_3 ||
569 check_in_drive_list(drive, bad_ata66_3))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200570 mask = ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200571 break;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200572 case HPT370:
573 if (!HPT370_ALLOW_ATA100_5 ||
574 check_in_drive_list(drive, bad_ata100_5))
575 mask = ATA_UDMA4;
576 break;
577 case HPT370A:
578 if (!HPT370_ALLOW_ATA100_5 ||
579 check_in_drive_list(drive, bad_ata100_5))
580 return ATA_UDMA4;
581 case HPT372 :
582 case HPT372A:
583 case HPT372N:
584 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200585 if (ata_id_is_sata(drive->id))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200586 mask &= ~0x0e;
587 /* Fall thru */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200588 default:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200589 return mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590 }
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200591
592 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593}
594
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200595static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
596{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100597 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200598 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200599
600 switch (info->chip_type) {
601 case HPT372 :
602 case HPT372A:
603 case HPT372N:
604 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200605 if (ata_id_is_sata(drive->id))
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200606 return 0x00;
607 /* Fall thru */
608 default:
609 return 0x07;
610 }
611}
612
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100613static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614{
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800615 int i;
616
617 /*
618 * Lookup the transfer mode table to get the index into
619 * the timing table.
620 *
621 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
622 */
623 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
624 if (xfer_speeds[i] == speed)
625 break;
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100626
627 return info->timings->clock_table[info->clock][i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628}
629
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100630static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631{
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +0200632 ide_hwif_t *hwif = drive->hwif;
633 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200634 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100635 struct hpt_timings *t = info->timings;
636 u8 itr_addr = 0x40 + (drive->dn * 4);
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100637 u32 old_itr = 0;
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100638 u32 new_itr = get_speed_setting(speed, info);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100639 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
640 (speed < XFER_UDMA_0 ? t->dma_mask :
641 t->ultra_mask);
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200642
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100643 pci_read_config_dword(dev, itr_addr, &old_itr);
644 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 /*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100646 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
647 * to avoid problems handling I/O errors later
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100649 new_itr &= ~0xc0000000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100651 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652}
653
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200654static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655{
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100656 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657}
658
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100659static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100661 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100662 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200663 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664
Bartlomiej Zolnierkiewicz734affd2009-06-07 15:37:10 +0200665 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200666 return;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100667
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200668 if (info->chip_type >= HPT370) {
669 u8 scr1 = 0;
670
671 pci_read_config_byte(dev, 0x5a, &scr1);
672 if (((scr1 & 0x10) >> 4) != mask) {
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100673 if (mask)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200674 scr1 |= 0x10;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100675 else
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200676 scr1 &= ~0x10;
677 pci_write_config_byte(dev, 0x5a, scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 }
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200679 } else if (mask)
680 disable_irq(hwif->irq);
681 else
682 enable_irq(hwif->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683}
684
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685/*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100686 * This is specific to the HPT366 UDMA chipset
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 * by HighPoint|Triones Technologies, Inc.
688 */
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200689static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100691 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100692 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100694 pci_read_config_byte(dev, 0x50, &mcr1);
695 pci_read_config_byte(dev, 0x52, &mcr3);
696 pci_read_config_byte(dev, 0x5a, &scr1);
697 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
Harvey Harrisoneb639632008-04-26 22:25:20 +0200698 drive->name, __func__, mcr1, mcr3, scr1);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100699 if (scr1 & 0x10)
700 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200701 ide_dma_lost_irq(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702}
703
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100704static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100706 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100707 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100708
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100709 pci_write_config_byte(dev, hwif->select_data, 0x37);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710 udelay(10);
711}
712
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100713static void hpt370_irq_timeout(ide_drive_t *drive)
714{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100715 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100716 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100717 u16 bfifo = 0;
718 u8 dma_cmd;
719
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100720 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100721 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
722
723 /* get DMA command mode */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200724 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100725 /* stop DMA */
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200726 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100727 hpt370_clear_engine(drive);
728}
729
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200730static void hpt370_dma_start(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731{
732#ifdef HPT_RESET_STATE_ENGINE
733 hpt370_clear_engine(drive);
734#endif
735 ide_dma_start(drive);
736}
737
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200738static int hpt370_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100740 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200741 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200743 if (dma_stat & ATA_DMA_ACTIVE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744 /* wait a little */
745 udelay(20);
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200746 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200747 if (dma_stat & ATA_DMA_ACTIVE)
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100748 hpt370_irq_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749 }
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200750 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751}
752
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753/* returns 1 if DMA IRQ issued, 0 otherwise */
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200754static int hpt374_dma_test_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100756 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100757 struct pci_dev *dev = to_pci_dev(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758 u16 bfifo = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100759 u8 dma_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100761 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762 if (bfifo & 0x1FF) {
763// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
764 return 0;
765 }
766
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200767 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768 /* return 1 if INTR asserted */
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200769 if (dma_stat & ATA_DMA_INTR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 return 1;
771
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 return 0;
773}
774
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200775static int hpt374_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100777 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100778 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100779 u8 mcr = 0, mcr_addr = hwif->select_data;
780 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100782 pci_read_config_byte(dev, 0x6a, &bwsr);
783 pci_read_config_byte(dev, mcr_addr, &mcr);
784 if (bwsr & mask)
785 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200786 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787}
788
789/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800790 * hpt3xxn_set_clock - perform clock switching dance
791 * @hwif: hwif to switch
792 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800794 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800796
797static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798{
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100799 unsigned long base = hwif->extra_base;
800 u8 scr2 = inb(base + 0x6b);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800801
802 if ((scr2 & 0x7f) == mode)
803 return;
804
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805 /* Tristate the bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100806 outb(0x80, base + 0x63);
807 outb(0x80, base + 0x67);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800808
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 /* Switch clock and reset channels */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100810 outb(mode, base + 0x6b);
811 outb(0xc0, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800812
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100813 /*
814 * Reset the state machines.
815 * NOTE: avoid accidentally enabling the disabled channels.
816 */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100817 outb(inb(base + 0x60) | 0x32, base + 0x60);
818 outb(inb(base + 0x64) | 0x32, base + 0x64);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800819
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820 /* Complete reset */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100821 outb(0x00, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800822
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823 /* Reconnect channels to bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100824 outb(0x00, base + 0x63);
825 outb(0x00, base + 0x67);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826}
827
828/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800829 * hpt3xxn_rw_disk - prepare for I/O
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830 * @drive: drive for command
831 * @rq: block request structure
832 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800833 * This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 * We need it because of the clock switching.
835 */
836
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800837static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100839 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840}
841
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100842/**
843 * hpt37x_calibrate_dpll - calibrate the DPLL
844 * @dev: PCI device
845 *
846 * Perform a calibration cycle on the DPLL.
847 * Returns 1 if this succeeds
848 */
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200849static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100851 u32 dpll = (f_high << 16) | f_low | 0x100;
852 u8 scr2;
853 int i;
Alan Coxb39b01f2005-06-27 15:24:27 -0700854
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100855 pci_write_config_dword(dev, 0x5c, dpll);
Alan Coxb39b01f2005-06-27 15:24:27 -0700856
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100857 /* Wait for oscillator ready */
858 for(i = 0; i < 0x5000; ++i) {
859 udelay(50);
860 pci_read_config_byte(dev, 0x5b, &scr2);
861 if (scr2 & 0x80)
Alan Coxb39b01f2005-06-27 15:24:27 -0700862 break;
863 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100864 /* See if it stays ready (we'll just bail out if it's not yet) */
865 for(i = 0; i < 0x1000; ++i) {
866 pci_read_config_byte(dev, 0x5b, &scr2);
867 /* DPLL destabilized? */
868 if(!(scr2 & 0x80))
869 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +0100870 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100871 /* Turn off tuning, we have the DPLL set */
872 pci_read_config_dword (dev, 0x5c, &dpll);
873 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
874 return 1;
Alan Coxb39b01f2005-06-27 15:24:27 -0700875}
876
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200877static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +0200878{
879 struct ide_host *host = pci_get_drvdata(dev);
880 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
881 u8 chip_type = info->chip_type;
882 u8 new_mcr, old_mcr = 0;
883
884 /*
885 * Disable the "fast interrupt" prediction. Don't hold off
886 * on interrupts. (== 0x01 despite what the docs say)
887 */
888 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
889
890 if (chip_type >= HPT374)
891 new_mcr = old_mcr & ~0x07;
892 else if (chip_type >= HPT370) {
893 new_mcr = old_mcr;
894 new_mcr &= ~0x02;
895#ifdef HPT_DELAY_INTERRUPT
896 new_mcr &= ~0x01;
897#else
898 new_mcr |= 0x01;
899#endif
900 } else /* HPT366 and HPT368 */
901 new_mcr = old_mcr & ~0x80;
902
903 if (new_mcr != old_mcr)
904 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
905}
906
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +0100907static int init_chipset_hpt366(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100909 unsigned long io_base = pci_resource_start(dev, 4);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200910 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
Bartlomiej Zolnierkiewicza326b022008-07-24 22:53:33 +0200911 const char *name = DRV_NAME;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100912 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200913 u8 chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100914 enum ata_clock clock;
915
Sergei Shtylyov72931362007-09-11 22:28:35 +0200916 chip_type = info->chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100917
Alan Coxb39b01f2005-06-27 15:24:27 -0700918 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
919 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
920 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
921 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100923 /*
924 * First, try to estimate the PCI clock frequency...
925 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200926 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100927 u8 scr1 = 0;
928 u16 f_cnt = 0;
929 u32 temp = 0;
Alan Coxb39b01f2005-06-27 15:24:27 -0700930
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100931 /* Interrupt force enable. */
932 pci_read_config_byte(dev, 0x5a, &scr1);
933 if (scr1 & 0x10)
934 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100935
936 /*
937 * HighPoint does this for HPT372A.
938 * NOTE: This register is only writeable via I/O space.
939 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200940 if (chip_type == HPT372A)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100941 outb(0x0e, io_base + 0x9c);
942
943 /*
944 * Default to PCI clock. Make sure MA15/16 are set to output
945 * to prevent drives having problems with 40-pin cables.
946 */
947 pci_write_config_byte(dev, 0x5b, 0x23);
948
949 /*
950 * We'll have to read f_CNT value in order to determine
951 * the PCI clock frequency according to the following ratio:
952 *
953 * f_CNT = Fpci * 192 / Fdpll
954 *
955 * First try reading the register in which the HighPoint BIOS
956 * saves f_CNT value before reprogramming the DPLL from its
957 * default setting (which differs for the various chips).
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100958 *
Sergei Shtylyov72931362007-09-11 22:28:35 +0200959 * NOTE: This register is only accessible via I/O space;
960 * HPT374 BIOS only saves it for the function 0, so we have to
961 * always read it from there -- no need to check the result of
962 * pci_get_slot() for the function 0 as the whole device has
963 * been already "pinned" (via function 1) in init_setup_hpt374()
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100964 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200965 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
966 struct pci_dev *dev1 = pci_get_slot(dev->bus,
967 dev->devfn - 1);
968 unsigned long io_base = pci_resource_start(dev1, 4);
969
970 temp = inl(io_base + 0x90);
971 pci_dev_put(dev1);
972 } else
973 temp = inl(io_base + 0x90);
974
975 /*
976 * In case the signature check fails, we'll have to
977 * resort to reading the f_CNT register itself in hopes
978 * that nobody has touched the DPLL yet...
979 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100980 if ((temp & 0xFFFFF000) != 0xABCDE000) {
981 int i;
982
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200983 printk(KERN_WARNING "%s %s: no clock data saved by "
984 "BIOS\n", name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100985
986 /* Calculate the average value of f_CNT. */
987 for (temp = i = 0; i < 128; i++) {
988 pci_read_config_word(dev, 0x78, &f_cnt);
989 temp += f_cnt & 0x1ff;
990 mdelay(1);
991 }
992 f_cnt = temp / 128;
993 } else
994 f_cnt = temp & 0x1ff;
995
996 dpll_clk = info->dpll_clk;
997 pci_clk = (f_cnt * dpll_clk) / 192;
998
999 /* Clamp PCI clock to bands. */
1000 if (pci_clk < 40)
1001 pci_clk = 33;
1002 else if(pci_clk < 45)
1003 pci_clk = 40;
1004 else if(pci_clk < 55)
1005 pci_clk = 50;
1006 else
1007 pci_clk = 66;
1008
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001009 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1010 "assuming %d MHz PCI\n", name, pci_name(dev),
1011 dpll_clk, f_cnt, pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001012 } else {
1013 u32 itr1 = 0;
1014
1015 pci_read_config_dword(dev, 0x40, &itr1);
1016
1017 /* Detect PCI clock by looking at cmd_high_time. */
1018 switch((itr1 >> 8) & 0x07) {
1019 case 0x09:
1020 pci_clk = 40;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001021 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001022 case 0x05:
1023 pci_clk = 25;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001024 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001025 case 0x07:
1026 default:
1027 pci_clk = 33;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001028 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001029 }
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001030 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001032 /* Let's assume we'll use PCI clock for the ATA clock... */
1033 switch (pci_clk) {
1034 case 25:
1035 clock = ATA_CLOCK_25MHZ;
1036 break;
1037 case 33:
1038 default:
1039 clock = ATA_CLOCK_33MHZ;
1040 break;
1041 case 40:
1042 clock = ATA_CLOCK_40MHZ;
1043 break;
1044 case 50:
1045 clock = ATA_CLOCK_50MHZ;
1046 break;
1047 case 66:
1048 clock = ATA_CLOCK_66MHZ;
1049 break;
1050 }
1051
1052 /*
1053 * Only try the DPLL if we don't have a table for the PCI clock that
1054 * we are running at for HPT370/A, always use it for anything newer...
1055 *
1056 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1057 * We also don't like using the DPLL because this causes glitches
1058 * on PRST-/SRST- when the state engine gets reset...
1059 */
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001060 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001061 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1062 int adjust;
1063
1064 /*
1065 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1066 * supported/enabled, use 50 MHz DPLL clock otherwise...
1067 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001068 if (info->udma_mask == ATA_UDMA6) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001069 dpll_clk = 66;
1070 clock = ATA_CLOCK_66MHZ;
1071 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1072 dpll_clk = 50;
1073 clock = ATA_CLOCK_50MHZ;
1074 }
1075
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001076 if (info->timings->clock_table[clock] == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001077 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1078 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001079 return -EIO;
1080 }
1081
1082 /* Select the DPLL clock. */
1083 pci_write_config_byte(dev, 0x5b, 0x21);
1084
1085 /*
1086 * Adjust the DPLL based upon PCI clock, enable it,
1087 * and wait for stabilization...
1088 */
1089 f_low = (pci_clk * 48) / dpll_clk;
1090
1091 for (adjust = 0; adjust < 8; adjust++) {
1092 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1093 break;
1094
1095 /*
1096 * See if it'll settle at a fractionally different clock
1097 */
1098 if (adjust & 1)
1099 f_low -= adjust >> 1;
1100 else
1101 f_low += adjust >> 1;
1102 }
1103 if (adjust == 8) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001104 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1105 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001106 return -EIO;
1107 }
1108
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001109 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1110 name, pci_name(dev), dpll_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001111 } else {
1112 /* Mark the fact that we're not using the DPLL. */
1113 dpll_clk = 0;
1114
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001115 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1116 name, pci_name(dev), pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001117 }
1118
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001119 /* Store the clock frequencies. */
1120 info->dpll_clk = dpll_clk;
1121 info->pci_clk = pci_clk;
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001122 info->clock = clock;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001123
Sergei Shtylyov72931362007-09-11 22:28:35 +02001124 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001125 u8 mcr1, mcr4;
1126
1127 /*
1128 * Reset the state engines.
1129 * NOTE: Avoid accidentally enabling the disabled channels.
1130 */
1131 pci_read_config_byte (dev, 0x50, &mcr1);
1132 pci_read_config_byte (dev, 0x54, &mcr4);
1133 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1134 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1135 udelay(100);
1136 }
1137
1138 /*
1139 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1140 * the MISC. register to stretch the UltraDMA Tss timing.
1141 * NOTE: This register is only writeable via I/O space.
1142 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001143 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001144 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1145
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +02001146 hpt3xx_disable_fast_irq(dev, 0x50);
1147 hpt3xx_disable_fast_irq(dev, 0x54);
1148
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +01001149 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150}
1151
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +02001152static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001153{
1154 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001155 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001156 u8 chip_type = info->chip_type;
1157 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1158
1159 /*
1160 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1161 * address lines to access an external EEPROM. To read valid
1162 * cable detect state the pins must be enabled as inputs.
1163 */
1164 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1165 /*
1166 * HPT374 PCI function 1
1167 * - set bit 15 of reg 0x52 to enable TCBLID as input
1168 * - set bit 15 of reg 0x56 to enable FCBLID as input
1169 */
1170 u8 mcr_addr = hwif->select_data + 2;
1171 u16 mcr;
1172
1173 pci_read_config_word(dev, mcr_addr, &mcr);
1174 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1175 /* now read cable id register */
1176 pci_read_config_byte(dev, 0x5a, &scr1);
1177 pci_write_config_word(dev, mcr_addr, mcr);
1178 } else if (chip_type >= HPT370) {
1179 /*
1180 * HPT370/372 and 374 pcifn 0
1181 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1182 */
1183 u8 scr2 = 0;
1184
1185 pci_read_config_byte(dev, 0x5b, &scr2);
1186 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1187 /* now read cable id register */
1188 pci_read_config_byte(dev, 0x5a, &scr1);
1189 pci_write_config_byte(dev, 0x5b, scr2);
1190 } else
1191 pci_read_config_byte(dev, 0x5a, &scr1);
1192
1193 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1194}
1195
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1197{
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001198 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001199 u8 chip_type = info->chip_type;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001200
1201 /* Cache the channel's MISC. control registers' offset */
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001202 hwif->select_data = hwif->channel ? 0x54 : 0x50;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001203
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001204 /*
1205 * HPT3xxN chips have some complications:
1206 *
1207 * - on 33 MHz PCI we must clock switch
1208 * - on 66 MHz PCI we must NOT use the PCI clock
1209 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001210 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001211 /*
1212 * Clock is shared between the channels,
1213 * so we'll have to serialize them... :-(
1214 */
Bartlomiej Zolnierkiewicz702c0262008-12-29 20:27:36 +01001215 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001216 hwif->rw_disk = &hpt3xxn_rw_disk;
1217 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218}
1219
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001220static int __devinit init_dma_hpt366(ide_hwif_t *hwif,
1221 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001223 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001224 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1225 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226
Bartlomiej Zolnierkiewiczebb00fb2008-07-23 19:55:51 +02001227 if (base == 0)
1228 return -1;
1229
1230 hwif->dma_base = base;
1231
1232 if (ide_pci_check_simplex(hwif, d) < 0)
1233 return -1;
1234
1235 if (ide_pci_set_master(dev, d->name) < 0)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001236 return -1;
1237
1238 dma_old = inb(base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239
1240 local_irq_save(flags);
1241
1242 dma_new = dma_old;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001243 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1244 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245
1246 if (masterdma & 0x30) dma_new |= 0x20;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001247 if ( slavedma & 0x30) dma_new |= 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248 if (dma_new != dma_old)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001249 outb(dma_new, base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250
1251 local_irq_restore(flags);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001252
1253 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1254 hwif->name, base, base + 7);
1255
1256 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1257
1258 if (ide_allocate_dma_engine(hwif))
1259 return -1;
1260
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001261 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262}
1263
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001264static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001265{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001266 if (dev2->irq != dev->irq) {
1267 /* FIXME: we need a core pci_set_interrupt() */
1268 dev2->irq = dev->irq;
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001269 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001270 "fixed\n", pci_name(dev2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001271 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001272}
1273
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001274static void __devinit hpt371_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275{
Auke Kok44c10132007-06-08 15:46:36 -07001276 u8 mcr1 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001277
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001278 /*
1279 * HPT371 chips physically have only one channel, the secondary one,
1280 * but the primary channel registers do exist! Go figure...
1281 * So, we manually disable the non-existing channel here
1282 * (if the BIOS hasn't done this already).
1283 */
1284 pci_read_config_byte(dev, 0x50, &mcr1);
1285 if (mcr1 & 0x04)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001286 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001287}
1288
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001289static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001290{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001291 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001292
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001293 /*
1294 * Now we'll have to force both channels enabled if
1295 * at least one of them has been enabled by BIOS...
1296 */
1297 pci_read_config_byte(dev, 0x50, &mcr1);
1298 if (mcr1 & 0x30)
1299 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001300
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001301 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1302 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001303
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001304 if (pin1 != pin2 && dev->irq == dev2->irq) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001305 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001306 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001307 return 1;
1308 }
1309
1310 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001311}
1312
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001313#define IDE_HFLAGS_HPT3XX \
1314 (IDE_HFLAG_NO_ATAPI_DMA | \
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001315 IDE_HFLAG_OFF_BOARD)
1316
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001317static const struct ide_port_ops hpt3xx_port_ops = {
1318 .set_pio_mode = hpt3xx_set_pio_mode,
1319 .set_dma_mode = hpt3xx_set_mode,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001320 .maskproc = hpt3xx_maskproc,
1321 .mdma_filter = hpt3xx_mdma_filter,
1322 .udma_filter = hpt3xx_udma_filter,
1323 .cable_detect = hpt3xx_cable_detect,
1324};
1325
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001326static const struct ide_dma_ops hpt37x_dma_ops = {
1327 .dma_host_set = ide_dma_host_set,
1328 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001329 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001330 .dma_end = hpt374_dma_end,
1331 .dma_test_irq = hpt374_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001332 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001333 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001334 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001335};
1336
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001337static const struct ide_dma_ops hpt370_dma_ops = {
1338 .dma_host_set = ide_dma_host_set,
1339 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001340 .dma_start = hpt370_dma_start,
1341 .dma_end = hpt370_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001342 .dma_test_irq = ide_dma_test_irq,
1343 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001344 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Bartlomiej Zolnierkiewicz35c9b4d2009-03-31 20:15:19 +02001345 .dma_clear = hpt370_irq_timeout,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001346 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001347};
1348
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001349static const struct ide_dma_ops hpt36x_dma_ops = {
1350 .dma_host_set = ide_dma_host_set,
1351 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001352 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +02001353 .dma_end = ide_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001354 .dma_test_irq = ide_dma_test_irq,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001355 .dma_lost_irq = hpt366_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001356 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001357 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001358};
1359
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +02001360static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001361 { /* 0: HPT36x */
1362 .name = DRV_NAME,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001363 .init_chipset = init_chipset_hpt366,
1364 .init_hwif = init_hwif_hpt366,
1365 .init_dma = init_dma_hpt366,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001366 /*
1367 * HPT36x chips have one channel per function and have
1368 * both channel enable bits located differently and visible
1369 * to both functions -- really stupid design decision... :-(
1370 * Bit 4 is for the primary channel, bit 5 for the secondary.
1371 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001372 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001373 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001374 .dma_ops = &hpt36x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001375 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001376 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001377 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001378 },
1379 { /* 1: HPT3xx */
1380 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001381 .init_chipset = init_chipset_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382 .init_hwif = init_hwif_hpt366,
1383 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001384 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001385 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001386 .dma_ops = &hpt37x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001387 .host_flags = IDE_HFLAGS_HPT3XX,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001388 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001389 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390 }
1391};
1392
1393/**
1394 * hpt366_init_one - called when an HPT366 is found
1395 * @dev: the hpt366 device
1396 * @id: the matching pci id
1397 *
1398 * Called when the PCI registration layer (or the IDE initialization)
1399 * finds a device matching our IDE device tables.
1400 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1402{
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +02001403 const struct hpt_info *info = NULL;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001404 struct hpt_info *dyn_info;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001405 struct pci_dev *dev2 = NULL;
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +02001406 struct ide_port_info d;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001407 u8 idx = id->driver_data;
1408 u8 rev = dev->revision;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001409 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001411 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1412 return -ENODEV;
1413
1414 switch (idx) {
1415 case 0:
1416 if (rev < 3)
1417 info = &hpt36x;
1418 else {
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001419 switch (min_t(u8, rev, 6)) {
1420 case 3: info = &hpt370; break;
1421 case 4: info = &hpt370a; break;
1422 case 5: info = &hpt372; break;
1423 case 6: info = &hpt372n; break;
1424 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001425 idx++;
1426 }
1427 break;
1428 case 1:
1429 info = (rev > 1) ? &hpt372n : &hpt372a;
1430 break;
1431 case 2:
1432 info = (rev > 1) ? &hpt302n : &hpt302;
1433 break;
1434 case 3:
1435 hpt371_init(dev);
1436 info = (rev > 1) ? &hpt371n : &hpt371;
1437 break;
1438 case 4:
1439 info = &hpt374;
1440 break;
1441 case 5:
1442 info = &hpt372n;
1443 break;
1444 }
1445
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001446 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001447
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001448 d = hpt366_chipsets[min_t(u8, idx, 1)];
1449
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001450 d.udma_mask = info->udma_mask;
1451
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001452 /* fixup ->dma_ops for HPT370/HPT370A */
1453 if (info == &hpt370 || info == &hpt370a)
1454 d.dma_ops = &hpt370_dma_ops;
1455
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001456 if (info == &hpt36x || info == &hpt374)
1457 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1458
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001459 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1460 if (dyn_info == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001461 printk(KERN_ERR "%s %s: out of memory!\n",
1462 d.name, pci_name(dev));
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001463 pci_dev_put(dev2);
1464 return -ENOMEM;
1465 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001466
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001467 /*
1468 * Copy everything from a static "template" structure
1469 * to just allocated per-chip hpt_info structure.
1470 */
1471 memcpy(dyn_info, info, sizeof(*dyn_info));
1472
1473 if (dev2) {
1474 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001475
1476 if (info == &hpt374)
1477 hpt374_init(dev, dev2);
1478 else {
1479 if (hpt36x_init(dev, dev2))
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +02001480 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001481 }
1482
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001483 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1484 if (ret < 0) {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001485 pci_dev_put(dev2);
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001486 kfree(dyn_info);
1487 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001488 return ret;
1489 }
1490
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001491 ret = ide_pci_init_one(dev, &d, dyn_info);
1492 if (ret < 0)
1493 kfree(dyn_info);
1494
1495 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496}
1497
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001498static void __devexit hpt366_remove(struct pci_dev *dev)
1499{
1500 struct ide_host *host = pci_get_drvdata(dev);
1501 struct ide_info *info = host->host_priv;
1502 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1503
1504 ide_pci_remove(dev);
1505 pci_dev_put(dev2);
1506 kfree(info);
1507}
1508
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001509static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = {
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001510 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1511 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1512 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1513 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1514 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1515 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516 { 0, },
1517};
1518MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1519
Bartlomiej Zolnierkiewicza9ab09e22008-10-13 21:39:41 +02001520static struct pci_driver hpt366_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521 .name = "HPT366_IDE",
1522 .id_table = hpt366_pci_tbl,
1523 .probe = hpt366_init_one,
Adrian Bunka69999e2008-08-18 21:40:03 +02001524 .remove = __devexit_p(hpt366_remove),
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +02001525 .suspend = ide_pci_suspend,
1526 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527};
1528
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +01001529static int __init hpt366_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530{
Bartlomiej Zolnierkiewicza9ab09e22008-10-13 21:39:41 +02001531 return ide_pci_register_driver(&hpt366_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532}
1533
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001534static void __exit hpt366_ide_exit(void)
1535{
Bartlomiej Zolnierkiewicza9ab09e22008-10-13 21:39:41 +02001536 pci_unregister_driver(&hpt366_pci_driver);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001537}
1538
Linus Torvalds1da177e2005-04-16 15:20:36 -07001539module_init(hpt366_ide_init);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001540module_exit(hpt366_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541
1542MODULE_AUTHOR("Andre Hedrick");
1543MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1544MODULE_LICENSE("GPL");