blob: 7d0a5ea086567fb03bfa2c024aaa04ac0921e4a6 [file] [log] [blame]
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
Greg Rosedc641b72013-12-18 13:45:51 +00004 * Copyright(c) 2013 - 2014 Intel Corporation.
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
Greg Rosedc641b72013-12-18 13:45:51 +000015 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000017 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
Mitch Williams1c112a62014-04-04 04:43:06 +000027#include <linux/prefetch.h>
Mitch Williamsa132af22015-01-24 09:58:35 +000028#include <net/busy_poll.h>
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000029#include "i40e.h"
Jesse Brandeburg206812b2014-02-12 01:45:33 +000030#include "i40e_prototype.h"
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000031
32static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34{
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40}
41
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +000042#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +000043#define I40E_FD_CLEAN_DELAY 10
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000044/**
45 * i40e_program_fdir_filter - Program a Flow Director filter
Joseph Gasparakis17a73f62014-02-12 01:45:30 +000046 * @fdir_data: Packet data that will be filter parameters
47 * @raw_packet: the pre-allocated packet buffer for FDir
Jeff Kirsherb40c82e2015-02-27 09:18:34 +000048 * @pf: The PF pointer
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000049 * @add: True for add/update, False for remove
50 **/
Joseph Gasparakis17a73f62014-02-12 01:45:30 +000051int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000052 struct i40e_pf *pf, bool add)
53{
54 struct i40e_filter_program_desc *fdir_desc;
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +000055 struct i40e_tx_buffer *tx_buf, *first;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000056 struct i40e_tx_desc *tx_desc;
57 struct i40e_ring *tx_ring;
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +000058 unsigned int fpt, dcc;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000059 struct i40e_vsi *vsi;
60 struct device *dev;
61 dma_addr_t dma;
62 u32 td_cmd = 0;
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +000063 u16 delay = 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000064 u16 i;
65
66 /* find existing FDIR VSI */
67 vsi = NULL;
Mitch Williams505682c2014-05-20 08:01:37 +000068 for (i = 0; i < pf->num_alloc_vsi; i++)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000069 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
70 vsi = pf->vsi[i];
71 if (!vsi)
72 return -ENOENT;
73
Alexander Duyck9f65e152013-09-28 06:00:58 +000074 tx_ring = vsi->tx_rings[0];
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000075 dev = tx_ring->dev;
76
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +000077 /* we need two descriptors to add/del a filter and we can wait */
78 do {
79 if (I40E_DESC_UNUSED(tx_ring) > 1)
80 break;
81 msleep_interruptible(1);
82 delay++;
83 } while (delay < I40E_FD_CLEAN_DELAY);
84
85 if (!(I40E_DESC_UNUSED(tx_ring) > 1))
86 return -EAGAIN;
87
Joseph Gasparakis17a73f62014-02-12 01:45:30 +000088 dma = dma_map_single(dev, raw_packet,
89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +000090 if (dma_mapping_error(dev, dma))
91 goto dma_fail;
92
93 /* grab the next descriptor */
Alexander Duyckfc4ac672013-09-28 06:00:22 +000094 i = tx_ring->next_to_use;
95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +000096 first = &tx_ring->tx_bi[i];
97 memset(first, 0, sizeof(struct i40e_tx_buffer));
Alexander Duyckfc4ac672013-09-28 06:00:22 +000098
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +000099 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000100
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
102 I40E_TXD_FLTR_QW0_QINDEX_MASK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000103
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000106
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
108 I40E_TXD_FLTR_QW0_PCTYPE_MASK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000109
110 /* Use LAN VSI Id if not programmed by user */
111 if (fdir_data->dest_vsi == 0)
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000112 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000114 else
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000115 fpt |= ((u32)fdir_data->dest_vsi <<
116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000118
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000120
121 if (add)
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
123 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000124 else
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
126 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000127
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
129 I40E_TXD_FLTR_QW1_DEST_MASK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000130
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000133
134 if (fdir_data->cnt_index != 0) {
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
136 dcc |= ((u32)fdir_data->cnt_index <<
137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
Anjali Singhai Jain433c47d2014-05-22 06:32:17 +0000138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000139 }
140
Jesse Brandeburg99753ea2014-06-04 04:22:49 +0000141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
142 fdir_desc->rsvd = cpu_to_le32(0);
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
145
146 /* Now program a dummy descriptor */
Alexander Duyckfc4ac672013-09-28 06:00:22 +0000147 i = tx_ring->next_to_use;
148 tx_desc = I40E_TX_DESC(tx_ring, i);
Anjali Singhai Jain298deef2013-11-28 06:39:33 +0000149 tx_buf = &tx_ring->tx_bi[i];
Alexander Duyckfc4ac672013-09-28 06:00:22 +0000150
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
152
153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000154
Anjali Singhai Jain298deef2013-11-28 06:39:33 +0000155 /* record length, and DMA address */
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
Anjali Singhai Jain298deef2013-11-28 06:39:33 +0000157 dma_unmap_addr_set(tx_buf, dma, dma);
158
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000159 tx_desc->buffer_addr = cpu_to_le64(dma);
Jesse Brandeburgeaefbd02013-09-28 07:13:54 +0000160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000161
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
163 tx_buf->raw_buf = (void *)raw_packet;
164
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000165 tx_desc->cmd_type_offset_bsz =
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000167
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000168 /* Force memory writes to complete before letting h/w
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000169 * know there are new descriptors to fetch.
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000170 */
171 wmb();
172
Alexander Duyckfc4ac672013-09-28 06:00:22 +0000173 /* Mark the data descriptor to be watched */
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000174 first->next_to_watch = tx_desc;
Alexander Duyckfc4ac672013-09-28 06:00:22 +0000175
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000176 writel(tx_ring->next_to_use, tx_ring->tail);
177 return 0;
178
179dma_fail:
180 return -1;
181}
182
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000183#define IP_HEADER_OFFSET 14
184#define I40E_UDPIP_DUMMY_PACKET_LEN 42
185/**
186 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
187 * @vsi: pointer to the targeted VSI
188 * @fd_data: the flow director data required for the FDir descriptor
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000189 * @add: true adds a filter, false removes it
190 *
191 * Returns 0 if the filters were successfully added or removed
192 **/
193static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
194 struct i40e_fdir_filter *fd_data,
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000195 bool add)
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000196{
197 struct i40e_pf *pf = vsi->back;
198 struct udphdr *udp;
199 struct iphdr *ip;
200 bool err = false;
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000201 u8 *raw_packet;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000202 int ret;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000203 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
204 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
206
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000207 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
208 if (!raw_packet)
209 return -ENOMEM;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000210 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
211
212 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
213 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
214 + sizeof(struct iphdr));
215
216 ip->daddr = fd_data->dst_ip[0];
217 udp->dest = fd_data->dst_port;
218 ip->saddr = fd_data->src_ip[0];
219 udp->source = fd_data->src_port;
220
Kevin Scottb2d36c02014-04-09 05:58:59 +0000221 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
222 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
223 if (ret) {
224 dev_info(&pf->pdev->dev,
Carolyn Wybornye99bdd32014-07-09 07:46:12 +0000225 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
226 fd_data->pctype, fd_data->fd_id, ret);
Kevin Scottb2d36c02014-04-09 05:58:59 +0000227 err = true;
Anjali Singhai Jain4205d372015-02-27 09:15:27 +0000228 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
Anjali Singhai Jainf7233c52014-07-09 07:46:16 +0000229 if (add)
230 dev_info(&pf->pdev->dev,
231 "Filter OK for PCTYPE %d loc = %d\n",
232 fd_data->pctype, fd_data->fd_id);
233 else
234 dev_info(&pf->pdev->dev,
235 "Filter deleted for PCTYPE %d loc = %d\n",
236 fd_data->pctype, fd_data->fd_id);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000237 }
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000238 return err ? -EOPNOTSUPP : 0;
239}
240
241#define I40E_TCPIP_DUMMY_PACKET_LEN 54
242/**
243 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
244 * @vsi: pointer to the targeted VSI
245 * @fd_data: the flow director data required for the FDir descriptor
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000246 * @add: true adds a filter, false removes it
247 *
248 * Returns 0 if the filters were successfully added or removed
249 **/
250static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
251 struct i40e_fdir_filter *fd_data,
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000252 bool add)
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000253{
254 struct i40e_pf *pf = vsi->back;
255 struct tcphdr *tcp;
256 struct iphdr *ip;
257 bool err = false;
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000258 u8 *raw_packet;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000259 int ret;
260 /* Dummy packet */
261 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
262 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
264 0x0, 0x72, 0, 0, 0, 0};
265
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000266 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
267 if (!raw_packet)
268 return -ENOMEM;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000269 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
270
271 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
272 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
273 + sizeof(struct iphdr));
274
275 ip->daddr = fd_data->dst_ip[0];
276 tcp->dest = fd_data->dst_port;
277 ip->saddr = fd_data->src_ip[0];
278 tcp->source = fd_data->src_port;
279
280 if (add) {
Anjali Singhai Jain1e1be8f2014-07-10 08:03:26 +0000281 pf->fd_tcp_rule++;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000282 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
Anjali Singhai Jain2e4875e2015-04-16 20:06:06 -0400283 if (I40E_DEBUG_FD & pf->hw.debug_mask)
284 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000285 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
286 }
Anjali Singhai Jain1e1be8f2014-07-10 08:03:26 +0000287 } else {
288 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
289 (pf->fd_tcp_rule - 1) : 0;
290 if (pf->fd_tcp_rule == 0) {
291 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
Anjali Singhai Jain2e4875e2015-04-16 20:06:06 -0400292 if (I40E_DEBUG_FD & pf->hw.debug_mask)
293 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
Anjali Singhai Jain1e1be8f2014-07-10 08:03:26 +0000294 }
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000295 }
296
Kevin Scottb2d36c02014-04-09 05:58:59 +0000297 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000298 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
299
300 if (ret) {
301 dev_info(&pf->pdev->dev,
Carolyn Wybornye99bdd32014-07-09 07:46:12 +0000302 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
303 fd_data->pctype, fd_data->fd_id, ret);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000304 err = true;
Anjali Singhai Jain4205d372015-02-27 09:15:27 +0000305 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
Anjali Singhai Jainf7233c52014-07-09 07:46:16 +0000306 if (add)
307 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
308 fd_data->pctype, fd_data->fd_id);
309 else
310 dev_info(&pf->pdev->dev,
311 "Filter deleted for PCTYPE %d loc = %d\n",
312 fd_data->pctype, fd_data->fd_id);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000313 }
314
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000315 return err ? -EOPNOTSUPP : 0;
316}
317
318/**
319 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
320 * a specific flow spec
321 * @vsi: pointer to the targeted VSI
322 * @fd_data: the flow director data required for the FDir descriptor
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000323 * @add: true adds a filter, false removes it
324 *
Jean Sacren21d3efd2014-03-17 18:14:39 +0000325 * Always returns -EOPNOTSUPP
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000326 **/
327static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
328 struct i40e_fdir_filter *fd_data,
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000329 bool add)
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000330{
331 return -EOPNOTSUPP;
332}
333
334#define I40E_IP_DUMMY_PACKET_LEN 34
335/**
336 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
337 * a specific flow spec
338 * @vsi: pointer to the targeted VSI
339 * @fd_data: the flow director data required for the FDir descriptor
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000340 * @add: true adds a filter, false removes it
341 *
342 * Returns 0 if the filters were successfully added or removed
343 **/
344static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
345 struct i40e_fdir_filter *fd_data,
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000346 bool add)
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000347{
348 struct i40e_pf *pf = vsi->back;
349 struct iphdr *ip;
350 bool err = false;
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000351 u8 *raw_packet;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000352 int ret;
353 int i;
354 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
355 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
356 0, 0, 0, 0};
357
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000358 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
359 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000360 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
361 if (!raw_packet)
362 return -ENOMEM;
363 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
364 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
365
366 ip->saddr = fd_data->src_ip[0];
367 ip->daddr = fd_data->dst_ip[0];
368 ip->protocol = 0;
369
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000370 fd_data->pctype = i;
371 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
372
373 if (ret) {
374 dev_info(&pf->pdev->dev,
Carolyn Wybornye99bdd32014-07-09 07:46:12 +0000375 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
376 fd_data->pctype, fd_data->fd_id, ret);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000377 err = true;
Anjali Singhai Jain4205d372015-02-27 09:15:27 +0000378 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
Anjali Singhai Jainf7233c52014-07-09 07:46:16 +0000379 if (add)
380 dev_info(&pf->pdev->dev,
381 "Filter OK for PCTYPE %d loc = %d\n",
382 fd_data->pctype, fd_data->fd_id);
383 else
384 dev_info(&pf->pdev->dev,
385 "Filter deleted for PCTYPE %d loc = %d\n",
386 fd_data->pctype, fd_data->fd_id);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000387 }
388 }
389
390 return err ? -EOPNOTSUPP : 0;
391}
392
393/**
394 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
395 * @vsi: pointer to the targeted VSI
396 * @cmd: command to get or set RX flow classification rules
397 * @add: true adds a filter, false removes it
398 *
399 **/
400int i40e_add_del_fdir(struct i40e_vsi *vsi,
401 struct i40e_fdir_filter *input, bool add)
402{
403 struct i40e_pf *pf = vsi->back;
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000404 int ret;
405
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000406 switch (input->flow_type & ~FLOW_EXT) {
407 case TCP_V4_FLOW:
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000408 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000409 break;
410 case UDP_V4_FLOW:
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000411 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000412 break;
413 case SCTP_V4_FLOW:
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000414 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000415 break;
416 case IPV4_FLOW:
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000417 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000418 break;
419 case IP_USER_FLOW:
420 switch (input->ip4_proto) {
421 case IPPROTO_TCP:
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000422 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000423 break;
424 case IPPROTO_UDP:
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000425 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000426 break;
427 case IPPROTO_SCTP:
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000428 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000429 break;
430 default:
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000431 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000432 break;
433 }
434 break;
435 default:
Jakub Kicinskic5ffe7e2014-04-02 10:33:22 +0000436 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000437 input->flow_type);
438 ret = -EINVAL;
439 }
440
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000441 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
Joseph Gasparakis17a73f62014-02-12 01:45:30 +0000442 return ret;
443}
444
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000445/**
446 * i40e_fd_handle_status - check the Programming Status for FD
447 * @rx_ring: the Rx ring for this descriptor
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000448 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000449 * @prog_id: the id originally used for programming
450 *
451 * This is used to verify if the FD programming or invalidation
452 * requested by SW to the HW is successful or not and take actions accordingly.
453 **/
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000454static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
455 union i40e_rx_desc *rx_desc, u8 prog_id)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000456{
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000457 struct i40e_pf *pf = rx_ring->vsi->back;
458 struct pci_dev *pdev = pf->pdev;
459 u32 fcnt_prog, fcnt_avail;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000460 u32 error;
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000461 u64 qw;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000462
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000463 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000464 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
465 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
466
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400467 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
Anjali Singhai Jainf7233c52014-07-09 07:46:16 +0000468 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
469 (I40E_DEBUG_FD & pf->hw.debug_mask))
470 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
471 rx_desc->wb.qword0.hi_dword.fd_id);
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000472
Anjali Singhai Jain04294e32015-02-27 09:15:28 +0000473 /* Check if the programming error is for ATR.
474 * If so, auto disable ATR and set a state for
475 * flush in progress. Next time we come here if flush is in
476 * progress do nothing, once flush is complete the state will
477 * be cleared.
478 */
479 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
480 return;
481
Anjali Singhai Jain1e1be8f2014-07-10 08:03:26 +0000482 pf->fd_add_err++;
483 /* store the current atr filter count */
484 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
485
Anjali Singhai Jain04294e32015-02-27 09:15:28 +0000486 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
487 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
488 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
489 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
490 }
491
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000492 /* filter programming failed most likely due to table full */
Anjali Singhai Jain04294e32015-02-27 09:15:28 +0000493 fcnt_prog = i40e_get_global_fd_count(pf);
Anjali Singhai Jain12957382014-06-04 04:22:47 +0000494 fcnt_avail = pf->fdir_pf_filter_count;
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000495 /* If ATR is running fcnt_prog can quickly change,
496 * if we are very close to full, it makes sense to disable
497 * FD ATR/SB and then re-enable it when there is room.
498 */
499 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
Anjali Singhai Jain1e1be8f2014-07-10 08:03:26 +0000500 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
Anjali Singhai Jainb814ba62014-06-04 20:41:48 +0000501 !(pf->auto_disable_flags &
Anjali Singhai Jainb814ba62014-06-04 20:41:48 +0000502 I40E_FLAG_FD_SB_ENABLED)) {
Anjali Singhai Jain2e4875e2015-04-16 20:06:06 -0400503 if (I40E_DEBUG_FD & pf->hw.debug_mask)
504 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000505 pf->auto_disable_flags |=
506 I40E_FLAG_FD_SB_ENABLED;
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000507 }
508 } else {
Carolyn Wybornye99bdd32014-07-09 07:46:12 +0000509 dev_info(&pdev->dev,
Anjali Singhai Jainf7233c52014-07-09 07:46:16 +0000510 "FD filter programming failed due to incorrect filter parameters\n");
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000511 }
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400512 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
Anjali Singhai Jain13c28842014-03-06 09:00:04 +0000513 if (I40E_DEBUG_FD & pf->hw.debug_mask)
Carolyn Wybornye99bdd32014-07-09 07:46:12 +0000514 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
Anjali Singhai Jain13c28842014-03-06 09:00:04 +0000515 rx_desc->wb.qword0.hi_dword.fd_id);
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000516 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000517}
518
519/**
Alexander Duycka5e9c572013-09-28 06:00:27 +0000520 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000521 * @ring: the ring that owns the buffer
522 * @tx_buffer: the buffer to free
523 **/
Alexander Duycka5e9c572013-09-28 06:00:27 +0000524static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
525 struct i40e_tx_buffer *tx_buffer)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000526{
Alexander Duycka5e9c572013-09-28 06:00:27 +0000527 if (tx_buffer->skb) {
Anjali Singhai Jain49d7d932014-06-04 08:45:15 +0000528 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
529 kfree(tx_buffer->raw_buf);
530 else
531 dev_kfree_skb_any(tx_buffer->skb);
532
Alexander Duycka5e9c572013-09-28 06:00:27 +0000533 if (dma_unmap_len(tx_buffer, len))
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000534 dma_unmap_single(ring->dev,
Alexander Duyck35a1e2a2013-09-28 06:00:17 +0000535 dma_unmap_addr(tx_buffer, dma),
536 dma_unmap_len(tx_buffer, len),
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000537 DMA_TO_DEVICE);
Alexander Duycka5e9c572013-09-28 06:00:27 +0000538 } else if (dma_unmap_len(tx_buffer, len)) {
539 dma_unmap_page(ring->dev,
540 dma_unmap_addr(tx_buffer, dma),
541 dma_unmap_len(tx_buffer, len),
542 DMA_TO_DEVICE);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000543 }
Alexander Duycka5e9c572013-09-28 06:00:27 +0000544 tx_buffer->next_to_watch = NULL;
545 tx_buffer->skb = NULL;
Alexander Duyck35a1e2a2013-09-28 06:00:17 +0000546 dma_unmap_len_set(tx_buffer, len, 0);
Alexander Duycka5e9c572013-09-28 06:00:27 +0000547 /* tx_buffer must be completely set up in the transmit path */
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000548}
549
550/**
551 * i40e_clean_tx_ring - Free any empty Tx buffers
552 * @tx_ring: ring to be cleaned
553 **/
554void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
555{
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000556 unsigned long bi_size;
557 u16 i;
558
559 /* ring already cleared, nothing to do */
560 if (!tx_ring->tx_bi)
561 return;
562
563 /* Free all the Tx ring sk_buffs */
Alexander Duycka5e9c572013-09-28 06:00:27 +0000564 for (i = 0; i < tx_ring->count; i++)
565 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000566
567 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
568 memset(tx_ring->tx_bi, 0, bi_size);
569
570 /* Zero out the descriptor ring */
571 memset(tx_ring->desc, 0, tx_ring->size);
572
573 tx_ring->next_to_use = 0;
574 tx_ring->next_to_clean = 0;
Alexander Duyck7070ce02013-09-28 06:00:37 +0000575
576 if (!tx_ring->netdev)
577 return;
578
579 /* cleanup Tx queue statistics */
580 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
581 tx_ring->queue_index));
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000582}
583
584/**
585 * i40e_free_tx_resources - Free Tx resources per queue
586 * @tx_ring: Tx descriptor ring for a specific queue
587 *
588 * Free all transmit software resources
589 **/
590void i40e_free_tx_resources(struct i40e_ring *tx_ring)
591{
592 i40e_clean_tx_ring(tx_ring);
593 kfree(tx_ring->tx_bi);
594 tx_ring->tx_bi = NULL;
595
596 if (tx_ring->desc) {
597 dma_free_coherent(tx_ring->dev, tx_ring->size,
598 tx_ring->desc, tx_ring->dma);
599 tx_ring->desc = NULL;
600 }
601}
602
603/**
Jesse Brandeburga68de582015-02-24 05:26:03 +0000604 * i40e_get_head - Retrieve head from head writeback
605 * @tx_ring: tx ring to fetch head of
606 *
607 * Returns value of Tx ring head based on value stored
608 * in head write-back location
609 **/
610static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
611{
612 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
613
614 return le32_to_cpu(*(volatile __le32 *)head);
615}
616
617/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000618 * i40e_get_tx_pending - how many tx descriptors not processed
619 * @tx_ring: the ring of descriptors
620 *
621 * Since there is no access to the ring head register
622 * in XL710, we need to use our local copies
623 **/
624static u32 i40e_get_tx_pending(struct i40e_ring *ring)
625{
Jesse Brandeburga68de582015-02-24 05:26:03 +0000626 u32 head, tail;
627
628 head = i40e_get_head(ring);
629 tail = readl(ring->tail);
630
631 if (head != tail)
632 return (head < tail) ?
633 tail - head : (tail + ring->count - head);
634
635 return 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000636}
637
638/**
639 * i40e_check_tx_hang - Is there a hang in the Tx queue
640 * @tx_ring: the ring of descriptors
641 **/
642static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
643{
Jesse Brandeburga68de582015-02-24 05:26:03 +0000644 u32 tx_done = tx_ring->stats.packets;
645 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000646 u32 tx_pending = i40e_get_tx_pending(tx_ring);
Anjali Singhai Jain810b3ae2014-07-10 07:58:25 +0000647 struct i40e_pf *pf = tx_ring->vsi->back;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000648 bool ret = false;
649
650 clear_check_for_tx_hang(tx_ring);
651
652 /* Check for a hung queue, but be thorough. This verifies
653 * that a transmit has been completed since the previous
654 * check AND there is at least one packet pending. The
655 * ARMED bit is set to indicate a potential hang. The
656 * bit is cleared if a pause frame is received to remove
657 * false hang detection due to PFC or 802.3x frames. By
658 * requiring this to fail twice we avoid races with
659 * PFC clearing the ARMED bit and conditions where we
660 * run the check_tx_hang logic with a transmit completion
661 * pending but without time to complete it yet.
662 */
Jesse Brandeburga68de582015-02-24 05:26:03 +0000663 if ((tx_done_old == tx_done) && tx_pending) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000664 /* make sure it is true for two checks in a row */
665 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
666 &tx_ring->state);
Jesse Brandeburga68de582015-02-24 05:26:03 +0000667 } else if (tx_done_old == tx_done &&
668 (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) {
Anjali Singhai Jain810b3ae2014-07-10 07:58:25 +0000669 if (I40E_DEBUG_FLOW & pf->hw.debug_mask)
670 dev_info(tx_ring->dev, "HW needs some more descs to do a cacheline flush. tx_pending %d, queue %d",
671 tx_pending, tx_ring->queue_index);
672 pf->tx_sluggish_count++;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000673 } else {
674 /* update completed stats and disarm the hang check */
Jesse Brandeburga68de582015-02-24 05:26:03 +0000675 tx_ring->tx_stats.tx_done_old = tx_done;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000676 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
677 }
678
679 return ret;
680}
681
Jesse Brandeburgd91649f2015-01-07 02:55:01 +0000682#define WB_STRIDE 0x3
683
Jesse Brandeburg1943d8b2014-02-14 02:14:40 +0000684/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000685 * i40e_clean_tx_irq - Reclaim resources after transmit completes
686 * @tx_ring: tx ring to clean
687 * @budget: how many cleans we're allowed
688 *
689 * Returns true if there's any budget left (e.g. the clean is finished)
690 **/
691static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
692{
693 u16 i = tx_ring->next_to_clean;
694 struct i40e_tx_buffer *tx_buf;
Jesse Brandeburg1943d8b2014-02-14 02:14:40 +0000695 struct i40e_tx_desc *tx_head;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000696 struct i40e_tx_desc *tx_desc;
697 unsigned int total_packets = 0;
698 unsigned int total_bytes = 0;
699
700 tx_buf = &tx_ring->tx_bi[i];
701 tx_desc = I40E_TX_DESC(tx_ring, i);
Alexander Duycka5e9c572013-09-28 06:00:27 +0000702 i -= tx_ring->count;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000703
Jesse Brandeburg1943d8b2014-02-14 02:14:40 +0000704 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
705
Alexander Duycka5e9c572013-09-28 06:00:27 +0000706 do {
707 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000708
709 /* if next_to_watch is not set then there is no work pending */
710 if (!eop_desc)
711 break;
712
Alexander Duycka5e9c572013-09-28 06:00:27 +0000713 /* prevent any other reads prior to eop_desc */
714 read_barrier_depends();
715
Jesse Brandeburg1943d8b2014-02-14 02:14:40 +0000716 /* we have caught up to head, no work left to do */
717 if (tx_head == tx_desc)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000718 break;
719
Alexander Duyckc304fda2013-09-28 06:00:12 +0000720 /* clear next_to_watch to prevent false hangs */
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000721 tx_buf->next_to_watch = NULL;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000722
Alexander Duycka5e9c572013-09-28 06:00:27 +0000723 /* update the statistics for this packet */
724 total_bytes += tx_buf->bytecount;
725 total_packets += tx_buf->gso_segs;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000726
Alexander Duycka5e9c572013-09-28 06:00:27 +0000727 /* free the skb */
Rick Jonesa81fb042014-09-17 03:56:20 +0000728 dev_consume_skb_any(tx_buf->skb);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000729
Alexander Duycka5e9c572013-09-28 06:00:27 +0000730 /* unmap skb header data */
731 dma_unmap_single(tx_ring->dev,
732 dma_unmap_addr(tx_buf, dma),
733 dma_unmap_len(tx_buf, len),
734 DMA_TO_DEVICE);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000735
Alexander Duycka5e9c572013-09-28 06:00:27 +0000736 /* clear tx_buffer data */
737 tx_buf->skb = NULL;
738 dma_unmap_len_set(tx_buf, len, 0);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000739
Alexander Duycka5e9c572013-09-28 06:00:27 +0000740 /* unmap remaining buffers */
741 while (tx_desc != eop_desc) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000742
743 tx_buf++;
744 tx_desc++;
745 i++;
Alexander Duycka5e9c572013-09-28 06:00:27 +0000746 if (unlikely(!i)) {
747 i -= tx_ring->count;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000748 tx_buf = tx_ring->tx_bi;
749 tx_desc = I40E_TX_DESC(tx_ring, 0);
750 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000751
Alexander Duycka5e9c572013-09-28 06:00:27 +0000752 /* unmap any remaining paged data */
753 if (dma_unmap_len(tx_buf, len)) {
754 dma_unmap_page(tx_ring->dev,
755 dma_unmap_addr(tx_buf, dma),
756 dma_unmap_len(tx_buf, len),
757 DMA_TO_DEVICE);
758 dma_unmap_len_set(tx_buf, len, 0);
759 }
760 }
761
762 /* move us one more past the eop_desc for start of next pkt */
763 tx_buf++;
764 tx_desc++;
765 i++;
766 if (unlikely(!i)) {
767 i -= tx_ring->count;
768 tx_buf = tx_ring->tx_bi;
769 tx_desc = I40E_TX_DESC(tx_ring, 0);
770 }
771
Jesse Brandeburg016890b2015-02-27 09:15:31 +0000772 prefetch(tx_desc);
773
Alexander Duycka5e9c572013-09-28 06:00:27 +0000774 /* update budget accounting */
775 budget--;
776 } while (likely(budget));
777
778 i += tx_ring->count;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000779 tx_ring->next_to_clean = i;
Alexander Duyck980e9b12013-09-28 06:01:03 +0000780 u64_stats_update_begin(&tx_ring->syncp);
Alexander Duycka114d0a2013-09-28 06:00:43 +0000781 tx_ring->stats.bytes += total_bytes;
782 tx_ring->stats.packets += total_packets;
Alexander Duyck980e9b12013-09-28 06:01:03 +0000783 u64_stats_update_end(&tx_ring->syncp);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000784 tx_ring->q_vector->tx.total_bytes += total_bytes;
785 tx_ring->q_vector->tx.total_packets += total_packets;
Alexander Duycka5e9c572013-09-28 06:00:27 +0000786
Jesse Brandeburgd91649f2015-01-07 02:55:01 +0000787 /* check to see if there are any non-cache aligned descriptors
788 * waiting to be written back, and kick the hardware to force
789 * them to be written back in case of napi polling
790 */
791 if (budget &&
792 !((i & WB_STRIDE) == WB_STRIDE) &&
793 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
794 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
795 tx_ring->arm_wb = true;
796 else
797 tx_ring->arm_wb = false;
798
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000799 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
800 /* schedule immediate reset if we believe we hung */
801 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
802 " VSI <%d>\n"
803 " Tx Queue <%d>\n"
804 " next_to_use <%x>\n"
805 " next_to_clean <%x>\n",
806 tx_ring->vsi->seid,
807 tx_ring->queue_index,
808 tx_ring->next_to_use, i);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000809
810 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
811
812 dev_info(tx_ring->dev,
Jesse Brandeburgd91649f2015-01-07 02:55:01 +0000813 "tx hang detected on queue %d, reset requested\n",
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000814 tx_ring->queue_index);
815
Jesse Brandeburgd91649f2015-01-07 02:55:01 +0000816 /* do not fire the reset immediately, wait for the stack to
817 * decide we are truly stuck, also prevents every queue from
818 * simultaneously requesting a reset
819 */
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000820
Jesse Brandeburgd91649f2015-01-07 02:55:01 +0000821 /* the adapter is about to reset, no point in enabling polling */
822 budget = 1;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000823 }
824
Alexander Duyck7070ce02013-09-28 06:00:37 +0000825 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
826 tx_ring->queue_index),
827 total_packets, total_bytes);
828
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000829#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
830 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
831 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
832 /* Make sure that anybody stopping the queue after this
833 * sees the new next_to_clean.
834 */
835 smp_mb();
836 if (__netif_subqueue_stopped(tx_ring->netdev,
837 tx_ring->queue_index) &&
838 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
839 netif_wake_subqueue(tx_ring->netdev,
840 tx_ring->queue_index);
841 ++tx_ring->tx_stats.restart_queue;
842 }
843 }
844
Jesse Brandeburgd91649f2015-01-07 02:55:01 +0000845 return !!budget;
846}
847
848/**
849 * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors
850 * @vsi: the VSI we care about
851 * @q_vector: the vector on which to force writeback
852 *
853 **/
854static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
855{
Anjali Singhai Jain8e0764b2015-06-05 12:20:30 -0400856 u16 flags = q_vector->tx.ring[0].flags;
Jesse Brandeburgd91649f2015-01-07 02:55:01 +0000857
Anjali Singhai Jain8e0764b2015-06-05 12:20:30 -0400858 if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
859 u32 val;
860
861 if (q_vector->arm_wb_state)
862 return;
863
864 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK;
865
866 wr32(&vsi->back->hw,
867 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
868 vsi->base_vector - 1),
869 val);
870 q_vector->arm_wb_state = true;
871 } else if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
872 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
873 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
874 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
875 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
876 /* allow 00 to be written to the index */
877
878 wr32(&vsi->back->hw,
879 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
880 vsi->base_vector - 1), val);
881 } else {
882 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
883 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
884 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
885 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
886 /* allow 00 to be written to the index */
887
888 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
889 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000890}
891
892/**
893 * i40e_set_new_dynamic_itr - Find new ITR level
894 * @rc: structure containing ring performance data
895 *
896 * Stores a new ITR value based on packets and byte counts during
897 * the last interrupt. The advantage of per interrupt computation
898 * is faster updates and more accurate ITR for the current traffic
899 * pattern. Constants in this function were computed based on
900 * theoretical maximum wire speed and thresholds were set based on
901 * testing data as well as attempting to minimize response time
902 * while increasing bulk throughput.
903 **/
904static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
905{
906 enum i40e_latency_range new_latency_range = rc->latency_range;
907 u32 new_itr = rc->itr;
908 int bytes_per_int;
909
910 if (rc->total_packets == 0 || !rc->itr)
911 return;
912
913 /* simple throttlerate management
914 * 0-10MB/s lowest (100000 ints/s)
915 * 10-20MB/s low (20000 ints/s)
916 * 20-1249MB/s bulk (8000 ints/s)
917 */
918 bytes_per_int = rc->total_bytes / rc->itr;
Carolyn Wybornyde32e3e2015-06-10 13:42:07 -0400919 switch (new_latency_range) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000920 case I40E_LOWEST_LATENCY:
921 if (bytes_per_int > 10)
922 new_latency_range = I40E_LOW_LATENCY;
923 break;
924 case I40E_LOW_LATENCY:
925 if (bytes_per_int > 20)
926 new_latency_range = I40E_BULK_LATENCY;
927 else if (bytes_per_int <= 10)
928 new_latency_range = I40E_LOWEST_LATENCY;
929 break;
930 case I40E_BULK_LATENCY:
931 if (bytes_per_int <= 20)
Carolyn Wybornyde32e3e2015-06-10 13:42:07 -0400932 new_latency_range = I40E_LOW_LATENCY;
933 break;
934 default:
935 if (bytes_per_int <= 20)
936 new_latency_range = I40E_LOW_LATENCY;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000937 break;
938 }
Carolyn Wybornyde32e3e2015-06-10 13:42:07 -0400939 rc->latency_range = new_latency_range;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000940
941 switch (new_latency_range) {
942 case I40E_LOWEST_LATENCY:
943 new_itr = I40E_ITR_100K;
944 break;
945 case I40E_LOW_LATENCY:
946 new_itr = I40E_ITR_20K;
947 break;
948 case I40E_BULK_LATENCY:
949 new_itr = I40E_ITR_8K;
950 break;
951 default:
952 break;
953 }
954
Carolyn Wybornyde32e3e2015-06-10 13:42:07 -0400955 if (new_itr != rc->itr)
956 rc->itr = new_itr;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000957
958 rc->total_bytes = 0;
959 rc->total_packets = 0;
960}
961
962/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000963 * i40e_clean_programming_status - clean the programming status descriptor
964 * @rx_ring: the rx ring that has this descriptor
965 * @rx_desc: the rx descriptor written back by HW
966 *
967 * Flow director should handle FD_FILTER_STATUS to check its filter programming
968 * status being successful or not and take actions accordingly. FCoE should
969 * handle its context/filter programming/invalidation status and take actions.
970 *
971 **/
972static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
973 union i40e_rx_desc *rx_desc)
974{
975 u64 qw;
976 u8 id;
977
978 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
979 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
980 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
981
982 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +0000983 i40e_fd_handle_status(rx_ring, rx_desc, id);
Vasu Dev38e00432014-08-01 13:27:03 -0700984#ifdef I40E_FCOE
985 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
986 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
987 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
988#endif
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +0000989}
990
991/**
992 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
993 * @tx_ring: the tx ring to set up
994 *
995 * Return 0 on success, negative on error
996 **/
997int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
998{
999 struct device *dev = tx_ring->dev;
1000 int bi_size;
1001
1002 if (!dev)
1003 return -ENOMEM;
1004
1005 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1006 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1007 if (!tx_ring->tx_bi)
1008 goto err;
1009
1010 /* round up to nearest 4K */
1011 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
Jesse Brandeburg1943d8b2014-02-14 02:14:40 +00001012 /* add u32 for head writeback, align after this takes care of
1013 * guaranteeing this is at least one cache line in size
1014 */
1015 tx_ring->size += sizeof(u32);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001016 tx_ring->size = ALIGN(tx_ring->size, 4096);
1017 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1018 &tx_ring->dma, GFP_KERNEL);
1019 if (!tx_ring->desc) {
1020 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1021 tx_ring->size);
1022 goto err;
1023 }
1024
1025 tx_ring->next_to_use = 0;
1026 tx_ring->next_to_clean = 0;
1027 return 0;
1028
1029err:
1030 kfree(tx_ring->tx_bi);
1031 tx_ring->tx_bi = NULL;
1032 return -ENOMEM;
1033}
1034
1035/**
1036 * i40e_clean_rx_ring - Free Rx buffers
1037 * @rx_ring: ring to be cleaned
1038 **/
1039void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1040{
1041 struct device *dev = rx_ring->dev;
1042 struct i40e_rx_buffer *rx_bi;
1043 unsigned long bi_size;
1044 u16 i;
1045
1046 /* ring already cleared, nothing to do */
1047 if (!rx_ring->rx_bi)
1048 return;
1049
Mitch Williamsa132af22015-01-24 09:58:35 +00001050 if (ring_is_ps_enabled(rx_ring)) {
1051 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
1052
1053 rx_bi = &rx_ring->rx_bi[0];
1054 if (rx_bi->hdr_buf) {
1055 dma_free_coherent(dev,
1056 bufsz,
1057 rx_bi->hdr_buf,
1058 rx_bi->dma);
1059 for (i = 0; i < rx_ring->count; i++) {
1060 rx_bi = &rx_ring->rx_bi[i];
1061 rx_bi->dma = 0;
Shannon Nelson37a29732015-02-27 09:15:19 +00001062 rx_bi->hdr_buf = NULL;
Mitch Williamsa132af22015-01-24 09:58:35 +00001063 }
1064 }
1065 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001066 /* Free all the Rx ring sk_buffs */
1067 for (i = 0; i < rx_ring->count; i++) {
1068 rx_bi = &rx_ring->rx_bi[i];
1069 if (rx_bi->dma) {
1070 dma_unmap_single(dev,
1071 rx_bi->dma,
1072 rx_ring->rx_buf_len,
1073 DMA_FROM_DEVICE);
1074 rx_bi->dma = 0;
1075 }
1076 if (rx_bi->skb) {
1077 dev_kfree_skb(rx_bi->skb);
1078 rx_bi->skb = NULL;
1079 }
1080 if (rx_bi->page) {
1081 if (rx_bi->page_dma) {
1082 dma_unmap_page(dev,
1083 rx_bi->page_dma,
1084 PAGE_SIZE / 2,
1085 DMA_FROM_DEVICE);
1086 rx_bi->page_dma = 0;
1087 }
1088 __free_page(rx_bi->page);
1089 rx_bi->page = NULL;
1090 rx_bi->page_offset = 0;
1091 }
1092 }
1093
1094 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1095 memset(rx_ring->rx_bi, 0, bi_size);
1096
1097 /* Zero out the descriptor ring */
1098 memset(rx_ring->desc, 0, rx_ring->size);
1099
1100 rx_ring->next_to_clean = 0;
1101 rx_ring->next_to_use = 0;
1102}
1103
1104/**
1105 * i40e_free_rx_resources - Free Rx resources
1106 * @rx_ring: ring to clean the resources from
1107 *
1108 * Free all receive software resources
1109 **/
1110void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1111{
1112 i40e_clean_rx_ring(rx_ring);
1113 kfree(rx_ring->rx_bi);
1114 rx_ring->rx_bi = NULL;
1115
1116 if (rx_ring->desc) {
1117 dma_free_coherent(rx_ring->dev, rx_ring->size,
1118 rx_ring->desc, rx_ring->dma);
1119 rx_ring->desc = NULL;
1120 }
1121}
1122
1123/**
Mitch Williamsa132af22015-01-24 09:58:35 +00001124 * i40e_alloc_rx_headers - allocate rx header buffers
1125 * @rx_ring: ring to alloc buffers
1126 *
1127 * Allocate rx header buffers for the entire ring. As these are static,
1128 * this is only called when setting up a new ring.
1129 **/
1130void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1131{
1132 struct device *dev = rx_ring->dev;
1133 struct i40e_rx_buffer *rx_bi;
1134 dma_addr_t dma;
1135 void *buffer;
1136 int buf_size;
1137 int i;
1138
1139 if (rx_ring->rx_bi[0].hdr_buf)
1140 return;
1141 /* Make sure the buffers don't cross cache line boundaries. */
1142 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1143 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1144 &dma, GFP_KERNEL);
1145 if (!buffer)
1146 return;
1147 for (i = 0; i < rx_ring->count; i++) {
1148 rx_bi = &rx_ring->rx_bi[i];
1149 rx_bi->dma = dma + (i * buf_size);
1150 rx_bi->hdr_buf = buffer + (i * buf_size);
1151 }
1152}
1153
1154/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001155 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1156 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1157 *
1158 * Returns 0 on success, negative on failure
1159 **/
1160int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1161{
1162 struct device *dev = rx_ring->dev;
1163 int bi_size;
1164
1165 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1166 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1167 if (!rx_ring->rx_bi)
1168 goto err;
1169
Carolyn Wybornyf217d6c2015-02-09 17:42:31 -08001170 u64_stats_init(&rx_ring->syncp);
Carolyn Wyborny638702b2015-01-24 09:58:32 +00001171
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001172 /* Round up to nearest 4K */
1173 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1174 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1175 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1176 rx_ring->size = ALIGN(rx_ring->size, 4096);
1177 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1178 &rx_ring->dma, GFP_KERNEL);
1179
1180 if (!rx_ring->desc) {
1181 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1182 rx_ring->size);
1183 goto err;
1184 }
1185
1186 rx_ring->next_to_clean = 0;
1187 rx_ring->next_to_use = 0;
1188
1189 return 0;
1190err:
1191 kfree(rx_ring->rx_bi);
1192 rx_ring->rx_bi = NULL;
1193 return -ENOMEM;
1194}
1195
1196/**
1197 * i40e_release_rx_desc - Store the new tail and head values
1198 * @rx_ring: ring to bump
1199 * @val: new head index
1200 **/
1201static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1202{
1203 rx_ring->next_to_use = val;
1204 /* Force memory writes to complete before letting h/w
1205 * know there are new descriptors to fetch. (Only
1206 * applicable for weak-ordered memory model archs,
1207 * such as IA-64).
1208 */
1209 wmb();
1210 writel(val, rx_ring->tail);
1211}
1212
1213/**
Mitch Williamsa132af22015-01-24 09:58:35 +00001214 * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001215 * @rx_ring: ring to place buffers on
1216 * @cleaned_count: number of buffers to replace
1217 **/
Mitch Williamsa132af22015-01-24 09:58:35 +00001218void i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1219{
1220 u16 i = rx_ring->next_to_use;
1221 union i40e_rx_desc *rx_desc;
1222 struct i40e_rx_buffer *bi;
1223
1224 /* do nothing if no valid netdev defined */
1225 if (!rx_ring->netdev || !cleaned_count)
1226 return;
1227
1228 while (cleaned_count--) {
1229 rx_desc = I40E_RX_DESC(rx_ring, i);
1230 bi = &rx_ring->rx_bi[i];
1231
1232 if (bi->skb) /* desc is in use */
1233 goto no_buffers;
1234 if (!bi->page) {
1235 bi->page = alloc_page(GFP_ATOMIC);
1236 if (!bi->page) {
1237 rx_ring->rx_stats.alloc_page_failed++;
1238 goto no_buffers;
1239 }
1240 }
1241
1242 if (!bi->page_dma) {
1243 /* use a half page if we're re-using */
1244 bi->page_offset ^= PAGE_SIZE / 2;
1245 bi->page_dma = dma_map_page(rx_ring->dev,
1246 bi->page,
1247 bi->page_offset,
1248 PAGE_SIZE / 2,
1249 DMA_FROM_DEVICE);
1250 if (dma_mapping_error(rx_ring->dev,
1251 bi->page_dma)) {
1252 rx_ring->rx_stats.alloc_page_failed++;
1253 bi->page_dma = 0;
1254 goto no_buffers;
1255 }
1256 }
1257
1258 dma_sync_single_range_for_device(rx_ring->dev,
1259 bi->dma,
1260 0,
1261 rx_ring->rx_hdr_len,
1262 DMA_FROM_DEVICE);
1263 /* Refresh the desc even if buffer_addrs didn't change
1264 * because each write-back erases this info.
1265 */
1266 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1267 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1268 i++;
1269 if (i == rx_ring->count)
1270 i = 0;
1271 }
1272
1273no_buffers:
1274 if (rx_ring->next_to_use != i)
1275 i40e_release_rx_desc(rx_ring, i);
1276}
1277
1278/**
1279 * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1280 * @rx_ring: ring to place buffers on
1281 * @cleaned_count: number of buffers to replace
1282 **/
1283void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001284{
1285 u16 i = rx_ring->next_to_use;
1286 union i40e_rx_desc *rx_desc;
1287 struct i40e_rx_buffer *bi;
1288 struct sk_buff *skb;
1289
1290 /* do nothing if no valid netdev defined */
1291 if (!rx_ring->netdev || !cleaned_count)
1292 return;
1293
1294 while (cleaned_count--) {
1295 rx_desc = I40E_RX_DESC(rx_ring, i);
1296 bi = &rx_ring->rx_bi[i];
1297 skb = bi->skb;
1298
1299 if (!skb) {
1300 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1301 rx_ring->rx_buf_len);
1302 if (!skb) {
Mitch Williams420136c2013-12-18 13:45:59 +00001303 rx_ring->rx_stats.alloc_buff_failed++;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001304 goto no_buffers;
1305 }
1306 /* initialize queue mapping */
1307 skb_record_rx_queue(skb, rx_ring->queue_index);
1308 bi->skb = skb;
1309 }
1310
1311 if (!bi->dma) {
1312 bi->dma = dma_map_single(rx_ring->dev,
1313 skb->data,
1314 rx_ring->rx_buf_len,
1315 DMA_FROM_DEVICE);
1316 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
Mitch Williams420136c2013-12-18 13:45:59 +00001317 rx_ring->rx_stats.alloc_buff_failed++;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001318 bi->dma = 0;
1319 goto no_buffers;
1320 }
1321 }
1322
Mitch Williamsa132af22015-01-24 09:58:35 +00001323 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1324 rx_desc->read.hdr_addr = 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001325 i++;
1326 if (i == rx_ring->count)
1327 i = 0;
1328 }
1329
1330no_buffers:
1331 if (rx_ring->next_to_use != i)
1332 i40e_release_rx_desc(rx_ring, i);
1333}
1334
1335/**
1336 * i40e_receive_skb - Send a completed packet up the stack
1337 * @rx_ring: rx ring in play
1338 * @skb: packet to send up
1339 * @vlan_tag: vlan tag for packet
1340 **/
1341static void i40e_receive_skb(struct i40e_ring *rx_ring,
1342 struct sk_buff *skb, u16 vlan_tag)
1343{
1344 struct i40e_q_vector *q_vector = rx_ring->q_vector;
1345 struct i40e_vsi *vsi = rx_ring->vsi;
1346 u64 flags = vsi->back->flags;
1347
1348 if (vlan_tag & VLAN_VID_MASK)
1349 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1350
1351 if (flags & I40E_FLAG_IN_NETPOLL)
1352 netif_rx(skb);
1353 else
1354 napi_gro_receive(&q_vector->napi, skb);
1355}
1356
1357/**
1358 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1359 * @vsi: the VSI we care about
1360 * @skb: skb currently being received and modified
1361 * @rx_status: status value of last descriptor in packet
1362 * @rx_error: error value of last descriptor in packet
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001363 * @rx_ptype: ptype value of last descriptor in packet
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001364 **/
1365static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1366 struct sk_buff *skb,
1367 u32 rx_status,
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001368 u32 rx_error,
1369 u16 rx_ptype)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001370{
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001371 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1372 bool ipv4 = false, ipv6 = false;
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001373 bool ipv4_tunnel, ipv6_tunnel;
1374 __wsum rx_udp_csum;
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001375 struct iphdr *iph;
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001376 __sum16 csum;
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001377
Anjali Singhai Jainf8faaa42015-02-24 06:58:48 +00001378 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1379 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1380 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1381 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001382
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001383 skb->ip_summed = CHECKSUM_NONE;
1384
1385 /* Rx csum enabled and ip headers found? */
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001386 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001387 return;
1388
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001389 /* did the hardware decode the packet and checksum? */
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001390 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001391 return;
1392
1393 /* both known and outer_ip must be set for the below code to work */
1394 if (!(decoded.known && decoded.outer_ip))
1395 return;
1396
1397 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1398 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
1399 ipv4 = true;
1400 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1401 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
1402 ipv6 = true;
1403
1404 if (ipv4 &&
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001405 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1406 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001407 goto checksum_fail;
1408
Jesse Brandeburgddf1d0d2014-02-13 03:48:39 -08001409 /* likely incorrect csum if alternate IP extension headers found */
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001410 if (ipv6 &&
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001411 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001412 /* don't increment checksum err here, non-fatal err */
Shannon Nelson8ee75a82013-12-21 05:44:46 +00001413 return;
1414
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001415 /* there was some L4 error, count error and punt packet to the stack */
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001416 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001417 goto checksum_fail;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001418
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001419 /* handle packets that were not able to be checksummed due
1420 * to arrival speed, in this case the stack can compute
1421 * the csum.
1422 */
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001423 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001424 return;
1425
1426 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
1427 * it in the driver, hardware does not do it for us.
1428 * Since L3L4P bit was set we assume a valid IHL value (>=5)
1429 * so the total length of IPv4 header is IHL*4 bytes
1430 * The UDP_0 bit *may* bet set if the *inner* header is UDP
1431 */
Anjali Singhaif6385972014-12-19 02:58:11 +00001432 if (ipv4_tunnel) {
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001433 skb->transport_header = skb->mac_header +
1434 sizeof(struct ethhdr) +
1435 (ip_hdr(skb)->ihl * 4);
1436
1437 /* Add 4 bytes for VLAN tagged packets */
1438 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1439 skb->protocol == htons(ETH_P_8021AD))
1440 ? VLAN_HLEN : 0;
1441
Anjali Singhaif6385972014-12-19 02:58:11 +00001442 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
1443 (udp_hdr(skb)->check != 0)) {
1444 rx_udp_csum = udp_csum(skb);
1445 iph = ip_hdr(skb);
1446 csum = csum_tcpudp_magic(
1447 iph->saddr, iph->daddr,
1448 (skb->len - skb_transport_offset(skb)),
1449 IPPROTO_UDP, rx_udp_csum);
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001450
Anjali Singhaif6385972014-12-19 02:58:11 +00001451 if (udp_hdr(skb)->check != csum)
1452 goto checksum_fail;
1453
1454 } /* else its GRE and so no outer UDP header */
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001455 }
1456
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001457 skb->ip_summed = CHECKSUM_UNNECESSARY;
Tom Herbertfa4ba692014-08-27 21:27:32 -07001458 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +00001459
1460 return;
1461
1462checksum_fail:
1463 vsi->back->hw_csum_rx_error++;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001464}
1465
1466/**
1467 * i40e_rx_hash - returns the hash value from the Rx descriptor
1468 * @ring: descriptor ring
1469 * @rx_desc: specific descriptor
1470 **/
1471static inline u32 i40e_rx_hash(struct i40e_ring *ring,
1472 union i40e_rx_desc *rx_desc)
1473{
Jesse Brandeburg8a494922013-11-20 10:02:49 +00001474 const __le64 rss_mask =
1475 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1476 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1477
1478 if ((ring->netdev->features & NETIF_F_RXHASH) &&
1479 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
1480 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1481 else
1482 return 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001483}
1484
1485/**
Jesse Brandeburg206812b2014-02-12 01:45:33 +00001486 * i40e_ptype_to_hash - get a hash type
1487 * @ptype: the ptype value from the descriptor
1488 *
1489 * Returns a hash type to be used by skb_set_hash
1490 **/
1491static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
1492{
1493 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1494
1495 if (!decoded.known)
1496 return PKT_HASH_TYPE_NONE;
1497
1498 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1499 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1500 return PKT_HASH_TYPE_L4;
1501 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1502 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1503 return PKT_HASH_TYPE_L3;
1504 else
1505 return PKT_HASH_TYPE_L2;
1506}
1507
1508/**
Mitch Williamsa132af22015-01-24 09:58:35 +00001509 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001510 * @rx_ring: rx ring to clean
1511 * @budget: how many cleans we're allowed
1512 *
1513 * Returns true if there's any budget left (e.g. the clean is finished)
1514 **/
Mitch Williamsa132af22015-01-24 09:58:35 +00001515static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001516{
1517 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1518 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1519 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1520 const int current_node = numa_node_id();
1521 struct i40e_vsi *vsi = rx_ring->vsi;
1522 u16 i = rx_ring->next_to_clean;
1523 union i40e_rx_desc *rx_desc;
1524 u32 rx_error, rx_status;
Jesse Brandeburg206812b2014-02-12 01:45:33 +00001525 u8 rx_ptype;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001526 u64 qword;
1527
Eric W. Biederman390f86d2014-03-14 17:59:10 -07001528 if (budget <= 0)
1529 return 0;
1530
Mitch Williamsa132af22015-01-24 09:58:35 +00001531 do {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001532 struct i40e_rx_buffer *rx_bi;
1533 struct sk_buff *skb;
1534 u16 vlan_tag;
Mitch Williamsa132af22015-01-24 09:58:35 +00001535 /* return some buffers to hardware, one at a time is too slow */
1536 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1537 i40e_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1538 cleaned_count = 0;
1539 }
1540
1541 i = rx_ring->next_to_clean;
1542 rx_desc = I40E_RX_DESC(rx_ring, i);
1543 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1544 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1545 I40E_RXD_QW1_STATUS_SHIFT;
1546
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001547 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
Mitch Williamsa132af22015-01-24 09:58:35 +00001548 break;
1549
1550 /* This memory barrier is needed to keep us from reading
1551 * any other fields out of the rx_desc until we know the
1552 * DD bit is set.
1553 */
Alexander Duyck67317162015-04-08 18:49:43 -07001554 dma_rmb();
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001555 if (i40e_rx_is_programming_status(qword)) {
1556 i40e_clean_programming_status(rx_ring, rx_desc);
Mitch Williamsa132af22015-01-24 09:58:35 +00001557 I40E_RX_INCREMENT(rx_ring, i);
1558 continue;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001559 }
1560 rx_bi = &rx_ring->rx_bi[i];
1561 skb = rx_bi->skb;
Mitch Williamsa132af22015-01-24 09:58:35 +00001562 if (likely(!skb)) {
1563 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1564 rx_ring->rx_hdr_len);
Jesse Brandeburg8b6ed9c2015-03-31 00:45:01 -07001565 if (!skb) {
Mitch Williamsa132af22015-01-24 09:58:35 +00001566 rx_ring->rx_stats.alloc_buff_failed++;
Jesse Brandeburg8b6ed9c2015-03-31 00:45:01 -07001567 break;
1568 }
1569
Mitch Williamsa132af22015-01-24 09:58:35 +00001570 /* initialize queue mapping */
1571 skb_record_rx_queue(skb, rx_ring->queue_index);
1572 /* we are reusing so sync this buffer for CPU use */
1573 dma_sync_single_range_for_cpu(rx_ring->dev,
1574 rx_bi->dma,
1575 0,
1576 rx_ring->rx_hdr_len,
1577 DMA_FROM_DEVICE);
1578 }
Mitch Williams829af3ac2013-12-18 13:46:00 +00001579 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1580 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1581 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1582 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1583 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1584 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001585
Mitch Williams829af3ac2013-12-18 13:46:00 +00001586 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1587 I40E_RXD_QW1_ERROR_SHIFT;
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001588 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1589 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001590
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001591 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1592 I40E_RXD_QW1_PTYPE_SHIFT;
Mitch Williamsa132af22015-01-24 09:58:35 +00001593 prefetch(rx_bi->page);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001594 rx_bi->skb = NULL;
Mitch Williamsa132af22015-01-24 09:58:35 +00001595 cleaned_count++;
1596 if (rx_hbo || rx_sph) {
1597 int len;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001598 if (rx_hbo)
1599 len = I40E_RX_HDR_SIZE;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001600 else
Mitch Williamsa132af22015-01-24 09:58:35 +00001601 len = rx_header_len;
1602 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1603 } else if (skb->len == 0) {
1604 int len;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001605
Mitch Williamsa132af22015-01-24 09:58:35 +00001606 len = (rx_packet_len > skb_headlen(skb) ?
1607 skb_headlen(skb) : rx_packet_len);
1608 memcpy(__skb_put(skb, len),
1609 rx_bi->page + rx_bi->page_offset,
1610 len);
1611 rx_bi->page_offset += len;
1612 rx_packet_len -= len;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001613 }
1614
1615 /* Get the rest of the data if this was a header split */
Mitch Williamsa132af22015-01-24 09:58:35 +00001616 if (rx_packet_len) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001617 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1618 rx_bi->page,
1619 rx_bi->page_offset,
1620 rx_packet_len);
1621
1622 skb->len += rx_packet_len;
1623 skb->data_len += rx_packet_len;
1624 skb->truesize += rx_packet_len;
1625
1626 if ((page_count(rx_bi->page) == 1) &&
1627 (page_to_nid(rx_bi->page) == current_node))
1628 get_page(rx_bi->page);
1629 else
1630 rx_bi->page = NULL;
1631
1632 dma_unmap_page(rx_ring->dev,
1633 rx_bi->page_dma,
1634 PAGE_SIZE / 2,
1635 DMA_FROM_DEVICE);
1636 rx_bi->page_dma = 0;
1637 }
Mitch Williamsa132af22015-01-24 09:58:35 +00001638 I40E_RX_INCREMENT(rx_ring, i);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001639
1640 if (unlikely(
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001641 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001642 struct i40e_rx_buffer *next_buffer;
1643
1644 next_buffer = &rx_ring->rx_bi[i];
Mitch Williamsa132af22015-01-24 09:58:35 +00001645 next_buffer->skb = skb;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001646 rx_ring->rx_stats.non_eop_descs++;
Mitch Williamsa132af22015-01-24 09:58:35 +00001647 continue;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001648 }
1649
1650 /* ERR_MASK will only have valid bits if EOP set */
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001651 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001652 dev_kfree_skb_any(skb);
Mitch Williamsa132af22015-01-24 09:58:35 +00001653 continue;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001654 }
1655
Jesse Brandeburg206812b2014-02-12 01:45:33 +00001656 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1657 i40e_ptype_to_hash(rx_ptype));
Jacob Kellerbeb0dff2014-01-11 05:43:19 +00001658 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1659 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1660 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1661 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1662 rx_ring->last_rx_timestamp = jiffies;
1663 }
1664
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001665 /* probably a little skewed due to removing CRC */
1666 total_rx_bytes += skb->len;
1667 total_rx_packets++;
1668
1669 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
Joseph Gasparakis8144f0f2013-12-28 05:27:57 +00001670
1671 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1672
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001673 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001674 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1675 : 0;
Vasu Dev38e00432014-08-01 13:27:03 -07001676#ifdef I40E_FCOE
1677 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1678 dev_kfree_skb_any(skb);
Mitch Williamsa132af22015-01-24 09:58:35 +00001679 continue;
Vasu Dev38e00432014-08-01 13:27:03 -07001680 }
1681#endif
Mitch Williamsa132af22015-01-24 09:58:35 +00001682 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001683 i40e_receive_skb(rx_ring, skb, vlan_tag);
1684
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001685 rx_desc->wb.qword1.status_error_len = 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001686
Mitch Williamsa132af22015-01-24 09:58:35 +00001687 } while (likely(total_rx_packets < budget));
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001688
Alexander Duyck980e9b12013-09-28 06:01:03 +00001689 u64_stats_update_begin(&rx_ring->syncp);
Alexander Duycka114d0a2013-09-28 06:00:43 +00001690 rx_ring->stats.packets += total_rx_packets;
1691 rx_ring->stats.bytes += total_rx_bytes;
Alexander Duyck980e9b12013-09-28 06:01:03 +00001692 u64_stats_update_end(&rx_ring->syncp);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001693 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1694 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1695
Mitch Williamsa132af22015-01-24 09:58:35 +00001696 return total_rx_packets;
1697}
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001698
Mitch Williamsa132af22015-01-24 09:58:35 +00001699/**
1700 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1701 * @rx_ring: rx ring to clean
1702 * @budget: how many cleans we're allowed
1703 *
1704 * Returns number of packets cleaned
1705 **/
1706static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1707{
1708 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1709 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1710 struct i40e_vsi *vsi = rx_ring->vsi;
1711 union i40e_rx_desc *rx_desc;
1712 u32 rx_error, rx_status;
1713 u16 rx_packet_len;
1714 u8 rx_ptype;
1715 u64 qword;
1716 u16 i;
1717
1718 do {
1719 struct i40e_rx_buffer *rx_bi;
1720 struct sk_buff *skb;
1721 u16 vlan_tag;
1722 /* return some buffers to hardware, one at a time is too slow */
1723 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1724 i40e_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1725 cleaned_count = 0;
1726 }
1727
1728 i = rx_ring->next_to_clean;
1729 rx_desc = I40E_RX_DESC(rx_ring, i);
1730 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1731 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1732 I40E_RXD_QW1_STATUS_SHIFT;
1733
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001734 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
Mitch Williamsa132af22015-01-24 09:58:35 +00001735 break;
1736
1737 /* This memory barrier is needed to keep us from reading
1738 * any other fields out of the rx_desc until we know the
1739 * DD bit is set.
1740 */
Alexander Duyck67317162015-04-08 18:49:43 -07001741 dma_rmb();
Mitch Williamsa132af22015-01-24 09:58:35 +00001742
1743 if (i40e_rx_is_programming_status(qword)) {
1744 i40e_clean_programming_status(rx_ring, rx_desc);
1745 I40E_RX_INCREMENT(rx_ring, i);
1746 continue;
1747 }
1748 rx_bi = &rx_ring->rx_bi[i];
1749 skb = rx_bi->skb;
1750 prefetch(skb->data);
1751
1752 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1753 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1754
1755 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1756 I40E_RXD_QW1_ERROR_SHIFT;
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001757 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
Mitch Williamsa132af22015-01-24 09:58:35 +00001758
1759 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1760 I40E_RXD_QW1_PTYPE_SHIFT;
1761 rx_bi->skb = NULL;
1762 cleaned_count++;
1763
1764 /* Get the header and possibly the whole packet
1765 * If this is an skb from previous receive dma will be 0
1766 */
1767 skb_put(skb, rx_packet_len);
1768 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1769 DMA_FROM_DEVICE);
1770 rx_bi->dma = 0;
1771
1772 I40E_RX_INCREMENT(rx_ring, i);
1773
1774 if (unlikely(
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001775 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
Mitch Williamsa132af22015-01-24 09:58:35 +00001776 rx_ring->rx_stats.non_eop_descs++;
1777 continue;
1778 }
1779
1780 /* ERR_MASK will only have valid bits if EOP set */
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001781 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
Mitch Williamsa132af22015-01-24 09:58:35 +00001782 dev_kfree_skb_any(skb);
1783 /* TODO: shouldn't we increment a counter indicating the
1784 * drop?
1785 */
1786 continue;
1787 }
1788
1789 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1790 i40e_ptype_to_hash(rx_ptype));
1791 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1792 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1793 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1794 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1795 rx_ring->last_rx_timestamp = jiffies;
1796 }
1797
1798 /* probably a little skewed due to removing CRC */
1799 total_rx_bytes += skb->len;
1800 total_rx_packets++;
1801
1802 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1803
1804 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1805
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001806 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
Mitch Williamsa132af22015-01-24 09:58:35 +00001807 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1808 : 0;
1809#ifdef I40E_FCOE
1810 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1811 dev_kfree_skb_any(skb);
1812 continue;
1813 }
1814#endif
1815 i40e_receive_skb(rx_ring, skb, vlan_tag);
1816
Mitch Williamsa132af22015-01-24 09:58:35 +00001817 rx_desc->wb.qword1.status_error_len = 0;
1818 } while (likely(total_rx_packets < budget));
1819
1820 u64_stats_update_begin(&rx_ring->syncp);
1821 rx_ring->stats.packets += total_rx_packets;
1822 rx_ring->stats.bytes += total_rx_bytes;
1823 u64_stats_update_end(&rx_ring->syncp);
1824 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1825 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1826
1827 return total_rx_packets;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001828}
1829
1830/**
Carolyn Wybornyde32e3e2015-06-10 13:42:07 -04001831 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1832 * @vsi: the VSI we care about
1833 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1834 *
1835 **/
1836static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1837 struct i40e_q_vector *q_vector)
1838{
1839 struct i40e_hw *hw = &vsi->back->hw;
1840 u16 old_itr;
1841 int vector;
1842 u32 val;
1843
1844 vector = (q_vector->v_idx + vsi->base_vector);
1845 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1846 old_itr = q_vector->rx.itr;
1847 i40e_set_new_dynamic_itr(&q_vector->rx);
1848 if (old_itr != q_vector->rx.itr) {
1849 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1850 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1851 (I40E_RX_ITR <<
1852 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1853 (q_vector->rx.itr <<
1854 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1855 } else {
1856 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1857 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1858 (I40E_ITR_NONE <<
1859 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1860 }
1861 if (!test_bit(__I40E_DOWN, &vsi->state))
1862 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1863 } else {
1864 i40e_irq_dynamic_enable(vsi,
1865 q_vector->v_idx + vsi->base_vector);
1866 }
1867 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1868 old_itr = q_vector->tx.itr;
1869 i40e_set_new_dynamic_itr(&q_vector->tx);
1870 if (old_itr != q_vector->tx.itr) {
1871 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1872 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1873 (I40E_TX_ITR <<
1874 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1875 (q_vector->tx.itr <<
1876 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1877 } else {
1878 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1879 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1880 (I40E_ITR_NONE <<
1881 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1882 }
1883 if (!test_bit(__I40E_DOWN, &vsi->state))
1884 wr32(hw, I40E_PFINT_DYN_CTLN(q_vector->v_idx +
1885 vsi->base_vector - 1), val);
1886 } else {
1887 i40e_irq_dynamic_enable(vsi,
1888 q_vector->v_idx + vsi->base_vector);
1889 }
1890}
1891
1892/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001893 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1894 * @napi: napi struct with our devices info in it
1895 * @budget: amount of work driver is allowed to do this pass, in packets
1896 *
1897 * This function will clean all queues associated with a q_vector.
1898 *
1899 * Returns the amount of work done
1900 **/
1901int i40e_napi_poll(struct napi_struct *napi, int budget)
1902{
1903 struct i40e_q_vector *q_vector =
1904 container_of(napi, struct i40e_q_vector, napi);
1905 struct i40e_vsi *vsi = q_vector->vsi;
Alexander Duyckcd0b6fa2013-09-28 06:00:53 +00001906 struct i40e_ring *ring;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001907 bool clean_complete = true;
Jesse Brandeburgd91649f2015-01-07 02:55:01 +00001908 bool arm_wb = false;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001909 int budget_per_ring;
Mitch Williamsa132af22015-01-24 09:58:35 +00001910 int cleaned;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001911
1912 if (test_bit(__I40E_DOWN, &vsi->state)) {
1913 napi_complete(napi);
1914 return 0;
1915 }
1916
Alexander Duyckcd0b6fa2013-09-28 06:00:53 +00001917 /* Since the actual Tx work is minimal, we can give the Tx a larger
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001918 * budget and be more aggressive about cleaning up the Tx descriptors.
1919 */
Jesse Brandeburgd91649f2015-01-07 02:55:01 +00001920 i40e_for_each_ring(ring, q_vector->tx) {
Alexander Duyckcd0b6fa2013-09-28 06:00:53 +00001921 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
Jesse Brandeburgd91649f2015-01-07 02:55:01 +00001922 arm_wb |= ring->arm_wb;
1923 }
Alexander Duyckcd0b6fa2013-09-28 06:00:53 +00001924
1925 /* We attempt to distribute budget to each Rx queue fairly, but don't
1926 * allow the budget to go below 1 because that would exit polling early.
1927 */
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001928 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
Alexander Duyckcd0b6fa2013-09-28 06:00:53 +00001929
Mitch Williamsa132af22015-01-24 09:58:35 +00001930 i40e_for_each_ring(ring, q_vector->rx) {
1931 if (ring_is_ps_enabled(ring))
1932 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1933 else
1934 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1935 /* if we didn't clean as many as budgeted, we must be done */
1936 clean_complete &= (budget_per_ring != cleaned);
1937 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001938
1939 /* If work not completed, return budget and polling will return */
Jesse Brandeburgd91649f2015-01-07 02:55:01 +00001940 if (!clean_complete) {
1941 if (arm_wb)
1942 i40e_force_wb(vsi, q_vector);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001943 return budget;
Jesse Brandeburgd91649f2015-01-07 02:55:01 +00001944 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001945
Anjali Singhai Jain8e0764b2015-06-05 12:20:30 -04001946 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1947 q_vector->arm_wb_state = false;
1948
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001949 /* Work is done so exit the polling mode and re-enable the interrupt */
1950 napi_complete(napi);
Carolyn Wybornyde32e3e2015-06-10 13:42:07 -04001951 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1952 i40e_update_enable_itr(vsi, q_vector);
1953 } else { /* Legacy mode */
1954 struct i40e_hw *hw = &vsi->back->hw;
1955 /* We re-enable the queue 0 cause, but
1956 * don't worry about dynamic_enable
1957 * because we left it on for the other
1958 * possible interrupts during napi
1959 */
1960 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |
1961 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001962
Carolyn Wybornyde32e3e2015-06-10 13:42:07 -04001963 wr32(hw, I40E_QINT_RQCTL(0), qval);
1964 qval = rd32(hw, I40E_QINT_TQCTL(0)) |
1965 I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1966 wr32(hw, I40E_QINT_TQCTL(0), qval);
1967 i40e_irq_dynamic_enable_icr0(vsi->back);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001968 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001969 return 0;
1970}
1971
1972/**
1973 * i40e_atr - Add a Flow Director ATR filter
1974 * @tx_ring: ring to add programming descriptor to
1975 * @skb: send buffer
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04001976 * @tx_flags: send tx flags
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001977 * @protocol: wire protocol
1978 **/
1979static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04001980 u32 tx_flags, __be16 protocol)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001981{
1982 struct i40e_filter_program_desc *fdir_desc;
1983 struct i40e_pf *pf = tx_ring->vsi->back;
1984 union {
1985 unsigned char *network;
1986 struct iphdr *ipv4;
1987 struct ipv6hdr *ipv6;
1988 } hdr;
1989 struct tcphdr *th;
1990 unsigned int hlen;
1991 u32 flex_ptype, dtype_cmd;
Alexander Duyckfc4ac672013-09-28 06:00:22 +00001992 u16 i;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001993
1994 /* make sure ATR is enabled */
Jesse Brandeburg60ea5f82014-01-17 15:36:34 -08001995 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00001996 return;
1997
Anjali Singhai Jain04294e32015-02-27 09:15:28 +00001998 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1999 return;
2000
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002001 /* if sampling is disabled do nothing */
2002 if (!tx_ring->atr_sample_rate)
2003 return;
2004
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002005 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002006 return;
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002007
2008 if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL)) {
2009 /* snag network header to get L4 type and address */
2010 hdr.network = skb_network_header(skb);
2011
2012 /* Currently only IPv4/IPv6 with TCP is supported
2013 * access ihl as u8 to avoid unaligned access on ia64
2014 */
2015 if (tx_flags & I40E_TX_FLAGS_IPV4)
2016 hlen = (hdr.network[0] & 0x0F) << 2;
2017 else if (protocol == htons(ETH_P_IPV6))
2018 hlen = sizeof(struct ipv6hdr);
2019 else
2020 return;
2021 } else {
2022 hdr.network = skb_inner_network_header(skb);
2023 hlen = skb_inner_network_header_len(skb);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002024 }
2025
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002026 /* Currently only IPv4/IPv6 with TCP is supported
2027 * Note: tx_flags gets modified to reflect inner protocols in
2028 * tx_enable_csum function if encap is enabled.
2029 */
2030 if ((tx_flags & I40E_TX_FLAGS_IPV4) &&
2031 (hdr.ipv4->protocol != IPPROTO_TCP))
2032 return;
2033 else if ((tx_flags & I40E_TX_FLAGS_IPV6) &&
2034 (hdr.ipv6->nexthdr != IPPROTO_TCP))
2035 return;
2036
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002037 th = (struct tcphdr *)(hdr.network + hlen);
2038
Anjali Singhai Jain55a5e602014-02-12 06:33:25 +00002039 /* Due to lack of space, no more new filters can be programmed */
2040 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2041 return;
2042
2043 tx_ring->atr_count++;
2044
Anjali Singhai Jaince806782014-03-06 08:59:54 +00002045 /* sample on all syn/fin/rst packets or once every atr sample rate */
2046 if (!th->fin &&
2047 !th->syn &&
2048 !th->rst &&
2049 (tx_ring->atr_count < tx_ring->atr_sample_rate))
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002050 return;
2051
2052 tx_ring->atr_count = 0;
2053
2054 /* grab the next descriptor */
Alexander Duyckfc4ac672013-09-28 06:00:22 +00002055 i = tx_ring->next_to_use;
2056 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2057
2058 i++;
2059 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002060
2061 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2062 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2063 flex_ptype |= (protocol == htons(ETH_P_IP)) ?
2064 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2065 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2066 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2067 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2068
2069 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2070
2071 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2072
Anjali Singhai Jaince806782014-03-06 08:59:54 +00002073 dtype_cmd |= (th->fin || th->rst) ?
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002074 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2075 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2076 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2077 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2078
2079 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2080 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2081
2082 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2083 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2084
Anjali Singhai Jain433c47d2014-05-22 06:32:17 +00002085 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
Anjali Singhai Jain60ccd452015-04-16 20:06:01 -04002086 if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL))
2087 dtype_cmd |=
2088 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2089 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2090 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2091 else
2092 dtype_cmd |=
2093 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2094 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2095 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
Anjali Singhai Jain433c47d2014-05-22 06:32:17 +00002096
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002097 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
Jesse Brandeburg99753ea2014-06-04 04:22:49 +00002098 fdir_desc->rsvd = cpu_to_le32(0);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002099 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
Jesse Brandeburg99753ea2014-06-04 04:22:49 +00002100 fdir_desc->fd_id = cpu_to_le32(0);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002101}
2102
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002103/**
2104 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2105 * @skb: send buffer
2106 * @tx_ring: ring to send buffer on
2107 * @flags: the tx flags to be set
2108 *
2109 * Checks the skb and set up correspondingly several generic transmit flags
2110 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2111 *
2112 * Returns error code indicate the frame should be dropped upon error and the
2113 * otherwise returns 0 to indicate the flags has been set properly.
2114 **/
Vasu Dev38e00432014-08-01 13:27:03 -07002115#ifdef I40E_FCOE
Jesse Brandeburg3e587cf2015-04-16 20:06:10 -04002116inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002117 struct i40e_ring *tx_ring,
2118 u32 *flags)
Jesse Brandeburg3e587cf2015-04-16 20:06:10 -04002119#else
2120static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2121 struct i40e_ring *tx_ring,
2122 u32 *flags)
Vasu Dev38e00432014-08-01 13:27:03 -07002123#endif
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002124{
2125 __be16 protocol = skb->protocol;
2126 u32 tx_flags = 0;
2127
Greg Rose31eaacc2015-03-31 00:45:03 -07002128 if (protocol == htons(ETH_P_8021Q) &&
2129 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2130 /* When HW VLAN acceleration is turned off by the user the
2131 * stack sets the protocol to 8021q so that the driver
2132 * can take any steps required to support the SW only
2133 * VLAN handling. In our case the driver doesn't need
2134 * to take any further steps so just set the protocol
2135 * to the encapsulated ethertype.
2136 */
2137 skb->protocol = vlan_get_protocol(skb);
2138 goto out;
2139 }
2140
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002141 /* if we have a HW VLAN tag being added, default to the HW one */
Jiri Pirkodf8a39d2015-01-13 17:13:44 +01002142 if (skb_vlan_tag_present(skb)) {
2143 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002144 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2145 /* else if it is a SW VLAN, check the next protocol and store the tag */
Jesse Brandeburg0e2fe46c2013-11-28 06:39:29 +00002146 } else if (protocol == htons(ETH_P_8021Q)) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002147 struct vlan_hdr *vhdr, _vhdr;
2148 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2149 if (!vhdr)
2150 return -EINVAL;
2151
2152 protocol = vhdr->h_vlan_encapsulated_proto;
2153 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2154 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2155 }
2156
Neerav Parikhd40d00b2015-02-24 06:58:40 +00002157 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2158 goto out;
2159
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002160 /* Insert 802.1p priority into VLAN header */
Vasu Dev38e00432014-08-01 13:27:03 -07002161 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2162 (skb->priority != TC_PRIO_CONTROL)) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002163 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2164 tx_flags |= (skb->priority & 0x7) <<
2165 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2166 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2167 struct vlan_ethhdr *vhdr;
Francois Romieudd225bc2014-03-30 03:14:48 +00002168 int rc;
2169
2170 rc = skb_cow_head(skb, 0);
2171 if (rc < 0)
2172 return rc;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002173 vhdr = (struct vlan_ethhdr *)skb->data;
2174 vhdr->h_vlan_TCI = htons(tx_flags >>
2175 I40E_TX_FLAGS_VLAN_SHIFT);
2176 } else {
2177 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2178 }
2179 }
Neerav Parikhd40d00b2015-02-24 06:58:40 +00002180
2181out:
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002182 *flags = tx_flags;
2183 return 0;
2184}
2185
2186/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002187 * i40e_tso - set up the tso context descriptor
2188 * @tx_ring: ptr to the ring to send
2189 * @skb: ptr to the skb we're sending
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002190 * @hdr_len: ptr to the size of the packet header
2191 * @cd_tunneling: ptr to context descriptor bits
2192 *
2193 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2194 **/
2195static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002196 u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
2197 u32 *cd_tunneling)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002198{
2199 u32 cd_cmd, cd_tso_len, cd_mss;
Francois Romieudd225bc2014-03-30 03:14:48 +00002200 struct ipv6hdr *ipv6h;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002201 struct tcphdr *tcph;
2202 struct iphdr *iph;
2203 u32 l4len;
2204 int err;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002205
2206 if (!skb_is_gso(skb))
2207 return 0;
2208
Francois Romieudd225bc2014-03-30 03:14:48 +00002209 err = skb_cow_head(skb, 0);
2210 if (err < 0)
2211 return err;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002212
Anjali Singhaidf230752014-12-19 02:58:16 +00002213 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
2214 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
2215
2216 if (iph->version == 4) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002217 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2218 iph->tot_len = 0;
2219 iph->check = 0;
2220 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
2221 0, IPPROTO_TCP, 0);
Anjali Singhaidf230752014-12-19 02:58:16 +00002222 } else if (ipv6h->version == 6) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002223 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2224 ipv6h->payload_len = 0;
2225 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
2226 0, IPPROTO_TCP, 0);
2227 }
2228
2229 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
2230 *hdr_len = (skb->encapsulation
2231 ? (skb_inner_transport_header(skb) - skb->data)
2232 : skb_transport_offset(skb)) + l4len;
2233
2234 /* find the field values */
2235 cd_cmd = I40E_TX_CTX_DESC_TSO;
2236 cd_tso_len = skb->len - *hdr_len;
2237 cd_mss = skb_shinfo(skb)->gso_size;
Mitch Williams829af3ac2013-12-18 13:46:00 +00002238 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2239 ((u64)cd_tso_len <<
2240 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2241 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002242 return 1;
2243}
2244
2245/**
Jacob Kellerbeb0dff2014-01-11 05:43:19 +00002246 * i40e_tsyn - set up the tsyn context descriptor
2247 * @tx_ring: ptr to the ring to send
2248 * @skb: ptr to the skb we're sending
2249 * @tx_flags: the collected send information
2250 *
2251 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2252 **/
2253static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2254 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2255{
2256 struct i40e_pf *pf;
2257
2258 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2259 return 0;
2260
2261 /* Tx timestamps cannot be sampled when doing TSO */
2262 if (tx_flags & I40E_TX_FLAGS_TSO)
2263 return 0;
2264
2265 /* only timestamp the outbound packet if the user has requested it and
2266 * we are not already transmitting a packet to be timestamped
2267 */
2268 pf = i40e_netdev_to_pf(tx_ring->netdev);
Jacob Keller22b47772014-12-14 01:55:09 +00002269 if (!(pf->flags & I40E_FLAG_PTP))
2270 return 0;
2271
Jakub Kicinski9ce34f02014-03-15 14:55:42 +00002272 if (pf->ptp_tx &&
2273 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
Jacob Kellerbeb0dff2014-01-11 05:43:19 +00002274 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2275 pf->ptp_tx_skb = skb_get(skb);
2276 } else {
2277 return 0;
2278 }
2279
2280 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2281 I40E_TXD_CTX_QW1_CMD_SHIFT;
2282
Jacob Kellerbeb0dff2014-01-11 05:43:19 +00002283 return 1;
2284}
2285
2286/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002287 * i40e_tx_enable_csum - Enable Tx checksum offloads
2288 * @skb: send buffer
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002289 * @tx_flags: pointer to Tx flags currently set
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002290 * @td_cmd: Tx descriptor command bits to set
2291 * @td_offset: Tx descriptor header offsets to set
2292 * @cd_tunneling: ptr to context desc bits
2293 **/
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002294static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002295 u32 *td_cmd, u32 *td_offset,
2296 struct i40e_ring *tx_ring,
2297 u32 *cd_tunneling)
2298{
2299 struct ipv6hdr *this_ipv6_hdr;
2300 unsigned int this_tcp_hdrlen;
2301 struct iphdr *this_ip_hdr;
2302 u32 network_hdr_len;
2303 u8 l4_hdr = 0;
Anjali Singhai Jain45991202015-02-27 09:15:29 +00002304 u32 l4_tunnel = 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002305
2306 if (skb->encapsulation) {
Anjali Singhai Jain45991202015-02-27 09:15:29 +00002307 switch (ip_hdr(skb)->protocol) {
2308 case IPPROTO_UDP:
2309 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002310 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
Anjali Singhai Jain45991202015-02-27 09:15:29 +00002311 break;
2312 default:
2313 return;
2314 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002315 network_hdr_len = skb_inner_network_header_len(skb);
2316 this_ip_hdr = inner_ip_hdr(skb);
2317 this_ipv6_hdr = inner_ipv6_hdr(skb);
2318 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
2319
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002320 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2321 if (*tx_flags & I40E_TX_FLAGS_TSO) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002322 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
2323 ip_hdr(skb)->check = 0;
2324 } else {
2325 *cd_tunneling |=
2326 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2327 }
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002328 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
Anjali Singhaidf230752014-12-19 02:58:16 +00002329 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002330 if (*tx_flags & I40E_TX_FLAGS_TSO)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002331 ip_hdr(skb)->check = 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002332 }
2333
2334 /* Now set the ctx descriptor fields */
2335 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
Anjali Singhai Jain45991202015-02-27 09:15:29 +00002336 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
2337 l4_tunnel |
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002338 ((skb_inner_network_offset(skb) -
2339 skb_transport_offset(skb)) >> 1) <<
2340 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
Anjali Singhaidf230752014-12-19 02:58:16 +00002341 if (this_ip_hdr->version == 6) {
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002342 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
2343 *tx_flags |= I40E_TX_FLAGS_IPV6;
Anjali Singhaidf230752014-12-19 02:58:16 +00002344 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002345 } else {
2346 network_hdr_len = skb_network_header_len(skb);
2347 this_ip_hdr = ip_hdr(skb);
2348 this_ipv6_hdr = ipv6_hdr(skb);
2349 this_tcp_hdrlen = tcp_hdrlen(skb);
2350 }
2351
2352 /* Enable IP checksum offloads */
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002353 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002354 l4_hdr = this_ip_hdr->protocol;
2355 /* the stack computes the IP header already, the only time we
2356 * need the hardware to recompute it is in the case of TSO.
2357 */
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002358 if (*tx_flags & I40E_TX_FLAGS_TSO) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002359 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
2360 this_ip_hdr->check = 0;
2361 } else {
2362 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
2363 }
2364 /* Now set the td_offset for IP header length */
2365 *td_offset = (network_hdr_len >> 2) <<
2366 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002367 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002368 l4_hdr = this_ipv6_hdr->nexthdr;
2369 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2370 /* Now set the td_offset for IP header length */
2371 *td_offset = (network_hdr_len >> 2) <<
2372 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2373 }
2374 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
2375 *td_offset |= (skb_network_offset(skb) >> 1) <<
2376 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2377
2378 /* Enable L4 checksum offloads */
2379 switch (l4_hdr) {
2380 case IPPROTO_TCP:
2381 /* enable checksum offloads */
2382 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2383 *td_offset |= (this_tcp_hdrlen >> 2) <<
2384 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2385 break;
2386 case IPPROTO_SCTP:
2387 /* enable SCTP checksum offload */
2388 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2389 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
2390 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2391 break;
2392 case IPPROTO_UDP:
2393 /* enable UDP checksum offload */
2394 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2395 *td_offset |= (sizeof(struct udphdr) >> 2) <<
2396 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2397 break;
2398 default:
2399 break;
2400 }
2401}
2402
2403/**
2404 * i40e_create_tx_ctx Build the Tx context descriptor
2405 * @tx_ring: ring to create the descriptor on
2406 * @cd_type_cmd_tso_mss: Quad Word 1
2407 * @cd_tunneling: Quad Word 0 - bits 0-31
2408 * @cd_l2tag2: Quad Word 0 - bits 32-63
2409 **/
2410static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2411 const u64 cd_type_cmd_tso_mss,
2412 const u32 cd_tunneling, const u32 cd_l2tag2)
2413{
2414 struct i40e_tx_context_desc *context_desc;
Alexander Duyckfc4ac672013-09-28 06:00:22 +00002415 int i = tx_ring->next_to_use;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002416
Jesse Brandeburgff40dd52014-02-14 02:14:41 +00002417 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2418 !cd_tunneling && !cd_l2tag2)
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002419 return;
2420
2421 /* grab the next descriptor */
Alexander Duyckfc4ac672013-09-28 06:00:22 +00002422 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2423
2424 i++;
2425 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002426
2427 /* cpu_to_le32 and assign to struct fields */
2428 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2429 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
Jesse Brandeburg3efbbb22014-06-04 20:41:54 +00002430 context_desc->rsvd = cpu_to_le16(0);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002431 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2432}
2433
2434/**
Eric Dumazet4567dc12014-10-07 13:30:23 -07002435 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2436 * @tx_ring: the ring to be checked
2437 * @size: the size buffer we want to assure is available
2438 *
2439 * Returns -EBUSY if a stop is needed, else 0
2440 **/
2441static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2442{
2443 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2444 /* Memory barrier before checking head and tail */
2445 smp_mb();
2446
2447 /* Check again in a case another CPU has just made room available. */
2448 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2449 return -EBUSY;
2450
2451 /* A reprieve! - use start_queue because it doesn't call schedule */
2452 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2453 ++tx_ring->tx_stats.restart_queue;
2454 return 0;
2455}
2456
2457/**
2458 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2459 * @tx_ring: the ring to be checked
2460 * @size: the size buffer we want to assure is available
2461 *
2462 * Returns 0 if stop is not needed
2463 **/
2464#ifdef I40E_FCOE
Jesse Brandeburg3e587cf2015-04-16 20:06:10 -04002465inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
Eric Dumazet4567dc12014-10-07 13:30:23 -07002466#else
Jesse Brandeburg3e587cf2015-04-16 20:06:10 -04002467static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
Eric Dumazet4567dc12014-10-07 13:30:23 -07002468#endif
2469{
2470 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2471 return 0;
2472 return __i40e_maybe_stop_tx(tx_ring, size);
2473}
2474
2475/**
Anjali Singhai71da6192015-02-21 06:42:35 +00002476 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
2477 * @skb: send buffer
2478 * @tx_flags: collected send information
Anjali Singhai71da6192015-02-21 06:42:35 +00002479 *
2480 * Note: Our HW can't scatter-gather more than 8 fragments to build
2481 * a packet on the wire and so we need to figure out the cases where we
2482 * need to linearize the skb.
2483 **/
Anjali Singhai Jain30520832015-05-08 15:35:52 -07002484static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
Anjali Singhai71da6192015-02-21 06:42:35 +00002485{
2486 struct skb_frag_struct *frag;
2487 bool linearize = false;
2488 unsigned int size = 0;
2489 u16 num_frags;
2490 u16 gso_segs;
2491
2492 num_frags = skb_shinfo(skb)->nr_frags;
2493 gso_segs = skb_shinfo(skb)->gso_segs;
2494
2495 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
Anjali Singhai Jain30520832015-05-08 15:35:52 -07002496 u16 j = 0;
Anjali Singhai71da6192015-02-21 06:42:35 +00002497
2498 if (num_frags < (I40E_MAX_BUFFER_TXD))
2499 goto linearize_chk_done;
2500 /* try the simple math, if we have too many frags per segment */
2501 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
2502 I40E_MAX_BUFFER_TXD) {
2503 linearize = true;
2504 goto linearize_chk_done;
2505 }
2506 frag = &skb_shinfo(skb)->frags[0];
Anjali Singhai71da6192015-02-21 06:42:35 +00002507 /* we might still have more fragments per segment */
2508 do {
2509 size += skb_frag_size(frag);
2510 frag++; j++;
Anjali Singhai Jain30520832015-05-08 15:35:52 -07002511 if ((size >= skb_shinfo(skb)->gso_size) &&
2512 (j < I40E_MAX_BUFFER_TXD)) {
2513 size = (size % skb_shinfo(skb)->gso_size);
2514 j = (size) ? 1 : 0;
2515 }
Anjali Singhai71da6192015-02-21 06:42:35 +00002516 if (j == I40E_MAX_BUFFER_TXD) {
Anjali Singhai Jain30520832015-05-08 15:35:52 -07002517 linearize = true;
2518 break;
Anjali Singhai71da6192015-02-21 06:42:35 +00002519 }
2520 num_frags--;
2521 } while (num_frags);
2522 } else {
2523 if (num_frags >= I40E_MAX_BUFFER_TXD)
2524 linearize = true;
2525 }
2526
2527linearize_chk_done:
2528 return linearize;
2529}
2530
2531/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002532 * i40e_tx_map - Build the Tx descriptor
2533 * @tx_ring: ring to send buffer on
2534 * @skb: send buffer
2535 * @first: first buffer info buffer to use
2536 * @tx_flags: collected send information
2537 * @hdr_len: size of the packet header
2538 * @td_cmd: the command field in the descriptor
2539 * @td_offset: offset for checksum or crc
2540 **/
Vasu Dev38e00432014-08-01 13:27:03 -07002541#ifdef I40E_FCOE
Jesse Brandeburg3e587cf2015-04-16 20:06:10 -04002542inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002543 struct i40e_tx_buffer *first, u32 tx_flags,
2544 const u8 hdr_len, u32 td_cmd, u32 td_offset)
Jesse Brandeburg3e587cf2015-04-16 20:06:10 -04002545#else
2546static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2547 struct i40e_tx_buffer *first, u32 tx_flags,
2548 const u8 hdr_len, u32 td_cmd, u32 td_offset)
Vasu Dev38e00432014-08-01 13:27:03 -07002549#endif
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002550{
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002551 unsigned int data_len = skb->data_len;
2552 unsigned int size = skb_headlen(skb);
Alexander Duycka5e9c572013-09-28 06:00:27 +00002553 struct skb_frag_struct *frag;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002554 struct i40e_tx_buffer *tx_bi;
2555 struct i40e_tx_desc *tx_desc;
Alexander Duycka5e9c572013-09-28 06:00:27 +00002556 u16 i = tx_ring->next_to_use;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002557 u32 td_tag = 0;
2558 dma_addr_t dma;
2559 u16 gso_segs;
2560
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002561 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2562 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2563 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2564 I40E_TX_FLAGS_VLAN_SHIFT;
2565 }
2566
Alexander Duycka5e9c572013-09-28 06:00:27 +00002567 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2568 gso_segs = skb_shinfo(skb)->gso_segs;
2569 else
2570 gso_segs = 1;
2571
2572 /* multiply data chunks by size of headers */
2573 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2574 first->gso_segs = gso_segs;
2575 first->skb = skb;
2576 first->tx_flags = tx_flags;
2577
2578 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2579
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002580 tx_desc = I40E_TX_DESC(tx_ring, i);
Alexander Duycka5e9c572013-09-28 06:00:27 +00002581 tx_bi = first;
2582
2583 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2584 if (dma_mapping_error(tx_ring->dev, dma))
2585 goto dma_error;
2586
2587 /* record length, and DMA address */
2588 dma_unmap_len_set(tx_bi, len, size);
2589 dma_unmap_addr_set(tx_bi, dma, dma);
2590
2591 tx_desc->buffer_addr = cpu_to_le64(dma);
2592
2593 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002594 tx_desc->cmd_type_offset_bsz =
2595 build_ctob(td_cmd, td_offset,
2596 I40E_MAX_DATA_PER_TXD, td_tag);
2597
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002598 tx_desc++;
2599 i++;
2600 if (i == tx_ring->count) {
2601 tx_desc = I40E_TX_DESC(tx_ring, 0);
2602 i = 0;
2603 }
Alexander Duycka5e9c572013-09-28 06:00:27 +00002604
2605 dma += I40E_MAX_DATA_PER_TXD;
2606 size -= I40E_MAX_DATA_PER_TXD;
2607
2608 tx_desc->buffer_addr = cpu_to_le64(dma);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002609 }
2610
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002611 if (likely(!data_len))
2612 break;
2613
Alexander Duycka5e9c572013-09-28 06:00:27 +00002614 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2615 size, td_tag);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002616
2617 tx_desc++;
2618 i++;
2619 if (i == tx_ring->count) {
2620 tx_desc = I40E_TX_DESC(tx_ring, 0);
2621 i = 0;
2622 }
2623
Alexander Duycka5e9c572013-09-28 06:00:27 +00002624 size = skb_frag_size(frag);
2625 data_len -= size;
2626
2627 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2628 DMA_TO_DEVICE);
2629
2630 tx_bi = &tx_ring->tx_bi[i];
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002631 }
2632
Jesse Brandeburg1943d8b2014-02-14 02:14:40 +00002633 /* Place RS bit on last descriptor of any packet that spans across the
2634 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
2635 */
Jesse Brandeburg1943d8b2014-02-14 02:14:40 +00002636 if (((i & WB_STRIDE) != WB_STRIDE) &&
2637 (first <= &tx_ring->tx_bi[i]) &&
2638 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
2639 tx_desc->cmd_type_offset_bsz =
2640 build_ctob(td_cmd, td_offset, size, td_tag) |
2641 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
2642 I40E_TXD_QW1_CMD_SHIFT);
2643 } else {
2644 tx_desc->cmd_type_offset_bsz =
2645 build_ctob(td_cmd, td_offset, size, td_tag) |
2646 cpu_to_le64((u64)I40E_TXD_CMD <<
2647 I40E_TXD_QW1_CMD_SHIFT);
2648 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002649
Alexander Duyck7070ce02013-09-28 06:00:37 +00002650 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2651 tx_ring->queue_index),
2652 first->bytecount);
2653
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002654 /* Force memory writes to complete before letting h/w
2655 * know there are new descriptors to fetch. (Only
2656 * applicable for weak-ordered memory model archs,
2657 * such as IA-64).
2658 */
2659 wmb();
2660
Alexander Duycka5e9c572013-09-28 06:00:27 +00002661 /* set next_to_watch value indicating a packet is present */
2662 first->next_to_watch = tx_desc;
2663
2664 i++;
2665 if (i == tx_ring->count)
2666 i = 0;
2667
2668 tx_ring->next_to_use = i;
2669
Eric Dumazet4567dc12014-10-07 13:30:23 -07002670 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
Alexander Duycka5e9c572013-09-28 06:00:27 +00002671 /* notify HW of packet */
Eric Dumazet4567dc12014-10-07 13:30:23 -07002672 if (!skb->xmit_more ||
2673 netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2674 tx_ring->queue_index)))
2675 writel(i, tx_ring->tail);
Jesse Brandeburg489ce7a2015-04-27 14:57:08 -04002676 else
2677 prefetchw(tx_desc + 1);
Alexander Duycka5e9c572013-09-28 06:00:27 +00002678
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002679 return;
2680
2681dma_error:
Alexander Duycka5e9c572013-09-28 06:00:27 +00002682 dev_info(tx_ring->dev, "TX DMA map failed\n");
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002683
2684 /* clear dma mappings for failed tx_bi map */
2685 for (;;) {
2686 tx_bi = &tx_ring->tx_bi[i];
Alexander Duycka5e9c572013-09-28 06:00:27 +00002687 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002688 if (tx_bi == first)
2689 break;
2690 if (i == 0)
2691 i = tx_ring->count;
2692 i--;
2693 }
2694
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002695 tx_ring->next_to_use = i;
2696}
2697
2698/**
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002699 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2700 * @skb: send buffer
2701 * @tx_ring: ring to send buffer on
2702 *
2703 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2704 * there is not enough descriptors available in this ring since we need at least
2705 * one descriptor.
2706 **/
Vasu Dev38e00432014-08-01 13:27:03 -07002707#ifdef I40E_FCOE
Jesse Brandeburg3e587cf2015-04-16 20:06:10 -04002708inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002709 struct i40e_ring *tx_ring)
Jesse Brandeburg3e587cf2015-04-16 20:06:10 -04002710#else
2711static inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2712 struct i40e_ring *tx_ring)
Vasu Dev38e00432014-08-01 13:27:03 -07002713#endif
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002714{
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002715 unsigned int f;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002716 int count = 0;
2717
2718 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2719 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
Jesse Brandeburgbe560522014-02-06 05:51:13 +00002720 * + 4 desc gap to avoid the cache line where head is,
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002721 * + 1 desc for context descriptor,
2722 * otherwise try next time
2723 */
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002724 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2725 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
Jesse Brandeburg980093e2014-05-10 04:49:12 +00002726
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002727 count += TXD_USE_COUNT(skb_headlen(skb));
Jesse Brandeburgbe560522014-02-06 05:51:13 +00002728 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002729 tx_ring->tx_stats.tx_busy++;
2730 return 0;
2731 }
2732 return count;
2733}
2734
2735/**
2736 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2737 * @skb: send buffer
2738 * @tx_ring: ring to send buffer on
2739 *
2740 * Returns NETDEV_TX_OK if sent, else an error code
2741 **/
2742static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2743 struct i40e_ring *tx_ring)
2744{
2745 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2746 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2747 struct i40e_tx_buffer *first;
2748 u32 td_offset = 0;
2749 u32 tx_flags = 0;
2750 __be16 protocol;
2751 u32 td_cmd = 0;
2752 u8 hdr_len = 0;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +00002753 int tsyn;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002754 int tso;
2755 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2756 return NETDEV_TX_BUSY;
2757
2758 /* prepare the xmit flags */
2759 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2760 goto out_drop;
2761
2762 /* obtain protocol of skb */
Vlad Yasevich3d34dd02014-08-25 10:34:52 -04002763 protocol = vlan_get_protocol(skb);
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002764
2765 /* record the location of the first descriptor for this packet */
2766 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2767
2768 /* setup IPv4/IPv6 offloads */
Jesse Brandeburg0e2fe46c2013-11-28 06:39:29 +00002769 if (protocol == htons(ETH_P_IP))
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002770 tx_flags |= I40E_TX_FLAGS_IPV4;
Jesse Brandeburg0e2fe46c2013-11-28 06:39:29 +00002771 else if (protocol == htons(ETH_P_IPV6))
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002772 tx_flags |= I40E_TX_FLAGS_IPV6;
2773
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002774 tso = i40e_tso(tx_ring, skb, &hdr_len,
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002775 &cd_type_cmd_tso_mss, &cd_tunneling);
2776
2777 if (tso < 0)
2778 goto out_drop;
2779 else if (tso)
2780 tx_flags |= I40E_TX_FLAGS_TSO;
2781
Jacob Kellerbeb0dff2014-01-11 05:43:19 +00002782 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2783
2784 if (tsyn)
2785 tx_flags |= I40E_TX_FLAGS_TSYN;
2786
Anjali Singhai Jain30520832015-05-08 15:35:52 -07002787 if (i40e_chk_linearize(skb, tx_flags))
Anjali Singhai71da6192015-02-21 06:42:35 +00002788 if (skb_linearize(skb))
2789 goto out_drop;
2790
Jakub Kicinski259afec2014-03-15 14:55:37 +00002791 skb_tx_timestamp(skb);
2792
Alexander Duyckb1941302013-09-28 06:00:32 +00002793 /* always enable CRC insertion offload */
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002794 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2795
Alexander Duyckb1941302013-09-28 06:00:32 +00002796 /* Always offload the checksum, since it's in the data descriptor */
2797 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2798 tx_flags |= I40E_TX_FLAGS_CSUM;
2799
Anjali Singhai Jain89232c32015-04-16 20:06:00 -04002800 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002801 tx_ring, &cd_tunneling);
Alexander Duyckb1941302013-09-28 06:00:32 +00002802 }
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002803
2804 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2805 cd_tunneling, cd_l2tag2);
2806
2807 /* Add Flow Director ATR if it's enabled.
2808 *
2809 * NOTE: this must always be directly before the data descriptor.
2810 */
2811 i40e_atr(tx_ring, skb, tx_flags, protocol);
2812
2813 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2814 td_cmd, td_offset);
2815
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002816 return NETDEV_TX_OK;
2817
2818out_drop:
2819 dev_kfree_skb_any(skb);
2820 return NETDEV_TX_OK;
2821}
2822
2823/**
2824 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2825 * @skb: send buffer
2826 * @netdev: network interface device structure
2827 *
2828 * Returns NETDEV_TX_OK if sent, else an error code
2829 **/
2830netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2831{
2832 struct i40e_netdev_priv *np = netdev_priv(netdev);
2833 struct i40e_vsi *vsi = np->vsi;
Alexander Duyck9f65e152013-09-28 06:00:58 +00002834 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002835
2836 /* hardware can't handle really short frames, hardware padding works
2837 * beyond this point
2838 */
Alexander Duycka94d9e22014-12-03 08:17:39 -08002839 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2840 return NETDEV_TX_OK;
Jesse Brandeburgfd0a05c2013-09-11 08:39:51 +00002841
2842 return i40e_xmit_frame_ring(skb, tx_ring);
2843}