Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Intel GTT (Graphics Translation Table) routines |
| 3 | * |
| 4 | * Caveat: This driver implements the linux agp interface, but this is far from |
| 5 | * a agp driver! GTT support ended up here for purely historical reasons: The |
| 6 | * old userspace intel graphics drivers needed an interface to map memory into |
| 7 | * the GTT. And the drm provides a default interface for graphic devices sitting |
| 8 | * on an agp port. So it made sense to fake the GTT support as an agp port to |
| 9 | * avoid having to create a new api. |
| 10 | * |
| 11 | * With gem this does not make much sense anymore, just needlessly complicates |
| 12 | * the code. But as long as the old graphics stack is still support, it's stuck |
| 13 | * here. |
| 14 | * |
| 15 | * /fairy-tale-mode off |
| 16 | */ |
| 17 | |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 18 | #include <linux/module.h> |
| 19 | #include <linux/pci.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/pagemap.h> |
| 23 | #include <linux/agp_backend.h> |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 24 | #include <linux/delay.h> |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 25 | #include <asm/smp.h> |
| 26 | #include "agp.h" |
| 27 | #include "intel-agp.h" |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 28 | #include <drm/intel-gtt.h> |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 29 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 30 | /* |
| 31 | * If we have Intel graphics, we're not going to have anything other than |
| 32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 33 | * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 34 | * Only newer chipsets need to bother with this, of course. |
| 35 | */ |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 36 | #ifdef CONFIG_INTEL_IOMMU |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 37 | #define USE_PCI_DMA_API 1 |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 38 | #else |
| 39 | #define USE_PCI_DMA_API 0 |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 40 | #endif |
| 41 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 42 | struct intel_gtt_driver { |
| 43 | unsigned int gen : 8; |
| 44 | unsigned int is_g33 : 1; |
| 45 | unsigned int is_pineview : 1; |
| 46 | unsigned int is_ironlake : 1; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 47 | unsigned int has_pgtbl_enable : 1; |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 48 | unsigned int dma_mask_size : 8; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 49 | /* Chipset specific GTT setup */ |
| 50 | int (*setup)(void); |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 51 | /* This should undo anything done in ->setup() save the unmapping |
| 52 | * of the mmio register file, that's done in the generic code. */ |
| 53 | void (*cleanup)(void); |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 54 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
| 55 | /* Flags is a more or less chipset specific opaque value. |
| 56 | * For chipsets that need to support old ums (non-gem) code, this |
| 57 | * needs to be identical to the various supported agp memory types! */ |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 58 | bool (*check_flags)(unsigned int flags); |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 59 | void (*chipset_flush)(void); |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 60 | }; |
| 61 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 62 | static struct _intel_private { |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 63 | struct intel_gtt base; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 64 | const struct intel_gtt_driver *driver; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 65 | struct pci_dev *pcidev; /* device one */ |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 66 | struct pci_dev *bridge_dev; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 67 | u8 __iomem *registers; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 68 | phys_addr_t gtt_bus_addr; |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 69 | u32 PGETBL_save; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 70 | u32 __iomem *gtt; /* I915G */ |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 71 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 72 | int num_dcache_entries; |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 73 | void __iomem *i9xx_flush_page; |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 74 | char *i81x_gtt_table; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 75 | struct resource ifp_resource; |
| 76 | int resource_valid; |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 77 | struct page *scratch_page; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 78 | int refcount; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 79 | } intel_private; |
| 80 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 81 | #define INTEL_GTT_GEN intel_private.driver->gen |
| 82 | #define IS_G33 intel_private.driver->is_g33 |
| 83 | #define IS_PINEVIEW intel_private.driver->is_pineview |
| 84 | #define IS_IRONLAKE intel_private.driver->is_ironlake |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 85 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 86 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 87 | int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, |
| 88 | struct scatterlist **sg_list, int *num_sg) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 89 | { |
| 90 | struct sg_table st; |
| 91 | struct scatterlist *sg; |
| 92 | int i; |
| 93 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 94 | if (*sg_list) |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 95 | return 0; /* already mapped (for e.g. resume */ |
| 96 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 97 | DBG("try mapping %lu pages\n", (unsigned long)num_entries); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 98 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 99 | if (sg_alloc_table(&st, num_entries, GFP_KERNEL)) |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 100 | goto err; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 101 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 102 | *sg_list = sg = st.sgl; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 103 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 104 | for (i = 0 ; i < num_entries; i++, sg = sg_next(sg)) |
| 105 | sg_set_page(sg, pages[i], PAGE_SIZE, 0); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 106 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 107 | *num_sg = pci_map_sg(intel_private.pcidev, *sg_list, |
| 108 | num_entries, PCI_DMA_BIDIRECTIONAL); |
| 109 | if (unlikely(!*num_sg)) |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 110 | goto err; |
| 111 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 112 | return 0; |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 113 | |
| 114 | err: |
| 115 | sg_free_table(&st); |
| 116 | return -ENOMEM; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 117 | } |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 118 | EXPORT_SYMBOL(intel_gtt_map_memory); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 119 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 120 | void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 121 | { |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 122 | struct sg_table st; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 123 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); |
| 124 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 125 | pci_unmap_sg(intel_private.pcidev, sg_list, |
| 126 | num_sg, PCI_DMA_BIDIRECTIONAL); |
| 127 | |
| 128 | st.sgl = sg_list; |
| 129 | st.orig_nents = st.nents = num_sg; |
| 130 | |
| 131 | sg_free_table(&st); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 132 | } |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 133 | EXPORT_SYMBOL(intel_gtt_unmap_memory); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 134 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 135 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 136 | { |
| 137 | return; |
| 138 | } |
| 139 | |
| 140 | /* Exists to support ARGB cursors */ |
| 141 | static struct page *i8xx_alloc_pages(void) |
| 142 | { |
| 143 | struct page *page; |
| 144 | |
| 145 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
| 146 | if (page == NULL) |
| 147 | return NULL; |
| 148 | |
| 149 | if (set_pages_uc(page, 4) < 0) { |
| 150 | set_pages_wb(page, 4); |
| 151 | __free_pages(page, 2); |
| 152 | return NULL; |
| 153 | } |
| 154 | get_page(page); |
| 155 | atomic_inc(&agp_bridge->current_memory_agp); |
| 156 | return page; |
| 157 | } |
| 158 | |
| 159 | static void i8xx_destroy_pages(struct page *page) |
| 160 | { |
| 161 | if (page == NULL) |
| 162 | return; |
| 163 | |
| 164 | set_pages_wb(page, 4); |
| 165 | put_page(page); |
| 166 | __free_pages(page, 2); |
| 167 | atomic_dec(&agp_bridge->current_memory_agp); |
| 168 | } |
| 169 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 170 | #define I810_GTT_ORDER 4 |
| 171 | static int i810_setup(void) |
| 172 | { |
| 173 | u32 reg_addr; |
| 174 | char *gtt_table; |
| 175 | |
| 176 | /* i81x does not preallocate the gtt. It's always 64kb in size. */ |
| 177 | gtt_table = alloc_gatt_pages(I810_GTT_ORDER); |
| 178 | if (gtt_table == NULL) |
| 179 | return -ENOMEM; |
| 180 | intel_private.i81x_gtt_table = gtt_table; |
| 181 | |
| 182 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); |
| 183 | reg_addr &= 0xfff80000; |
| 184 | |
| 185 | intel_private.registers = ioremap(reg_addr, KB(64)); |
| 186 | if (!intel_private.registers) |
| 187 | return -ENOMEM; |
| 188 | |
| 189 | writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, |
| 190 | intel_private.registers+I810_PGETBL_CTL); |
| 191 | |
| 192 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
| 193 | |
| 194 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
| 195 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
| 196 | dev_info(&intel_private.pcidev->dev, |
| 197 | "detected 4MB dedicated video ram\n"); |
| 198 | intel_private.num_dcache_entries = 1024; |
| 199 | } |
| 200 | |
| 201 | return 0; |
| 202 | } |
| 203 | |
| 204 | static void i810_cleanup(void) |
| 205 | { |
| 206 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
| 207 | free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); |
| 208 | } |
| 209 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 210 | static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, |
| 211 | int type) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 212 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 213 | int i; |
| 214 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 215 | if ((pg_start + mem->page_count) |
| 216 | > intel_private.num_dcache_entries) |
| 217 | return -EINVAL; |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 218 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 219 | if (!mem->is_flushed) |
| 220 | global_cache_flush(); |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 221 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 222 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
| 223 | dma_addr_t addr = i << PAGE_SHIFT; |
| 224 | intel_private.driver->write_entry(addr, |
| 225 | i, type); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 226 | } |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 227 | readl(intel_private.gtt+i-1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 228 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 229 | return 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 230 | } |
| 231 | |
| 232 | /* |
| 233 | * The i810/i830 requires a physical address to program its mouse |
| 234 | * pointer into hardware. |
| 235 | * However the Xserver still writes to it through the agp aperture. |
| 236 | */ |
| 237 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) |
| 238 | { |
| 239 | struct agp_memory *new; |
| 240 | struct page *page; |
| 241 | |
| 242 | switch (pg_count) { |
| 243 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); |
| 244 | break; |
| 245 | case 4: |
| 246 | /* kludge to get 4 physical pages for ARGB cursor */ |
| 247 | page = i8xx_alloc_pages(); |
| 248 | break; |
| 249 | default: |
| 250 | return NULL; |
| 251 | } |
| 252 | |
| 253 | if (page == NULL) |
| 254 | return NULL; |
| 255 | |
| 256 | new = agp_create_memory(pg_count); |
| 257 | if (new == NULL) |
| 258 | return NULL; |
| 259 | |
| 260 | new->pages[0] = page; |
| 261 | if (pg_count == 4) { |
| 262 | /* kludge to get 4 physical pages for ARGB cursor */ |
| 263 | new->pages[1] = new->pages[0] + 1; |
| 264 | new->pages[2] = new->pages[1] + 1; |
| 265 | new->pages[3] = new->pages[2] + 1; |
| 266 | } |
| 267 | new->page_count = pg_count; |
| 268 | new->num_scratch_pages = pg_count; |
| 269 | new->type = AGP_PHYS_MEMORY; |
| 270 | new->physical = page_to_phys(new->pages[0]); |
| 271 | return new; |
| 272 | } |
| 273 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 274 | static void intel_i810_free_by_type(struct agp_memory *curr) |
| 275 | { |
| 276 | agp_free_key(curr->key); |
| 277 | if (curr->type == AGP_PHYS_MEMORY) { |
| 278 | if (curr->page_count == 4) |
| 279 | i8xx_destroy_pages(curr->pages[0]); |
| 280 | else { |
| 281 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
| 282 | AGP_PAGE_DESTROY_UNMAP); |
| 283 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
| 284 | AGP_PAGE_DESTROY_FREE); |
| 285 | } |
| 286 | agp_free_page_array(curr); |
| 287 | } |
| 288 | kfree(curr); |
| 289 | } |
| 290 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 291 | static int intel_gtt_setup_scratch_page(void) |
| 292 | { |
| 293 | struct page *page; |
| 294 | dma_addr_t dma_addr; |
| 295 | |
| 296 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
| 297 | if (page == NULL) |
| 298 | return -ENOMEM; |
| 299 | get_page(page); |
| 300 | set_pages_uc(page, 1); |
| 301 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 302 | if (intel_private.base.needs_dmar) { |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 303 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, |
| 304 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 305 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) |
| 306 | return -EINVAL; |
| 307 | |
Daniel Vetter | 50a4c4a | 2012-02-09 17:15:44 +0100 | [diff] [blame] | 308 | intel_private.base.scratch_page_dma = dma_addr; |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 309 | } else |
Daniel Vetter | 50a4c4a | 2012-02-09 17:15:44 +0100 | [diff] [blame] | 310 | intel_private.base.scratch_page_dma = page_to_phys(page); |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 311 | |
| 312 | intel_private.scratch_page = page; |
| 313 | |
| 314 | return 0; |
| 315 | } |
| 316 | |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 317 | static void i810_write_entry(dma_addr_t addr, unsigned int entry, |
| 318 | unsigned int flags) |
| 319 | { |
| 320 | u32 pte_flags = I810_PTE_VALID; |
| 321 | |
| 322 | switch (flags) { |
| 323 | case AGP_DCACHE_MEMORY: |
| 324 | pte_flags |= I810_PTE_LOCAL; |
| 325 | break; |
| 326 | case AGP_USER_CACHED_MEMORY: |
| 327 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
| 328 | break; |
| 329 | } |
| 330 | |
| 331 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 332 | } |
| 333 | |
Chris Wilson | 7bdc9ab | 2010-11-09 17:53:20 +0000 | [diff] [blame] | 334 | static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 335 | {32, 8192, 3}, |
| 336 | {64, 16384, 4}, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 337 | {128, 32768, 5}, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 338 | {256, 65536, 6}, |
| 339 | {512, 131072, 7}, |
| 340 | }; |
| 341 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 342 | static unsigned int intel_gtt_stolen_size(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 343 | { |
| 344 | u16 gmch_ctrl; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 345 | u8 rdct; |
| 346 | int local = 0; |
| 347 | static const int ddt[4] = { 0, 16, 32, 64 }; |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 348 | unsigned int stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 349 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 350 | if (INTEL_GTT_GEN == 1) |
| 351 | return 0; /* no stolen mem on i81x */ |
| 352 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 353 | pci_read_config_word(intel_private.bridge_dev, |
| 354 | I830_GMCH_CTRL, &gmch_ctrl); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 355 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 356 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
| 357 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 358 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
| 359 | case I830_GMCH_GMS_STOLEN_512: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 360 | stolen_size = KB(512); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 361 | break; |
| 362 | case I830_GMCH_GMS_STOLEN_1024: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 363 | stolen_size = MB(1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 364 | break; |
| 365 | case I830_GMCH_GMS_STOLEN_8192: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 366 | stolen_size = MB(8); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 367 | break; |
| 368 | case I830_GMCH_GMS_LOCAL: |
| 369 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 370 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 371 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
| 372 | local = 1; |
| 373 | break; |
| 374 | default: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 375 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 376 | break; |
| 377 | } |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 378 | } else if (INTEL_GTT_GEN == 6) { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 379 | /* |
| 380 | * SandyBridge has new memory control reg at 0x50.w |
| 381 | */ |
| 382 | u16 snb_gmch_ctl; |
| 383 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
| 384 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { |
| 385 | case SNB_GMCH_GMS_STOLEN_32M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 386 | stolen_size = MB(32); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 387 | break; |
| 388 | case SNB_GMCH_GMS_STOLEN_64M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 389 | stolen_size = MB(64); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 390 | break; |
| 391 | case SNB_GMCH_GMS_STOLEN_96M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 392 | stolen_size = MB(96); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 393 | break; |
| 394 | case SNB_GMCH_GMS_STOLEN_128M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 395 | stolen_size = MB(128); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 396 | break; |
| 397 | case SNB_GMCH_GMS_STOLEN_160M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 398 | stolen_size = MB(160); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 399 | break; |
| 400 | case SNB_GMCH_GMS_STOLEN_192M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 401 | stolen_size = MB(192); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 402 | break; |
| 403 | case SNB_GMCH_GMS_STOLEN_224M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 404 | stolen_size = MB(224); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 405 | break; |
| 406 | case SNB_GMCH_GMS_STOLEN_256M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 407 | stolen_size = MB(256); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 408 | break; |
| 409 | case SNB_GMCH_GMS_STOLEN_288M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 410 | stolen_size = MB(288); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 411 | break; |
| 412 | case SNB_GMCH_GMS_STOLEN_320M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 413 | stolen_size = MB(320); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 414 | break; |
| 415 | case SNB_GMCH_GMS_STOLEN_352M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 416 | stolen_size = MB(352); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 417 | break; |
| 418 | case SNB_GMCH_GMS_STOLEN_384M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 419 | stolen_size = MB(384); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 420 | break; |
| 421 | case SNB_GMCH_GMS_STOLEN_416M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 422 | stolen_size = MB(416); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 423 | break; |
| 424 | case SNB_GMCH_GMS_STOLEN_448M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 425 | stolen_size = MB(448); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 426 | break; |
| 427 | case SNB_GMCH_GMS_STOLEN_480M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 428 | stolen_size = MB(480); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 429 | break; |
| 430 | case SNB_GMCH_GMS_STOLEN_512M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 431 | stolen_size = MB(512); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 432 | break; |
| 433 | } |
| 434 | } else { |
| 435 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
| 436 | case I855_GMCH_GMS_STOLEN_1M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 437 | stolen_size = MB(1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 438 | break; |
| 439 | case I855_GMCH_GMS_STOLEN_4M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 440 | stolen_size = MB(4); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 441 | break; |
| 442 | case I855_GMCH_GMS_STOLEN_8M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 443 | stolen_size = MB(8); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 444 | break; |
| 445 | case I855_GMCH_GMS_STOLEN_16M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 446 | stolen_size = MB(16); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 447 | break; |
| 448 | case I855_GMCH_GMS_STOLEN_32M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 449 | stolen_size = MB(32); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 450 | break; |
| 451 | case I915_GMCH_GMS_STOLEN_48M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 452 | stolen_size = MB(48); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 453 | break; |
| 454 | case I915_GMCH_GMS_STOLEN_64M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 455 | stolen_size = MB(64); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 456 | break; |
| 457 | case G33_GMCH_GMS_STOLEN_128M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 458 | stolen_size = MB(128); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 459 | break; |
| 460 | case G33_GMCH_GMS_STOLEN_256M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 461 | stolen_size = MB(256); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 462 | break; |
| 463 | case INTEL_GMCH_GMS_STOLEN_96M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 464 | stolen_size = MB(96); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 465 | break; |
| 466 | case INTEL_GMCH_GMS_STOLEN_160M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 467 | stolen_size = MB(160); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 468 | break; |
| 469 | case INTEL_GMCH_GMS_STOLEN_224M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 470 | stolen_size = MB(224); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 471 | break; |
| 472 | case INTEL_GMCH_GMS_STOLEN_352M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 473 | stolen_size = MB(352); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 474 | break; |
| 475 | default: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 476 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 477 | break; |
| 478 | } |
| 479 | } |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 480 | |
Chris Wilson | 1b6064d | 2010-11-23 12:33:54 +0000 | [diff] [blame] | 481 | if (stolen_size > 0) { |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 482 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 483 | stolen_size / KB(1), local ? "local" : "stolen"); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 484 | } else { |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 485 | dev_info(&intel_private.bridge_dev->dev, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 486 | "no pre-allocated video memory detected\n"); |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 487 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 488 | } |
| 489 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 490 | return stolen_size; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 491 | } |
| 492 | |
Daniel Vetter | 2017284 | 2010-09-24 18:25:59 +0200 | [diff] [blame] | 493 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
| 494 | { |
| 495 | u32 pgetbl_ctl, pgetbl_ctl2; |
| 496 | |
| 497 | /* ensure that ppgtt is disabled */ |
| 498 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); |
| 499 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; |
| 500 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); |
| 501 | |
| 502 | /* write the new ggtt size */ |
| 503 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
| 504 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; |
| 505 | pgetbl_ctl |= size_flag; |
| 506 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); |
| 507 | } |
| 508 | |
| 509 | static unsigned int i965_gtt_total_entries(void) |
| 510 | { |
| 511 | int size; |
| 512 | u32 pgetbl_ctl; |
| 513 | u16 gmch_ctl; |
| 514 | |
| 515 | pci_read_config_word(intel_private.bridge_dev, |
| 516 | I830_GMCH_CTRL, &gmch_ctl); |
| 517 | |
| 518 | if (INTEL_GTT_GEN == 5) { |
| 519 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { |
| 520 | case G4x_GMCH_SIZE_1M: |
| 521 | case G4x_GMCH_SIZE_VT_1M: |
| 522 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); |
| 523 | break; |
| 524 | case G4x_GMCH_SIZE_VT_1_5M: |
| 525 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); |
| 526 | break; |
| 527 | case G4x_GMCH_SIZE_2M: |
| 528 | case G4x_GMCH_SIZE_VT_2M: |
| 529 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); |
| 530 | break; |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
| 535 | |
| 536 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { |
| 537 | case I965_PGETBL_SIZE_128KB: |
| 538 | size = KB(128); |
| 539 | break; |
| 540 | case I965_PGETBL_SIZE_256KB: |
| 541 | size = KB(256); |
| 542 | break; |
| 543 | case I965_PGETBL_SIZE_512KB: |
| 544 | size = KB(512); |
| 545 | break; |
| 546 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ |
| 547 | case I965_PGETBL_SIZE_1MB: |
| 548 | size = KB(1024); |
| 549 | break; |
| 550 | case I965_PGETBL_SIZE_2MB: |
| 551 | size = KB(2048); |
| 552 | break; |
| 553 | case I965_PGETBL_SIZE_1_5MB: |
| 554 | size = KB(1024 + 512); |
| 555 | break; |
| 556 | default: |
| 557 | dev_info(&intel_private.pcidev->dev, |
| 558 | "unknown page table size, assuming 512KB\n"); |
| 559 | size = KB(512); |
| 560 | } |
| 561 | |
| 562 | return size/4; |
| 563 | } |
| 564 | |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 565 | static unsigned int intel_gtt_total_entries(void) |
| 566 | { |
| 567 | int size; |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 568 | |
Daniel Vetter | 2017284 | 2010-09-24 18:25:59 +0200 | [diff] [blame] | 569 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) |
| 570 | return i965_gtt_total_entries(); |
| 571 | else if (INTEL_GTT_GEN == 6) { |
Daniel Vetter | 210b23c | 2010-08-28 16:14:32 +0200 | [diff] [blame] | 572 | u16 snb_gmch_ctl; |
| 573 | |
| 574 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
| 575 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { |
| 576 | default: |
| 577 | case SNB_GTT_SIZE_0M: |
| 578 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); |
| 579 | size = MB(0); |
| 580 | break; |
| 581 | case SNB_GTT_SIZE_1M: |
| 582 | size = MB(1); |
| 583 | break; |
| 584 | case SNB_GTT_SIZE_2M: |
| 585 | size = MB(2); |
| 586 | break; |
| 587 | } |
| 588 | return size/4; |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 589 | } else { |
| 590 | /* On previous hardware, the GTT size was just what was |
| 591 | * required to map the aperture. |
| 592 | */ |
Daniel Vetter | e5e408f | 2010-08-28 11:04:32 +0200 | [diff] [blame] | 593 | return intel_private.base.gtt_mappable_entries; |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 594 | } |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 595 | } |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 596 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 597 | static unsigned int intel_gtt_mappable_entries(void) |
| 598 | { |
| 599 | unsigned int aperture_size; |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 600 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 601 | if (INTEL_GTT_GEN == 1) { |
| 602 | u32 smram_miscc; |
| 603 | |
| 604 | pci_read_config_dword(intel_private.bridge_dev, |
| 605 | I810_SMRAM_MISCC, &smram_miscc); |
| 606 | |
| 607 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) |
| 608 | == I810_GFX_MEM_WIN_32M) |
| 609 | aperture_size = MB(32); |
| 610 | else |
| 611 | aperture_size = MB(64); |
| 612 | } else if (INTEL_GTT_GEN == 2) { |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 613 | u16 gmch_ctrl; |
| 614 | |
| 615 | pci_read_config_word(intel_private.bridge_dev, |
| 616 | I830_GMCH_CTRL, &gmch_ctrl); |
| 617 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 618 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 619 | aperture_size = MB(64); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 620 | else |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 621 | aperture_size = MB(128); |
Daniel Vetter | 239918f | 2010-08-31 22:30:43 +0200 | [diff] [blame] | 622 | } else { |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 623 | /* 9xx supports large sizes, just look at the length */ |
| 624 | aperture_size = pci_resource_len(intel_private.pcidev, 2); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 625 | } |
| 626 | |
| 627 | return aperture_size >> PAGE_SHIFT; |
| 628 | } |
| 629 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 630 | static void intel_gtt_teardown_scratch_page(void) |
| 631 | { |
| 632 | set_pages_wb(intel_private.scratch_page, 1); |
Daniel Vetter | 50a4c4a | 2012-02-09 17:15:44 +0100 | [diff] [blame] | 633 | pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma, |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 634 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 635 | put_page(intel_private.scratch_page); |
| 636 | __free_page(intel_private.scratch_page); |
| 637 | } |
| 638 | |
| 639 | static void intel_gtt_cleanup(void) |
| 640 | { |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 641 | intel_private.driver->cleanup(); |
| 642 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 643 | iounmap(intel_private.gtt); |
| 644 | iounmap(intel_private.registers); |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 645 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 646 | intel_gtt_teardown_scratch_page(); |
| 647 | } |
| 648 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 649 | static int intel_gtt_init(void) |
| 650 | { |
Daniel Vetter | 32e3cd6 | 2012-06-07 15:56:02 +0200 | [diff] [blame] | 651 | u32 gma_addr; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 652 | u32 gtt_map_size; |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 653 | int ret; |
| 654 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 655 | ret = intel_private.driver->setup(); |
| 656 | if (ret != 0) |
| 657 | return ret; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 658 | |
| 659 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); |
| 660 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); |
| 661 | |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 662 | /* save the PGETBL reg for resume */ |
| 663 | intel_private.PGETBL_save = |
| 664 | readl(intel_private.registers+I810_PGETBL_CTL) |
| 665 | & ~I810_PGETBL_ENABLED; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 666 | /* we only ever restore the register when enabling the PGTBL... */ |
| 667 | if (HAS_PGTBL_EN) |
| 668 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 669 | |
Daniel Vetter | 0af9e92 | 2010-09-12 14:04:03 +0200 | [diff] [blame] | 670 | dev_info(&intel_private.bridge_dev->dev, |
| 671 | "detected gtt size: %dK total, %dK mappable\n", |
| 672 | intel_private.base.gtt_total_entries * 4, |
| 673 | intel_private.base.gtt_mappable_entries * 4); |
| 674 | |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 675 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
| 676 | |
| 677 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, |
| 678 | gtt_map_size); |
| 679 | if (!intel_private.gtt) { |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 680 | intel_private.driver->cleanup(); |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 681 | iounmap(intel_private.registers); |
| 682 | return -ENOMEM; |
| 683 | } |
Daniel Vetter | 428ccb2 | 2012-02-09 17:15:45 +0100 | [diff] [blame] | 684 | intel_private.base.gtt = intel_private.gtt; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 685 | |
| 686 | global_cache_flush(); /* FIXME: ? */ |
| 687 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 688 | intel_private.base.stolen_size = intel_gtt_stolen_size(); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 689 | |
Dave Airlie | a46f310 | 2011-01-12 11:38:37 +1000 | [diff] [blame] | 690 | intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; |
| 691 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 692 | ret = intel_gtt_setup_scratch_page(); |
| 693 | if (ret != 0) { |
| 694 | intel_gtt_cleanup(); |
| 695 | return ret; |
| 696 | } |
| 697 | |
Daniel Vetter | 32e3cd6 | 2012-06-07 15:56:02 +0200 | [diff] [blame] | 698 | if (INTEL_GTT_GEN <= 2) |
| 699 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, |
| 700 | &gma_addr); |
| 701 | else |
| 702 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, |
| 703 | &gma_addr); |
| 704 | |
| 705 | intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); |
| 706 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 707 | return 0; |
| 708 | } |
| 709 | |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 710 | static int intel_fake_agp_fetch_size(void) |
| 711 | { |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 712 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 713 | unsigned int aper_size; |
| 714 | int i; |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 715 | |
| 716 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) |
| 717 | / MB(1); |
| 718 | |
| 719 | for (i = 0; i < num_sizes; i++) { |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 720 | if (aper_size == intel_fake_agp_sizes[i].size) { |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 721 | agp_bridge->current_size = |
| 722 | (void *) (intel_fake_agp_sizes + i); |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 723 | return aper_size; |
| 724 | } |
| 725 | } |
| 726 | |
| 727 | return 0; |
| 728 | } |
| 729 | |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 730 | static void i830_cleanup(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 731 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 732 | } |
| 733 | |
| 734 | /* The chipset_flush interface needs to get data that has already been |
| 735 | * flushed out of the CPU all the way out to main memory, because the GPU |
| 736 | * doesn't snoop those buffers. |
| 737 | * |
| 738 | * The 8xx series doesn't have the same lovely interface for flushing the |
| 739 | * chipset write buffers that the later chips do. According to the 865 |
| 740 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in |
| 741 | * that buffer out, we just fill 1KB and clflush it out, on the assumption |
| 742 | * that it'll push whatever was in there out. It appears to work. |
| 743 | */ |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 744 | static void i830_chipset_flush(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 745 | { |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 746 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 747 | |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 748 | /* Forcibly evict everything from the CPU write buffers. |
| 749 | * clflush appears to be insufficient. |
| 750 | */ |
| 751 | wbinvd_on_all_cpus(); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 752 | |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 753 | /* Now we've only seen documents for this magic bit on 855GM, |
| 754 | * we hope it exists for the other gen2 chipsets... |
| 755 | * |
| 756 | * Also works as advertised on my 845G. |
| 757 | */ |
| 758 | writel(readl(intel_private.registers+I830_HIC) | (1<<31), |
| 759 | intel_private.registers+I830_HIC); |
| 760 | |
| 761 | while (readl(intel_private.registers+I830_HIC) & (1<<31)) { |
| 762 | if (time_after(jiffies, timeout)) |
| 763 | break; |
| 764 | |
| 765 | udelay(50); |
| 766 | } |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 767 | } |
| 768 | |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 769 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
| 770 | unsigned int flags) |
| 771 | { |
| 772 | u32 pte_flags = I810_PTE_VALID; |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 773 | |
Daniel Vetter | b47cf66 | 2010-11-04 18:41:50 +0100 | [diff] [blame] | 774 | if (flags == AGP_USER_CACHED_MEMORY) |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 775 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 776 | |
| 777 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 778 | } |
| 779 | |
Daniel Vetter | 8ecd1a6 | 2012-06-07 15:56:03 +0200 | [diff] [blame^] | 780 | bool intel_enable_gtt(void) |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 781 | { |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 782 | u8 __iomem *reg; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 783 | |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 784 | if (INTEL_GTT_GEN >= 6) |
| 785 | return true; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 786 | |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 787 | if (INTEL_GTT_GEN == 2) { |
| 788 | u16 gmch_ctrl; |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 789 | |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 790 | pci_read_config_word(intel_private.bridge_dev, |
| 791 | I830_GMCH_CTRL, &gmch_ctrl); |
| 792 | gmch_ctrl |= I830_GMCH_ENABLED; |
| 793 | pci_write_config_word(intel_private.bridge_dev, |
| 794 | I830_GMCH_CTRL, gmch_ctrl); |
| 795 | |
| 796 | pci_read_config_word(intel_private.bridge_dev, |
| 797 | I830_GMCH_CTRL, &gmch_ctrl); |
| 798 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { |
| 799 | dev_err(&intel_private.pcidev->dev, |
| 800 | "failed to enable the GTT: GMCH_CTRL=%x\n", |
| 801 | gmch_ctrl); |
| 802 | return false; |
| 803 | } |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 804 | } |
| 805 | |
Chris Wilson | c97689d | 2010-12-23 10:40:38 +0000 | [diff] [blame] | 806 | /* On the resume path we may be adjusting the PGTBL value, so |
| 807 | * be paranoid and flush all chipset write buffers... |
| 808 | */ |
| 809 | if (INTEL_GTT_GEN >= 3) |
| 810 | writel(0, intel_private.registers+GFX_FLSH_CNTL); |
| 811 | |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 812 | reg = intel_private.registers+I810_PGETBL_CTL; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 813 | writel(intel_private.PGETBL_save, reg); |
| 814 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 815 | dev_err(&intel_private.pcidev->dev, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 816 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 817 | readl(reg), intel_private.PGETBL_save); |
| 818 | return false; |
| 819 | } |
| 820 | |
Chris Wilson | c97689d | 2010-12-23 10:40:38 +0000 | [diff] [blame] | 821 | if (INTEL_GTT_GEN >= 3) |
| 822 | writel(0, intel_private.registers+GFX_FLSH_CNTL); |
| 823 | |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 824 | return true; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 825 | } |
Daniel Vetter | 8ecd1a6 | 2012-06-07 15:56:03 +0200 | [diff] [blame^] | 826 | EXPORT_SYMBOL(intel_enable_gtt); |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 827 | |
| 828 | static int i830_setup(void) |
| 829 | { |
| 830 | u32 reg_addr; |
| 831 | |
| 832 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); |
| 833 | reg_addr &= 0xfff80000; |
| 834 | |
| 835 | intel_private.registers = ioremap(reg_addr, KB(64)); |
| 836 | if (!intel_private.registers) |
| 837 | return -ENOMEM; |
| 838 | |
| 839 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
| 840 | |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 841 | return 0; |
| 842 | } |
| 843 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 844 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 845 | { |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 846 | agp_bridge->gatt_table_real = NULL; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 847 | agp_bridge->gatt_table = NULL; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 848 | agp_bridge->gatt_bus_addr = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 849 | |
| 850 | return 0; |
| 851 | } |
| 852 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 853 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 854 | { |
| 855 | return 0; |
| 856 | } |
| 857 | |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 858 | static int intel_fake_agp_configure(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 859 | { |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 860 | if (!intel_enable_gtt()) |
| 861 | return -EIO; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 862 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 863 | intel_private.clear_fake_agp = true; |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 864 | agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 865 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 866 | return 0; |
| 867 | } |
| 868 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 869 | static bool i830_check_flags(unsigned int flags) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 870 | { |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 871 | switch (flags) { |
| 872 | case 0: |
| 873 | case AGP_PHYS_MEMORY: |
| 874 | case AGP_USER_CACHED_MEMORY: |
| 875 | case AGP_USER_MEMORY: |
| 876 | return true; |
| 877 | } |
| 878 | |
| 879 | return false; |
| 880 | } |
| 881 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 882 | void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, |
| 883 | unsigned int sg_len, |
| 884 | unsigned int pg_start, |
| 885 | unsigned int flags) |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 886 | { |
| 887 | struct scatterlist *sg; |
| 888 | unsigned int len, m; |
| 889 | int i, j; |
| 890 | |
| 891 | j = pg_start; |
| 892 | |
| 893 | /* sg may merge pages, but we have to separate |
| 894 | * per-page addr for GTT */ |
| 895 | for_each_sg(sg_list, sg, sg_len, i) { |
| 896 | len = sg_dma_len(sg) >> PAGE_SHIFT; |
| 897 | for (m = 0; m < len; m++) { |
| 898 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); |
| 899 | intel_private.driver->write_entry(addr, |
| 900 | j, flags); |
| 901 | j++; |
| 902 | } |
| 903 | } |
| 904 | readl(intel_private.gtt+j-1); |
| 905 | } |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 906 | EXPORT_SYMBOL(intel_gtt_insert_sg_entries); |
| 907 | |
| 908 | void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, |
| 909 | struct page **pages, unsigned int flags) |
| 910 | { |
| 911 | int i, j; |
| 912 | |
| 913 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { |
| 914 | dma_addr_t addr = page_to_phys(pages[i]); |
| 915 | intel_private.driver->write_entry(addr, |
| 916 | j, flags); |
| 917 | } |
| 918 | readl(intel_private.gtt+j-1); |
| 919 | } |
| 920 | EXPORT_SYMBOL(intel_gtt_insert_pages); |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 921 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 922 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
| 923 | off_t pg_start, int type) |
| 924 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 925 | int ret = -EINVAL; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 926 | |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 927 | if (intel_private.base.do_idle_maps) |
| 928 | return -ENODEV; |
| 929 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 930 | if (intel_private.clear_fake_agp) { |
| 931 | int start = intel_private.base.stolen_size / PAGE_SIZE; |
| 932 | int end = intel_private.base.gtt_mappable_entries; |
| 933 | intel_gtt_clear_range(start, end - start); |
| 934 | intel_private.clear_fake_agp = false; |
| 935 | } |
| 936 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 937 | if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) |
| 938 | return i810_insert_dcache_entries(mem, pg_start, type); |
| 939 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 940 | if (mem->page_count == 0) |
| 941 | goto out; |
| 942 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 943 | if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 944 | goto out_err; |
| 945 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 946 | if (type != mem->type) |
| 947 | goto out_err; |
| 948 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 949 | if (!intel_private.driver->check_flags(type)) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 950 | goto out_err; |
| 951 | |
| 952 | if (!mem->is_flushed) |
| 953 | global_cache_flush(); |
| 954 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 955 | if (intel_private.base.needs_dmar) { |
| 956 | ret = intel_gtt_map_memory(mem->pages, mem->page_count, |
| 957 | &mem->sg_list, &mem->num_sg); |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 958 | if (ret != 0) |
| 959 | return ret; |
| 960 | |
| 961 | intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, |
| 962 | pg_start, type); |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 963 | } else |
| 964 | intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, |
| 965 | type); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 966 | |
| 967 | out: |
| 968 | ret = 0; |
| 969 | out_err: |
| 970 | mem->is_flushed = true; |
| 971 | return ret; |
| 972 | } |
| 973 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 974 | void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 975 | { |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 976 | unsigned int i; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 977 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 978 | for (i = first_entry; i < (first_entry + num_entries); i++) { |
Daniel Vetter | 50a4c4a | 2012-02-09 17:15:44 +0100 | [diff] [blame] | 979 | intel_private.driver->write_entry(intel_private.base.scratch_page_dma, |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 980 | i, 0); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 981 | } |
Daniel Vetter | fdfb58a | 2010-08-29 00:15:03 +0200 | [diff] [blame] | 982 | readl(intel_private.gtt+i-1); |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 983 | } |
| 984 | EXPORT_SYMBOL(intel_gtt_clear_range); |
| 985 | |
| 986 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
| 987 | off_t pg_start, int type) |
| 988 | { |
| 989 | if (mem->page_count == 0) |
| 990 | return 0; |
| 991 | |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 992 | if (intel_private.base.do_idle_maps) |
| 993 | return -ENODEV; |
| 994 | |
Dave Airlie | d15eda5 | 2011-01-12 11:39:48 +1000 | [diff] [blame] | 995 | intel_gtt_clear_range(pg_start, mem->page_count); |
| 996 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 997 | if (intel_private.base.needs_dmar) { |
| 998 | intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); |
| 999 | mem->sg_list = NULL; |
| 1000 | mem->num_sg = 0; |
| 1001 | } |
| 1002 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1003 | return 0; |
| 1004 | } |
| 1005 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1006 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
| 1007 | int type) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1008 | { |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1009 | struct agp_memory *new; |
| 1010 | |
| 1011 | if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { |
| 1012 | if (pg_count != intel_private.num_dcache_entries) |
| 1013 | return NULL; |
| 1014 | |
| 1015 | new = agp_create_memory(1); |
| 1016 | if (new == NULL) |
| 1017 | return NULL; |
| 1018 | |
| 1019 | new->type = AGP_DCACHE_MEMORY; |
| 1020 | new->page_count = pg_count; |
| 1021 | new->num_scratch_pages = 0; |
| 1022 | agp_free_page_array(new); |
| 1023 | return new; |
| 1024 | } |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1025 | if (type == AGP_PHYS_MEMORY) |
| 1026 | return alloc_agpphysmem_i8xx(pg_count, type); |
| 1027 | /* always return NULL for other allocation types for now */ |
| 1028 | return NULL; |
| 1029 | } |
| 1030 | |
| 1031 | static int intel_alloc_chipset_flush_resource(void) |
| 1032 | { |
| 1033 | int ret; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1034 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1035 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1036 | pcibios_align_resource, intel_private.bridge_dev); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1037 | |
| 1038 | return ret; |
| 1039 | } |
| 1040 | |
| 1041 | static void intel_i915_setup_chipset_flush(void) |
| 1042 | { |
| 1043 | int ret; |
| 1044 | u32 temp; |
| 1045 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1046 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1047 | if (!(temp & 0x1)) { |
| 1048 | intel_alloc_chipset_flush_resource(); |
| 1049 | intel_private.resource_valid = 1; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1050 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1051 | } else { |
| 1052 | temp &= ~1; |
| 1053 | |
| 1054 | intel_private.resource_valid = 1; |
| 1055 | intel_private.ifp_resource.start = temp; |
| 1056 | intel_private.ifp_resource.end = temp + PAGE_SIZE; |
| 1057 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); |
| 1058 | /* some BIOSes reserve this area in a pnp some don't */ |
| 1059 | if (ret) |
| 1060 | intel_private.resource_valid = 0; |
| 1061 | } |
| 1062 | } |
| 1063 | |
| 1064 | static void intel_i965_g33_setup_chipset_flush(void) |
| 1065 | { |
| 1066 | u32 temp_hi, temp_lo; |
| 1067 | int ret; |
| 1068 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1069 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
| 1070 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1071 | |
| 1072 | if (!(temp_lo & 0x1)) { |
| 1073 | |
| 1074 | intel_alloc_chipset_flush_resource(); |
| 1075 | |
| 1076 | intel_private.resource_valid = 1; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1077 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1078 | upper_32_bits(intel_private.ifp_resource.start)); |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1079 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1080 | } else { |
| 1081 | u64 l64; |
| 1082 | |
| 1083 | temp_lo &= ~0x1; |
| 1084 | l64 = ((u64)temp_hi << 32) | temp_lo; |
| 1085 | |
| 1086 | intel_private.resource_valid = 1; |
| 1087 | intel_private.ifp_resource.start = l64; |
| 1088 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; |
| 1089 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); |
| 1090 | /* some BIOSes reserve this area in a pnp some don't */ |
| 1091 | if (ret) |
| 1092 | intel_private.resource_valid = 0; |
| 1093 | } |
| 1094 | } |
| 1095 | |
| 1096 | static void intel_i9xx_setup_flush(void) |
| 1097 | { |
| 1098 | /* return if already configured */ |
| 1099 | if (intel_private.ifp_resource.start) |
| 1100 | return; |
| 1101 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1102 | if (INTEL_GTT_GEN == 6) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1103 | return; |
| 1104 | |
| 1105 | /* setup a resource for this object */ |
| 1106 | intel_private.ifp_resource.name = "Intel Flush Page"; |
| 1107 | intel_private.ifp_resource.flags = IORESOURCE_MEM; |
| 1108 | |
| 1109 | /* Setup chipset flush for 915 */ |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1110 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1111 | intel_i965_g33_setup_chipset_flush(); |
| 1112 | } else { |
| 1113 | intel_i915_setup_chipset_flush(); |
| 1114 | } |
| 1115 | |
Chris Wilson | df51e7a | 2010-09-04 14:57:27 +0100 | [diff] [blame] | 1116 | if (intel_private.ifp_resource.start) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1117 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
Chris Wilson | df51e7a | 2010-09-04 14:57:27 +0100 | [diff] [blame] | 1118 | if (!intel_private.i9xx_flush_page) |
| 1119 | dev_err(&intel_private.pcidev->dev, |
| 1120 | "can't ioremap flush page - no chipset flushing\n"); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1121 | } |
| 1122 | |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1123 | static void i9xx_cleanup(void) |
| 1124 | { |
| 1125 | if (intel_private.i9xx_flush_page) |
| 1126 | iounmap(intel_private.i9xx_flush_page); |
| 1127 | if (intel_private.resource_valid) |
| 1128 | release_resource(&intel_private.ifp_resource); |
| 1129 | intel_private.ifp_resource.start = 0; |
| 1130 | intel_private.resource_valid = 0; |
| 1131 | } |
| 1132 | |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1133 | static void i9xx_chipset_flush(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1134 | { |
| 1135 | if (intel_private.i9xx_flush_page) |
| 1136 | writel(1, intel_private.i9xx_flush_page); |
| 1137 | } |
| 1138 | |
Chris Wilson | 71f4566 | 2010-12-14 11:29:23 +0000 | [diff] [blame] | 1139 | static void i965_write_entry(dma_addr_t addr, |
| 1140 | unsigned int entry, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1141 | unsigned int flags) |
| 1142 | { |
Chris Wilson | 71f4566 | 2010-12-14 11:29:23 +0000 | [diff] [blame] | 1143 | u32 pte_flags; |
| 1144 | |
| 1145 | pte_flags = I810_PTE_VALID; |
| 1146 | if (flags == AGP_USER_CACHED_MEMORY) |
| 1147 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
| 1148 | |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1149 | /* Shift high bits down */ |
| 1150 | addr |= (addr >> 28) & 0xf0; |
Chris Wilson | 71f4566 | 2010-12-14 11:29:23 +0000 | [diff] [blame] | 1151 | writel(addr | pte_flags, intel_private.gtt + entry); |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1152 | } |
| 1153 | |
Daniel Vetter | 90cb149 | 2010-09-11 23:55:20 +0200 | [diff] [blame] | 1154 | static bool gen6_check_flags(unsigned int flags) |
| 1155 | { |
| 1156 | return true; |
| 1157 | } |
| 1158 | |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1159 | static void gen6_write_entry(dma_addr_t addr, unsigned int entry, |
| 1160 | unsigned int flags) |
| 1161 | { |
| 1162 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; |
| 1163 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; |
| 1164 | u32 pte_flags; |
| 1165 | |
Zhenyu Wang | 897ef19 | 2010-11-02 17:30:47 +0800 | [diff] [blame] | 1166 | if (type_mask == AGP_USER_MEMORY) |
Chris Wilson | 85ccc35 | 2010-10-22 14:59:29 +0100 | [diff] [blame] | 1167 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1168 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
Zhenyu Wang | d110852 | 2010-11-02 17:30:46 +0800 | [diff] [blame] | 1169 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1170 | if (gfdt) |
| 1171 | pte_flags |= GEN6_PTE_GFDT; |
| 1172 | } else { /* set 'normal'/'cached' to LLC by default */ |
Zhenyu Wang | d110852 | 2010-11-02 17:30:46 +0800 | [diff] [blame] | 1173 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1174 | if (gfdt) |
| 1175 | pte_flags |= GEN6_PTE_GFDT; |
| 1176 | } |
| 1177 | |
| 1178 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
| 1179 | addr |= (addr >> 28) & 0xff0; |
| 1180 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 1181 | } |
| 1182 | |
Jesse Barnes | 6475787 | 2012-03-28 13:39:34 -0700 | [diff] [blame] | 1183 | static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, |
| 1184 | unsigned int flags) |
| 1185 | { |
| 1186 | u32 pte_flags; |
| 1187 | |
| 1188 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
| 1189 | |
| 1190 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
| 1191 | addr |= (addr >> 28) & 0xff0; |
| 1192 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 1193 | |
| 1194 | writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV); |
| 1195 | } |
| 1196 | |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1197 | static void gen6_cleanup(void) |
| 1198 | { |
| 1199 | } |
| 1200 | |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1201 | /* Certain Gen5 chipsets require require idling the GPU before |
| 1202 | * unmapping anything from the GTT when VT-d is enabled. |
| 1203 | */ |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1204 | static inline int needs_idle_maps(void) |
| 1205 | { |
Keith Packard | a08185a | 2011-10-28 10:28:00 -0700 | [diff] [blame] | 1206 | #ifdef CONFIG_INTEL_IOMMU |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1207 | const unsigned short gpu_devid = intel_private.pcidev->device; |
| 1208 | |
| 1209 | /* Query intel_iommu to see if we need the workaround. Presumably that |
| 1210 | * was loaded first. |
| 1211 | */ |
| 1212 | if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || |
| 1213 | gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && |
| 1214 | intel_iommu_gfx_mapped) |
| 1215 | return 1; |
Keith Packard | a08185a | 2011-10-28 10:28:00 -0700 | [diff] [blame] | 1216 | #endif |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1217 | return 0; |
| 1218 | } |
| 1219 | |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1220 | static int i9xx_setup(void) |
| 1221 | { |
| 1222 | u32 reg_addr; |
Jesse Barnes | 4b60d29 | 2012-03-28 13:39:33 -0700 | [diff] [blame] | 1223 | int size = KB(512); |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1224 | |
| 1225 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
| 1226 | |
| 1227 | reg_addr &= 0xfff80000; |
| 1228 | |
Jesse Barnes | 4b60d29 | 2012-03-28 13:39:33 -0700 | [diff] [blame] | 1229 | if (INTEL_GTT_GEN >= 7) |
| 1230 | size = MB(2); |
| 1231 | |
| 1232 | intel_private.registers = ioremap(reg_addr, size); |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1233 | if (!intel_private.registers) |
| 1234 | return -ENOMEM; |
| 1235 | |
| 1236 | if (INTEL_GTT_GEN == 3) { |
| 1237 | u32 gtt_addr; |
Chris Wilson | 3f08e4e | 2010-09-14 20:15:22 +0100 | [diff] [blame] | 1238 | |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1239 | pci_read_config_dword(intel_private.pcidev, |
| 1240 | I915_PTEADDR, >t_addr); |
| 1241 | intel_private.gtt_bus_addr = gtt_addr; |
| 1242 | } else { |
| 1243 | u32 gtt_offset; |
| 1244 | |
| 1245 | switch (INTEL_GTT_GEN) { |
| 1246 | case 5: |
| 1247 | case 6: |
| 1248 | gtt_offset = MB(2); |
| 1249 | break; |
| 1250 | case 4: |
| 1251 | default: |
| 1252 | gtt_offset = KB(512); |
| 1253 | break; |
| 1254 | } |
| 1255 | intel_private.gtt_bus_addr = reg_addr + gtt_offset; |
| 1256 | } |
| 1257 | |
Dan Carpenter | 35b09c9 | 2011-10-28 14:42:41 +0300 | [diff] [blame] | 1258 | if (needs_idle_maps()) |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1259 | intel_private.base.do_idle_maps = 1; |
| 1260 | |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1261 | intel_i9xx_setup_flush(); |
| 1262 | |
| 1263 | return 0; |
| 1264 | } |
| 1265 | |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1266 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1267 | .owner = THIS_MODULE, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1268 | .size_type = FIXED_APER_SIZE, |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 1269 | .aperture_sizes = intel_fake_agp_sizes, |
| 1270 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1271 | .configure = intel_fake_agp_configure, |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 1272 | .fetch_size = intel_fake_agp_fetch_size, |
Daniel Vetter | fdfb58a | 2010-08-29 00:15:03 +0200 | [diff] [blame] | 1273 | .cleanup = intel_gtt_cleanup, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1274 | .agp_enable = intel_fake_agp_enable, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1275 | .cache_flush = global_cache_flush, |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 1276 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1277 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1278 | .insert_memory = intel_fake_agp_insert_entries, |
| 1279 | .remove_memory = intel_fake_agp_remove_entries, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1280 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1281 | .free_by_type = intel_i810_free_by_type, |
| 1282 | .agp_alloc_page = agp_generic_alloc_page, |
| 1283 | .agp_alloc_pages = agp_generic_alloc_pages, |
| 1284 | .agp_destroy_page = agp_generic_destroy_page, |
| 1285 | .agp_destroy_pages = agp_generic_destroy_pages, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1286 | }; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1287 | |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1288 | static const struct intel_gtt_driver i81x_gtt_driver = { |
| 1289 | .gen = 1, |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 1290 | .has_pgtbl_enable = 1, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1291 | .dma_mask_size = 32, |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 1292 | .setup = i810_setup, |
| 1293 | .cleanup = i810_cleanup, |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1294 | .check_flags = i830_check_flags, |
| 1295 | .write_entry = i810_write_entry, |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1296 | }; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1297 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
| 1298 | .gen = 2, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1299 | .has_pgtbl_enable = 1, |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 1300 | .setup = i830_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1301 | .cleanup = i830_cleanup, |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 1302 | .write_entry = i830_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1303 | .dma_mask_size = 32, |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 1304 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1305 | .chipset_flush = i830_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1306 | }; |
| 1307 | static const struct intel_gtt_driver i915_gtt_driver = { |
| 1308 | .gen = 3, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1309 | .has_pgtbl_enable = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1310 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1311 | .cleanup = i9xx_cleanup, |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 1312 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1313 | .write_entry = i830_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1314 | .dma_mask_size = 32, |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 1315 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1316 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1317 | }; |
| 1318 | static const struct intel_gtt_driver g33_gtt_driver = { |
| 1319 | .gen = 3, |
| 1320 | .is_g33 = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1321 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1322 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1323 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1324 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1325 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1326 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1327 | }; |
| 1328 | static const struct intel_gtt_driver pineview_gtt_driver = { |
| 1329 | .gen = 3, |
| 1330 | .is_pineview = 1, .is_g33 = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1331 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1332 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1333 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1334 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1335 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1336 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1337 | }; |
| 1338 | static const struct intel_gtt_driver i965_gtt_driver = { |
| 1339 | .gen = 4, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1340 | .has_pgtbl_enable = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1341 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1342 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1343 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1344 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1345 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1346 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1347 | }; |
| 1348 | static const struct intel_gtt_driver g4x_gtt_driver = { |
| 1349 | .gen = 5, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1350 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1351 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1352 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1353 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1354 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1355 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1356 | }; |
| 1357 | static const struct intel_gtt_driver ironlake_gtt_driver = { |
| 1358 | .gen = 5, |
| 1359 | .is_ironlake = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1360 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1361 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1362 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1363 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1364 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1365 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1366 | }; |
| 1367 | static const struct intel_gtt_driver sandybridge_gtt_driver = { |
| 1368 | .gen = 6, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1369 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1370 | .cleanup = gen6_cleanup, |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1371 | .write_entry = gen6_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1372 | .dma_mask_size = 40, |
Daniel Vetter | 90cb149 | 2010-09-11 23:55:20 +0200 | [diff] [blame] | 1373 | .check_flags = gen6_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1374 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1375 | }; |
Jesse Barnes | 6475787 | 2012-03-28 13:39:34 -0700 | [diff] [blame] | 1376 | static const struct intel_gtt_driver valleyview_gtt_driver = { |
| 1377 | .gen = 7, |
| 1378 | .setup = i9xx_setup, |
| 1379 | .cleanup = gen6_cleanup, |
| 1380 | .write_entry = valleyview_write_entry, |
| 1381 | .dma_mask_size = 40, |
| 1382 | .check_flags = gen6_check_flags, |
| 1383 | .chipset_flush = i9xx_chipset_flush, |
| 1384 | }; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1385 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1386 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
| 1387 | * driver and gmch_driver must be non-null, and find_gmch will determine |
| 1388 | * which one should be used if a gmch_chip_id is present. |
| 1389 | */ |
| 1390 | static const struct intel_gtt_driver_description { |
| 1391 | unsigned int gmch_chip_id; |
| 1392 | char *name; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1393 | const struct intel_gtt_driver *gtt_driver; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1394 | } intel_gtt_chipsets[] = { |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1395 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1396 | &i81x_gtt_driver}, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1397 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1398 | &i81x_gtt_driver}, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1399 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1400 | &i81x_gtt_driver}, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1401 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1402 | &i81x_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1403 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1404 | &i8xx_gtt_driver}, |
Oswald Buddenhagen | 53371ed | 2010-06-19 23:08:37 +0200 | [diff] [blame] | 1405 | { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1406 | &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1407 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1408 | &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1409 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1410 | &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1411 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1412 | &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1413 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1414 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1415 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1416 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1417 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1418 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1419 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1420 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1421 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1422 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1423 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1424 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1425 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1426 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1427 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1428 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1429 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1430 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1431 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1432 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1433 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1434 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1435 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1436 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1437 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1438 | &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1439 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1440 | &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1441 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1442 | &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1443 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1444 | &pineview_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1445 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1446 | &pineview_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1447 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1448 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1449 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1450 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1451 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1452 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1453 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1454 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1455 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1456 | &g4x_gtt_driver }, |
Chris Wilson | e9e5f8e | 2010-09-21 11:19:32 +0100 | [diff] [blame] | 1457 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1458 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1459 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1460 | &g4x_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1461 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1462 | "HD Graphics", &ironlake_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1463 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1464 | "HD Graphics", &ironlake_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1465 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1466 | "Sandybridge", &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1467 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1468 | "Sandybridge", &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1469 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1470 | "Sandybridge", &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1471 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1472 | "Sandybridge", &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1473 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1474 | "Sandybridge", &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1475 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1476 | "Sandybridge", &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1477 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1478 | "Sandybridge", &sandybridge_gtt_driver }, |
Jesse Barnes | 246d08b | 2011-02-17 11:50:19 -0800 | [diff] [blame] | 1479 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG, |
| 1480 | "Ivybridge", &sandybridge_gtt_driver }, |
| 1481 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG, |
| 1482 | "Ivybridge", &sandybridge_gtt_driver }, |
| 1483 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG, |
| 1484 | "Ivybridge", &sandybridge_gtt_driver }, |
| 1485 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG, |
| 1486 | "Ivybridge", &sandybridge_gtt_driver }, |
| 1487 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, |
| 1488 | "Ivybridge", &sandybridge_gtt_driver }, |
Eugeni Dodonov | cc22a93 | 2012-03-29 20:55:48 -0300 | [diff] [blame] | 1489 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG, |
| 1490 | "Ivybridge", &sandybridge_gtt_driver }, |
Jesse Barnes | 6475787 | 2012-03-28 13:39:34 -0700 | [diff] [blame] | 1491 | { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG, |
| 1492 | "ValleyView", &valleyview_gtt_driver }, |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 1493 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG, |
| 1494 | "Haswell", &sandybridge_gtt_driver }, |
| 1495 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG, |
| 1496 | "Haswell", &sandybridge_gtt_driver }, |
| 1497 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG, |
| 1498 | "Haswell", &sandybridge_gtt_driver }, |
| 1499 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG, |
| 1500 | "Haswell", &sandybridge_gtt_driver }, |
| 1501 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG, |
| 1502 | "Haswell", &sandybridge_gtt_driver }, |
| 1503 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG, |
| 1504 | "Haswell", &sandybridge_gtt_driver }, |
| 1505 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV, |
| 1506 | "Haswell", &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1507 | { 0, NULL, NULL } |
| 1508 | }; |
| 1509 | |
| 1510 | static int find_gmch(u16 device) |
| 1511 | { |
| 1512 | struct pci_dev *gmch_device; |
| 1513 | |
| 1514 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
| 1515 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { |
| 1516 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1517 | device, gmch_device); |
| 1518 | } |
| 1519 | |
| 1520 | if (!gmch_device) |
| 1521 | return 0; |
| 1522 | |
| 1523 | intel_private.pcidev = gmch_device; |
| 1524 | return 1; |
| 1525 | } |
| 1526 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1527 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
| 1528 | struct agp_bridge_data *bridge) |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1529 | { |
| 1530 | int i, mask; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1531 | |
| 1532 | /* |
| 1533 | * Can be called from the fake agp driver but also directly from |
| 1534 | * drm/i915.ko. Hence we need to check whether everything is set up |
| 1535 | * already. |
| 1536 | */ |
| 1537 | if (intel_private.driver) { |
| 1538 | intel_private.refcount++; |
| 1539 | return 1; |
| 1540 | } |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1541 | |
| 1542 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1543 | if (gpu_pdev) { |
| 1544 | if (gpu_pdev->device == |
| 1545 | intel_gtt_chipsets[i].gmch_chip_id) { |
| 1546 | intel_private.pcidev = pci_dev_get(gpu_pdev); |
| 1547 | intel_private.driver = |
| 1548 | intel_gtt_chipsets[i].gtt_driver; |
| 1549 | |
| 1550 | break; |
| 1551 | } |
| 1552 | } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1553 | intel_private.driver = |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1554 | intel_gtt_chipsets[i].gtt_driver; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1555 | break; |
| 1556 | } |
| 1557 | } |
| 1558 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1559 | if (!intel_private.driver) |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1560 | return 0; |
| 1561 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1562 | intel_private.refcount++; |
| 1563 | |
Daniel Vetter | 7e8f630 | 2012-06-07 15:55:58 +0200 | [diff] [blame] | 1564 | if (bridge) { |
| 1565 | bridge->driver = &intel_fake_agp_driver; |
| 1566 | bridge->dev_private_data = &intel_private; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1567 | bridge->dev = bridge_pdev; |
Daniel Vetter | 7e8f630 | 2012-06-07 15:55:58 +0200 | [diff] [blame] | 1568 | } |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1569 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1570 | intel_private.bridge_dev = pci_dev_get(bridge_pdev); |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1571 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1572 | dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1573 | |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1574 | mask = intel_private.driver->dma_mask_size; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1575 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
| 1576 | dev_err(&intel_private.pcidev->dev, |
| 1577 | "set gfx device dma mask %d-bit failed!\n", mask); |
| 1578 | else |
| 1579 | pci_set_consistent_dma_mask(intel_private.pcidev, |
| 1580 | DMA_BIT_MASK(mask)); |
| 1581 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1582 | if (intel_gtt_init() != 0) { |
| 1583 | intel_gmch_remove(); |
| 1584 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 1585 | return 0; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1586 | } |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 1587 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1588 | return 1; |
| 1589 | } |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 1590 | EXPORT_SYMBOL(intel_gmch_probe); |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1591 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 1592 | const struct intel_gtt *intel_gtt_get(void) |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 1593 | { |
| 1594 | return &intel_private.base; |
| 1595 | } |
| 1596 | EXPORT_SYMBOL(intel_gtt_get); |
| 1597 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 1598 | void intel_gtt_chipset_flush(void) |
| 1599 | { |
| 1600 | if (intel_private.driver->chipset_flush) |
| 1601 | intel_private.driver->chipset_flush(); |
| 1602 | } |
| 1603 | EXPORT_SYMBOL(intel_gtt_chipset_flush); |
| 1604 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1605 | void intel_gmch_remove(void) |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1606 | { |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1607 | if (--intel_private.refcount) |
| 1608 | return; |
| 1609 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1610 | if (intel_private.pcidev) |
| 1611 | pci_dev_put(intel_private.pcidev); |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1612 | if (intel_private.bridge_dev) |
| 1613 | pci_dev_put(intel_private.bridge_dev); |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1614 | intel_private.driver = NULL; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1615 | } |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 1616 | EXPORT_SYMBOL(intel_gmch_remove); |
| 1617 | |
| 1618 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); |
| 1619 | MODULE_LICENSE("GPL and additional rights"); |