Christoffer Dall | 64a959d | 2015-11-24 16:51:12 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015, 2016 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __KVM_ARM_VGIC_NEW_H__ |
| 17 | #define __KVM_ARM_VGIC_NEW_H__ |
| 18 | |
Eric Auger | 9097773 | 2015-12-01 15:02:35 +0100 | [diff] [blame] | 19 | #include <linux/irqchip/arm-gic-common.h> |
| 20 | |
Marc Zyngier | 2b0cda8 | 2016-04-26 11:06:47 +0100 | [diff] [blame] | 21 | #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ |
| 22 | #define IMPLEMENTER_ARM 0x43b |
| 23 | |
Eric Auger | e2c1f9a | 2015-12-21 16:36:04 +0100 | [diff] [blame] | 24 | #define VGIC_ADDR_UNDEF (-1) |
| 25 | #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) |
| 26 | |
Andre Przywara | fd59ed3 | 2016-01-27 14:54:30 +0000 | [diff] [blame] | 27 | #define INTERRUPT_ID_BITS_SPIS 10 |
Andre Przywara | 33d3bc9 | 2016-07-15 12:43:34 +0100 | [diff] [blame] | 28 | #define INTERRUPT_ID_BITS_ITS 16 |
Andre Przywara | 055658b | 2015-12-01 14:34:02 +0000 | [diff] [blame] | 29 | #define VGIC_PRI_BITS 5 |
| 30 | |
Marc Zyngier | 0919e84 | 2015-11-26 17:19:25 +0000 | [diff] [blame] | 31 | #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) |
| 32 | |
Vijaya Kumar K | 94574c9 | 2017-01-26 19:50:47 +0530 | [diff] [blame] | 33 | #define VGIC_AFFINITY_0_SHIFT 0 |
| 34 | #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT) |
| 35 | #define VGIC_AFFINITY_1_SHIFT 8 |
| 36 | #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT) |
| 37 | #define VGIC_AFFINITY_2_SHIFT 16 |
| 38 | #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT) |
| 39 | #define VGIC_AFFINITY_3_SHIFT 24 |
| 40 | #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT) |
| 41 | |
| 42 | #define VGIC_AFFINITY_LEVEL(reg, level) \ |
| 43 | ((((reg) & VGIC_AFFINITY_## level ##_MASK) \ |
| 44 | >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) |
| 45 | |
| 46 | /* |
| 47 | * The Userspace encodes the affinity differently from the MPIDR, |
| 48 | * Below macro converts vgic userspace format to MPIDR reg format. |
| 49 | */ |
| 50 | #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \ |
| 51 | VGIC_AFFINITY_LEVEL(val, 1) | \ |
| 52 | VGIC_AFFINITY_LEVEL(val, 2) | \ |
| 53 | VGIC_AFFINITY_LEVEL(val, 3)) |
| 54 | |
Vijaya Kumar K | d017d7b | 2017-01-26 19:50:51 +0530 | [diff] [blame] | 55 | /* |
| 56 | * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt, |
| 57 | * below macros are defined for CPUREG encoding. |
| 58 | */ |
| 59 | #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000 |
| 60 | #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14 |
| 61 | #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800 |
| 62 | #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11 |
| 63 | #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780 |
| 64 | #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7 |
| 65 | #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078 |
| 66 | #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3 |
| 67 | #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007 |
| 68 | #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0 |
| 69 | |
| 70 | #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \ |
| 71 | KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \ |
| 72 | KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \ |
| 73 | KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \ |
| 74 | KVM_REG_ARM_VGIC_SYSREG_OP2_MASK) |
| 75 | |
Eric Auger | ea1ad53 | 2017-01-09 16:19:41 +0100 | [diff] [blame] | 76 | /* |
| 77 | * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt, |
| 78 | * below macros are defined for ITS table entry encoding. |
| 79 | */ |
| 80 | #define KVM_ITS_CTE_VALID_SHIFT 63 |
| 81 | #define KVM_ITS_CTE_VALID_MASK BIT_ULL(63) |
| 82 | #define KVM_ITS_CTE_RDBASE_SHIFT 16 |
| 83 | #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0) |
Eric Auger | eff484e | 2017-05-03 17:38:01 +0200 | [diff] [blame] | 84 | #define KVM_ITS_ITE_NEXT_SHIFT 48 |
| 85 | #define KVM_ITS_ITE_PINTID_SHIFT 16 |
| 86 | #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16) |
| 87 | #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0) |
Eric Auger | 57a9a11 | 2017-01-09 16:27:07 +0100 | [diff] [blame] | 88 | #define KVM_ITS_DTE_VALID_SHIFT 63 |
| 89 | #define KVM_ITS_DTE_VALID_MASK BIT_ULL(63) |
| 90 | #define KVM_ITS_DTE_NEXT_SHIFT 49 |
| 91 | #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49) |
| 92 | #define KVM_ITS_DTE_ITTADDR_SHIFT 5 |
| 93 | #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5) |
| 94 | #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0) |
| 95 | #define KVM_ITS_L1E_VALID_MASK BIT_ULL(63) |
| 96 | /* we only support 64 kB translation table page size */ |
| 97 | #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16) |
Eric Auger | ea1ad53 | 2017-01-09 16:19:41 +0100 | [diff] [blame] | 98 | |
Eric Auger | 04c1109 | 2018-05-22 09:55:17 +0200 | [diff] [blame] | 99 | #define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0) |
| 100 | #define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12) |
| 101 | #define KVM_VGIC_V3_RDIST_FLAGS_SHIFT 12 |
| 102 | #define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16) |
| 103 | #define KVM_VGIC_V3_RDIST_COUNT_MASK GENMASK_ULL(63, 52) |
| 104 | #define KVM_VGIC_V3_RDIST_COUNT_SHIFT 52 |
| 105 | |
Andre Przywara | 62b06f8 | 2018-03-06 09:21:06 +0000 | [diff] [blame] | 106 | /* Requires the irq_lock to be held by the caller. */ |
Christoffer Dall | 8694e4d | 2017-01-23 14:07:18 +0100 | [diff] [blame] | 107 | static inline bool irq_is_pending(struct vgic_irq *irq) |
| 108 | { |
| 109 | if (irq->config == VGIC_CONFIG_EDGE) |
| 110 | return irq->pending_latch; |
| 111 | else |
| 112 | return irq->pending_latch || irq->line_level; |
| 113 | } |
| 114 | |
Christoffer Dall | e40cc57 | 2017-08-29 10:40:44 +0200 | [diff] [blame] | 115 | static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq) |
| 116 | { |
| 117 | return irq->config == VGIC_CONFIG_LEVEL && irq->hw; |
| 118 | } |
| 119 | |
Marc Zyngier | 5369290 | 2018-04-18 10:39:04 +0100 | [diff] [blame] | 120 | static inline int vgic_irq_get_lr_count(struct vgic_irq *irq) |
| 121 | { |
| 122 | /* Account for the active state as an interrupt */ |
| 123 | if (vgic_irq_is_sgi(irq->intid) && irq->source) |
| 124 | return hweight8(irq->source) + irq->active; |
| 125 | |
| 126 | return irq_is_pending(irq) || irq->active; |
| 127 | } |
| 128 | |
| 129 | static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq) |
| 130 | { |
| 131 | return vgic_irq_get_lr_count(irq) > 1; |
| 132 | } |
| 133 | |
Christoffer Dall | 6d56111 | 2017-03-21 22:05:22 +0100 | [diff] [blame] | 134 | /* |
| 135 | * This struct provides an intermediate representation of the fields contained |
| 136 | * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC |
| 137 | * state to userspace can generate either GICv2 or GICv3 CPU interface |
| 138 | * registers regardless of the hardware backed GIC used. |
| 139 | */ |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 140 | struct vgic_vmcr { |
Christoffer Dall | 28232a4 | 2017-05-20 14:12:34 +0200 | [diff] [blame] | 141 | u32 grpen0; |
| 142 | u32 grpen1; |
| 143 | |
| 144 | u32 ackctl; |
| 145 | u32 fiqen; |
| 146 | u32 cbpr; |
| 147 | u32 eoim; |
| 148 | |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 149 | u32 abpr; |
| 150 | u32 bpr; |
Christoffer Dall | 6d56111 | 2017-03-21 22:05:22 +0100 | [diff] [blame] | 151 | u32 pmr; /* Priority mask field in the GICC_PMR and |
| 152 | * ICC_PMR_EL1 priority field format */ |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 153 | }; |
| 154 | |
Vijaya Kumar K | 94574c9 | 2017-01-26 19:50:47 +0530 | [diff] [blame] | 155 | struct vgic_reg_attr { |
| 156 | struct kvm_vcpu *vcpu; |
| 157 | gpa_t addr; |
| 158 | }; |
| 159 | |
| 160 | int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr, |
| 161 | struct vgic_reg_attr *reg_attr); |
| 162 | int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr, |
| 163 | struct vgic_reg_attr *reg_attr); |
| 164 | const struct vgic_register_region * |
| 165 | vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev, |
| 166 | gpa_t addr, int len); |
Christoffer Dall | 64a959d | 2015-11-24 16:51:12 +0100 | [diff] [blame] | 167 | struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu, |
| 168 | u32 intid); |
Andre Przywara | 5dd4b92 | 2016-07-15 12:43:27 +0100 | [diff] [blame] | 169 | void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq); |
Christoffer Dall | e40cc57 | 2017-08-29 10:40:44 +0200 | [diff] [blame] | 170 | bool vgic_get_phys_line_level(struct vgic_irq *irq); |
Christoffer Dall | df635c5 | 2017-09-01 16:25:12 +0200 | [diff] [blame] | 171 | void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending); |
Christoffer Dall | e40cc57 | 2017-08-29 10:40:44 +0200 | [diff] [blame] | 172 | void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active); |
Christoffer Dall | 006df0f | 2016-10-16 22:19:11 +0200 | [diff] [blame] | 173 | bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq, |
| 174 | unsigned long flags); |
Marc Zyngier | 2b0cda8 | 2016-04-26 11:06:47 +0100 | [diff] [blame] | 175 | void vgic_kick_vcpus(struct kvm *kvm); |
Christoffer Dall | 64a959d | 2015-11-24 16:51:12 +0100 | [diff] [blame] | 176 | |
Andre Przywara | 1085fdc | 2016-07-15 12:43:31 +0100 | [diff] [blame] | 177 | int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr, |
| 178 | phys_addr_t addr, phys_addr_t alignment); |
| 179 | |
Marc Zyngier | 140b086 | 2015-11-26 17:19:25 +0000 | [diff] [blame] | 180 | void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu); |
| 181 | void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); |
| 182 | void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr); |
| 183 | void vgic_v2_set_underflow(struct kvm_vcpu *vcpu); |
Marc Zyngier | 16ca6a6 | 2018-03-06 21:48:01 +0000 | [diff] [blame] | 184 | void vgic_v2_set_npie(struct kvm_vcpu *vcpu); |
Eric Auger | f94591e | 2015-12-21 17:34:52 +0100 | [diff] [blame] | 185 | int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr); |
Christoffer Dall | c3199f2 | 2016-04-25 01:11:37 +0200 | [diff] [blame] | 186 | int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 187 | int offset, u32 *val); |
Andre Przywara | 878c569 | 2015-12-03 11:48:42 +0000 | [diff] [blame] | 188 | int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 189 | int offset, u32 *val); |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 190 | void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
| 191 | void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
Eric Auger | ad275b8b | 2015-12-21 18:09:38 +0100 | [diff] [blame] | 192 | void vgic_v2_enable(struct kvm_vcpu *vcpu); |
Eric Auger | 9097773 | 2015-12-01 15:02:35 +0100 | [diff] [blame] | 193 | int vgic_v2_probe(const struct gic_kvm_info *info); |
Eric Auger | b0442ee | 2015-12-21 15:04:42 +0100 | [diff] [blame] | 194 | int vgic_v2_map_resources(struct kvm *kvm); |
Andre Przywara | fb848db | 2016-04-26 21:32:49 +0100 | [diff] [blame] | 195 | int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address, |
| 196 | enum vgic_type); |
Marc Zyngier | 140b086 | 2015-11-26 17:19:25 +0000 | [diff] [blame] | 197 | |
Christoffer Dall | 5b0d2cc | 2017-03-18 13:56:56 +0100 | [diff] [blame] | 198 | void vgic_v2_init_lrs(void); |
Christoffer Dall | 328e566 | 2016-03-24 11:21:04 +0100 | [diff] [blame] | 199 | void vgic_v2_load(struct kvm_vcpu *vcpu); |
| 200 | void vgic_v2_put(struct kvm_vcpu *vcpu); |
Christoffer Dall | 5b0d2cc | 2017-03-18 13:56:56 +0100 | [diff] [blame] | 201 | |
Christoffer Dall | 75174ba | 2016-12-22 20:39:10 +0100 | [diff] [blame] | 202 | void vgic_v2_save_state(struct kvm_vcpu *vcpu); |
| 203 | void vgic_v2_restore_state(struct kvm_vcpu *vcpu); |
| 204 | |
Marc Zyngier | d97594e | 2016-07-17 11:27:23 +0100 | [diff] [blame] | 205 | static inline void vgic_get_irq_kref(struct vgic_irq *irq) |
| 206 | { |
| 207 | if (irq->intid < VGIC_MIN_LPI) |
| 208 | return; |
| 209 | |
| 210 | kref_get(&irq->refcount); |
| 211 | } |
| 212 | |
Marc Zyngier | 59529f6 | 2015-11-30 13:09:53 +0000 | [diff] [blame] | 213 | void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu); |
| 214 | void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); |
| 215 | void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr); |
| 216 | void vgic_v3_set_underflow(struct kvm_vcpu *vcpu); |
Marc Zyngier | 16ca6a6 | 2018-03-06 21:48:01 +0000 | [diff] [blame] | 217 | void vgic_v3_set_npie(struct kvm_vcpu *vcpu); |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 218 | void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
| 219 | void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
Eric Auger | ad275b8b | 2015-12-21 18:09:38 +0100 | [diff] [blame] | 220 | void vgic_v3_enable(struct kvm_vcpu *vcpu); |
Eric Auger | 9097773 | 2015-12-01 15:02:35 +0100 | [diff] [blame] | 221 | int vgic_v3_probe(const struct gic_kvm_info *info); |
Eric Auger | b0442ee | 2015-12-21 15:04:42 +0100 | [diff] [blame] | 222 | int vgic_v3_map_resources(struct kvm *kvm); |
Eric Auger | 44de9d6 | 2017-05-04 11:19:52 +0200 | [diff] [blame] | 223 | int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq); |
Eric Auger | 2807712 | 2017-01-09 16:28:27 +0100 | [diff] [blame] | 224 | int vgic_v3_save_pending_tables(struct kvm *kvm); |
Eric Auger | 04c1109 | 2018-05-22 09:55:17 +0200 | [diff] [blame] | 225 | int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count); |
Christoffer Dall | 1aab6f4 | 2017-05-08 12:30:24 +0200 | [diff] [blame] | 226 | int vgic_register_redist_iodev(struct kvm_vcpu *vcpu); |
Christoffer Dall | 9a746d7 | 2017-05-08 12:23:51 +0200 | [diff] [blame] | 227 | bool vgic_v3_check_base(struct kvm *kvm); |
Vladimir Murzin | 7a1ff70 | 2016-09-12 15:49:18 +0100 | [diff] [blame] | 228 | |
Christoffer Dall | 328e566 | 2016-03-24 11:21:04 +0100 | [diff] [blame] | 229 | void vgic_v3_load(struct kvm_vcpu *vcpu); |
| 230 | void vgic_v3_put(struct kvm_vcpu *vcpu); |
| 231 | |
Andre Przywara | 59c5ab4 | 2016-07-15 12:43:30 +0100 | [diff] [blame] | 232 | bool vgic_has_its(struct kvm *kvm); |
Andre Przywara | 0e4e82f | 2016-07-15 12:43:38 +0100 | [diff] [blame] | 233 | int kvm_vgic_register_its_device(void); |
Andre Przywara | 33d3bc9 | 2016-07-15 12:43:34 +0100 | [diff] [blame] | 234 | void vgic_enable_lpis(struct kvm_vcpu *vcpu); |
Andre Przywara | 2891a7d | 2016-07-15 12:43:37 +0100 | [diff] [blame] | 235 | int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi); |
Vijaya Kumar K | 94574c9 | 2017-01-26 19:50:47 +0530 | [diff] [blame] | 236 | int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr); |
| 237 | int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 238 | int offset, u32 *val); |
| 239 | int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 240 | int offset, u32 *val); |
Vijaya Kumar K | d017d7b | 2017-01-26 19:50:51 +0530 | [diff] [blame] | 241 | int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 242 | u64 id, u64 *val); |
| 243 | int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id, |
| 244 | u64 *reg); |
Vijaya Kumar K | e96a006 | 2017-01-26 19:50:52 +0530 | [diff] [blame] | 245 | int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 246 | u32 intid, u64 *val); |
Andre Przywara | 42c8870 | 2016-07-15 12:43:23 +0100 | [diff] [blame] | 247 | int kvm_register_vgic_device(unsigned long type); |
Vijaya Kumar K | 5fb247d | 2017-01-26 19:50:50 +0530 | [diff] [blame] | 248 | void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
| 249 | void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
Eric Auger | ad275b8b | 2015-12-21 18:09:38 +0100 | [diff] [blame] | 250 | int vgic_lazy_init(struct kvm *kvm); |
| 251 | int vgic_init(struct kvm *kvm); |
Eric Auger | c86c772 | 2015-11-30 14:01:58 +0100 | [diff] [blame] | 252 | |
Greg Kroah-Hartman | 929f45e | 2018-05-29 18:22:04 +0200 | [diff] [blame^] | 253 | void vgic_debug_init(struct kvm *kvm); |
| 254 | void vgic_debug_destroy(struct kvm *kvm); |
Christoffer Dall | 10f92c4 | 2017-01-17 23:09:13 +0100 | [diff] [blame] | 255 | |
Eric Auger | dfc99f8 | 2017-03-23 11:51:52 +0100 | [diff] [blame] | 256 | bool lock_all_vcpus(struct kvm *kvm); |
| 257 | void unlock_all_vcpus(struct kvm *kvm); |
| 258 | |
Christoffer Dall | 50f5bd5 | 2017-09-01 11:41:52 +0200 | [diff] [blame] | 259 | static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu) |
| 260 | { |
| 261 | struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu; |
| 262 | |
| 263 | /* |
| 264 | * num_pri_bits are initialized with HW supported values. |
| 265 | * We can rely safely on num_pri_bits even if VM has not |
| 266 | * restored ICC_CTLR_EL1 before restoring APnR registers. |
| 267 | */ |
| 268 | switch (cpu_if->num_pri_bits) { |
| 269 | case 7: return 3; |
| 270 | case 6: return 1; |
| 271 | default: return 0; |
| 272 | } |
| 273 | } |
| 274 | |
Eric Auger | dc52461 | 2018-05-22 09:55:09 +0200 | [diff] [blame] | 275 | static inline bool |
| 276 | vgic_v3_redist_region_full(struct vgic_redist_region *region) |
| 277 | { |
| 278 | if (!region->count) |
| 279 | return false; |
| 280 | |
| 281 | return (region->free_index >= region->count); |
| 282 | } |
| 283 | |
| 284 | struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rdregs); |
| 285 | |
Eric Auger | 028bf27 | 2018-05-22 09:55:11 +0200 | [diff] [blame] | 286 | static inline size_t |
| 287 | vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg) |
| 288 | { |
| 289 | if (!rdreg->count) |
| 290 | return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE; |
| 291 | else |
| 292 | return rdreg->count * KVM_VGIC_V3_REDIST_SIZE; |
| 293 | } |
Eric Auger | 04c1109 | 2018-05-22 09:55:17 +0200 | [diff] [blame] | 294 | |
| 295 | struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm, |
| 296 | u32 index); |
| 297 | |
Eric Auger | 028bf27 | 2018-05-22 09:55:11 +0200 | [diff] [blame] | 298 | bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size); |
| 299 | |
Eric Auger | ccc27bf | 2018-05-22 09:55:12 +0200 | [diff] [blame] | 300 | static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size) |
| 301 | { |
| 302 | struct vgic_dist *d = &kvm->arch.vgic; |
| 303 | |
| 304 | return (base + size > d->vgic_dist_base) && |
| 305 | (base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE); |
| 306 | } |
| 307 | |
Marc Zyngier | bebfd2a | 2017-10-27 15:28:35 +0100 | [diff] [blame] | 308 | int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its, |
| 309 | u32 devid, u32 eventid, struct vgic_irq **irq); |
| 310 | struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi); |
| 311 | |
Marc Zyngier | e7c4805 | 2017-10-27 15:28:37 +0100 | [diff] [blame] | 312 | bool vgic_supports_direct_msis(struct kvm *kvm); |
Marc Zyngier | 74fe55d | 2017-10-27 15:28:38 +0100 | [diff] [blame] | 313 | int vgic_v4_init(struct kvm *kvm); |
| 314 | void vgic_v4_teardown(struct kvm *kvm); |
Marc Zyngier | 6277579 | 2017-10-27 15:28:50 +0100 | [diff] [blame] | 315 | int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu); |
| 316 | int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu); |
Marc Zyngier | e7c4805 | 2017-10-27 15:28:37 +0100 | [diff] [blame] | 317 | |
Christoffer Dall | 64a959d | 2015-11-24 16:51:12 +0100 | [diff] [blame] | 318 | #endif |