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Fabio Estevam9aaf8802013-11-29 08:46:32 -02001/*
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03002 * DesignWare High-Definition Multimedia Interface (HDMI) driver
3 *
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
Fabio Estevam9aaf8802013-11-29 08:46:32 -02005 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03006 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Fabio Estevam9aaf8802013-11-29 08:46:32 -02007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
Fabio Estevam9aaf8802013-11-29 08:46:32 -020013 */
Andy Yanb21f4b62014-12-05 14:26:31 +080014#include <linux/module.h>
Fabio Estevam9aaf8802013-11-29 08:46:32 -020015#include <linux/irq.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/clk.h>
Sachin Kamat5a819ed2014-01-28 10:33:16 +053019#include <linux/hdmi.h>
Russell King6bcf4952015-02-02 11:01:08 +000020#include <linux/mutex.h>
Fabio Estevam9aaf8802013-11-29 08:46:32 -020021#include <linux/of_device.h>
Neil Armstrong80e2f972017-03-03 19:20:06 +020022#include <linux/regmap.h>
Russell Kingb90120a2015-03-27 12:59:58 +000023#include <linux/spinlock.h>
Fabio Estevam9aaf8802013-11-29 08:46:32 -020024
Andy Yan3d1b35a2014-12-05 14:25:05 +080025#include <drm/drm_of.h>
Fabio Estevam9aaf8802013-11-29 08:46:32 -020026#include <drm/drmP.h>
Mark Yao2c5b2cc2015-11-30 18:33:40 +080027#include <drm/drm_atomic_helper.h>
Fabio Estevam9aaf8802013-11-29 08:46:32 -020028#include <drm/drm_crtc_helper.h>
29#include <drm/drm_edid.h>
30#include <drm/drm_encoder_slave.h>
Andy Yanb21f4b62014-12-05 14:26:31 +080031#include <drm/bridge/dw_hdmi.h>
Fabio Estevam9aaf8802013-11-29 08:46:32 -020032
Thierry Reding248a86f2015-11-24 17:52:58 +010033#include "dw-hdmi.h"
34#include "dw-hdmi-audio.h"
Fabio Estevam9aaf8802013-11-29 08:46:32 -020035
Nickey Yang94bb4dc2017-03-20 10:57:31 +080036#define DDC_SEGMENT_ADDR 0x30
Fabio Estevam9aaf8802013-11-29 08:46:32 -020037#define HDMI_EDID_LEN 512
38
39#define RGB 0
40#define YCBCR444 1
41#define YCBCR422_16BITS 2
42#define YCBCR422_8BITS 3
43#define XVYCC444 4
44
45enum hdmi_datamap {
46 RGB444_8B = 0x01,
47 RGB444_10B = 0x03,
48 RGB444_12B = 0x05,
49 RGB444_16B = 0x07,
50 YCbCr444_8B = 0x09,
51 YCbCr444_10B = 0x0B,
52 YCbCr444_12B = 0x0D,
53 YCbCr444_16B = 0x0F,
54 YCbCr422_8B = 0x16,
55 YCbCr422_10B = 0x14,
56 YCbCr422_12B = 0x12,
57};
58
Fabio Estevam9aaf8802013-11-29 08:46:32 -020059static const u16 csc_coeff_default[3][4] = {
60 { 0x2000, 0x0000, 0x0000, 0x0000 },
61 { 0x0000, 0x2000, 0x0000, 0x0000 },
62 { 0x0000, 0x0000, 0x2000, 0x0000 }
63};
64
65static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
66 { 0x2000, 0x6926, 0x74fd, 0x010e },
67 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
68 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
69};
70
71static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
72 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
73 { 0x2000, 0x3264, 0x0000, 0x7e6d },
74 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
75};
76
77static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
78 { 0x2591, 0x1322, 0x074b, 0x0000 },
79 { 0x6535, 0x2000, 0x7acc, 0x0200 },
80 { 0x6acd, 0x7534, 0x2000, 0x0200 }
81};
82
83static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
84 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
85 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
86 { 0x6756, 0x78ab, 0x2000, 0x0200 }
87};
88
89struct hdmi_vmode {
Fabio Estevam9aaf8802013-11-29 08:46:32 -020090 bool mdataenablepolarity;
91
92 unsigned int mpixelclock;
93 unsigned int mpixelrepetitioninput;
94 unsigned int mpixelrepetitionoutput;
95};
96
97struct hdmi_data_info {
98 unsigned int enc_in_format;
99 unsigned int enc_out_format;
100 unsigned int enc_color_depth;
101 unsigned int colorimetry;
102 unsigned int pix_repet_factor;
103 unsigned int hdcp_enable;
104 struct hdmi_vmode video_mode;
105};
106
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300107struct dw_hdmi_i2c {
108 struct i2c_adapter adap;
109
110 struct mutex lock; /* used to serialize data transfers */
111 struct completion cmp;
112 u8 stat;
113
114 u8 slave_reg;
115 bool is_regaddr;
Nickey Yang94bb4dc2017-03-20 10:57:31 +0800116 bool is_segment;
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300117};
118
Laurent Pinchartfaba6c32017-01-17 10:29:06 +0200119struct dw_hdmi_phy_data {
120 enum dw_hdmi_phy_type type;
121 const char *name;
Laurent Pinchartb0e583e2017-03-06 01:35:39 +0200122 unsigned int gen;
Laurent Pinchartfaba6c32017-01-17 10:29:06 +0200123 bool has_svsret;
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +0200124 int (*configure)(struct dw_hdmi *hdmi,
125 const struct dw_hdmi_plat_data *pdata,
126 unsigned long mpixelclock);
Laurent Pinchartfaba6c32017-01-17 10:29:06 +0200127};
128
Andy Yanb21f4b62014-12-05 14:26:31 +0800129struct dw_hdmi {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200130 struct drm_connector connector;
Laurent Pinchart70c963e2017-01-17 10:28:54 +0200131 struct drm_bridge bridge;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200132
Laurent Pinchartbe41fc52017-01-17 10:29:05 +0200133 unsigned int version;
134
135 struct platform_device *audio;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200136 struct device *dev;
137 struct clk *isfr_clk;
138 struct clk *iahb_clk;
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300139 struct dw_hdmi_i2c *i2c;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200140
141 struct hdmi_data_info hdmi_data;
Andy Yanb21f4b62014-12-05 14:26:31 +0800142 const struct dw_hdmi_plat_data *plat_data;
143
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200144 int vic;
145
146 u8 edid[HDMI_EDID_LEN];
147 bool cable_plugin;
148
Laurent Pinchartf1585f62017-03-06 01:36:15 +0200149 struct {
150 const struct dw_hdmi_phy_ops *ops;
151 const char *name;
152 void *data;
153 bool enabled;
154 } phy;
Laurent Pinchartfaba6c32017-01-17 10:29:06 +0200155
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200156 struct drm_display_mode previous_mode;
157
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200158 struct i2c_adapter *ddc;
159 void __iomem *regs;
Russell King05b13422015-07-21 15:35:52 +0100160 bool sink_is_hdmi;
Russell Kingf709ec02015-07-21 16:09:39 +0100161 bool sink_has_audio;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200162
Russell Kingb872a8e2015-06-05 12:22:46 +0100163 struct mutex mutex; /* for state below and previous_mode */
Russell King381f05a2015-06-05 15:25:08 +0100164 enum drm_connector_force force; /* mutex-protected force state */
Russell Kingb872a8e2015-06-05 12:22:46 +0100165 bool disabled; /* DRM has disabled our bridge */
Russell King381f05a2015-06-05 15:25:08 +0100166 bool bridge_is_on; /* indicates the bridge is on */
Russell Kingaeac23b2015-06-05 13:46:22 +0100167 bool rxsense; /* rxsense state */
168 u8 phy_mask; /* desired phy int mask settings */
Russell Kingb872a8e2015-06-05 12:22:46 +0100169
Russell Kingb90120a2015-03-27 12:59:58 +0000170 spinlock_t audio_lock;
Russell King6bcf4952015-02-02 11:01:08 +0000171 struct mutex audio_mutex;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200172 unsigned int sample_rate;
Russell Kingb90120a2015-03-27 12:59:58 +0000173 unsigned int audio_cts;
174 unsigned int audio_n;
175 bool audio_enable;
Andy Yan0cd9d142014-12-05 14:28:24 +0800176
Neil Armstrong80e2f972017-03-03 19:20:06 +0200177 unsigned int reg_shift;
178 struct regmap *regm;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200179};
180
Russell Kingaeac23b2015-06-05 13:46:22 +0100181#define HDMI_IH_PHY_STAT0_RX_SENSE \
182 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
183 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
184
185#define HDMI_PHY_RX_SENSE \
186 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
187 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
188
Andy Yan0cd9d142014-12-05 14:28:24 +0800189static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
190{
Neil Armstrong80e2f972017-03-03 19:20:06 +0200191 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
Andy Yan0cd9d142014-12-05 14:28:24 +0800192}
193
194static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
195{
Neil Armstrong80e2f972017-03-03 19:20:06 +0200196 unsigned int val = 0;
197
198 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
199
200 return val;
Andy Yan0cd9d142014-12-05 14:28:24 +0800201}
202
Andy Yanb21f4b62014-12-05 14:26:31 +0800203static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
Russell King812bc612013-11-04 12:42:02 +0000204{
Neil Armstrong80e2f972017-03-03 19:20:06 +0200205 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
Russell King812bc612013-11-04 12:42:02 +0000206}
207
Andy Yanb21f4b62014-12-05 14:26:31 +0800208static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
Andy Yanb5878332014-12-05 14:23:52 +0800209 u8 shift, u8 mask)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200210{
Russell King812bc612013-11-04 12:42:02 +0000211 hdmi_modb(hdmi, data << shift, mask, reg);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200212}
213
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300214static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
215{
216 /* Software reset */
217 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
218
219 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
220 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
221
222 /* Set done, not acknowledged and arbitration interrupt polarities */
223 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
224 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
225 HDMI_I2CM_CTLINT);
226
227 /* Clear DONE and ERROR interrupts */
228 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
229 HDMI_IH_I2CM_STAT0);
230
231 /* Mute DONE and ERROR interrupts */
232 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
233 HDMI_IH_MUTE_I2CM_STAT0);
234}
235
236static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
237 unsigned char *buf, unsigned int length)
238{
239 struct dw_hdmi_i2c *i2c = hdmi->i2c;
240 int stat;
241
242 if (!i2c->is_regaddr) {
243 dev_dbg(hdmi->dev, "set read register address to 0\n");
244 i2c->slave_reg = 0x00;
245 i2c->is_regaddr = true;
246 }
247
248 while (length--) {
249 reinit_completion(&i2c->cmp);
250
251 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
Nickey Yang94bb4dc2017-03-20 10:57:31 +0800252 if (i2c->is_segment)
253 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
254 HDMI_I2CM_OPERATION);
255 else
256 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
257 HDMI_I2CM_OPERATION);
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300258
259 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
260 if (!stat)
261 return -EAGAIN;
262
263 /* Check for error condition on the bus */
264 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
265 return -EIO;
266
267 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
268 }
Nickey Yang94bb4dc2017-03-20 10:57:31 +0800269 i2c->is_segment = false;
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300270
271 return 0;
272}
273
274static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
275 unsigned char *buf, unsigned int length)
276{
277 struct dw_hdmi_i2c *i2c = hdmi->i2c;
278 int stat;
279
280 if (!i2c->is_regaddr) {
281 /* Use the first write byte as register address */
282 i2c->slave_reg = buf[0];
283 length--;
284 buf++;
285 i2c->is_regaddr = true;
286 }
287
288 while (length--) {
289 reinit_completion(&i2c->cmp);
290
291 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
292 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
293 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
294 HDMI_I2CM_OPERATION);
295
296 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
297 if (!stat)
298 return -EAGAIN;
299
300 /* Check for error condition on the bus */
301 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
302 return -EIO;
303 }
304
305 return 0;
306}
307
308static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
309 struct i2c_msg *msgs, int num)
310{
311 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
312 struct dw_hdmi_i2c *i2c = hdmi->i2c;
313 u8 addr = msgs[0].addr;
314 int i, ret = 0;
315
316 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
317
318 for (i = 0; i < num; i++) {
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300319 if (msgs[i].len == 0) {
320 dev_dbg(hdmi->dev,
321 "unsupported transfer %d/%d, no data\n",
322 i + 1, num);
323 return -EOPNOTSUPP;
324 }
325 }
326
327 mutex_lock(&i2c->lock);
328
329 /* Unmute DONE and ERROR interrupts */
330 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
331
332 /* Set slave device address taken from the first I2C message */
333 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
334
335 /* Set slave device register address on transfer */
336 i2c->is_regaddr = false;
337
Nickey Yang94bb4dc2017-03-20 10:57:31 +0800338 /* Set segment pointer for I2C extended read mode operation */
339 i2c->is_segment = false;
340
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300341 for (i = 0; i < num; i++) {
342 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
343 i + 1, num, msgs[i].len, msgs[i].flags);
Nickey Yang94bb4dc2017-03-20 10:57:31 +0800344 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
345 i2c->is_segment = true;
346 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
347 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
348 } else {
349 if (msgs[i].flags & I2C_M_RD)
350 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
351 msgs[i].len);
352 else
353 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
354 msgs[i].len);
355 }
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +0300356 if (ret < 0)
357 break;
358 }
359
360 if (!ret)
361 ret = num;
362
363 /* Mute DONE and ERROR interrupts */
364 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
365 HDMI_IH_MUTE_I2CM_STAT0);
366
367 mutex_unlock(&i2c->lock);
368
369 return ret;
370}
371
372static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
373{
374 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
375}
376
377static const struct i2c_algorithm dw_hdmi_algorithm = {
378 .master_xfer = dw_hdmi_i2c_xfer,
379 .functionality = dw_hdmi_i2c_func,
380};
381
382static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
383{
384 struct i2c_adapter *adap;
385 struct dw_hdmi_i2c *i2c;
386 int ret;
387
388 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
389 if (!i2c)
390 return ERR_PTR(-ENOMEM);
391
392 mutex_init(&i2c->lock);
393 init_completion(&i2c->cmp);
394
395 adap = &i2c->adap;
396 adap->class = I2C_CLASS_DDC;
397 adap->owner = THIS_MODULE;
398 adap->dev.parent = hdmi->dev;
399 adap->algo = &dw_hdmi_algorithm;
400 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
401 i2c_set_adapdata(adap, hdmi);
402
403 ret = i2c_add_adapter(adap);
404 if (ret) {
405 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
406 devm_kfree(hdmi->dev, i2c);
407 return ERR_PTR(ret);
408 }
409
410 hdmi->i2c = i2c;
411
412 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
413
414 return adap;
415}
416
Russell King351e1352015-01-31 14:50:23 +0000417static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
418 unsigned int n)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200419{
Russell King622494a2015-02-02 10:55:38 +0000420 /* Must be set/cleared first */
421 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200422
423 /* nshift factor = 0 */
Russell King812bc612013-11-04 12:42:02 +0000424 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200425
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200426 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
427 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
Russell King622494a2015-02-02 10:55:38 +0000428 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
429 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
430
431 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
432 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
433 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200434}
435
Russell Kingb195fbd2015-07-22 11:28:16 +0100436static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200437{
438 unsigned int n = (128 * freq) / 1000;
Russell Kingd0c96d12015-07-22 10:35:41 +0100439 unsigned int mult = 1;
440
441 while (freq > 48000) {
442 mult *= 2;
443 freq /= 2;
444 }
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200445
446 switch (freq) {
447 case 32000:
Russell King426701d2015-07-22 10:39:27 +0100448 if (pixel_clk == 25175000)
Russell Kingb195fbd2015-07-22 11:28:16 +0100449 n = 4576;
Russell King426701d2015-07-22 10:39:27 +0100450 else if (pixel_clk == 27027000)
Russell Kingb195fbd2015-07-22 11:28:16 +0100451 n = 4096;
Russell King426701d2015-07-22 10:39:27 +0100452 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200453 n = 11648;
454 else
455 n = 4096;
Russell Kingd0c96d12015-07-22 10:35:41 +0100456 n *= mult;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200457 break;
458
459 case 44100:
Russell King426701d2015-07-22 10:39:27 +0100460 if (pixel_clk == 25175000)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200461 n = 7007;
Russell King426701d2015-07-22 10:39:27 +0100462 else if (pixel_clk == 74176000)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200463 n = 17836;
Russell King426701d2015-07-22 10:39:27 +0100464 else if (pixel_clk == 148352000)
Russell Kingb195fbd2015-07-22 11:28:16 +0100465 n = 8918;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200466 else
467 n = 6272;
Russell Kingd0c96d12015-07-22 10:35:41 +0100468 n *= mult;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200469 break;
470
471 case 48000:
Russell King426701d2015-07-22 10:39:27 +0100472 if (pixel_clk == 25175000)
Russell Kingb195fbd2015-07-22 11:28:16 +0100473 n = 6864;
Russell King426701d2015-07-22 10:39:27 +0100474 else if (pixel_clk == 27027000)
Russell Kingb195fbd2015-07-22 11:28:16 +0100475 n = 6144;
Russell King426701d2015-07-22 10:39:27 +0100476 else if (pixel_clk == 74176000)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200477 n = 11648;
Russell King426701d2015-07-22 10:39:27 +0100478 else if (pixel_clk == 148352000)
Russell Kingb195fbd2015-07-22 11:28:16 +0100479 n = 5824;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200480 else
481 n = 6144;
Russell Kingd0c96d12015-07-22 10:35:41 +0100482 n *= mult;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200483 break;
484
485 default:
486 break;
487 }
488
489 return n;
490}
491
Andy Yanb21f4b62014-12-05 14:26:31 +0800492static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
Russell Kingb195fbd2015-07-22 11:28:16 +0100493 unsigned long pixel_clk, unsigned int sample_rate)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200494{
Russell Kingdfbdaf52015-07-22 16:54:37 +0100495 unsigned long ftdms = pixel_clk;
Russell Kingf879b382015-03-27 12:53:29 +0000496 unsigned int n, cts;
Russell Kingdfbdaf52015-07-22 16:54:37 +0100497 u64 tmp;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200498
Russell Kingb195fbd2015-07-22 11:28:16 +0100499 n = hdmi_compute_n(sample_rate, pixel_clk);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200500
Russell Kingdfbdaf52015-07-22 16:54:37 +0100501 /*
502 * Compute the CTS value from the N value. Note that CTS and N
503 * can be up to 20 bits in total, so we need 64-bit math. Also
504 * note that our TDMS clock is not fully accurate; it is accurate
505 * to kHz. This can introduce an unnecessary remainder in the
506 * calculation below, so we don't try to warn about that.
507 */
508 tmp = (u64)ftdms * n;
509 do_div(tmp, 128 * sample_rate);
510 cts = tmp;
511
512 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
513 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
514 n, cts);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200515
Russell Kingb90120a2015-03-27 12:59:58 +0000516 spin_lock_irq(&hdmi->audio_lock);
517 hdmi->audio_n = n;
518 hdmi->audio_cts = cts;
519 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
520 spin_unlock_irq(&hdmi->audio_lock);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200521}
522
Andy Yanb21f4b62014-12-05 14:26:31 +0800523static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200524{
Russell King6bcf4952015-02-02 11:01:08 +0000525 mutex_lock(&hdmi->audio_mutex);
Russell Kingb195fbd2015-07-22 11:28:16 +0100526 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
Russell King6bcf4952015-02-02 11:01:08 +0000527 mutex_unlock(&hdmi->audio_mutex);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200528}
529
Andy Yanb21f4b62014-12-05 14:26:31 +0800530static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200531{
Russell King6bcf4952015-02-02 11:01:08 +0000532 mutex_lock(&hdmi->audio_mutex);
Russell Kingf879b382015-03-27 12:53:29 +0000533 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
Russell Kingb195fbd2015-07-22 11:28:16 +0100534 hdmi->sample_rate);
Russell King6bcf4952015-02-02 11:01:08 +0000535 mutex_unlock(&hdmi->audio_mutex);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200536}
537
Russell Kingb5814ff2015-03-27 12:50:58 +0000538void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
539{
540 mutex_lock(&hdmi->audio_mutex);
541 hdmi->sample_rate = rate;
542 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
Russell Kingb195fbd2015-07-22 11:28:16 +0100543 hdmi->sample_rate);
Russell Kingb5814ff2015-03-27 12:50:58 +0000544 mutex_unlock(&hdmi->audio_mutex);
545}
546EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
547
Russell Kingb90120a2015-03-27 12:59:58 +0000548void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
549{
550 unsigned long flags;
551
552 spin_lock_irqsave(&hdmi->audio_lock, flags);
553 hdmi->audio_enable = true;
554 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
555 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
556}
557EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
558
559void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
560{
561 unsigned long flags;
562
563 spin_lock_irqsave(&hdmi->audio_lock, flags);
564 hdmi->audio_enable = false;
565 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
566 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
567}
568EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
569
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200570/*
571 * this submodule is responsible for the video data synchronization.
572 * for example, for RGB 4:4:4 input, the data map is defined as
573 * pin{47~40} <==> R[7:0]
574 * pin{31~24} <==> G[7:0]
575 * pin{15~8} <==> B[7:0]
576 */
Andy Yanb21f4b62014-12-05 14:26:31 +0800577static void hdmi_video_sample(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200578{
579 int color_format = 0;
580 u8 val;
581
582 if (hdmi->hdmi_data.enc_in_format == RGB) {
583 if (hdmi->hdmi_data.enc_color_depth == 8)
584 color_format = 0x01;
585 else if (hdmi->hdmi_data.enc_color_depth == 10)
586 color_format = 0x03;
587 else if (hdmi->hdmi_data.enc_color_depth == 12)
588 color_format = 0x05;
589 else if (hdmi->hdmi_data.enc_color_depth == 16)
590 color_format = 0x07;
591 else
592 return;
593 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
594 if (hdmi->hdmi_data.enc_color_depth == 8)
595 color_format = 0x09;
596 else if (hdmi->hdmi_data.enc_color_depth == 10)
597 color_format = 0x0B;
598 else if (hdmi->hdmi_data.enc_color_depth == 12)
599 color_format = 0x0D;
600 else if (hdmi->hdmi_data.enc_color_depth == 16)
601 color_format = 0x0F;
602 else
603 return;
604 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
605 if (hdmi->hdmi_data.enc_color_depth == 8)
606 color_format = 0x16;
607 else if (hdmi->hdmi_data.enc_color_depth == 10)
608 color_format = 0x14;
609 else if (hdmi->hdmi_data.enc_color_depth == 12)
610 color_format = 0x12;
611 else
612 return;
613 }
614
615 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
616 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
617 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
618 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
619
620 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
621 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
622 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
623 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
624 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
625 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
626 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
627 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
628 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
629 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
630 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
631}
632
Andy Yanb21f4b62014-12-05 14:26:31 +0800633static int is_color_space_conversion(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200634{
Fabio Estevamba92b222014-02-06 10:12:03 -0200635 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200636}
637
Andy Yanb21f4b62014-12-05 14:26:31 +0800638static int is_color_space_decimation(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200639{
Fabio Estevamba92b222014-02-06 10:12:03 -0200640 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
641 return 0;
642 if (hdmi->hdmi_data.enc_in_format == RGB ||
643 hdmi->hdmi_data.enc_in_format == YCBCR444)
644 return 1;
645 return 0;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200646}
647
Andy Yanb21f4b62014-12-05 14:26:31 +0800648static int is_color_space_interpolation(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200649{
Fabio Estevamba92b222014-02-06 10:12:03 -0200650 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
651 return 0;
652 if (hdmi->hdmi_data.enc_out_format == RGB ||
653 hdmi->hdmi_data.enc_out_format == YCBCR444)
654 return 1;
655 return 0;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200656}
657
Andy Yanb21f4b62014-12-05 14:26:31 +0800658static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200659{
660 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
Russell Kingc082f9d2013-11-04 12:10:40 +0000661 unsigned i;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200662 u32 csc_scale = 1;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200663
664 if (is_color_space_conversion(hdmi)) {
665 if (hdmi->hdmi_data.enc_out_format == RGB) {
Gulsah Kose256a38b2014-03-09 20:11:07 +0200666 if (hdmi->hdmi_data.colorimetry ==
667 HDMI_COLORIMETRY_ITU_601)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200668 csc_coeff = &csc_coeff_rgb_out_eitu601;
669 else
670 csc_coeff = &csc_coeff_rgb_out_eitu709;
671 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
Gulsah Kose256a38b2014-03-09 20:11:07 +0200672 if (hdmi->hdmi_data.colorimetry ==
673 HDMI_COLORIMETRY_ITU_601)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200674 csc_coeff = &csc_coeff_rgb_in_eitu601;
675 else
676 csc_coeff = &csc_coeff_rgb_in_eitu709;
677 csc_scale = 0;
678 }
679 }
680
Russell Kingc082f9d2013-11-04 12:10:40 +0000681 /* The CSC registers are sequential, alternating MSB then LSB */
682 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
683 u16 coeff_a = (*csc_coeff)[0][i];
684 u16 coeff_b = (*csc_coeff)[1][i];
685 u16 coeff_c = (*csc_coeff)[2][i];
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200686
Andy Yanb5878332014-12-05 14:23:52 +0800687 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
Russell Kingc082f9d2013-11-04 12:10:40 +0000688 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
689 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
690 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
Andy Yanb5878332014-12-05 14:23:52 +0800691 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
Russell Kingc082f9d2013-11-04 12:10:40 +0000692 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
693 }
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200694
Russell King812bc612013-11-04 12:42:02 +0000695 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
696 HDMI_CSC_SCALE);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200697}
698
Andy Yanb21f4b62014-12-05 14:26:31 +0800699static void hdmi_video_csc(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200700{
701 int color_depth = 0;
702 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
703 int decimation = 0;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200704
705 /* YCC422 interpolation to 444 mode */
706 if (is_color_space_interpolation(hdmi))
707 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
708 else if (is_color_space_decimation(hdmi))
709 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
710
711 if (hdmi->hdmi_data.enc_color_depth == 8)
712 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
713 else if (hdmi->hdmi_data.enc_color_depth == 10)
714 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
715 else if (hdmi->hdmi_data.enc_color_depth == 12)
716 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
717 else if (hdmi->hdmi_data.enc_color_depth == 16)
718 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
719 else
720 return;
721
722 /* Configure the CSC registers */
723 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
Russell King812bc612013-11-04 12:42:02 +0000724 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
725 HDMI_CSC_SCALE);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200726
Andy Yanb21f4b62014-12-05 14:26:31 +0800727 dw_hdmi_update_csc_coeffs(hdmi);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200728}
729
730/*
731 * HDMI video packetizer is used to packetize the data.
732 * for example, if input is YCC422 mode or repeater is used,
733 * data should be repacked this module can be bypassed.
734 */
Andy Yanb21f4b62014-12-05 14:26:31 +0800735static void hdmi_video_packetize(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200736{
737 unsigned int color_depth = 0;
738 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
739 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
740 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
Russell Kingbebdf662013-11-04 12:55:30 +0000741 u8 val, vp_conf;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200742
Andy Yanb5878332014-12-05 14:23:52 +0800743 if (hdmi_data->enc_out_format == RGB ||
744 hdmi_data->enc_out_format == YCBCR444) {
745 if (!hdmi_data->enc_color_depth) {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200746 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
Andy Yanb5878332014-12-05 14:23:52 +0800747 } else if (hdmi_data->enc_color_depth == 8) {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200748 color_depth = 4;
749 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
Andy Yanb5878332014-12-05 14:23:52 +0800750 } else if (hdmi_data->enc_color_depth == 10) {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200751 color_depth = 5;
Andy Yanb5878332014-12-05 14:23:52 +0800752 } else if (hdmi_data->enc_color_depth == 12) {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200753 color_depth = 6;
Andy Yanb5878332014-12-05 14:23:52 +0800754 } else if (hdmi_data->enc_color_depth == 16) {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200755 color_depth = 7;
Andy Yanb5878332014-12-05 14:23:52 +0800756 } else {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200757 return;
Andy Yanb5878332014-12-05 14:23:52 +0800758 }
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200759 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
760 if (!hdmi_data->enc_color_depth ||
761 hdmi_data->enc_color_depth == 8)
762 remap_size = HDMI_VP_REMAP_YCC422_16bit;
763 else if (hdmi_data->enc_color_depth == 10)
764 remap_size = HDMI_VP_REMAP_YCC422_20bit;
765 else if (hdmi_data->enc_color_depth == 12)
766 remap_size = HDMI_VP_REMAP_YCC422_24bit;
767 else
768 return;
769 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
Andy Yanb5878332014-12-05 14:23:52 +0800770 } else {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200771 return;
Andy Yanb5878332014-12-05 14:23:52 +0800772 }
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200773
774 /* set the packetizer registers */
775 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
776 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
777 ((hdmi_data->pix_repet_factor <<
778 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
779 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
780 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
781
Russell King812bc612013-11-04 12:42:02 +0000782 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
783 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200784
785 /* Data from pixel repeater block */
786 if (hdmi_data->pix_repet_factor > 1) {
Russell Kingbebdf662013-11-04 12:55:30 +0000787 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
788 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200789 } else { /* data from packetizer block */
Russell Kingbebdf662013-11-04 12:55:30 +0000790 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
791 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200792 }
793
Russell Kingbebdf662013-11-04 12:55:30 +0000794 hdmi_modb(hdmi, vp_conf,
795 HDMI_VP_CONF_PR_EN_MASK |
796 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
797
Russell King812bc612013-11-04 12:42:02 +0000798 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
799 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200800
801 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
802
803 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
Russell Kingbebdf662013-11-04 12:55:30 +0000804 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
805 HDMI_VP_CONF_PP_EN_ENABLE |
806 HDMI_VP_CONF_YCC422_EN_DISABLE;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200807 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
Russell Kingbebdf662013-11-04 12:55:30 +0000808 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
809 HDMI_VP_CONF_PP_EN_DISABLE |
810 HDMI_VP_CONF_YCC422_EN_ENABLE;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200811 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
Russell Kingbebdf662013-11-04 12:55:30 +0000812 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
813 HDMI_VP_CONF_PP_EN_DISABLE |
814 HDMI_VP_CONF_YCC422_EN_DISABLE;
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200815 } else {
816 return;
817 }
818
Russell Kingbebdf662013-11-04 12:55:30 +0000819 hdmi_modb(hdmi, vp_conf,
820 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
821 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200822
Russell King812bc612013-11-04 12:42:02 +0000823 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
824 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
825 HDMI_VP_STUFF_PP_STUFFING_MASK |
826 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200827
Russell King812bc612013-11-04 12:42:02 +0000828 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
829 HDMI_VP_CONF);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200830}
831
Laurent Pinchartf1585f62017-03-06 01:36:15 +0200832/* -----------------------------------------------------------------------------
833 * Synopsys PHY Handling
834 */
835
Andy Yanb21f4b62014-12-05 14:26:31 +0800836static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
Andy Yanb5878332014-12-05 14:23:52 +0800837 unsigned char bit)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200838{
Russell King812bc612013-11-04 12:42:02 +0000839 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
840 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200841}
842
Andy Yanb21f4b62014-12-05 14:26:31 +0800843static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200844{
Andy Yana4d3b8b2014-12-05 14:31:09 +0800845 u32 val;
846
847 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200848 if (msec-- == 0)
849 return false;
Emil Renner Berthing0e6bcf32014-03-30 00:21:21 +0100850 udelay(1000);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200851 }
Andy Yana4d3b8b2014-12-05 14:31:09 +0800852 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
853
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200854 return true;
855}
856
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +0200857void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
858 unsigned char addr)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200859{
860 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
861 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
862 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
Andy Yanb5878332014-12-05 14:23:52 +0800863 HDMI_PHY_I2CM_DATAO_1_ADDR);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200864 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
Andy Yanb5878332014-12-05 14:23:52 +0800865 HDMI_PHY_I2CM_DATAO_0_ADDR);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200866 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
Andy Yanb5878332014-12-05 14:23:52 +0800867 HDMI_PHY_I2CM_OPERATION_ADDR);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200868 hdmi_phy_wait_i2c_done(hdmi, 1000);
869}
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +0200870EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200871
Russell King2fada102015-07-28 12:21:34 +0100872static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200873{
Russell King2fada102015-07-28 12:21:34 +0100874 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200875 HDMI_PHY_CONF0_PDZ_OFFSET,
876 HDMI_PHY_CONF0_PDZ_MASK);
877}
878
Andy Yanb21f4b62014-12-05 14:26:31 +0800879static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200880{
881 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
882 HDMI_PHY_CONF0_ENTMDS_OFFSET,
883 HDMI_PHY_CONF0_ENTMDS_MASK);
884}
885
Laurent Pinchartf4104e82017-01-17 10:29:02 +0200886static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
Andy Yand346c142014-12-05 14:31:53 +0800887{
888 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
Laurent Pinchartf4104e82017-01-17 10:29:02 +0200889 HDMI_PHY_CONF0_SVSRET_OFFSET,
890 HDMI_PHY_CONF0_SVSRET_MASK);
Andy Yand346c142014-12-05 14:31:53 +0800891}
892
Andy Yanb21f4b62014-12-05 14:26:31 +0800893static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200894{
895 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
896 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
897 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
898}
899
Andy Yanb21f4b62014-12-05 14:26:31 +0800900static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200901{
902 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
903 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
904 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
905}
906
Andy Yanb21f4b62014-12-05 14:26:31 +0800907static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200908{
909 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
910 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
911 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
912}
913
Andy Yanb21f4b62014-12-05 14:26:31 +0800914static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200915{
916 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
917 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
918 HDMI_PHY_CONF0_SELDIPIF_MASK);
919}
920
Laurent Pinchartb0e583e2017-03-06 01:35:39 +0200921static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
922{
Laurent Pinchartf1585f62017-03-06 01:36:15 +0200923 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
Laurent Pinchartb0e583e2017-03-06 01:35:39 +0200924 unsigned int i;
925 u16 val;
926
927 if (phy->gen == 1) {
928 dw_hdmi_phy_enable_tmds(hdmi, 0);
929 dw_hdmi_phy_enable_powerdown(hdmi, true);
930 return;
931 }
932
933 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
934
935 /*
936 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
937 * to low power mode.
938 */
939 for (i = 0; i < 5; ++i) {
940 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
941 if (!(val & HDMI_PHY_TX_PHY_LOCK))
942 break;
943
944 usleep_range(1000, 2000);
945 }
946
947 if (val & HDMI_PHY_TX_PHY_LOCK)
948 dev_warn(hdmi->dev, "PHY failed to power down\n");
949 else
950 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
951
952 dw_hdmi_phy_gen2_pddq(hdmi, 1);
953}
954
Laurent Pinchart181e0ef2017-03-06 01:35:57 +0200955static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
956{
Laurent Pinchartf1585f62017-03-06 01:36:15 +0200957 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
Laurent Pinchart181e0ef2017-03-06 01:35:57 +0200958 unsigned int i;
959 u8 val;
960
961 if (phy->gen == 1) {
962 dw_hdmi_phy_enable_powerdown(hdmi, false);
963
964 /* Toggle TMDS enable. */
965 dw_hdmi_phy_enable_tmds(hdmi, 0);
966 dw_hdmi_phy_enable_tmds(hdmi, 1);
967 return 0;
968 }
969
970 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
971 dw_hdmi_phy_gen2_pddq(hdmi, 0);
972
973 /* Wait for PHY PLL lock */
974 for (i = 0; i < 5; ++i) {
975 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
976 if (val)
977 break;
978
979 usleep_range(1000, 2000);
980 }
981
982 if (!val) {
983 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
984 return -ETIMEDOUT;
985 }
986
987 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
988 return 0;
989}
990
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +0200991/*
992 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
993 * information the DWC MHL PHY has the same register layout and is thus also
994 * supported by this function.
995 */
996static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
997 const struct dw_hdmi_plat_data *pdata,
998 unsigned long mpixelclock)
Fabio Estevam9aaf8802013-11-29 08:46:32 -0200999{
Russell King39cc1532015-03-31 18:34:11 +01001000 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1001 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1002 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001003
Russell King39cc1532015-03-31 18:34:11 +01001004 /* PLL/MPLL Cfg - always match on final entry */
1005 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001006 if (mpixelclock <= mpll_config->mpixelclock)
Russell King39cc1532015-03-31 18:34:11 +01001007 break;
1008
1009 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001010 if (mpixelclock <= curr_ctrl->mpixelclock)
Russell King39cc1532015-03-31 18:34:11 +01001011 break;
1012
1013 for (; phy_config->mpixelclock != ~0UL; phy_config++)
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001014 if (mpixelclock <= phy_config->mpixelclock)
Russell King39cc1532015-03-31 18:34:11 +01001015 break;
1016
1017 if (mpll_config->mpixelclock == ~0UL ||
1018 curr_ctrl->mpixelclock == ~0UL ||
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001019 phy_config->mpixelclock == ~0UL)
Russell King39cc1532015-03-31 18:34:11 +01001020 return -EINVAL;
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001021
1022 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1023 HDMI_3D_TX_PHY_CPCE_CTRL);
1024 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1025 HDMI_3D_TX_PHY_GMPCTRL);
1026 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1027 HDMI_3D_TX_PHY_CURRCTRL);
1028
1029 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1030 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1031 HDMI_3D_TX_PHY_MSM_CTRL);
1032
1033 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1034 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1035 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1036 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1037 HDMI_3D_TX_PHY_VLEVCTRL);
1038
1039 /* Override and disable clock termination. */
1040 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1041 HDMI_3D_TX_PHY_CKCALCTRL);
1042
1043 return 0;
1044}
1045
1046static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1047{
1048 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1049 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1050 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1051 int ret;
Russell King39cc1532015-03-31 18:34:11 +01001052
Laurent Pinchartb0e583e2017-03-06 01:35:39 +02001053 dw_hdmi_phy_power_off(hdmi);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001054
Laurent Pinchart2668db32017-01-17 10:29:09 +02001055 /* Leave low power consumption mode by asserting SVSRET. */
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001056 if (phy->has_svsret)
Laurent Pinchart2668db32017-01-17 10:29:09 +02001057 dw_hdmi_phy_enable_svsret(hdmi, 1);
1058
Laurent Pinchart54d72732017-01-17 10:29:08 +02001059 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1060 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1061 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001062
1063 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1064
1065 hdmi_phy_test_clear(hdmi, 1);
1066 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
Andy Yanb5878332014-12-05 14:23:52 +08001067 HDMI_PHY_I2CM_SLAVE_ADDR);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001068 hdmi_phy_test_clear(hdmi, 0);
1069
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001070 /* Write to the PHY as configured by the platform */
1071 if (pdata->configure_phy)
1072 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1073 else
1074 ret = phy->configure(hdmi, pdata, mpixelclock);
1075 if (ret) {
1076 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1077 mpixelclock);
1078 return ret;
1079 }
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001080
Laurent Pinchart181e0ef2017-03-06 01:35:57 +02001081 return dw_hdmi_phy_power_on(hdmi);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001082}
1083
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001084static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1085 struct drm_display_mode *mode)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001086{
1087 int i, ret;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001088
1089 /* HDMI Phy spec says to do the phy initialization sequence twice */
1090 for (i = 0; i < 2; i++) {
Andy Yanb21f4b62014-12-05 14:26:31 +08001091 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1092 dw_hdmi_phy_sel_interface_control(hdmi, 0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001093
Laurent Pinchart8b9e1c02017-03-03 19:19:59 +02001094 ret = hdmi_phy_configure(hdmi);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001095 if (ret)
1096 return ret;
1097 }
1098
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001099 return 0;
1100}
1101
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001102static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1103{
1104 dw_hdmi_phy_power_off(hdmi);
1105}
1106
1107static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1108 void *data)
1109{
1110 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1111 connector_status_connected : connector_status_disconnected;
1112}
1113
1114static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1115 .init = dw_hdmi_phy_init,
1116 .disable = dw_hdmi_phy_disable,
1117 .read_hpd = dw_hdmi_phy_read_hpd,
1118};
1119
1120/* -----------------------------------------------------------------------------
1121 * HDMI TX Setup
1122 */
1123
Andy Yanb21f4b62014-12-05 14:26:31 +08001124static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001125{
Russell King812bc612013-11-04 12:42:02 +00001126 u8 de;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001127
1128 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1129 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1130 else
1131 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1132
1133 /* disable rx detect */
Russell King812bc612013-11-04 12:42:02 +00001134 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1135 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001136
Russell King812bc612013-11-04 12:42:02 +00001137 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001138
Russell King812bc612013-11-04 12:42:02 +00001139 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1140 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001141}
1142
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001143static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001144{
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001145 struct hdmi_avi_infoframe frame;
1146 u8 val;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001147
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001148 /* Initialise info frame from DRM mode */
1149 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001150
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001151 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001152 frame.colorspace = HDMI_COLORSPACE_YUV444;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001153 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001154 frame.colorspace = HDMI_COLORSPACE_YUV422;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001155 else
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001156 frame.colorspace = HDMI_COLORSPACE_RGB;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001157
1158 /* Set up colorimetry */
1159 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001160 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
Sachin Kamat5a819ed2014-01-28 10:33:16 +05301161 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001162 frame.extended_colorimetry =
1163 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
Sachin Kamat5a819ed2014-01-28 10:33:16 +05301164 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001165 frame.extended_colorimetry =
1166 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001167 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
Russell Kingd083c312015-03-27 23:14:16 +00001168 frame.colorimetry = hdmi->hdmi_data.colorimetry;
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001169 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001170 } else { /* Carries no data */
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001171 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1172 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001173 }
1174
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001175 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1176
1177 /*
1178 * The Designware IP uses a different byte format from standard
1179 * AVI info frames, though generally the bits are in the correct
1180 * bytes.
1181 */
1182
1183 /*
Jose Abreub0118e72016-08-29 10:30:51 +01001184 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1185 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1186 * bit 6 rather than 4.
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001187 */
Jose Abreub0118e72016-08-29 10:30:51 +01001188 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001189 if (frame.active_aspect & 15)
1190 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1191 if (frame.top_bar || frame.bottom_bar)
1192 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1193 if (frame.left_bar || frame.right_bar)
1194 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1195 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1196
1197 /* AVI data byte 2 differences: none */
1198 val = ((frame.colorimetry & 0x3) << 6) |
1199 ((frame.picture_aspect & 0x3) << 4) |
1200 (frame.active_aspect & 0xf);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001201 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1202
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001203 /* AVI data byte 3 differences: none */
1204 val = ((frame.extended_colorimetry & 0x7) << 4) |
1205 ((frame.quantization_range & 0x3) << 2) |
1206 (frame.nups & 0x3);
1207 if (frame.itc)
1208 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001209 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1210
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001211 /* AVI data byte 4 differences: none */
1212 val = frame.video_code & 0x7f;
1213 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001214
1215 /* AVI Data Byte 5- set up input and output pixel repetition */
1216 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1217 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1218 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1219 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1220 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1221 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1222 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1223
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001224 /*
1225 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1226 * ycc range in bits 2,3 rather than 6,7
1227 */
1228 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1229 (frame.content_type & 0x3);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001230 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1231
1232 /* AVI Data Bytes 6-13 */
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001233 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1234 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1235 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1236 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1237 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1238 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1239 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1240 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001241}
1242
Andy Yanb21f4b62014-12-05 14:26:31 +08001243static void hdmi_av_composer(struct dw_hdmi *hdmi,
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001244 const struct drm_display_mode *mode)
1245{
1246 u8 inv_val;
1247 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1248 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
Russell Kinge80b9f42015-07-21 11:08:25 +01001249 unsigned int vdisplay;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001250
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001251 vmode->mpixelclock = mode->clock * 1000;
1252
1253 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1254
1255 /* Set up HDMI_FC_INVIDCONF */
1256 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1257 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1258 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1259
Russell Kingb91eee82015-03-27 23:27:17 +00001260 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001261 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
Russell Kingb91eee82015-03-27 23:27:17 +00001262 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001263
Russell Kingb91eee82015-03-27 23:27:17 +00001264 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001265 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
Russell Kingb91eee82015-03-27 23:27:17 +00001266 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001267
1268 inv_val |= (vmode->mdataenablepolarity ?
1269 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1270 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1271
1272 if (hdmi->vic == 39)
1273 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1274 else
Russell Kingb91eee82015-03-27 23:27:17 +00001275 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001276 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
Russell Kingb91eee82015-03-27 23:27:17 +00001277 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001278
Russell Kingb91eee82015-03-27 23:27:17 +00001279 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001280 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
Russell Kingb91eee82015-03-27 23:27:17 +00001281 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001282
Russell King05b13422015-07-21 15:35:52 +01001283 inv_val |= hdmi->sink_is_hdmi ?
1284 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1285 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001286
1287 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1288
Russell Kinge80b9f42015-07-21 11:08:25 +01001289 vdisplay = mode->vdisplay;
1290 vblank = mode->vtotal - mode->vdisplay;
1291 v_de_vs = mode->vsync_start - mode->vdisplay;
1292 vsync_len = mode->vsync_end - mode->vsync_start;
1293
1294 /*
1295 * When we're setting an interlaced mode, we need
1296 * to adjust the vertical timing to suit.
1297 */
1298 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1299 vdisplay /= 2;
1300 vblank /= 2;
1301 v_de_vs /= 2;
1302 vsync_len /= 2;
1303 }
1304
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001305 /* Set up horizontal active pixel width */
1306 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1307 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1308
1309 /* Set up vertical active lines */
Russell Kinge80b9f42015-07-21 11:08:25 +01001310 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1311 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001312
1313 /* Set up horizontal blanking pixel region width */
1314 hblank = mode->htotal - mode->hdisplay;
1315 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1316 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1317
1318 /* Set up vertical blanking pixel region width */
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001319 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1320
1321 /* Set up HSYNC active edge delay width (in pixel clks) */
1322 h_de_hs = mode->hsync_start - mode->hdisplay;
1323 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1324 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1325
1326 /* Set up VSYNC active edge delay (in lines) */
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001327 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1328
1329 /* Set up HSYNC active pulse width (in pixel clks) */
1330 hsync_len = mode->hsync_end - mode->hsync_start;
1331 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1332 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1333
1334 /* Set up VSYNC active edge delay (in lines) */
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001335 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1336}
1337
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001338/* HDMI Initialization Step B.4 */
Andy Yanb21f4b62014-12-05 14:26:31 +08001339static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001340{
1341 u8 clkdis;
1342
1343 /* control period minimum duration */
1344 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1345 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1346 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1347
1348 /* Set to fill TMDS data channels */
1349 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1350 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1351 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1352
1353 /* Enable pixel clock and tmds data path */
1354 clkdis = 0x7F;
1355 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1356 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1357
1358 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1359 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1360
1361 /* Enable csc path */
1362 if (is_color_space_conversion(hdmi)) {
1363 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1364 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1365 }
Laurent Pinchart8b9e1c02017-03-03 19:19:59 +02001366
Neil Armstrong14247d72017-03-03 19:20:00 +02001367 /* Enable color space conversion if needed */
1368 if (is_color_space_conversion(hdmi))
Laurent Pinchart8b9e1c02017-03-03 19:19:59 +02001369 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1370 HDMI_MC_FLOWCTRL);
1371 else
1372 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1373 HDMI_MC_FLOWCTRL);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001374}
1375
Andy Yanb21f4b62014-12-05 14:26:31 +08001376static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001377{
Russell King812bc612013-11-04 12:42:02 +00001378 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001379}
1380
1381/* Workaround to clear the overflow condition */
Andy Yanb21f4b62014-12-05 14:26:31 +08001382static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001383{
Laurent Pinchartbe41fc52017-01-17 10:29:05 +02001384 unsigned int count;
1385 unsigned int i;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001386 u8 val;
1387
Laurent Pinchartbe41fc52017-01-17 10:29:05 +02001388 /*
1389 * Under some circumstances the Frame Composer arithmetic unit can miss
1390 * an FC register write due to being busy processing the previous one.
1391 * The issue can be worked around by issuing a TMDS software reset and
1392 * then write one of the FC registers several times.
1393 *
1394 * The number of iterations matters and depends on the HDMI TX revision
1395 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1396 * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1397 * 4 and 1 iterations respectively.
1398 */
1399
1400 switch (hdmi->version) {
1401 case 0x130a:
1402 count = 4;
1403 break;
1404 case 0x131a:
1405 count = 1;
1406 break;
1407 default:
1408 return;
1409 }
1410
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001411 /* TMDS software reset */
1412 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1413
1414 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
Laurent Pinchartbe41fc52017-01-17 10:29:05 +02001415 for (i = 0; i < count; i++)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001416 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1417}
1418
Andy Yanb21f4b62014-12-05 14:26:31 +08001419static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001420{
1421 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1422 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1423}
1424
Andy Yanb21f4b62014-12-05 14:26:31 +08001425static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001426{
1427 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1428 HDMI_IH_MUTE_FC_STAT2);
1429}
1430
Andy Yanb21f4b62014-12-05 14:26:31 +08001431static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001432{
1433 int ret;
1434
1435 hdmi_disable_overflow_interrupts(hdmi);
1436
1437 hdmi->vic = drm_match_cea_mode(mode);
1438
1439 if (!hdmi->vic) {
1440 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001441 } else {
1442 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001443 }
1444
1445 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
Andy Yanb5878332014-12-05 14:23:52 +08001446 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1447 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1448 (hdmi->vic == 17) || (hdmi->vic == 18))
Sachin Kamat5a819ed2014-01-28 10:33:16 +05301449 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001450 else
Sachin Kamat5a819ed2014-01-28 10:33:16 +05301451 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001452
Russell Kingd10ca822015-07-21 11:25:00 +01001453 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001454 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1455
1456 /* TODO: Get input format from IPU (via FB driver interface) */
1457 hdmi->hdmi_data.enc_in_format = RGB;
1458
1459 hdmi->hdmi_data.enc_out_format = RGB;
1460
1461 hdmi->hdmi_data.enc_color_depth = 8;
1462 hdmi->hdmi_data.pix_repet_factor = 0;
1463 hdmi->hdmi_data.hdcp_enable = 0;
1464 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1465
1466 /* HDMI Initialization Step B.1 */
1467 hdmi_av_composer(hdmi, mode);
1468
1469 /* HDMI Initializateion Step B.2 */
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001470 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001471 if (ret)
1472 return ret;
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001473 hdmi->phy.enabled = true;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001474
1475 /* HDMI Initialization Step B.3 */
Andy Yanb21f4b62014-12-05 14:26:31 +08001476 dw_hdmi_enable_video_path(hdmi);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001477
Russell Kingf709ec02015-07-21 16:09:39 +01001478 if (hdmi->sink_has_audio) {
1479 dev_dbg(hdmi->dev, "sink has audio support\n");
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001480
1481 /* HDMI Initialization Step E - Configure audio */
1482 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1483 hdmi_enable_audio_clk(hdmi);
Russell Kingf709ec02015-07-21 16:09:39 +01001484 }
1485
1486 /* not for DVI mode */
1487 if (hdmi->sink_is_hdmi) {
1488 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001489
1490 /* HDMI Initialization Step F - Configure AVI InfoFrame */
Russell Kingd4ac4cb2015-03-27 20:06:50 +00001491 hdmi_config_AVI(hdmi, mode);
Russell King05b13422015-07-21 15:35:52 +01001492 } else {
1493 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001494 }
1495
1496 hdmi_video_packetize(hdmi);
1497 hdmi_video_csc(hdmi);
1498 hdmi_video_sample(hdmi);
1499 hdmi_tx_hdcp_config(hdmi);
1500
Andy Yanb21f4b62014-12-05 14:26:31 +08001501 dw_hdmi_clear_overflow(hdmi);
Russell King05b13422015-07-21 15:35:52 +01001502 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001503 hdmi_enable_overflow_interrupts(hdmi);
1504
1505 return 0;
1506}
1507
1508/* Wait until we are registered to enable interrupts */
Andy Yanb21f4b62014-12-05 14:26:31 +08001509static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001510{
1511 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1512 HDMI_PHY_I2CM_INT_ADDR);
1513
1514 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1515 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1516 HDMI_PHY_I2CM_CTLINT_ADDR);
1517
1518 /* enable cable hot plug irq */
Russell Kingaeac23b2015-06-05 13:46:22 +01001519 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001520
1521 /* Clear Hotplug interrupts */
Russell Kingaeac23b2015-06-05 13:46:22 +01001522 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1523 HDMI_IH_PHY_STAT0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001524
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001525 return 0;
1526}
1527
Andy Yanb21f4b62014-12-05 14:26:31 +08001528static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001529{
1530 u8 ih_mute;
1531
1532 /*
1533 * Boot up defaults are:
1534 * HDMI_IH_MUTE = 0x03 (disabled)
1535 * HDMI_IH_MUTE_* = 0x00 (enabled)
1536 *
1537 * Disable top level interrupt bits in HDMI block
1538 */
1539 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1540 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1541 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1542
1543 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1544
1545 /* by default mask all interrupts */
1546 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1547 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1548 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1549 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1550 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1551 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1552 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1553 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1554 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1555 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1556 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1557 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1558 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1559 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1560 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1561
1562 /* Disable interrupts in the IH_MUTE_* registers */
1563 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1564 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1565 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1566 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1567 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1568 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1569 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1570 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1571 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1572 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1573
1574 /* Enable top level interrupt bits in HDMI block */
1575 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1576 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1577 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1578}
1579
Andy Yanb21f4b62014-12-05 14:26:31 +08001580static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001581{
Russell King381f05a2015-06-05 15:25:08 +01001582 hdmi->bridge_is_on = true;
Andy Yanb21f4b62014-12-05 14:26:31 +08001583 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001584}
1585
Andy Yanb21f4b62014-12-05 14:26:31 +08001586static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001587{
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001588 if (hdmi->phy.enabled) {
1589 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1590 hdmi->phy.enabled = false;
1591 }
1592
Russell King381f05a2015-06-05 15:25:08 +01001593 hdmi->bridge_is_on = false;
1594}
1595
1596static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1597{
1598 int force = hdmi->force;
1599
1600 if (hdmi->disabled) {
1601 force = DRM_FORCE_OFF;
1602 } else if (force == DRM_FORCE_UNSPECIFIED) {
Russell Kingaeac23b2015-06-05 13:46:22 +01001603 if (hdmi->rxsense)
Russell King381f05a2015-06-05 15:25:08 +01001604 force = DRM_FORCE_ON;
1605 else
1606 force = DRM_FORCE_OFF;
1607 }
1608
1609 if (force == DRM_FORCE_OFF) {
1610 if (hdmi->bridge_is_on)
1611 dw_hdmi_poweroff(hdmi);
1612 } else {
1613 if (!hdmi->bridge_is_on)
1614 dw_hdmi_poweron(hdmi);
1615 }
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001616}
1617
Russell Kingaeac23b2015-06-05 13:46:22 +01001618/*
1619 * Adjust the detection of RXSENSE according to whether we have a forced
1620 * connection mode enabled, or whether we have been disabled. There is
1621 * no point processing RXSENSE interrupts if we have a forced connection
1622 * state, or DRM has us disabled.
1623 *
1624 * We also disable rxsense interrupts when we think we're disconnected
1625 * to avoid floating TDMS signals giving false rxsense interrupts.
1626 *
1627 * Note: we still need to listen for HPD interrupts even when DRM has us
1628 * disabled so that we can detect a connect event.
1629 */
1630static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1631{
1632 u8 old_mask = hdmi->phy_mask;
1633
1634 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1635 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1636 else
1637 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1638
1639 if (old_mask != hdmi->phy_mask)
1640 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1641}
1642
Andy Yanb21f4b62014-12-05 14:26:31 +08001643static enum drm_connector_status
1644dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001645{
Andy Yanb21f4b62014-12-05 14:26:31 +08001646 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
Russell Kingd94905e2013-11-03 22:23:24 +00001647 connector);
Russell King98dbead2014-04-18 10:46:45 +01001648
Russell King381f05a2015-06-05 15:25:08 +01001649 mutex_lock(&hdmi->mutex);
1650 hdmi->force = DRM_FORCE_UNSPECIFIED;
1651 dw_hdmi_update_power(hdmi);
Russell Kingaeac23b2015-06-05 13:46:22 +01001652 dw_hdmi_update_phy_mask(hdmi);
Russell King381f05a2015-06-05 15:25:08 +01001653 mutex_unlock(&hdmi->mutex);
1654
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001655 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001656}
1657
Andy Yanb21f4b62014-12-05 14:26:31 +08001658static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001659{
Andy Yanb21f4b62014-12-05 14:26:31 +08001660 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001661 connector);
1662 struct edid *edid;
Doug Anderson6c7e66e2015-06-04 11:04:36 -07001663 int ret = 0;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001664
1665 if (!hdmi->ddc)
1666 return 0;
1667
1668 edid = drm_get_edid(connector, hdmi->ddc);
1669 if (edid) {
1670 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1671 edid->width_cm, edid->height_cm);
1672
Russell King05b13422015-07-21 15:35:52 +01001673 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
Russell Kingf709ec02015-07-21 16:09:39 +01001674 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001675 drm_mode_connector_update_edid_property(connector, edid);
1676 ret = drm_add_edid_modes(connector, edid);
Russell Kingf5ce4052013-11-07 16:06:01 +00001677 /* Store the ELD */
1678 drm_edid_to_eld(connector, edid);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001679 kfree(edid);
1680 } else {
1681 dev_dbg(hdmi->dev, "failed to get edid\n");
1682 }
1683
Doug Anderson6c7e66e2015-06-04 11:04:36 -07001684 return ret;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001685}
1686
Andy Yan632d0352014-12-05 14:30:21 +08001687static enum drm_mode_status
1688dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1689 struct drm_display_mode *mode)
1690{
1691 struct dw_hdmi *hdmi = container_of(connector,
1692 struct dw_hdmi, connector);
1693 enum drm_mode_status mode_status = MODE_OK;
1694
Russell King8add4192015-07-22 11:14:00 +01001695 /* We don't support double-clocked modes */
1696 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1697 return MODE_BAD;
1698
Andy Yan632d0352014-12-05 14:30:21 +08001699 if (hdmi->plat_data->mode_valid)
1700 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1701
1702 return mode_status;
1703}
1704
Russell King381f05a2015-06-05 15:25:08 +01001705static void dw_hdmi_connector_force(struct drm_connector *connector)
1706{
1707 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1708 connector);
1709
1710 mutex_lock(&hdmi->mutex);
1711 hdmi->force = connector->force;
1712 dw_hdmi_update_power(hdmi);
Russell Kingaeac23b2015-06-05 13:46:22 +01001713 dw_hdmi_update_phy_mask(hdmi);
Russell King381f05a2015-06-05 15:25:08 +01001714 mutex_unlock(&hdmi->mutex);
1715}
1716
Ville Syrjälädae91e42015-12-15 12:21:02 +01001717static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
Mark Yao2c5b2cc2015-11-30 18:33:40 +08001718 .dpms = drm_atomic_helper_connector_dpms,
1719 .fill_modes = drm_helper_probe_single_connector_modes,
1720 .detect = dw_hdmi_connector_detect,
Marek Vasutfdd83262016-10-05 16:31:33 +02001721 .destroy = drm_connector_cleanup,
Mark Yao2c5b2cc2015-11-30 18:33:40 +08001722 .force = dw_hdmi_connector_force,
1723 .reset = drm_atomic_helper_connector_reset,
1724 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1725 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1726};
1727
Ville Syrjälädae91e42015-12-15 12:21:02 +01001728static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
Andy Yanb21f4b62014-12-05 14:26:31 +08001729 .get_modes = dw_hdmi_connector_get_modes,
Andy Yan632d0352014-12-05 14:30:21 +08001730 .mode_valid = dw_hdmi_connector_mode_valid,
Boris Brezillonc2a441f2016-06-07 13:48:15 +02001731 .best_encoder = drm_atomic_helper_best_encoder,
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001732};
1733
Laurent Pinchartd2ae94a2017-01-17 10:28:59 +02001734static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
1735{
1736 struct dw_hdmi *hdmi = bridge->driver_private;
1737 struct drm_encoder *encoder = bridge->encoder;
1738 struct drm_connector *connector = &hdmi->connector;
1739
1740 connector->interlace_allowed = 1;
1741 connector->polled = DRM_CONNECTOR_POLL_HPD;
1742
1743 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1744
1745 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1746 DRM_MODE_CONNECTOR_HDMIA);
1747
1748 drm_mode_connector_attach_encoder(connector, encoder);
1749
1750 return 0;
1751}
1752
Laurent Pinchartfd30b382017-01-17 10:28:58 +02001753static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1754 struct drm_display_mode *orig_mode,
1755 struct drm_display_mode *mode)
1756{
1757 struct dw_hdmi *hdmi = bridge->driver_private;
1758
1759 mutex_lock(&hdmi->mutex);
1760
1761 /* Store the display mode for plugin/DKMS poweron events */
1762 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1763
1764 mutex_unlock(&hdmi->mutex);
1765}
1766
1767static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1768{
1769 struct dw_hdmi *hdmi = bridge->driver_private;
1770
1771 mutex_lock(&hdmi->mutex);
1772 hdmi->disabled = true;
1773 dw_hdmi_update_power(hdmi);
1774 dw_hdmi_update_phy_mask(hdmi);
1775 mutex_unlock(&hdmi->mutex);
1776}
1777
1778static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1779{
1780 struct dw_hdmi *hdmi = bridge->driver_private;
1781
1782 mutex_lock(&hdmi->mutex);
1783 hdmi->disabled = false;
1784 dw_hdmi_update_power(hdmi);
1785 dw_hdmi_update_phy_mask(hdmi);
1786 mutex_unlock(&hdmi->mutex);
1787}
1788
Ville Syrjälädae91e42015-12-15 12:21:02 +01001789static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
Laurent Pinchartd2ae94a2017-01-17 10:28:59 +02001790 .attach = dw_hdmi_bridge_attach,
Andy Yanb21f4b62014-12-05 14:26:31 +08001791 .enable = dw_hdmi_bridge_enable,
1792 .disable = dw_hdmi_bridge_disable,
Andy Yanb21f4b62014-12-05 14:26:31 +08001793 .mode_set = dw_hdmi_bridge_mode_set,
Andy Yan3d1b35a2014-12-05 14:25:05 +08001794};
1795
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03001796static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1797{
1798 struct dw_hdmi_i2c *i2c = hdmi->i2c;
1799 unsigned int stat;
1800
1801 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1802 if (!stat)
1803 return IRQ_NONE;
1804
1805 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1806
1807 i2c->stat = stat;
1808
1809 complete(&i2c->cmp);
1810
1811 return IRQ_HANDLED;
1812}
1813
Andy Yanb21f4b62014-12-05 14:26:31 +08001814static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
Russell Kingd94905e2013-11-03 22:23:24 +00001815{
Andy Yanb21f4b62014-12-05 14:26:31 +08001816 struct dw_hdmi *hdmi = dev_id;
Russell Kingd94905e2013-11-03 22:23:24 +00001817 u8 intr_stat;
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03001818 irqreturn_t ret = IRQ_NONE;
1819
1820 if (hdmi->i2c)
1821 ret = dw_hdmi_i2c_irq(hdmi);
Russell Kingd94905e2013-11-03 22:23:24 +00001822
1823 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03001824 if (intr_stat) {
Russell Kingd94905e2013-11-03 22:23:24 +00001825 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03001826 return IRQ_WAKE_THREAD;
1827 }
Russell Kingd94905e2013-11-03 22:23:24 +00001828
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03001829 return ret;
Russell Kingd94905e2013-11-03 22:23:24 +00001830}
1831
Andy Yanb21f4b62014-12-05 14:26:31 +08001832static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001833{
Andy Yanb21f4b62014-12-05 14:26:31 +08001834 struct dw_hdmi *hdmi = dev_id;
Russell Kingaeac23b2015-06-05 13:46:22 +01001835 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001836
1837 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001838 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
Russell Kingaeac23b2015-06-05 13:46:22 +01001839 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001840
Russell Kingaeac23b2015-06-05 13:46:22 +01001841 phy_pol_mask = 0;
1842 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1843 phy_pol_mask |= HDMI_PHY_HPD;
1844 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1845 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1846 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1847 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1848 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1849 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1850 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1851 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1852
1853 if (phy_pol_mask)
1854 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1855
1856 /*
1857 * RX sense tells us whether the TDMS transmitters are detecting
1858 * load - in other words, there's something listening on the
1859 * other end of the link. Use this to decide whether we should
1860 * power on the phy as HPD may be toggled by the sink to merely
1861 * ask the source to re-read the EDID.
1862 */
1863 if (intr_stat &
1864 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
Russell Kingb872a8e2015-06-05 12:22:46 +01001865 mutex_lock(&hdmi->mutex);
Russell Kingaeac23b2015-06-05 13:46:22 +01001866 if (!hdmi->disabled && !hdmi->force) {
1867 /*
1868 * If the RX sense status indicates we're disconnected,
1869 * clear the software rxsense status.
1870 */
1871 if (!(phy_stat & HDMI_PHY_RX_SENSE))
1872 hdmi->rxsense = false;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001873
Russell Kingaeac23b2015-06-05 13:46:22 +01001874 /*
1875 * Only set the software rxsense status when both
1876 * rxsense and hpd indicates we're connected.
1877 * This avoids what seems to be bad behaviour in
1878 * at least iMX6S versions of the phy.
1879 */
1880 if (phy_stat & HDMI_PHY_HPD)
1881 hdmi->rxsense = true;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001882
Russell Kingaeac23b2015-06-05 13:46:22 +01001883 dw_hdmi_update_power(hdmi);
1884 dw_hdmi_update_phy_mask(hdmi);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001885 }
Russell Kingb872a8e2015-06-05 12:22:46 +01001886 mutex_unlock(&hdmi->mutex);
Russell Kingaeac23b2015-06-05 13:46:22 +01001887 }
1888
1889 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1890 dev_dbg(hdmi->dev, "EVENT=%s\n",
1891 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
Laurent Pinchartba5d7e62017-01-17 10:28:56 +02001892 if (hdmi->bridge.dev)
1893 drm_helper_hpd_irq_event(hdmi->bridge.dev);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001894 }
1895
1896 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
Russell Kingaeac23b2015-06-05 13:46:22 +01001897 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1898 HDMI_IH_MUTE_PHY_STAT0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02001899
1900 return IRQ_HANDLED;
1901}
1902
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001903static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
1904 {
1905 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
1906 .name = "DWC HDMI TX PHY",
Laurent Pinchartb0e583e2017-03-06 01:35:39 +02001907 .gen = 1,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001908 }, {
1909 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
1910 .name = "DWC MHL PHY + HEAC PHY",
Laurent Pinchartb0e583e2017-03-06 01:35:39 +02001911 .gen = 2,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001912 .has_svsret = true,
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001913 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001914 }, {
1915 .type = DW_HDMI_PHY_DWC_MHL_PHY,
1916 .name = "DWC MHL PHY",
Laurent Pinchartb0e583e2017-03-06 01:35:39 +02001917 .gen = 2,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001918 .has_svsret = true,
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001919 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001920 }, {
1921 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
1922 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
Laurent Pinchartb0e583e2017-03-06 01:35:39 +02001923 .gen = 2,
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001924 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001925 }, {
1926 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
1927 .name = "DWC HDMI 3D TX PHY",
Laurent Pinchartb0e583e2017-03-06 01:35:39 +02001928 .gen = 2,
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001929 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001930 }, {
1931 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
1932 .name = "DWC HDMI 2.0 TX PHY",
Laurent Pinchartb0e583e2017-03-06 01:35:39 +02001933 .gen = 2,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001934 .has_svsret = true,
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001935 }, {
1936 .type = DW_HDMI_PHY_VENDOR_PHY,
1937 .name = "Vendor PHY",
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001938 }
1939};
1940
1941static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
1942{
1943 unsigned int i;
1944 u8 phy_type;
1945
1946 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
1947
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001948 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
1949 /* Vendor PHYs require support from the glue layer. */
1950 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
1951 dev_err(hdmi->dev,
1952 "Vendor HDMI PHY not supported by glue layer\n");
1953 return -ENODEV;
1954 }
1955
1956 hdmi->phy.ops = hdmi->plat_data->phy_ops;
1957 hdmi->phy.data = hdmi->plat_data->phy_data;
1958 hdmi->phy.name = hdmi->plat_data->phy_name;
1959 return 0;
1960 }
1961
1962 /* Synopsys PHYs are handled internally. */
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001963 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
1964 if (dw_hdmi_phys[i].type == phy_type) {
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001965 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
1966 hdmi->phy.name = dw_hdmi_phys[i].name;
1967 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
Kieran Bingham2ef9dfe2017-03-03 19:20:04 +02001968
1969 if (!dw_hdmi_phys[i].configure &&
1970 !hdmi->plat_data->configure_phy) {
1971 dev_err(hdmi->dev, "%s requires platform support\n",
1972 hdmi->phy.name);
1973 return -ENODEV;
1974 }
1975
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001976 return 0;
1977 }
1978 }
1979
Laurent Pinchartf1585f62017-03-06 01:36:15 +02001980 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02001981 return -ENODEV;
1982}
1983
Neil Armstrong80e2f972017-03-03 19:20:06 +02001984static const struct regmap_config hdmi_regmap_8bit_config = {
1985 .reg_bits = 32,
1986 .val_bits = 8,
1987 .reg_stride = 1,
1988 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
1989};
1990
1991static const struct regmap_config hdmi_regmap_32bit_config = {
1992 .reg_bits = 32,
1993 .val_bits = 32,
1994 .reg_stride = 4,
1995 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
1996};
1997
Laurent Pinchart69497eb2017-01-17 10:29:00 +02001998static struct dw_hdmi *
1999__dw_hdmi_probe(struct platform_device *pdev,
2000 const struct dw_hdmi_plat_data *plat_data)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002001{
Laurent Pinchartc6081192017-01-17 10:28:57 +02002002 struct device *dev = &pdev->dev;
Russell King17b50012013-11-03 11:23:34 +00002003 struct device_node *np = dev->of_node;
Russell King7ed6c662013-11-07 16:01:45 +00002004 struct platform_device_info pdevinfo;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002005 struct device_node *ddc_node;
Andy Yanb21f4b62014-12-05 14:26:31 +08002006 struct dw_hdmi *hdmi;
Neil Armstrong80e2f972017-03-03 19:20:06 +02002007 struct resource *iores = NULL;
Laurent Pinchartc6081192017-01-17 10:28:57 +02002008 int irq;
Andy Yan3d1b35a2014-12-05 14:25:05 +08002009 int ret;
Andy Yan0cd9d142014-12-05 14:28:24 +08002010 u32 val = 1;
Laurent Pinchart0527e122017-01-17 10:29:03 +02002011 u8 prod_id0;
2012 u8 prod_id1;
Kuninori Morimoto2761ba62016-11-08 01:00:57 +00002013 u8 config0;
Laurent Pinchart0c674942017-01-17 10:29:04 +02002014 u8 config3;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002015
Russell King17b50012013-11-03 11:23:34 +00002016 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002017 if (!hdmi)
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002018 return ERR_PTR(-ENOMEM);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002019
Andy Yan3d1b35a2014-12-05 14:25:05 +08002020 hdmi->plat_data = plat_data;
Russell King17b50012013-11-03 11:23:34 +00002021 hdmi->dev = dev;
Russell King40678382013-11-07 15:35:06 +00002022 hdmi->sample_rate = 48000;
Russell Kingb872a8e2015-06-05 12:22:46 +01002023 hdmi->disabled = true;
Russell Kingaeac23b2015-06-05 13:46:22 +01002024 hdmi->rxsense = true;
2025 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002026
Russell Kingb872a8e2015-06-05 12:22:46 +01002027 mutex_init(&hdmi->mutex);
Russell King6bcf4952015-02-02 11:01:08 +00002028 mutex_init(&hdmi->audio_mutex);
Russell Kingb90120a2015-03-27 12:59:58 +00002029 spin_lock_init(&hdmi->audio_lock);
Russell King6bcf4952015-02-02 11:01:08 +00002030
Philipp Zabelb5d45902014-03-05 10:20:56 +01002031 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002032 if (ddc_node) {
Vladimir Zapolskiy9f04a1f2016-08-16 23:26:43 +03002033 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002034 of_node_put(ddc_node);
Andy Yanc2c38482014-12-05 14:24:28 +08002035 if (!hdmi->ddc) {
2036 dev_dbg(hdmi->dev, "failed to read ddc node\n");
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002037 return ERR_PTR(-EPROBE_DEFER);
Andy Yanc2c38482014-12-05 14:24:28 +08002038 }
2039
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002040 } else {
2041 dev_dbg(hdmi->dev, "no ddc property found\n");
2042 }
2043
Neil Armstrong80e2f972017-03-03 19:20:06 +02002044 if (!plat_data->regm) {
2045 const struct regmap_config *reg_config;
2046
2047 of_property_read_u32(np, "reg-io-width", &val);
2048 switch (val) {
2049 case 4:
2050 reg_config = &hdmi_regmap_32bit_config;
2051 hdmi->reg_shift = 2;
2052 break;
2053 case 1:
2054 reg_config = &hdmi_regmap_8bit_config;
2055 break;
2056 default:
2057 dev_err(dev, "reg-io-width must be 1 or 4\n");
2058 return ERR_PTR(-EINVAL);
2059 }
2060
2061 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2062 hdmi->regs = devm_ioremap_resource(dev, iores);
2063 if (IS_ERR(hdmi->regs)) {
2064 ret = PTR_ERR(hdmi->regs);
2065 goto err_res;
2066 }
2067
2068 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2069 if (IS_ERR(hdmi->regm)) {
2070 dev_err(dev, "Failed to configure regmap\n");
2071 ret = PTR_ERR(hdmi->regm);
2072 goto err_res;
2073 }
2074 } else {
2075 hdmi->regm = plat_data->regm;
Vladimir Zapolskiy9f04a1f2016-08-16 23:26:43 +03002076 }
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002077
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002078 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2079 if (IS_ERR(hdmi->isfr_clk)) {
2080 ret = PTR_ERR(hdmi->isfr_clk);
Andy Yanb5878332014-12-05 14:23:52 +08002081 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
Vladimir Zapolskiy9f04a1f2016-08-16 23:26:43 +03002082 goto err_res;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002083 }
2084
2085 ret = clk_prepare_enable(hdmi->isfr_clk);
2086 if (ret) {
Andy Yanb5878332014-12-05 14:23:52 +08002087 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
Vladimir Zapolskiy9f04a1f2016-08-16 23:26:43 +03002088 goto err_res;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002089 }
2090
2091 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2092 if (IS_ERR(hdmi->iahb_clk)) {
2093 ret = PTR_ERR(hdmi->iahb_clk);
Andy Yanb5878332014-12-05 14:23:52 +08002094 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002095 goto err_isfr;
2096 }
2097
2098 ret = clk_prepare_enable(hdmi->iahb_clk);
2099 if (ret) {
Andy Yanb5878332014-12-05 14:23:52 +08002100 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002101 goto err_isfr;
2102 }
2103
2104 /* Product and revision IDs */
Laurent Pinchartbe41fc52017-01-17 10:29:05 +02002105 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2106 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
Laurent Pinchart0527e122017-01-17 10:29:03 +02002107 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2108 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2109
2110 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2111 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2112 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
Laurent Pinchartbe41fc52017-01-17 10:29:05 +02002113 hdmi->version, prod_id0, prod_id1);
Laurent Pinchart0527e122017-01-17 10:29:03 +02002114 ret = -ENODEV;
2115 goto err_iahb;
2116 }
2117
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02002118 ret = dw_hdmi_detect_phy(hdmi);
2119 if (ret < 0)
2120 goto err_iahb;
2121
2122 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
Laurent Pinchartbe41fc52017-01-17 10:29:05 +02002123 hdmi->version >> 12, hdmi->version & 0xfff,
Laurent Pinchartfaba6c32017-01-17 10:29:06 +02002124 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
Laurent Pinchartf1585f62017-03-06 01:36:15 +02002125 hdmi->phy.name);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002126
2127 initialize_hdmi_ih_mutes(hdmi);
2128
Laurent Pinchartc6081192017-01-17 10:28:57 +02002129 irq = platform_get_irq(pdev, 0);
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002130 if (irq < 0) {
2131 ret = irq;
Laurent Pinchartc6081192017-01-17 10:28:57 +02002132 goto err_iahb;
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002133 }
Laurent Pinchartc6081192017-01-17 10:28:57 +02002134
Philipp Zabel639a2022015-01-07 13:43:50 +01002135 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2136 dw_hdmi_irq, IRQF_SHARED,
2137 dev_name(dev), hdmi);
2138 if (ret)
Fabio Estevamb33ef612015-01-27 10:54:12 -02002139 goto err_iahb;
Philipp Zabel639a2022015-01-07 13:43:50 +01002140
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002141 /*
2142 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2143 * N and cts values before enabling phy
2144 */
2145 hdmi_init_clk_regenerator(hdmi);
2146
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03002147 /* If DDC bus is not specified, try to register HDMI I2C bus */
2148 if (!hdmi->ddc) {
2149 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2150 if (IS_ERR(hdmi->ddc))
2151 hdmi->ddc = NULL;
2152 }
2153
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002154 /*
2155 * Configure registers related to HDMI interrupt
2156 * generation before registering IRQ.
2157 */
Russell Kingaeac23b2015-06-05 13:46:22 +01002158 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002159
2160 /* Clear Hotplug interrupts */
Russell Kingaeac23b2015-06-05 13:46:22 +01002161 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
2162 HDMI_IH_PHY_STAT0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002163
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002164 hdmi->bridge.driver_private = hdmi;
2165 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
Arnd Bergmannd5ad7842017-01-23 13:20:38 +01002166#ifdef CONFIG_OF
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002167 hdmi->bridge.of_node = pdev->dev.of_node;
Arnd Bergmannd5ad7842017-01-23 13:20:38 +01002168#endif
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002169
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002170 ret = dw_hdmi_fb_registered(hdmi);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002171 if (ret)
2172 goto err_iahb;
2173
Russell Kingd94905e2013-11-03 22:23:24 +00002174 /* Unmute interrupts */
Russell Kingaeac23b2015-06-05 13:46:22 +01002175 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2176 HDMI_IH_MUTE_PHY_STAT0);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002177
Russell King7ed6c662013-11-07 16:01:45 +00002178 memset(&pdevinfo, 0, sizeof(pdevinfo));
2179 pdevinfo.parent = dev;
2180 pdevinfo.id = PLATFORM_DEVID_AUTO;
2181
Kuninori Morimoto2761ba62016-11-08 01:00:57 +00002182 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
Laurent Pinchart0c674942017-01-17 10:29:04 +02002183 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
Kuninori Morimoto2761ba62016-11-08 01:00:57 +00002184
Neil Armstrong80e2f972017-03-03 19:20:06 +02002185 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
Kuninori Morimoto2761ba62016-11-08 01:00:57 +00002186 struct dw_hdmi_audio_data audio;
2187
Russell King7ed6c662013-11-07 16:01:45 +00002188 audio.phys = iores->start;
2189 audio.base = hdmi->regs;
2190 audio.irq = irq;
2191 audio.hdmi = hdmi;
Russell Kingf5ce4052013-11-07 16:06:01 +00002192 audio.eld = hdmi->connector.eld;
Russell King7ed6c662013-11-07 16:01:45 +00002193
2194 pdevinfo.name = "dw-hdmi-ahb-audio";
2195 pdevinfo.data = &audio;
2196 pdevinfo.size_data = sizeof(audio);
2197 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2198 hdmi->audio = platform_device_register_full(&pdevinfo);
Kuninori Morimoto2761ba62016-11-08 01:00:57 +00002199 } else if (config0 & HDMI_CONFIG0_I2S) {
2200 struct dw_hdmi_i2s_audio_data audio;
2201
2202 audio.hdmi = hdmi;
2203 audio.write = hdmi_writeb;
2204 audio.read = hdmi_readb;
2205
2206 pdevinfo.name = "dw-hdmi-i2s-audio";
2207 pdevinfo.data = &audio;
2208 pdevinfo.size_data = sizeof(audio);
2209 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2210 hdmi->audio = platform_device_register_full(&pdevinfo);
Russell King7ed6c662013-11-07 16:01:45 +00002211 }
2212
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03002213 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2214 if (hdmi->i2c)
2215 dw_hdmi_i2c_init(hdmi);
2216
Laurent Pinchartc6081192017-01-17 10:28:57 +02002217 platform_set_drvdata(pdev, hdmi);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002218
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002219 return hdmi;
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002220
2221err_iahb:
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03002222 if (hdmi->i2c) {
2223 i2c_del_adapter(&hdmi->i2c->adap);
2224 hdmi->ddc = NULL;
2225 }
2226
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002227 clk_disable_unprepare(hdmi->iahb_clk);
2228err_isfr:
2229 clk_disable_unprepare(hdmi->isfr_clk);
Vladimir Zapolskiy9f04a1f2016-08-16 23:26:43 +03002230err_res:
2231 i2c_put_adapter(hdmi->ddc);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002232
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002233 return ERR_PTR(ret);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002234}
2235
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002236static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002237{
Russell King7ed6c662013-11-07 16:01:45 +00002238 if (hdmi->audio && !IS_ERR(hdmi->audio))
2239 platform_device_unregister(hdmi->audio);
2240
Russell Kingd94905e2013-11-03 22:23:24 +00002241 /* Disable all interrupts */
2242 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2243
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002244 clk_disable_unprepare(hdmi->iahb_clk);
2245 clk_disable_unprepare(hdmi->isfr_clk);
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03002246
2247 if (hdmi->i2c)
2248 i2c_del_adapter(&hdmi->i2c->adap);
2249 else
2250 i2c_put_adapter(hdmi->ddc);
Russell King17b50012013-11-03 11:23:34 +00002251}
Laurent Pinchart69497eb2017-01-17 10:29:00 +02002252
2253/* -----------------------------------------------------------------------------
2254 * Probe/remove API, used from platforms based on the DRM bridge API.
2255 */
2256int dw_hdmi_probe(struct platform_device *pdev,
2257 const struct dw_hdmi_plat_data *plat_data)
2258{
2259 struct dw_hdmi *hdmi;
2260 int ret;
2261
2262 hdmi = __dw_hdmi_probe(pdev, plat_data);
2263 if (IS_ERR(hdmi))
2264 return PTR_ERR(hdmi);
2265
2266 ret = drm_bridge_add(&hdmi->bridge);
2267 if (ret < 0) {
2268 __dw_hdmi_remove(hdmi);
2269 return ret;
2270 }
2271
2272 return 0;
2273}
2274EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2275
2276void dw_hdmi_remove(struct platform_device *pdev)
2277{
2278 struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
2279
2280 drm_bridge_remove(&hdmi->bridge);
2281
2282 __dw_hdmi_remove(hdmi);
2283}
2284EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2285
2286/* -----------------------------------------------------------------------------
2287 * Bind/unbind API, used from platforms based on the component framework.
2288 */
2289int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
2290 const struct dw_hdmi_plat_data *plat_data)
2291{
2292 struct dw_hdmi *hdmi;
2293 int ret;
2294
2295 hdmi = __dw_hdmi_probe(pdev, plat_data);
2296 if (IS_ERR(hdmi))
2297 return PTR_ERR(hdmi);
2298
2299 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2300 if (ret) {
2301 dw_hdmi_remove(pdev);
2302 DRM_ERROR("Failed to initialize bridge with drm\n");
2303 return ret;
2304 }
2305
2306 return 0;
2307}
2308EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2309
2310void dw_hdmi_unbind(struct device *dev)
2311{
2312 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2313
2314 __dw_hdmi_remove(hdmi);
2315}
Andy Yanb21f4b62014-12-05 14:26:31 +08002316EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002317
2318MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Andy Yan3d1b35a2014-12-05 14:25:05 +08002319MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2320MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
Vladimir Zapolskiy3efc2fa2016-08-24 08:46:37 +03002321MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
Andy Yanb21f4b62014-12-05 14:26:31 +08002322MODULE_DESCRIPTION("DW HDMI transmitter driver");
Fabio Estevam9aaf8802013-11-29 08:46:32 -02002323MODULE_LICENSE("GPL");
Andy Yanb21f4b62014-12-05 14:26:31 +08002324MODULE_ALIAS("platform:dw-hdmi");