blob: 688db03ef5b8f606b1db8de5db7221e4643b3b3e [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08005 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07006 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01007 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01008 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02009 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010010 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000011 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000012 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000013 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000014 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000015 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010016 select AUDIT_ARCH_COMPAT_GENERIC
Marc Zyngier021f6532014-06-30 16:01:31 +010017 select ARM_GIC_V3
Will Deaconadace892013-05-08 17:29:24 +010018 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000019 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070020 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000021 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000022 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070023 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010024 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010025 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000026 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070027 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010028 select GENERIC_IRQ_PROBE
29 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010030 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070031 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010032 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000033 select GENERIC_STRNCPY_FROM_USER
34 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010035 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010036 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010038 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010039 select HAVE_ARCH_AUDITSYSCALL
Jiang Liu9732caf2014-01-07 22:17:13 +080040 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000041 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000042 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010043 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070044 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010045 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010046 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010047 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070048 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070049 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010050 select HAVE_DMA_API_DEBUG
51 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000052 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010053 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000054 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010055 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090056 select HAVE_FUNCTION_TRACER
57 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010058 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010059 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010060 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000061 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010063 select HAVE_PERF_REGS
64 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070065 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010066 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010067 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010068 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010069 select NO_BOOTMEM
70 select OF
71 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010072 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010073 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000074 select POWER_RESET
75 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010076 select RTC_LIB
77 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070078 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070079 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010080 help
81 ARM 64-bit (AArch64) Linux support.
82
83config 64BIT
84 def_bool y
85
86config ARCH_PHYS_ADDR_T_64BIT
87 def_bool y
88
89config MMU
90 def_bool y
91
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070092config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010093 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010094
95config STACKTRACE_SUPPORT
96 def_bool y
97
98config LOCKDEP_SUPPORT
99 def_bool y
100
101config TRACE_IRQFLAGS_SUPPORT
102 def_bool y
103
Will Deaconc209f792014-03-14 17:47:05 +0000104config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100105 def_bool y
106
107config GENERIC_HWEIGHT
108 def_bool y
109
110config GENERIC_CSUM
111 def_bool y
112
113config GENERIC_CALIBRATE_DELAY
114 def_bool y
115
Catalin Marinas19e76402014-02-27 12:09:22 +0000116config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100117 def_bool y
118
Steve Capper29e56942014-10-09 15:29:25 -0700119config HAVE_GENERIC_RCU_GUP
120 def_bool y
121
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100122config ARCH_DMA_ADDR_T_64BIT
123 def_bool y
124
125config NEED_DMA_MAP_STATE
126 def_bool y
127
128config NEED_SG_DMA_LENGTH
129 def_bool y
130
131config SWIOTLB
132 def_bool y
133
134config IOMMU_HELPER
135 def_bool SWIOTLB
136
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100137config KERNEL_MODE_NEON
138 def_bool y
139
Rob Herring92cc15f2014-04-18 17:19:59 -0500140config FIX_EARLYCON_MEM
141 def_bool y
142
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100143source "init/Kconfig"
144
145source "kernel/Kconfig.freezer"
146
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100147menu "Platform selection"
148
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700149config ARCH_SEATTLE
150 bool "AMD Seattle SoC Family"
151 help
152 This enables support for AMD Seattle SOC Family
153
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530154config ARCH_THUNDER
155 bool "Cavium Inc. Thunder SoC Family"
156 help
157 This enables support for Cavium's Thunder Family of SoCs.
158
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100159config ARCH_VEXPRESS
160 bool "ARMv8 software model (Versatile Express)"
161 select ARCH_REQUIRE_GPIOLIB
162 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000163 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100164 select VEXPRESS_CONFIG
165 help
166 This enables support for the ARMv8 software model (Versatile
167 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100168
Vinayak Kale15942852013-04-24 10:06:57 +0100169config ARCH_XGENE
170 bool "AppliedMicro X-Gene SOC Family"
171 help
172 This enables support for AppliedMicro X-Gene SOC Family
173
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100174endmenu
175
176menu "Bus support"
177
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100178config PCI
179 bool "PCI support"
180 help
181 This feature enables support for PCI bus system. If you say Y
182 here, the kernel will include drivers and infrastructure code
183 to support PCI bus devices.
184
185config PCI_DOMAINS
186 def_bool PCI
187
188config PCI_DOMAINS_GENERIC
189 def_bool PCI
190
191config PCI_SYSCALL
192 def_bool PCI
193
194source "drivers/pci/Kconfig"
195source "drivers/pci/pcie/Kconfig"
196source "drivers/pci/hotplug/Kconfig"
197
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100198endmenu
199
200menu "Kernel Features"
201
Andre Przywarac0a01b82014-11-14 15:54:12 +0000202menu "ARM errata workarounds via the alternatives framework"
203
204config ARM64_ERRATUM_826319
205 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
206 default y
207 help
208 This option adds an alternative code sequence to work around ARM
209 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
210 AXI master interface and an L2 cache.
211
212 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
213 and is unable to accept a certain write via this interface, it will
214 not progress on read data presented on the read data channel and the
215 system can deadlock.
216
217 The workaround promotes data cache clean instructions to
218 data cache clean-and-invalidate.
219 Please note that this does not necessarily enable the workaround,
220 as it depends on the alternative framework, which will only patch
221 the kernel if an affected CPU is detected.
222
223 If unsure, say Y.
224
225config ARM64_ERRATUM_827319
226 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
227 default y
228 help
229 This option adds an alternative code sequence to work around ARM
230 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
231 master interface and an L2 cache.
232
233 Under certain conditions this erratum can cause a clean line eviction
234 to occur at the same time as another transaction to the same address
235 on the AMBA 5 CHI interface, which can cause data corruption if the
236 interconnect reorders the two transactions.
237
238 The workaround promotes data cache clean instructions to
239 data cache clean-and-invalidate.
240 Please note that this does not necessarily enable the workaround,
241 as it depends on the alternative framework, which will only patch
242 the kernel if an affected CPU is detected.
243
244 If unsure, say Y.
245
246config ARM64_ERRATUM_824069
247 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
248 default y
249 help
250 This option adds an alternative code sequence to work around ARM
251 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
252 to a coherent interconnect.
253
254 If a Cortex-A53 processor is executing a store or prefetch for
255 write instruction at the same time as a processor in another
256 cluster is executing a cache maintenance operation to the same
257 address, then this erratum might cause a clean cache line to be
258 incorrectly marked as dirty.
259
260 The workaround promotes data cache clean instructions to
261 data cache clean-and-invalidate.
262 Please note that this option does not necessarily enable the
263 workaround, as it depends on the alternative framework, which will
264 only patch the kernel if an affected CPU is detected.
265
266 If unsure, say Y.
267
268config ARM64_ERRATUM_819472
269 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
270 default y
271 help
272 This option adds an alternative code sequence to work around ARM
273 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
274 present when it is connected to a coherent interconnect.
275
276 If the processor is executing a load and store exclusive sequence at
277 the same time as a processor in another cluster is executing a cache
278 maintenance operation to the same address, then this erratum might
279 cause data corruption.
280
281 The workaround promotes data cache clean instructions to
282 data cache clean-and-invalidate.
283 Please note that this does not necessarily enable the workaround,
284 as it depends on the alternative framework, which will only patch
285 the kernel if an affected CPU is detected.
286
287 If unsure, say Y.
288
289config ARM64_ERRATUM_832075
290 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
291 default y
292 help
293 This option adds an alternative code sequence to work around ARM
294 erratum 832075 on Cortex-A57 parts up to r1p2.
295
296 Affected Cortex-A57 parts might deadlock when exclusive load/store
297 instructions to Write-Back memory are mixed with Device loads.
298
299 The workaround is to promote device loads to use Load-Acquire
300 semantics.
301 Please note that this does not necessarily enable the workaround,
302 as it depends on the alternative framework, which will only patch
303 the kernel if an affected CPU is detected.
304
305 If unsure, say Y.
306
307endmenu
308
309
Jungseok Leee41ceed2014-05-12 10:40:38 +0100310choice
311 prompt "Page size"
312 default ARM64_4K_PAGES
313 help
314 Page size (translation granule) configuration.
315
316config ARM64_4K_PAGES
317 bool "4KB"
318 help
319 This feature enables 4KB pages support.
320
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100321config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100322 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100323 help
324 This feature enables 64KB pages support (4KB by default)
325 allowing only two levels of page tables and faster TLB
326 look-up. AArch32 emulation is not available when this feature
327 is enabled.
328
Jungseok Leee41ceed2014-05-12 10:40:38 +0100329endchoice
330
331choice
332 prompt "Virtual address space size"
333 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
334 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
335 help
336 Allows choosing one of multiple possible virtual address
337 space sizes. The level of translation table is determined by
338 a combination of page size and virtual address space size.
339
340config ARM64_VA_BITS_39
341 bool "39-bit"
342 depends on ARM64_4K_PAGES
343
344config ARM64_VA_BITS_42
345 bool "42-bit"
346 depends on ARM64_64K_PAGES
347
Jungseok Leec79b9542014-05-12 18:40:51 +0900348config ARM64_VA_BITS_48
349 bool "48-bit"
Christoffer Dall04f905a2014-10-10 11:14:30 +0100350 depends on !ARM_SMMU
Jungseok Leec79b9542014-05-12 18:40:51 +0900351
Jungseok Leee41ceed2014-05-12 10:40:38 +0100352endchoice
353
354config ARM64_VA_BITS
355 int
356 default 39 if ARM64_VA_BITS_39
357 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900358 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100359
Catalin Marinasabe669d2014-07-15 15:37:21 +0100360config ARM64_PGTABLE_LEVELS
361 int
362 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100363 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100364 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
365 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900366
Will Deacona8720132013-10-11 14:52:19 +0100367config CPU_BIG_ENDIAN
368 bool "Build big-endian kernel"
369 help
370 Say Y if you plan on running a kernel in big-endian mode.
371
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100372config SMP
373 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100374 help
375 This enables support for systems with more than one CPU. If
376 you say N here, the kernel will run on single and
377 multiprocessor machines, but will use only one CPU of a
378 multiprocessor machine. If you say Y here, the kernel will run
379 on many, but not all, single processor machines. On a single
380 processor machine, the kernel will run faster if you say N
381 here.
382
383 If you don't know what to do here, say N.
384
Mark Brownf6e763b2014-03-04 07:51:17 +0000385config SCHED_MC
386 bool "Multi-core scheduler support"
387 depends on SMP
388 help
389 Multi-core scheduler support improves the CPU scheduler's decision
390 making when dealing with multi-core CPU chips at a cost of slightly
391 increased overhead in some places. If unsure say N here.
392
393config SCHED_SMT
394 bool "SMT scheduler support"
395 depends on SMP
396 help
397 Improves the CPU scheduler's decision making when dealing with
398 MultiThreading at a cost of slightly increased overhead in some
399 places. If unsure say N here.
400
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100401config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100402 int "Maximum number of CPUs (2-64)"
403 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100404 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100405 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100406 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100407
Mark Rutland9327e2c2013-10-24 20:30:18 +0100408config HOTPLUG_CPU
409 bool "Support for hot-pluggable CPUs"
410 depends on SMP
411 help
412 Say Y here to experiment with turning CPUs off and on. CPUs
413 can be controlled through /sys/devices/system/cpu.
414
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100415source kernel/Kconfig.preempt
416
417config HZ
418 int
419 default 100
420
421config ARCH_HAS_HOLES_MEMORYMODEL
422 def_bool y if SPARSEMEM
423
424config ARCH_SPARSEMEM_ENABLE
425 def_bool y
426 select SPARSEMEM_VMEMMAP_ENABLE
427
428config ARCH_SPARSEMEM_DEFAULT
429 def_bool ARCH_SPARSEMEM_ENABLE
430
431config ARCH_SELECT_MEMORY_MODEL
432 def_bool ARCH_SPARSEMEM_ENABLE
433
434config HAVE_ARCH_PFN_VALID
435 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
436
437config HW_PERF_EVENTS
438 bool "Enable hardware performance counter support for perf events"
439 depends on PERF_EVENTS
440 default y
441 help
442 Enable hardware performance counter support for perf events. If
443 disabled, perf events will use software events only.
444
Steve Capper084bd292013-04-10 13:48:00 +0100445config SYS_SUPPORTS_HUGETLBFS
446 def_bool y
447
448config ARCH_WANT_GENERAL_HUGETLB
449 def_bool y
450
451config ARCH_WANT_HUGE_PMD_SHARE
452 def_bool y if !ARM64_64K_PAGES
453
Steve Capperaf074842013-04-19 16:23:57 +0100454config HAVE_ARCH_TRANSPARENT_HUGEPAGE
455 def_bool y
456
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100457config ARCH_HAS_CACHE_LINE_SIZE
458 def_bool y
459
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100460source "mm/Kconfig"
461
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000462config SECCOMP
463 bool "Enable seccomp to safely compute untrusted bytecode"
464 ---help---
465 This kernel feature is useful for number crunching applications
466 that may need to compute untrusted bytecode during their
467 execution. By using pipes or other transports made available to
468 the process as file descriptors supporting the read/write
469 syscalls, it's possible to isolate those applications in
470 their own address space using seccomp. Once seccomp is
471 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
472 and the task is only allowed to execute a few safe syscalls
473 defined by each seccomp mode.
474
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000475config XEN_DOM0
476 def_bool y
477 depends on XEN
478
479config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700480 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000481 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000482 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000483 help
484 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
485
Steve Capperd03bb142013-04-25 15:19:21 +0100486config FORCE_MAX_ZONEORDER
487 int
488 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
489 default "11"
490
Will Deacon1b907f42014-11-20 16:51:10 +0000491menuconfig ARMV8_DEPRECATED
492 bool "Emulate deprecated/obsolete ARMv8 instructions"
493 depends on COMPAT
494 help
495 Legacy software support may require certain instructions
496 that have been deprecated or obsoleted in the architecture.
497
498 Enable this config to enable selective emulation of these
499 features.
500
501 If unsure, say Y
502
503if ARMV8_DEPRECATED
504
505config SWP_EMULATION
506 bool "Emulate SWP/SWPB instructions"
507 help
508 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
509 they are always undefined. Say Y here to enable software
510 emulation of these instructions for userspace using LDXR/STXR.
511
512 In some older versions of glibc [<=2.8] SWP is used during futex
513 trylock() operations with the assumption that the code will not
514 be preempted. This invalid assumption may be more likely to fail
515 with SWP emulation enabled, leading to deadlock of the user
516 application.
517
518 NOTE: when accessing uncached shared regions, LDXR/STXR rely
519 on an external transaction monitoring block called a global
520 monitor to maintain update atomicity. If your system does not
521 implement a global monitor, this option can cause programs that
522 perform SWP operations to uncached memory to deadlock.
523
524 If unsure, say Y
525
526config CP15_BARRIER_EMULATION
527 bool "Emulate CP15 Barrier instructions"
528 help
529 The CP15 barrier instructions - CP15ISB, CP15DSB, and
530 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
531 strongly recommended to use the ISB, DSB, and DMB
532 instructions instead.
533
534 Say Y here to enable software emulation of these
535 instructions for AArch32 userspace code. When this option is
536 enabled, CP15 barrier usage is traced which can help
537 identify software that needs updating.
538
539 If unsure, say Y
540
541endif
542
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100543endmenu
544
545menu "Boot options"
546
547config CMDLINE
548 string "Default kernel command string"
549 default ""
550 help
551 Provide a set of default command-line options at build time by
552 entering them here. As a minimum, you should specify the the
553 root device (e.g. root=/dev/nfs).
554
555config CMDLINE_FORCE
556 bool "Always use the default kernel command string"
557 help
558 Always use the default kernel command string, even if the boot
559 loader passes other arguments to the kernel.
560 This is useful if you cannot or don't want to change the
561 command-line options your boot loader passes to the kernel.
562
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200563config EFI_STUB
564 bool
565
Mark Salterf84d0272014-04-15 21:59:30 -0400566config EFI
567 bool "UEFI runtime support"
568 depends on OF && !CPU_BIG_ENDIAN
569 select LIBFDT
570 select UCS2_STRING
571 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200572 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200573 select EFI_STUB
574 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400575 default y
576 help
577 This option provides support for runtime services provided
578 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400579 clock, and platform reset). A UEFI stub is also provided to
580 allow the kernel to be booted as an EFI application. This
581 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400582
Yi Lid1ae8c02014-10-04 23:46:43 +0800583config DMI
584 bool "Enable support for SMBIOS (DMI) tables"
585 depends on EFI
586 default y
587 help
588 This enables SMBIOS/DMI feature for systems.
589
590 This option is only useful on systems that have UEFI firmware.
591 However, even with this option, the resultant kernel should
592 continue to boot on existing non-UEFI platforms.
593
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100594endmenu
595
596menu "Userspace binary formats"
597
598source "fs/Kconfig.binfmt"
599
600config COMPAT
601 bool "Kernel support for 32-bit EL0"
602 depends on !ARM64_64K_PAGES
603 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700604 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500605 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500606 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100607 help
608 This option enables support for a 32-bit EL0 running under a 64-bit
609 kernel at EL1. AArch32-specific components such as system calls,
610 the user helper functions, VFP support and the ptrace interface are
611 handled appropriately by the kernel.
612
613 If you want to execute 32-bit userspace applications, say Y.
614
615config SYSVIPC_COMPAT
616 def_bool y
617 depends on COMPAT && SYSVIPC
618
619endmenu
620
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000621menu "Power management options"
622
623source "kernel/power/Kconfig"
624
625config ARCH_SUSPEND_POSSIBLE
626 def_bool y
627
628config ARM64_CPU_SUSPEND
629 def_bool PM_SLEEP
630
631endmenu
632
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100633menu "CPU Power Management"
634
635source "drivers/cpuidle/Kconfig"
636
Rob Herring52e7e812014-02-24 11:27:57 +0900637source "drivers/cpufreq/Kconfig"
638
639endmenu
640
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100641source "net/Kconfig"
642
643source "drivers/Kconfig"
644
Mark Salterf84d0272014-04-15 21:59:30 -0400645source "drivers/firmware/Kconfig"
646
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100647source "fs/Kconfig"
648
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100649source "arch/arm64/kvm/Kconfig"
650
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100651source "arch/arm64/Kconfig.debug"
652
653source "security/Kconfig"
654
655source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800656if CRYPTO
657source "arch/arm64/crypto/Kconfig"
658endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100659
660source "lib/Kconfig"