Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Tony Lindgren | 3b59b6b | 2005-07-10 19:58:09 +0100 | [diff] [blame] | 2 | * linux/arch/arm/mach-omap1/time.c |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * OMAP Timers |
| 5 | * |
| 6 | * Copyright (C) 2004 Nokia Corporation |
Tony Lindgren | b3402cf | 2005-06-29 19:59:48 +0100 | [diff] [blame] | 7 | * Partial timer rewrite and additional dynamic tick timer support by |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * Tony Lindgen <tony@atomide.com> and |
| 9 | * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 10 | * |
| 11 | * MPU timer code based on the older MPU timer code for OMAP |
| 12 | * Copyright (C) 2000 RidgeRun, Inc. |
| 13 | * Author: Greg Lonnon <glonnon@ridgerun.com> |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify it |
| 16 | * under the terms of the GNU General Public License as published by the |
| 17 | * Free Software Foundation; either version 2 of the License, or (at your |
| 18 | * option) any later version. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 30 | * |
| 31 | * You should have received a copy of the GNU General Public License along |
| 32 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 33 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 34 | */ |
| 35 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <linux/kernel.h> |
| 37 | #include <linux/init.h> |
| 38 | #include <linux/delay.h> |
| 39 | #include <linux/interrupt.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #include <linux/spinlock.h> |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 41 | #include <linux/clk.h> |
| 42 | #include <linux/err.h> |
| 43 | #include <linux/clocksource.h> |
| 44 | #include <linux/clockchips.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 45 | #include <linux/io.h> |
Stephen Boyd | 38ff87f | 2013-06-01 23:39:40 -0700 | [diff] [blame] | 46 | #include <linux/sched_clock.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | #include <asm/irq.h> |
Tony Lindgren | f376ea1 | 2011-01-18 13:25:39 -0800 | [diff] [blame] | 49 | |
Tony Lindgren | 2e3ee9f | 2012-02-24 10:34:34 -0800 | [diff] [blame] | 50 | #include <mach/hardware.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | #include <asm/mach/irq.h> |
| 52 | #include <asm/mach/time.h> |
| 53 | |
Tony Lindgren | 2e3ee9f | 2012-02-24 10:34:34 -0800 | [diff] [blame] | 54 | #include "iomap.h" |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 55 | #include "common.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | |
Tony Lindgren | 05b5ca9 | 2011-01-18 12:42:23 -0800 | [diff] [blame] | 57 | #ifdef CONFIG_OMAP_MPU_TIMER |
| 58 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE |
| 60 | #define OMAP_MPU_TIMER_OFFSET 0x100 |
| 61 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | typedef struct { |
| 63 | u32 cntl; /* CNTL_TIMER, R/W */ |
| 64 | u32 load_tim; /* LOAD_TIM, W */ |
| 65 | u32 read_tim; /* READ_TIM, R */ |
| 66 | } omap_mpu_timer_regs_t; |
| 67 | |
Tony Lindgren | 9411326 | 2009-08-28 10:50:33 -0700 | [diff] [blame] | 68 | #define omap_mpu_timer_base(n) \ |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 69 | ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | (n)*OMAP_MPU_TIMER_OFFSET)) |
| 71 | |
Tony Lindgren | f376ea1 | 2011-01-18 13:25:39 -0800 | [diff] [blame] | 72 | static inline unsigned long notrace omap_mpu_timer_read(int nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | { |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 74 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
| 75 | return readl(&timer->read_tim); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | } |
| 77 | |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 78 | static inline void omap_mpu_set_autoreset(int nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | { |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 80 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 82 | writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | static inline void omap_mpu_remove_autoreset(int nr) |
| 86 | { |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 87 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 88 | |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 89 | writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | static inline void omap_mpu_timer_start(int nr, unsigned long load_val, |
| 93 | int autoreset) |
| 94 | { |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 95 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
| 96 | unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST; |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 97 | |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 98 | if (autoreset) |
| 99 | timerflags |= MPU_TIMER_AR; |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 100 | |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 101 | writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | udelay(1); |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 103 | writel(load_val, &timer->load_tim); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | udelay(1); |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 105 | writel(timerflags, &timer->cntl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | } |
| 107 | |
Kevin Hilman | 06cad09 | 2007-10-18 23:04:43 -0700 | [diff] [blame] | 108 | static inline void omap_mpu_timer_stop(int nr) |
| 109 | { |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 110 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
Kevin Hilman | 06cad09 | 2007-10-18 23:04:43 -0700 | [diff] [blame] | 111 | |
Russell King | 111c775 | 2011-05-09 09:45:45 +0100 | [diff] [blame] | 112 | writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); |
Kevin Hilman | 06cad09 | 2007-10-18 23:04:43 -0700 | [diff] [blame] | 113 | } |
| 114 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | /* |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 116 | * --------------------------------------------------------------------------- |
| 117 | * MPU timer 1 ... count down to zero, interrupt, reload |
| 118 | * --------------------------------------------------------------------------- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 119 | */ |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 120 | static int omap_mpu_set_next_event(unsigned long cycles, |
Kevin Hilman | 06cad09 | 2007-10-18 23:04:43 -0700 | [diff] [blame] | 121 | struct clock_event_device *evt) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 122 | { |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 123 | omap_mpu_timer_start(0, cycles, 0); |
| 124 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | } |
| 126 | |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 127 | static void omap_mpu_set_mode(enum clock_event_mode mode, |
| 128 | struct clock_event_device *evt) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | { |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 130 | switch (mode) { |
| 131 | case CLOCK_EVT_MODE_PERIODIC: |
| 132 | omap_mpu_set_autoreset(0); |
| 133 | break; |
| 134 | case CLOCK_EVT_MODE_ONESHOT: |
Kevin Hilman | 06cad09 | 2007-10-18 23:04:43 -0700 | [diff] [blame] | 135 | omap_mpu_timer_stop(0); |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 136 | omap_mpu_remove_autoreset(0); |
| 137 | break; |
| 138 | case CLOCK_EVT_MODE_UNUSED: |
| 139 | case CLOCK_EVT_MODE_SHUTDOWN: |
Thomas Gleixner | 18de5bc | 2007-07-21 04:37:34 -0700 | [diff] [blame] | 140 | case CLOCK_EVT_MODE_RESUME: |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 141 | break; |
| 142 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | } |
| 144 | |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 145 | static struct clock_event_device clockevent_mpu_timer1 = { |
| 146 | .name = "mpu_timer1", |
Will Newton | c6b349e | 2008-03-11 09:47:43 +0000 | [diff] [blame] | 147 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 148 | .set_next_event = omap_mpu_set_next_event, |
| 149 | .set_mode = omap_mpu_set_mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | }; |
| 151 | |
Linus Torvalds | 0cd61b6 | 2006-10-06 10:53:39 -0700 | [diff] [blame] | 152 | static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | { |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 154 | struct clock_event_device *evt = &clockevent_mpu_timer1; |
| 155 | |
| 156 | evt->event_handler(evt); |
| 157 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | return IRQ_HANDLED; |
| 159 | } |
| 160 | |
| 161 | static struct irqaction omap_mpu_timer1_irq = { |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 162 | .name = "mpu_timer1", |
Michael Opdenacker | fe806d0 | 2013-09-07 09:19:25 +0200 | [diff] [blame] | 163 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
Russell King | 09b8b5f | 2005-06-26 17:06:36 +0100 | [diff] [blame] | 164 | .handler = omap_mpu_timer1_interrupt, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 165 | }; |
| 166 | |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 167 | static __init void omap_init_mpu_timer(unsigned long rate) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 170 | omap_mpu_timer_start(0, (rate / HZ) - 1, 1); |
| 171 | |
Rusty Russell | 320ab2b | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 172 | clockevent_mpu_timer1.cpumask = cpumask_of(0); |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 173 | clockevents_config_and_register(&clockevent_mpu_timer1, rate, |
| 174 | 1, -1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | } |
| 176 | |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 177 | |
| 178 | /* |
| 179 | * --------------------------------------------------------------------------- |
| 180 | * MPU timer 2 ... free running 32-bit clock source and scheduler clock |
| 181 | * --------------------------------------------------------------------------- |
| 182 | */ |
| 183 | |
Stephen Boyd | 50f6dca | 2013-11-15 15:26:17 -0800 | [diff] [blame] | 184 | static u64 notrace omap_mpu_read_sched_clock(void) |
Tony Lindgren | 4912cf0 | 2011-01-18 17:00:00 -0800 | [diff] [blame] | 185 | { |
Marc Zyngier | 2f0778af | 2011-12-15 12:19:23 +0100 | [diff] [blame] | 186 | return ~omap_mpu_timer_read(1); |
Tony Lindgren | f376ea1 | 2011-01-18 13:25:39 -0800 | [diff] [blame] | 187 | } |
| 188 | |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 189 | static void __init omap_init_clocksource(unsigned long rate) |
| 190 | { |
Russell King | 933e54a | 2011-05-09 09:51:03 +0100 | [diff] [blame] | 191 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1); |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 192 | static char err[] __initdata = KERN_ERR |
| 193 | "%s: can't register clocksource!\n"; |
| 194 | |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 195 | omap_mpu_timer_start(1, ~0, 1); |
Stephen Boyd | 50f6dca | 2013-11-15 15:26:17 -0800 | [diff] [blame] | 196 | sched_clock_register(omap_mpu_read_sched_clock, 32, rate); |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 197 | |
Russell King | 933e54a | 2011-05-09 09:51:03 +0100 | [diff] [blame] | 198 | if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, |
| 199 | 300, 32, clocksource_mmio_readl_down)) |
| 200 | printk(err, "mpu_timer2"); |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 201 | } |
| 202 | |
Tony Lindgren | 05b5ca9 | 2011-01-18 12:42:23 -0800 | [diff] [blame] | 203 | static void __init omap_mpu_timer_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | { |
Kevin Hilman | 075192a | 2007-03-08 20:32:19 +0100 | [diff] [blame] | 205 | struct clk *ck_ref = clk_get(NULL, "ck_ref"); |
| 206 | unsigned long rate; |
| 207 | |
| 208 | BUG_ON(IS_ERR(ck_ref)); |
| 209 | |
| 210 | rate = clk_get_rate(ck_ref); |
| 211 | clk_put(ck_ref); |
| 212 | |
| 213 | /* PTV = 0 */ |
| 214 | rate /= 2; |
| 215 | |
| 216 | omap_init_mpu_timer(rate); |
| 217 | omap_init_clocksource(rate); |
Tony Lindgren | 05b5ca9 | 2011-01-18 12:42:23 -0800 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | #else |
| 221 | static inline void omap_mpu_timer_init(void) |
| 222 | { |
| 223 | pr_err("Bogus timer, should not happen\n"); |
| 224 | } |
| 225 | #endif /* CONFIG_OMAP_MPU_TIMER */ |
| 226 | |
Tony Lindgren | 05b5ca9 | 2011-01-18 12:42:23 -0800 | [diff] [blame] | 227 | /* |
| 228 | * --------------------------------------------------------------------------- |
| 229 | * Timer initialization |
| 230 | * --------------------------------------------------------------------------- |
| 231 | */ |
Stephen Warren | 6bb27d7 | 2012-11-08 12:40:59 -0700 | [diff] [blame] | 232 | void __init omap1_timer_init(void) |
Tony Lindgren | 05b5ca9 | 2011-01-18 12:42:23 -0800 | [diff] [blame] | 233 | { |
Vaibhav Hiremath | 1879991 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 234 | if (omap_32k_timer_init() != 0) |
Tony Lindgren | 05b5ca9 | 2011-01-18 12:42:23 -0800 | [diff] [blame] | 235 | omap_mpu_timer_init(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | } |