Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2010 Daniel Vetter |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 25 | #include <drm/drmP.h> |
| 26 | #include <drm/i915_drm.h> |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 27 | #include "i915_drv.h" |
| 28 | #include "i915_trace.h" |
| 29 | #include "intel_drv.h" |
| 30 | |
Ben Widawsky | 6670a5a | 2013-06-27 16:30:04 -0700 | [diff] [blame] | 31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
| 32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) |
Ben Widawsky | d31eb10 | 2013-11-02 21:07:17 -0700 | [diff] [blame] | 33 | typedef uint64_t gen8_gtt_pte_t; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 34 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
Ben Widawsky | 6670a5a | 2013-06-27 16:30:04 -0700 | [diff] [blame] | 35 | |
Ben Widawsky | 26b1ff3 | 2012-11-04 09:21:31 -0800 | [diff] [blame] | 36 | /* PPGTT stuff */ |
| 37 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) |
Ben Widawsky | 0d8ff15 | 2013-07-04 11:02:03 -0700 | [diff] [blame] | 38 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
Ben Widawsky | 26b1ff3 | 2012-11-04 09:21:31 -0800 | [diff] [blame] | 39 | |
| 40 | #define GEN6_PDE_VALID (1 << 0) |
| 41 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ |
| 42 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
| 43 | |
| 44 | #define GEN6_PTE_VALID (1 << 0) |
| 45 | #define GEN6_PTE_UNCACHED (1 << 1) |
| 46 | #define HSW_PTE_UNCACHED (0) |
| 47 | #define GEN6_PTE_CACHE_LLC (2 << 1) |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 48 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
Ben Widawsky | 26b1ff3 | 2012-11-04 09:21:31 -0800 | [diff] [blame] | 49 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
Ben Widawsky | 0d8ff15 | 2013-07-04 11:02:03 -0700 | [diff] [blame] | 50 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
| 51 | |
| 52 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * |
| 53 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. |
| 54 | */ |
| 55 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ |
| 56 | (((bits) & 0x8) << (11 - 3))) |
Ben Widawsky | 87a6b68 | 2013-08-04 23:47:29 -0700 | [diff] [blame] | 57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
Ben Widawsky | 0d8ff15 | 2013-07-04 11:02:03 -0700 | [diff] [blame] | 58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 60 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
Ben Widawsky | 26b1ff3 | 2012-11-04 09:21:31 -0800 | [diff] [blame] | 61 | |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 62 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 63 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
| 64 | #define GEN8_LEGACY_PDPS 4 |
| 65 | |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 66 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
| 67 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ |
| 68 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ |
| 69 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ |
| 70 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 71 | static void ppgtt_bind_vma(struct i915_vma *vma, |
| 72 | enum i915_cache_level cache_level, |
| 73 | u32 flags); |
| 74 | static void ppgtt_unbind_vma(struct i915_vma *vma); |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 75 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 76 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 77 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
| 78 | enum i915_cache_level level, |
| 79 | bool valid) |
| 80 | { |
| 81 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
| 82 | pte |= addr; |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 83 | if (level != I915_CACHE_NONE) |
| 84 | pte |= PPAT_CACHED_INDEX; |
| 85 | else |
| 86 | pte |= PPAT_UNCACHED_INDEX; |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 87 | return pte; |
| 88 | } |
| 89 | |
Ben Widawsky | b1fe667 | 2013-11-04 21:20:14 -0800 | [diff] [blame] | 90 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
| 91 | dma_addr_t addr, |
| 92 | enum i915_cache_level level) |
| 93 | { |
| 94 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
| 95 | pde |= addr; |
| 96 | if (level != I915_CACHE_NONE) |
| 97 | pde |= PPAT_CACHED_PDE_INDEX; |
| 98 | else |
| 99 | pde |= PPAT_UNCACHED_INDEX; |
| 100 | return pde; |
| 101 | } |
| 102 | |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 103 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 104 | enum i915_cache_level level, |
| 105 | bool valid) |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 106 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 107 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 108 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 109 | |
| 110 | switch (level) { |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 111 | case I915_CACHE_L3_LLC: |
| 112 | case I915_CACHE_LLC: |
| 113 | pte |= GEN6_PTE_CACHE_LLC; |
| 114 | break; |
| 115 | case I915_CACHE_NONE: |
| 116 | pte |= GEN6_PTE_UNCACHED; |
| 117 | break; |
| 118 | default: |
| 119 | WARN_ON(1); |
| 120 | } |
| 121 | |
| 122 | return pte; |
| 123 | } |
| 124 | |
| 125 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 126 | enum i915_cache_level level, |
| 127 | bool valid) |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 128 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 129 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 130 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
| 131 | |
| 132 | switch (level) { |
| 133 | case I915_CACHE_L3_LLC: |
| 134 | pte |= GEN7_PTE_CACHE_L3_LLC; |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 135 | break; |
| 136 | case I915_CACHE_LLC: |
| 137 | pte |= GEN6_PTE_CACHE_LLC; |
| 138 | break; |
| 139 | case I915_CACHE_NONE: |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 140 | pte |= GEN6_PTE_UNCACHED; |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 141 | break; |
| 142 | default: |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 143 | WARN_ON(1); |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 146 | return pte; |
| 147 | } |
| 148 | |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 149 | #define BYT_PTE_WRITEABLE (1 << 1) |
| 150 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) |
| 151 | |
Ben Widawsky | 80a74f7 | 2013-06-27 16:30:19 -0700 | [diff] [blame] | 152 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 153 | enum i915_cache_level level, |
| 154 | bool valid) |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 155 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 156 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 157 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
| 158 | |
| 159 | /* Mark the page as writeable. Other platforms don't have a |
| 160 | * setting for read-only/writable, so this matches that behavior. |
| 161 | */ |
| 162 | pte |= BYT_PTE_WRITEABLE; |
| 163 | |
| 164 | if (level != I915_CACHE_NONE) |
| 165 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; |
| 166 | |
| 167 | return pte; |
| 168 | } |
| 169 | |
Ben Widawsky | 80a74f7 | 2013-06-27 16:30:19 -0700 | [diff] [blame] | 170 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 171 | enum i915_cache_level level, |
| 172 | bool valid) |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 173 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 174 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 0d8ff15 | 2013-07-04 11:02:03 -0700 | [diff] [blame] | 175 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 176 | |
| 177 | if (level != I915_CACHE_NONE) |
Ben Widawsky | 87a6b68 | 2013-08-04 23:47:29 -0700 | [diff] [blame] | 178 | pte |= HSW_WB_LLC_AGE3; |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 179 | |
| 180 | return pte; |
| 181 | } |
| 182 | |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 183 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 184 | enum i915_cache_level level, |
| 185 | bool valid) |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 186 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 187 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 188 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
| 189 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 190 | switch (level) { |
| 191 | case I915_CACHE_NONE: |
| 192 | break; |
| 193 | case I915_CACHE_WT: |
| 194 | pte |= HSW_WT_ELLC_LLC_AGE0; |
| 195 | break; |
| 196 | default: |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 197 | pte |= HSW_WB_ELLC_LLC_AGE0; |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 198 | break; |
| 199 | } |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 200 | |
| 201 | return pte; |
| 202 | } |
| 203 | |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 204 | /* Broadwell Page Directory Pointer Descriptors */ |
| 205 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, |
Ben Widawsky | e178f70 | 2013-12-06 14:10:47 -0800 | [diff] [blame] | 206 | uint64_t val, bool synchronous) |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 207 | { |
Ben Widawsky | e178f70 | 2013-12-06 14:10:47 -0800 | [diff] [blame] | 208 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 209 | int ret; |
| 210 | |
| 211 | BUG_ON(entry >= 4); |
| 212 | |
Ben Widawsky | e178f70 | 2013-12-06 14:10:47 -0800 | [diff] [blame] | 213 | if (synchronous) { |
| 214 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); |
| 215 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); |
| 216 | return 0; |
| 217 | } |
| 218 | |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 219 | ret = intel_ring_begin(ring, 6); |
| 220 | if (ret) |
| 221 | return ret; |
| 222 | |
| 223 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 224 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); |
| 225 | intel_ring_emit(ring, (u32)(val >> 32)); |
| 226 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 227 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); |
| 228 | intel_ring_emit(ring, (u32)(val)); |
| 229 | intel_ring_advance(ring); |
| 230 | |
| 231 | return 0; |
| 232 | } |
| 233 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 234 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
| 235 | struct intel_ring_buffer *ring, |
| 236 | bool synchronous) |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 237 | { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 238 | int i, ret; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 239 | |
| 240 | /* bit of a hack to find the actual last used pd */ |
| 241 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; |
| 242 | |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 243 | for (i = used_pd - 1; i >= 0; i--) { |
| 244 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 245 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
| 246 | if (ret) |
| 247 | return ret; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 248 | } |
Ben Widawsky | d595bd4 | 2013-11-25 09:54:32 -0800 | [diff] [blame] | 249 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 250 | return 0; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 251 | } |
| 252 | |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 253 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
| 254 | unsigned first_entry, |
| 255 | unsigned num_entries, |
| 256 | bool use_scratch) |
| 257 | { |
| 258 | struct i915_hw_ppgtt *ppgtt = |
| 259 | container_of(vm, struct i915_hw_ppgtt, base); |
| 260 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; |
| 261 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; |
| 262 | unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE; |
| 263 | unsigned last_pte, i; |
| 264 | |
| 265 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, |
| 266 | I915_CACHE_LLC, use_scratch); |
| 267 | |
| 268 | while (num_entries) { |
| 269 | struct page *page_table = &ppgtt->gen8_pt_pages[act_pt]; |
| 270 | |
| 271 | last_pte = first_pte + num_entries; |
| 272 | if (last_pte > GEN8_PTES_PER_PAGE) |
| 273 | last_pte = GEN8_PTES_PER_PAGE; |
| 274 | |
| 275 | pt_vaddr = kmap_atomic(page_table); |
| 276 | |
| 277 | for (i = first_pte; i < last_pte; i++) |
| 278 | pt_vaddr[i] = scratch_pte; |
| 279 | |
| 280 | kunmap_atomic(pt_vaddr); |
| 281 | |
| 282 | num_entries -= last_pte - first_pte; |
| 283 | first_pte = 0; |
| 284 | act_pt++; |
| 285 | } |
| 286 | } |
| 287 | |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 288 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
| 289 | struct sg_table *pages, |
| 290 | unsigned first_entry, |
| 291 | enum i915_cache_level cache_level) |
| 292 | { |
| 293 | struct i915_hw_ppgtt *ppgtt = |
| 294 | container_of(vm, struct i915_hw_ppgtt, base); |
| 295 | gen8_gtt_pte_t *pt_vaddr; |
| 296 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; |
| 297 | unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE; |
| 298 | struct sg_page_iter sg_iter; |
| 299 | |
| 300 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); |
| 301 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
| 302 | dma_addr_t page_addr; |
| 303 | |
| 304 | page_addr = sg_dma_address(sg_iter.sg) + |
| 305 | (sg_iter.sg_pgoffset << PAGE_SHIFT); |
| 306 | pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level, |
| 307 | true); |
| 308 | if (++act_pte == GEN8_PTES_PER_PAGE) { |
| 309 | kunmap_atomic(pt_vaddr); |
| 310 | act_pt++; |
| 311 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); |
| 312 | act_pte = 0; |
| 313 | |
| 314 | } |
| 315 | } |
| 316 | kunmap_atomic(pt_vaddr); |
| 317 | } |
| 318 | |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 319 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
| 320 | { |
| 321 | struct i915_hw_ppgtt *ppgtt = |
| 322 | container_of(vm, struct i915_hw_ppgtt, base); |
| 323 | int i, j; |
| 324 | |
Ben Widawsky | 686e1f6f | 2013-11-25 09:54:34 -0800 | [diff] [blame] | 325 | drm_mm_takedown(&vm->mm); |
| 326 | |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 327 | for (i = 0; i < ppgtt->num_pd_pages ; i++) { |
| 328 | if (ppgtt->pd_dma_addr[i]) { |
| 329 | pci_unmap_page(ppgtt->base.dev->pdev, |
| 330 | ppgtt->pd_dma_addr[i], |
| 331 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 332 | |
| 333 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
| 334 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; |
| 335 | if (addr) |
| 336 | pci_unmap_page(ppgtt->base.dev->pdev, |
| 337 | addr, |
| 338 | PAGE_SIZE, |
| 339 | PCI_DMA_BIDIRECTIONAL); |
| 340 | |
| 341 | } |
| 342 | } |
| 343 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
| 344 | } |
| 345 | |
Ben Widawsky | 230f955 | 2013-11-07 21:40:48 -0800 | [diff] [blame] | 346 | __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT)); |
| 347 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 348 | } |
| 349 | |
| 350 | /** |
| 351 | * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a |
| 352 | * net effect resembling a 2-level page table in normal x86 terms. Each PDP |
| 353 | * represents 1GB of memory |
| 354 | * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. |
| 355 | * |
| 356 | * TODO: Do something with the size parameter |
| 357 | **/ |
| 358 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
| 359 | { |
| 360 | struct page *pt_pages; |
| 361 | int i, j, ret = -ENOMEM; |
| 362 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
| 363 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
| 364 | |
| 365 | if (size % (1<<30)) |
| 366 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); |
| 367 | |
| 368 | /* FIXME: split allocation into smaller pieces. For now we only ever do |
| 369 | * this once, but with full PPGTT, the multiple contiguous allocations |
| 370 | * will be bad. |
| 371 | */ |
| 372 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); |
| 373 | if (!ppgtt->pd_pages) |
| 374 | return -ENOMEM; |
| 375 | |
| 376 | pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); |
| 377 | if (!pt_pages) { |
| 378 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); |
| 379 | return -ENOMEM; |
| 380 | } |
| 381 | |
| 382 | ppgtt->gen8_pt_pages = pt_pages; |
| 383 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); |
| 384 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); |
| 385 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 386 | ppgtt->enable = gen8_ppgtt_enable; |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 387 | ppgtt->switch_mm = gen8_mm_switch; |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 388 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 389 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 390 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
Ben Widawsky | 686e1f6f | 2013-11-25 09:54:34 -0800 | [diff] [blame] | 391 | ppgtt->base.start = 0; |
| 392 | ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 393 | |
| 394 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); |
| 395 | |
| 396 | /* |
| 397 | * - Create a mapping for the page directories. |
| 398 | * - For each page directory: |
| 399 | * allocate space for page table mappings. |
| 400 | * map each page table |
| 401 | */ |
| 402 | for (i = 0; i < max_pdp; i++) { |
| 403 | dma_addr_t temp; |
| 404 | temp = pci_map_page(ppgtt->base.dev->pdev, |
| 405 | &ppgtt->pd_pages[i], 0, |
| 406 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 407 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) |
| 408 | goto err_out; |
| 409 | |
| 410 | ppgtt->pd_dma_addr[i] = temp; |
| 411 | |
| 412 | ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); |
| 413 | if (!ppgtt->gen8_pt_dma_addr[i]) |
| 414 | goto err_out; |
| 415 | |
| 416 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
| 417 | struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; |
| 418 | temp = pci_map_page(ppgtt->base.dev->pdev, |
| 419 | p, 0, PAGE_SIZE, |
| 420 | PCI_DMA_BIDIRECTIONAL); |
| 421 | |
| 422 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) |
| 423 | goto err_out; |
| 424 | |
| 425 | ppgtt->gen8_pt_dma_addr[i][j] = temp; |
| 426 | } |
| 427 | } |
| 428 | |
Ben Widawsky | b1fe667 | 2013-11-04 21:20:14 -0800 | [diff] [blame] | 429 | /* For now, the PPGTT helper functions all require that the PDEs are |
| 430 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
| 431 | * will never need to touch the PDEs again */ |
| 432 | for (i = 0; i < max_pdp; i++) { |
| 433 | gen8_ppgtt_pde_t *pd_vaddr; |
| 434 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); |
| 435 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
| 436 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; |
| 437 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, |
| 438 | I915_CACHE_LLC); |
| 439 | } |
| 440 | kunmap_atomic(pd_vaddr); |
| 441 | } |
| 442 | |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 443 | ppgtt->base.clear_range(&ppgtt->base, 0, |
| 444 | ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE, |
| 445 | true); |
| 446 | |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 447 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
| 448 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); |
| 449 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", |
| 450 | ppgtt->num_pt_pages, |
| 451 | (ppgtt->num_pt_pages - num_pt_pages) + |
| 452 | size % (1<<30)); |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 453 | return 0; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 454 | |
| 455 | err_out: |
| 456 | ppgtt->base.cleanup(&ppgtt->base); |
| 457 | return ret; |
| 458 | } |
| 459 | |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 460 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 461 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 462 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 463 | gen6_gtt_pte_t __iomem *pd_addr; |
| 464 | uint32_t pd_entry; |
| 465 | int i; |
| 466 | |
Ben Widawsky | 0a73287 | 2013-04-23 23:15:30 -0700 | [diff] [blame] | 467 | WARN_ON(ppgtt->pd_offset & 0x3f); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 468 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
| 469 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); |
| 470 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 471 | dma_addr_t pt_addr; |
| 472 | |
| 473 | pt_addr = ppgtt->pt_dma_addr[i]; |
| 474 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
| 475 | pd_entry |= GEN6_PDE_VALID; |
| 476 | |
| 477 | writel(pd_entry, pd_addr + i); |
| 478 | } |
| 479 | readl(pd_addr); |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 480 | } |
| 481 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 482 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
| 483 | { |
| 484 | BUG_ON(ppgtt->pd_offset & 0x3f); |
| 485 | |
| 486 | return (ppgtt->pd_offset / 64) << 16; |
| 487 | } |
| 488 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 489 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
| 490 | struct intel_ring_buffer *ring, |
| 491 | bool synchronous) |
| 492 | { |
| 493 | struct drm_device *dev = ppgtt->base.dev; |
| 494 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 495 | int ret; |
| 496 | |
| 497 | /* If we're in reset, we can assume the GPU is sufficiently idle to |
| 498 | * manually frob these bits. Ideally we could use the ring functions, |
| 499 | * except our error handling makes it quite difficult (can't use |
| 500 | * intel_ring_begin, ring->flush, or intel_ring_advance) |
| 501 | * |
| 502 | * FIXME: We should try not to special case reset |
| 503 | */ |
| 504 | if (synchronous || |
| 505 | i915_reset_in_progress(&dev_priv->gpu_error)) { |
| 506 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); |
| 507 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 508 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
| 509 | POSTING_READ(RING_PP_DIR_BASE(ring)); |
| 510 | return 0; |
| 511 | } |
| 512 | |
| 513 | /* NB: TLBs must be flushed and invalidated before a switch */ |
| 514 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 515 | if (ret) |
| 516 | return ret; |
| 517 | |
| 518 | ret = intel_ring_begin(ring, 6); |
| 519 | if (ret) |
| 520 | return ret; |
| 521 | |
| 522 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
| 523 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); |
| 524 | intel_ring_emit(ring, PP_DIR_DCLV_2G); |
| 525 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); |
| 526 | intel_ring_emit(ring, get_pd_offset(ppgtt)); |
| 527 | intel_ring_emit(ring, MI_NOOP); |
| 528 | intel_ring_advance(ring); |
| 529 | |
| 530 | return 0; |
| 531 | } |
| 532 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 533 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
| 534 | struct intel_ring_buffer *ring, |
| 535 | bool synchronous) |
| 536 | { |
| 537 | struct drm_device *dev = ppgtt->base.dev; |
| 538 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 539 | int ret; |
| 540 | |
| 541 | /* If we're in reset, we can assume the GPU is sufficiently idle to |
| 542 | * manually frob these bits. Ideally we could use the ring functions, |
| 543 | * except our error handling makes it quite difficult (can't use |
| 544 | * intel_ring_begin, ring->flush, or intel_ring_advance) |
| 545 | * |
| 546 | * FIXME: We should try not to special case reset |
| 547 | */ |
| 548 | if (synchronous || |
| 549 | i915_reset_in_progress(&dev_priv->gpu_error)) { |
| 550 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); |
| 551 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 552 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
| 553 | POSTING_READ(RING_PP_DIR_BASE(ring)); |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | /* NB: TLBs must be flushed and invalidated before a switch */ |
| 558 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 559 | if (ret) |
| 560 | return ret; |
| 561 | |
| 562 | ret = intel_ring_begin(ring, 6); |
| 563 | if (ret) |
| 564 | return ret; |
| 565 | |
| 566 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
| 567 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); |
| 568 | intel_ring_emit(ring, PP_DIR_DCLV_2G); |
| 569 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); |
| 570 | intel_ring_emit(ring, get_pd_offset(ppgtt)); |
| 571 | intel_ring_emit(ring, MI_NOOP); |
| 572 | intel_ring_advance(ring); |
| 573 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 574 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
| 575 | if (ring->id != RCS) { |
| 576 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 577 | if (ret) |
| 578 | return ret; |
| 579 | } |
| 580 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 581 | return 0; |
| 582 | } |
| 583 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 584 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
| 585 | struct intel_ring_buffer *ring, |
| 586 | bool synchronous) |
| 587 | { |
| 588 | struct drm_device *dev = ppgtt->base.dev; |
| 589 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 590 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 591 | if (!synchronous) |
| 592 | return 0; |
| 593 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 594 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 595 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
| 596 | |
| 597 | POSTING_READ(RING_PP_DIR_DCLV(ring)); |
| 598 | |
| 599 | return 0; |
| 600 | } |
| 601 | |
| 602 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
| 603 | { |
| 604 | struct drm_device *dev = ppgtt->base.dev; |
| 605 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 606 | struct intel_ring_buffer *ring; |
| 607 | int j, ret; |
| 608 | |
| 609 | for_each_ring(ring, dev_priv, j) { |
| 610 | I915_WRITE(RING_MODE_GEN7(ring), |
| 611 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
| 612 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
| 613 | if (ret) |
| 614 | goto err_out; |
| 615 | } |
| 616 | |
| 617 | return 0; |
| 618 | |
| 619 | err_out: |
| 620 | for_each_ring(ring, dev_priv, j) |
| 621 | I915_WRITE(RING_MODE_GEN7(ring), |
| 622 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); |
| 623 | return ret; |
| 624 | } |
| 625 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 626 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
| 627 | { |
| 628 | struct drm_device *dev = ppgtt->base.dev; |
| 629 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 630 | struct intel_ring_buffer *ring; |
| 631 | uint32_t ecochk, ecobits; |
| 632 | int i; |
| 633 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 634 | ecobits = I915_READ(GAC_ECO_BITS); |
| 635 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); |
| 636 | |
| 637 | ecochk = I915_READ(GAM_ECOCHK); |
| 638 | if (IS_HASWELL(dev)) { |
| 639 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
| 640 | } else { |
| 641 | ecochk |= ECOCHK_PPGTT_LLC_IVB; |
| 642 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; |
| 643 | } |
| 644 | I915_WRITE(GAM_ECOCHK, ecochk); |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 645 | |
| 646 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 647 | int ret; |
| 648 | /* GFX_MODE is per-ring on gen7+ */ |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 649 | I915_WRITE(RING_MODE_GEN7(ring), |
| 650 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 651 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
| 652 | if (ret) |
| 653 | return ret; |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 654 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 655 | } |
| 656 | return 0; |
| 657 | } |
| 658 | |
Ben Widawsky | a3d67d2 | 2013-12-06 14:11:06 -0800 | [diff] [blame] | 659 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 660 | { |
Ben Widawsky | a3d67d2 | 2013-12-06 14:11:06 -0800 | [diff] [blame] | 661 | struct drm_device *dev = ppgtt->base.dev; |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 662 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 663 | struct intel_ring_buffer *ring; |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 664 | uint32_t ecochk, gab_ctl, ecobits; |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 665 | int i; |
| 666 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 667 | ecobits = I915_READ(GAC_ECO_BITS); |
| 668 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
| 669 | ECOBITS_PPGTT_CACHE64B); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 670 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 671 | gab_ctl = I915_READ(GAB_CTL); |
| 672 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 673 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 674 | ecochk = I915_READ(GAM_ECOCHK); |
| 675 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 676 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 677 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 678 | |
| 679 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 680 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
| 681 | if (ret) |
| 682 | return ret; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 683 | } |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 684 | |
Ben Widawsky | b7c36d2 | 2013-04-08 18:43:56 -0700 | [diff] [blame] | 685 | return 0; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 686 | } |
| 687 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 688 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 689 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 690 | unsigned first_entry, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 691 | unsigned num_entries, |
| 692 | bool use_scratch) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 693 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 694 | struct i915_hw_ppgtt *ppgtt = |
| 695 | container_of(vm, struct i915_hw_ppgtt, base); |
Ben Widawsky | e7c2b58 | 2013-04-08 18:43:48 -0700 | [diff] [blame] | 696 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 697 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 698 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
| 699 | unsigned last_pte, i; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 700 | |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 701 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 702 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 703 | while (num_entries) { |
| 704 | last_pte = first_pte + num_entries; |
| 705 | if (last_pte > I915_PPGTT_PT_ENTRIES) |
| 706 | last_pte = I915_PPGTT_PT_ENTRIES; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 707 | |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 708 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 709 | |
| 710 | for (i = first_pte; i < last_pte; i++) |
| 711 | pt_vaddr[i] = scratch_pte; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 712 | |
| 713 | kunmap_atomic(pt_vaddr); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 714 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 715 | num_entries -= last_pte - first_pte; |
| 716 | first_pte = 0; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 717 | act_pt++; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 718 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 719 | } |
| 720 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 721 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 722 | struct sg_table *pages, |
| 723 | unsigned first_entry, |
| 724 | enum i915_cache_level cache_level) |
| 725 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 726 | struct i915_hw_ppgtt *ppgtt = |
| 727 | container_of(vm, struct i915_hw_ppgtt, base); |
Ben Widawsky | e7c2b58 | 2013-04-08 18:43:48 -0700 | [diff] [blame] | 728 | gen6_gtt_pte_t *pt_vaddr; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 729 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 730 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
| 731 | struct sg_page_iter sg_iter; |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 732 | |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 733 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 734 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
| 735 | dma_addr_t page_addr; |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 736 | |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 737 | page_addr = sg_page_iter_dma_address(&sg_iter); |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 738 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 739 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
| 740 | kunmap_atomic(pt_vaddr); |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 741 | act_pt++; |
| 742 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 743 | act_pte = 0; |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 744 | |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 745 | } |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 746 | } |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 747 | kunmap_atomic(pt_vaddr); |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 748 | } |
| 749 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 750 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 751 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 752 | struct i915_hw_ppgtt *ppgtt = |
| 753 | container_of(vm, struct i915_hw_ppgtt, base); |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 754 | int i; |
| 755 | |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 756 | drm_mm_takedown(&ppgtt->base.mm); |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 757 | drm_mm_remove_node(&ppgtt->node); |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 758 | |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 759 | if (ppgtt->pt_dma_addr) { |
| 760 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 761 | pci_unmap_page(ppgtt->base.dev->pdev, |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 762 | ppgtt->pt_dma_addr[i], |
| 763 | 4096, PCI_DMA_BIDIRECTIONAL); |
| 764 | } |
| 765 | |
| 766 | kfree(ppgtt->pt_dma_addr); |
| 767 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
| 768 | __free_page(ppgtt->pt_pages[i]); |
| 769 | kfree(ppgtt->pt_pages); |
| 770 | kfree(ppgtt); |
| 771 | } |
| 772 | |
| 773 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
| 774 | { |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 775 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
| 776 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 777 | struct drm_device *dev = ppgtt->base.dev; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 778 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 779 | bool retried = false; |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 780 | int i, ret; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 781 | |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 782 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
| 783 | * allocator works in address space sizes, so it's multiplied by page |
| 784 | * size. We allocate at the top of the GTT to avoid fragmentation. |
| 785 | */ |
| 786 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 787 | alloc: |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 788 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
| 789 | &ppgtt->node, GEN6_PD_SIZE, |
| 790 | GEN6_PD_ALIGN, 0, |
| 791 | 0, dev_priv->gtt.base.total, |
| 792 | DRM_MM_SEARCH_DEFAULT); |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 793 | if (ret == -ENOSPC && !retried) { |
| 794 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, |
| 795 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
| 796 | I915_CACHE_NONE, false, true); |
| 797 | if (ret) |
| 798 | return ret; |
| 799 | |
| 800 | retried = true; |
| 801 | goto alloc; |
| 802 | } |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 803 | |
| 804 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
| 805 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 806 | |
Chris Wilson | 08c4526 | 2013-07-30 19:04:37 +0100 | [diff] [blame] | 807 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
Ben Widawsky | 6670a5a | 2013-06-27 16:30:04 -0700 | [diff] [blame] | 808 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 809 | if (IS_GEN6(dev)) { |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 810 | ppgtt->enable = gen6_ppgtt_enable; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 811 | ppgtt->switch_mm = gen6_mm_switch; |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 812 | } else if (IS_HASWELL(dev)) { |
| 813 | ppgtt->enable = gen7_ppgtt_enable; |
| 814 | ppgtt->switch_mm = hsw_mm_switch; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 815 | } else if (IS_GEN7(dev)) { |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 816 | ppgtt->enable = gen7_ppgtt_enable; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 817 | ppgtt->switch_mm = gen7_mm_switch; |
| 818 | } else |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 819 | BUG(); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 820 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
| 821 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; |
| 822 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
| 823 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
Ben Widawsky | 686e1f6f | 2013-11-25 09:54:34 -0800 | [diff] [blame] | 824 | ppgtt->base.start = 0; |
| 825 | ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
Daniel Vetter | a1e2265 | 2013-09-21 00:35:38 +0200 | [diff] [blame] | 826 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 827 | GFP_KERNEL); |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 828 | if (!ppgtt->pt_pages) { |
| 829 | drm_mm_remove_node(&ppgtt->node); |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 830 | return -ENOMEM; |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 831 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 832 | |
| 833 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 834 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); |
| 835 | if (!ppgtt->pt_pages[i]) |
| 836 | goto err_pt_alloc; |
| 837 | } |
| 838 | |
Daniel Vetter | a1e2265 | 2013-09-21 00:35:38 +0200 | [diff] [blame] | 839 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 840 | GFP_KERNEL); |
| 841 | if (!ppgtt->pt_dma_addr) |
| 842 | goto err_pt_alloc; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 843 | |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 844 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 845 | dma_addr_t pt_addr; |
Daniel Vetter | 211c568 | 2012-04-10 17:29:17 +0200 | [diff] [blame] | 846 | |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 847 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
| 848 | PCI_DMA_BIDIRECTIONAL); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 849 | |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 850 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
| 851 | ret = -EIO; |
| 852 | goto err_pd_pin; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 853 | |
Daniel Vetter | 211c568 | 2012-04-10 17:29:17 +0200 | [diff] [blame] | 854 | } |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 855 | ppgtt->pt_dma_addr[i] = pt_addr; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 856 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 857 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 858 | ppgtt->base.clear_range(&ppgtt->base, 0, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 859 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 860 | |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 861 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
| 862 | ppgtt->node.size >> 20, |
| 863 | ppgtt->node.start / PAGE_SIZE); |
| 864 | ppgtt->pd_offset = |
| 865 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 866 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 867 | return 0; |
| 868 | |
| 869 | err_pd_pin: |
| 870 | if (ppgtt->pt_dma_addr) { |
| 871 | for (i--; i >= 0; i--) |
| 872 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], |
| 873 | 4096, PCI_DMA_BIDIRECTIONAL); |
| 874 | } |
| 875 | err_pt_alloc: |
| 876 | kfree(ppgtt->pt_dma_addr); |
| 877 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 878 | if (ppgtt->pt_pages[i]) |
| 879 | __free_page(ppgtt->pt_pages[i]); |
| 880 | } |
| 881 | kfree(ppgtt->pt_pages); |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 882 | drm_mm_remove_node(&ppgtt->node); |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 883 | |
| 884 | return ret; |
| 885 | } |
| 886 | |
Ben Widawsky | 246cbfb | 2013-12-06 14:11:14 -0800 | [diff] [blame] | 887 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 888 | { |
| 889 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | d6660ad | 2013-12-06 14:11:13 -0800 | [diff] [blame] | 890 | int ret = 0; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 891 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 892 | ppgtt->base.dev = dev; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 893 | |
Ben Widawsky | 3ed124b | 2013-04-08 18:43:53 -0700 | [diff] [blame] | 894 | if (INTEL_INFO(dev)->gen < 8) |
| 895 | ret = gen6_ppgtt_init(ppgtt); |
Daniel Vetter | 8fe6bd2 | 2013-11-02 21:07:01 -0700 | [diff] [blame] | 896 | else if (IS_GEN8(dev)) |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 897 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
Ben Widawsky | 3ed124b | 2013-04-08 18:43:53 -0700 | [diff] [blame] | 898 | else |
| 899 | BUG(); |
| 900 | |
Ben Widawsky | c7c48df | 2013-12-06 14:11:15 -0800 | [diff] [blame] | 901 | if (!ret) { |
| 902 | kref_init(&ppgtt->ref); |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 903 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
| 904 | ppgtt->base.total); |
Ben Widawsky | 9f273d4 | 2013-12-06 14:11:16 -0800 | [diff] [blame^] | 905 | if (INTEL_INFO(dev)->gen < 8) |
| 906 | gen6_write_pdes(ppgtt); |
Ben Widawsky | c7c48df | 2013-12-06 14:11:15 -0800 | [diff] [blame] | 907 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 908 | |
| 909 | return ret; |
| 910 | } |
| 911 | |
| 912 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) |
| 913 | { |
| 914 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 915 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 916 | |
| 917 | if (!ppgtt) |
| 918 | return; |
| 919 | |
Ben Widawsky | c7c48df | 2013-12-06 14:11:15 -0800 | [diff] [blame] | 920 | kref_put(&dev_priv->mm.aliasing_ppgtt->ref, ppgtt_release); |
| 921 | |
Ben Widawsky | 5963cf0 | 2013-04-08 18:43:55 -0700 | [diff] [blame] | 922 | dev_priv->mm.aliasing_ppgtt = NULL; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 923 | } |
| 924 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 925 | static void __always_unused |
| 926 | ppgtt_bind_vma(struct i915_vma *vma, |
| 927 | enum i915_cache_level cache_level, |
| 928 | u32 flags) |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 929 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 930 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
| 931 | |
| 932 | WARN_ON(flags); |
| 933 | |
| 934 | vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 935 | } |
| 936 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 937 | static void __always_unused ppgtt_unbind_vma(struct i915_vma *vma) |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 938 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 939 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
| 940 | |
| 941 | vma->vm->clear_range(vma->vm, |
| 942 | entry, |
| 943 | vma->obj->base.size >> PAGE_SHIFT, |
| 944 | true); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 945 | } |
| 946 | |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 947 | extern int intel_iommu_gfx_mapped; |
| 948 | /* Certain Gen5 chipsets require require idling the GPU before |
| 949 | * unmapping anything from the GTT when VT-d is enabled. |
| 950 | */ |
| 951 | static inline bool needs_idle_maps(struct drm_device *dev) |
| 952 | { |
| 953 | #ifdef CONFIG_INTEL_IOMMU |
| 954 | /* Query intel_iommu to see if we need the workaround. Presumably that |
| 955 | * was loaded first. |
| 956 | */ |
| 957 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) |
| 958 | return true; |
| 959 | #endif |
| 960 | return false; |
| 961 | } |
| 962 | |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 963 | static bool do_idling(struct drm_i915_private *dev_priv) |
| 964 | { |
| 965 | bool ret = dev_priv->mm.interruptible; |
| 966 | |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 967 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 968 | dev_priv->mm.interruptible = false; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 969 | if (i915_gpu_idle(dev_priv->dev)) { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 970 | DRM_ERROR("Couldn't idle GPU\n"); |
| 971 | /* Wait a bit, in hopes it avoids the hang */ |
| 972 | udelay(10); |
| 973 | } |
| 974 | } |
| 975 | |
| 976 | return ret; |
| 977 | } |
| 978 | |
| 979 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) |
| 980 | { |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 981 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 982 | dev_priv->mm.interruptible = interruptible; |
| 983 | } |
| 984 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 985 | void i915_check_and_clear_faults(struct drm_device *dev) |
| 986 | { |
| 987 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 988 | struct intel_ring_buffer *ring; |
| 989 | int i; |
| 990 | |
| 991 | if (INTEL_INFO(dev)->gen < 6) |
| 992 | return; |
| 993 | |
| 994 | for_each_ring(ring, dev_priv, i) { |
| 995 | u32 fault_reg; |
| 996 | fault_reg = I915_READ(RING_FAULT_REG(ring)); |
| 997 | if (fault_reg & RING_FAULT_VALID) { |
| 998 | DRM_DEBUG_DRIVER("Unexpected fault\n" |
| 999 | "\tAddr: 0x%08lx\\n" |
| 1000 | "\tAddress space: %s\n" |
| 1001 | "\tSource ID: %d\n" |
| 1002 | "\tType: %d\n", |
| 1003 | fault_reg & PAGE_MASK, |
| 1004 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", |
| 1005 | RING_FAULT_SRCID(fault_reg), |
| 1006 | RING_FAULT_FAULT_TYPE(fault_reg)); |
| 1007 | I915_WRITE(RING_FAULT_REG(ring), |
| 1008 | fault_reg & ~RING_FAULT_VALID); |
| 1009 | } |
| 1010 | } |
| 1011 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); |
| 1012 | } |
| 1013 | |
| 1014 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
| 1015 | { |
| 1016 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1017 | |
| 1018 | /* Don't bother messing with faults pre GEN6 as we have little |
| 1019 | * documentation supporting that it's a good idea. |
| 1020 | */ |
| 1021 | if (INTEL_INFO(dev)->gen < 6) |
| 1022 | return; |
| 1023 | |
| 1024 | i915_check_and_clear_faults(dev); |
| 1025 | |
| 1026 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
| 1027 | dev_priv->gtt.base.start / PAGE_SIZE, |
| 1028 | dev_priv->gtt.base.total / PAGE_SIZE, |
| 1029 | false); |
| 1030 | } |
| 1031 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1032 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
| 1033 | { |
| 1034 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1035 | struct drm_i915_gem_object *obj; |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1036 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1037 | i915_check_and_clear_faults(dev); |
| 1038 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 1039 | /* First fill our portion of the GTT with scratch pages */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1040 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
| 1041 | dev_priv->gtt.base.start / PAGE_SIZE, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1042 | dev_priv->gtt.base.total / PAGE_SIZE, |
| 1043 | true); |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 1044 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1045 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1046 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
| 1047 | &dev_priv->gtt.base); |
| 1048 | if (!vma) |
| 1049 | continue; |
| 1050 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1051 | i915_gem_clflush_object(obj, obj->pin_display); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1052 | /* The bind_vma code tries to be smart about tracking mappings. |
| 1053 | * Unfortunately above, we've just wiped out the mappings |
| 1054 | * without telling our object about it. So we need to fake it. |
| 1055 | */ |
| 1056 | obj->has_global_gtt_mapping = 0; |
| 1057 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1058 | } |
| 1059 | |
Ben Widawsky | 9f273d4 | 2013-12-06 14:11:16 -0800 | [diff] [blame^] | 1060 | if (dev_priv->mm.aliasing_ppgtt) |
| 1061 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); |
| 1062 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1063 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1064 | } |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1065 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1066 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1067 | { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1068 | if (obj->has_dma_mapping) |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1069 | return 0; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1070 | |
| 1071 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
| 1072 | obj->pages->sgl, obj->pages->nents, |
| 1073 | PCI_DMA_BIDIRECTIONAL)) |
| 1074 | return -ENOSPC; |
| 1075 | |
| 1076 | return 0; |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1077 | } |
| 1078 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1079 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
| 1080 | { |
| 1081 | #ifdef writeq |
| 1082 | writeq(pte, addr); |
| 1083 | #else |
| 1084 | iowrite32((u32)pte, addr); |
| 1085 | iowrite32(pte >> 32, addr + 4); |
| 1086 | #endif |
| 1087 | } |
| 1088 | |
| 1089 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
| 1090 | struct sg_table *st, |
| 1091 | unsigned int first_entry, |
| 1092 | enum i915_cache_level level) |
| 1093 | { |
| 1094 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
| 1095 | gen8_gtt_pte_t __iomem *gtt_entries = |
| 1096 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
| 1097 | int i = 0; |
| 1098 | struct sg_page_iter sg_iter; |
| 1099 | dma_addr_t addr; |
| 1100 | |
| 1101 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
| 1102 | addr = sg_dma_address(sg_iter.sg) + |
| 1103 | (sg_iter.sg_pgoffset << PAGE_SHIFT); |
| 1104 | gen8_set_pte(>t_entries[i], |
| 1105 | gen8_pte_encode(addr, level, true)); |
| 1106 | i++; |
| 1107 | } |
| 1108 | |
| 1109 | /* |
| 1110 | * XXX: This serves as a posting read to make sure that the PTE has |
| 1111 | * actually been updated. There is some concern that even though |
| 1112 | * registers and PTEs are within the same BAR that they are potentially |
| 1113 | * of NUMA access patterns. Therefore, even with the way we assume |
| 1114 | * hardware should work, we must keep this posting read for paranoia. |
| 1115 | */ |
| 1116 | if (i != 0) |
| 1117 | WARN_ON(readq(>t_entries[i-1]) |
| 1118 | != gen8_pte_encode(addr, level, true)); |
| 1119 | |
| 1120 | #if 0 /* TODO: Still needed on GEN8? */ |
| 1121 | /* This next bit makes the above posting read even more important. We |
| 1122 | * want to flush the TLBs only after we're certain all the PTE updates |
| 1123 | * have finished. |
| 1124 | */ |
| 1125 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
| 1126 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
| 1127 | #endif |
| 1128 | } |
| 1129 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1130 | /* |
| 1131 | * Binds an object into the global gtt with the specified cache level. The object |
| 1132 | * will be accessible to the GPU via commands whose operands reference offsets |
| 1133 | * within the global GTT as well as accessible by the GPU through the GMADR |
| 1134 | * mapped BAR (dev_priv->mm.gtt->gtt). |
| 1135 | */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1136 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1137 | struct sg_table *st, |
| 1138 | unsigned int first_entry, |
| 1139 | enum i915_cache_level level) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1140 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1141 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | e7c2b58 | 2013-04-08 18:43:48 -0700 | [diff] [blame] | 1142 | gen6_gtt_pte_t __iomem *gtt_entries = |
| 1143 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1144 | int i = 0; |
| 1145 | struct sg_page_iter sg_iter; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1146 | dma_addr_t addr; |
| 1147 | |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1148 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1149 | addr = sg_page_iter_dma_address(&sg_iter); |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 1150 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1151 | i++; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1152 | } |
| 1153 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1154 | /* XXX: This serves as a posting read to make sure that the PTE has |
| 1155 | * actually been updated. There is some concern that even though |
| 1156 | * registers and PTEs are within the same BAR that they are potentially |
| 1157 | * of NUMA access patterns. Therefore, even with the way we assume |
| 1158 | * hardware should work, we must keep this posting read for paranoia. |
| 1159 | */ |
| 1160 | if (i != 0) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1161 | WARN_ON(readl(>t_entries[i-1]) != |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 1162 | vm->pte_encode(addr, level, true)); |
Ben Widawsky | 0f9b91c | 2012-11-04 09:21:30 -0800 | [diff] [blame] | 1163 | |
| 1164 | /* This next bit makes the above posting read even more important. We |
| 1165 | * want to flush the TLBs only after we're certain all the PTE updates |
| 1166 | * have finished. |
| 1167 | */ |
| 1168 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
| 1169 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1170 | } |
| 1171 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1172 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
| 1173 | unsigned int first_entry, |
| 1174 | unsigned int num_entries, |
| 1175 | bool use_scratch) |
| 1176 | { |
| 1177 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
| 1178 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
| 1179 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
| 1180 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
| 1181 | int i; |
| 1182 | |
| 1183 | if (WARN(num_entries > max_entries, |
| 1184 | "First entry = %d; Num entries = %d (max=%d)\n", |
| 1185 | first_entry, num_entries, max_entries)) |
| 1186 | num_entries = max_entries; |
| 1187 | |
| 1188 | scratch_pte = gen8_pte_encode(vm->scratch.addr, |
| 1189 | I915_CACHE_LLC, |
| 1190 | use_scratch); |
| 1191 | for (i = 0; i < num_entries; i++) |
| 1192 | gen8_set_pte(>t_base[i], scratch_pte); |
| 1193 | readl(gtt_base); |
| 1194 | } |
| 1195 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1196 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1197 | unsigned int first_entry, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1198 | unsigned int num_entries, |
| 1199 | bool use_scratch) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1200 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1201 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | e7c2b58 | 2013-04-08 18:43:48 -0700 | [diff] [blame] | 1202 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
| 1203 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
Ben Widawsky | a54c0c2 | 2013-01-24 14:45:00 -0800 | [diff] [blame] | 1204 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1205 | int i; |
| 1206 | |
| 1207 | if (WARN(num_entries > max_entries, |
| 1208 | "First entry = %d; Num entries = %d (max=%d)\n", |
| 1209 | first_entry, num_entries, max_entries)) |
| 1210 | num_entries = max_entries; |
| 1211 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1212 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
| 1213 | |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1214 | for (i = 0; i < num_entries; i++) |
| 1215 | iowrite32(scratch_pte, >t_base[i]); |
| 1216 | readl(gtt_base); |
| 1217 | } |
| 1218 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1219 | |
| 1220 | static void i915_ggtt_bind_vma(struct i915_vma *vma, |
| 1221 | enum i915_cache_level cache_level, |
| 1222 | u32 unused) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1223 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1224 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1225 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
| 1226 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; |
| 1227 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1228 | BUG_ON(!i915_is_ggtt(vma->vm)); |
| 1229 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); |
| 1230 | vma->obj->has_global_gtt_mapping = 1; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1231 | } |
| 1232 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1233 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1234 | unsigned int first_entry, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1235 | unsigned int num_entries, |
| 1236 | bool unused) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1237 | { |
| 1238 | intel_gtt_clear_range(first_entry, num_entries); |
| 1239 | } |
| 1240 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1241 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
Chris Wilson | d5bd144 | 2011-04-14 06:48:26 +0100 | [diff] [blame] | 1242 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1243 | const unsigned int first = vma->node.start >> PAGE_SHIFT; |
| 1244 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1245 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1246 | BUG_ON(!i915_is_ggtt(vma->vm)); |
| 1247 | vma->obj->has_global_gtt_mapping = 0; |
| 1248 | intel_gtt_clear_range(first, size); |
Chris Wilson | d5bd144 | 2011-04-14 06:48:26 +0100 | [diff] [blame] | 1249 | } |
| 1250 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1251 | static void ggtt_bind_vma(struct i915_vma *vma, |
| 1252 | enum i915_cache_level cache_level, |
| 1253 | u32 flags) |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1254 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1255 | struct drm_device *dev = vma->vm->dev; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1256 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1257 | struct drm_i915_gem_object *obj = vma->obj; |
| 1258 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1259 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1260 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
| 1261 | * or we have a global mapping already but the cacheability flags have |
| 1262 | * changed, set the global PTEs. |
| 1263 | * |
| 1264 | * If there is an aliasing PPGTT it is anecdotally faster, so use that |
| 1265 | * instead if none of the above hold true. |
| 1266 | * |
| 1267 | * NB: A global mapping should only be needed for special regions like |
| 1268 | * "gtt mappable", SNB errata, or if specified via special execbuf |
| 1269 | * flags. At all other times, the GPU will use the aliasing PPGTT. |
| 1270 | */ |
| 1271 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
| 1272 | if (!obj->has_global_gtt_mapping || |
| 1273 | (cache_level != obj->cache_level)) { |
| 1274 | vma->vm->insert_entries(vma->vm, obj->pages, entry, |
| 1275 | cache_level); |
| 1276 | obj->has_global_gtt_mapping = 1; |
| 1277 | } |
| 1278 | } |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1279 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1280 | if (dev_priv->mm.aliasing_ppgtt && |
| 1281 | (!obj->has_aliasing_ppgtt_mapping || |
| 1282 | (cache_level != obj->cache_level))) { |
| 1283 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
| 1284 | appgtt->base.insert_entries(&appgtt->base, |
| 1285 | vma->obj->pages, entry, cache_level); |
| 1286 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
| 1287 | } |
| 1288 | } |
| 1289 | |
| 1290 | static void ggtt_unbind_vma(struct i915_vma *vma) |
| 1291 | { |
| 1292 | struct drm_device *dev = vma->vm->dev; |
| 1293 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1294 | struct drm_i915_gem_object *obj = vma->obj; |
| 1295 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
| 1296 | |
| 1297 | if (obj->has_global_gtt_mapping) { |
| 1298 | vma->vm->clear_range(vma->vm, entry, |
| 1299 | vma->obj->base.size >> PAGE_SHIFT, |
| 1300 | true); |
| 1301 | obj->has_global_gtt_mapping = 0; |
| 1302 | } |
| 1303 | |
| 1304 | if (obj->has_aliasing_ppgtt_mapping) { |
| 1305 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
| 1306 | appgtt->base.clear_range(&appgtt->base, |
| 1307 | entry, |
| 1308 | obj->base.size >> PAGE_SHIFT, |
| 1309 | true); |
| 1310 | obj->has_aliasing_ppgtt_mapping = 0; |
| 1311 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1312 | } |
| 1313 | |
| 1314 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) |
| 1315 | { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1316 | struct drm_device *dev = obj->base.dev; |
| 1317 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1318 | bool interruptible; |
| 1319 | |
| 1320 | interruptible = do_idling(dev_priv); |
| 1321 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1322 | if (!obj->has_dma_mapping) |
| 1323 | dma_unmap_sg(&dev->pdev->dev, |
| 1324 | obj->pages->sgl, obj->pages->nents, |
| 1325 | PCI_DMA_BIDIRECTIONAL); |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1326 | |
| 1327 | undo_idling(dev_priv, interruptible); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1328 | } |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1329 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 1330 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
| 1331 | unsigned long color, |
| 1332 | unsigned long *start, |
| 1333 | unsigned long *end) |
| 1334 | { |
| 1335 | if (node->color != color) |
| 1336 | *start += 4096; |
| 1337 | |
| 1338 | if (!list_empty(&node->node_list)) { |
| 1339 | node = list_entry(node->node_list.next, |
| 1340 | struct drm_mm_node, |
| 1341 | node_list); |
| 1342 | if (node->allocated && node->color != color) |
| 1343 | *end -= 4096; |
| 1344 | } |
| 1345 | } |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 1346 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 1347 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
| 1348 | unsigned long start, |
| 1349 | unsigned long mappable_end, |
| 1350 | unsigned long end) |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1351 | { |
Ben Widawsky | e78891c | 2013-01-25 16:41:04 -0800 | [diff] [blame] | 1352 | /* Let GEM Manage all of the aperture. |
| 1353 | * |
| 1354 | * However, leave one page at the end still bound to the scratch page. |
| 1355 | * There are a number of places where the hardware apparently prefetches |
| 1356 | * past the end of the object, and we've seen multiple hangs with the |
| 1357 | * GPU head pointer stuck in a batchbuffer bound at the last page of the |
| 1358 | * aperture. One page should be enough to keep any prefetching inside |
| 1359 | * of the aperture. |
| 1360 | */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1361 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1362 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1363 | struct drm_mm_node *entry; |
| 1364 | struct drm_i915_gem_object *obj; |
| 1365 | unsigned long hole_start, hole_end; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1366 | |
Ben Widawsky | 35451cb | 2013-01-17 12:45:13 -0800 | [diff] [blame] | 1367 | BUG_ON(mappable_end > end); |
| 1368 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1369 | /* Subtract the guard page ... */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1370 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 1371 | if (!HAS_LLC(dev)) |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 1372 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1373 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1374 | /* Mark any preallocated objects as occupied */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1375 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1376 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
Ben Widawsky | b3a070c | 2013-07-05 14:41:02 -0700 | [diff] [blame] | 1377 | int ret; |
Ben Widawsky | edd41a8 | 2013-07-05 14:41:05 -0700 | [diff] [blame] | 1378 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 1379 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1380 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 1381 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1382 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 1383 | if (ret) |
Ben Widawsky | b3a070c | 2013-07-05 14:41:02 -0700 | [diff] [blame] | 1384 | DRM_DEBUG_KMS("Reservation failed\n"); |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1385 | obj->has_global_gtt_mapping = 1; |
| 1386 | } |
| 1387 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1388 | dev_priv->gtt.base.start = start; |
| 1389 | dev_priv->gtt.base.total = end - start; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1390 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1391 | /* Clear any non-preallocated blocks */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1392 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1393 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1394 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
| 1395 | hole_start, hole_end); |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1396 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1397 | } |
| 1398 | |
| 1399 | /* And finally clear the reserved guard page */ |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1400 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1401 | } |
| 1402 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 1403 | void i915_gem_init_global_gtt(struct drm_device *dev) |
| 1404 | { |
| 1405 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1406 | unsigned long gtt_size, mappable_size; |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 1407 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1408 | gtt_size = dev_priv->gtt.base.total; |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 1409 | mappable_size = dev_priv->gtt.mappable_end; |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 1410 | |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 1411 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
Ben Widawsky | 246cbfb | 2013-12-06 14:11:14 -0800 | [diff] [blame] | 1412 | if (USES_ALIASING_PPGTT(dev)) { |
Ben Widawsky | d6660ad | 2013-12-06 14:11:13 -0800 | [diff] [blame] | 1413 | struct i915_hw_ppgtt *ppgtt; |
Ben Widawsky | e78891c | 2013-01-25 16:41:04 -0800 | [diff] [blame] | 1414 | int ret; |
Ben Widawsky | 3eb1c00 | 2013-04-08 18:43:52 -0700 | [diff] [blame] | 1415 | |
Ben Widawsky | d6660ad | 2013-12-06 14:11:13 -0800 | [diff] [blame] | 1416 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
| 1417 | if (!ppgtt) { |
| 1418 | DRM_ERROR("Aliased PPGTT setup failed -ENOMEM\n"); |
| 1419 | return; |
| 1420 | } |
| 1421 | |
| 1422 | ret = i915_gem_init_ppgtt(dev, ppgtt); |
| 1423 | if (!ret) { |
| 1424 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
| 1425 | return; |
| 1426 | } |
| 1427 | |
| 1428 | kfree(ppgtt); |
| 1429 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 1430 | } |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1431 | } |
| 1432 | |
| 1433 | static int setup_scratch_page(struct drm_device *dev) |
| 1434 | { |
| 1435 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1436 | struct page *page; |
| 1437 | dma_addr_t dma_addr; |
| 1438 | |
| 1439 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
| 1440 | if (page == NULL) |
| 1441 | return -ENOMEM; |
| 1442 | get_page(page); |
| 1443 | set_pages_uc(page, 1); |
| 1444 | |
| 1445 | #ifdef CONFIG_INTEL_IOMMU |
| 1446 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, |
| 1447 | PCI_DMA_BIDIRECTIONAL); |
| 1448 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) |
| 1449 | return -EINVAL; |
| 1450 | #else |
| 1451 | dma_addr = page_to_phys(page); |
| 1452 | #endif |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1453 | dev_priv->gtt.base.scratch.page = page; |
| 1454 | dev_priv->gtt.base.scratch.addr = dma_addr; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1455 | |
| 1456 | return 0; |
| 1457 | } |
| 1458 | |
| 1459 | static void teardown_scratch_page(struct drm_device *dev) |
| 1460 | { |
| 1461 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1462 | struct page *page = dev_priv->gtt.base.scratch.page; |
| 1463 | |
| 1464 | set_pages_wb(page, 1); |
| 1465 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1466 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1467 | put_page(page); |
| 1468 | __free_page(page); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1469 | } |
| 1470 | |
| 1471 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
| 1472 | { |
| 1473 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; |
| 1474 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; |
| 1475 | return snb_gmch_ctl << 20; |
| 1476 | } |
| 1477 | |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 1478 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
| 1479 | { |
| 1480 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; |
| 1481 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; |
| 1482 | if (bdw_gmch_ctl) |
| 1483 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; |
Ben Widawsky | 3a2ffb6 | 2013-11-07 21:40:51 -0800 | [diff] [blame] | 1484 | if (bdw_gmch_ctl > 4) { |
| 1485 | WARN_ON(!i915_preliminary_hw_support); |
| 1486 | return 4<<20; |
| 1487 | } |
| 1488 | |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 1489 | return bdw_gmch_ctl << 20; |
| 1490 | } |
| 1491 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1492 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1493 | { |
| 1494 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; |
| 1495 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; |
| 1496 | return snb_gmch_ctl << 25; /* 32 MB units */ |
| 1497 | } |
| 1498 | |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 1499 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
| 1500 | { |
| 1501 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; |
| 1502 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; |
| 1503 | return bdw_gmch_ctl << 25; /* 32 MB units */ |
| 1504 | } |
| 1505 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1506 | static int ggtt_probe_common(struct drm_device *dev, |
| 1507 | size_t gtt_size) |
| 1508 | { |
| 1509 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1510 | phys_addr_t gtt_bus_addr; |
| 1511 | int ret; |
| 1512 | |
| 1513 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
| 1514 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + |
| 1515 | (pci_resource_len(dev->pdev, 0) / 2); |
| 1516 | |
| 1517 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
| 1518 | if (!dev_priv->gtt.gsm) { |
| 1519 | DRM_ERROR("Failed to map the gtt page table\n"); |
| 1520 | return -ENOMEM; |
| 1521 | } |
| 1522 | |
| 1523 | ret = setup_scratch_page(dev); |
| 1524 | if (ret) { |
| 1525 | DRM_ERROR("Scratch setup failed\n"); |
| 1526 | /* iounmap will also get called at remove, but meh */ |
| 1527 | iounmap(dev_priv->gtt.gsm); |
| 1528 | } |
| 1529 | |
| 1530 | return ret; |
| 1531 | } |
| 1532 | |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 1533 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
| 1534 | * bits. When using advanced contexts each context stores its own PAT, but |
| 1535 | * writing this data shouldn't be harmful even in those cases. */ |
| 1536 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) |
| 1537 | { |
| 1538 | #define GEN8_PPAT_UC (0<<0) |
| 1539 | #define GEN8_PPAT_WC (1<<0) |
| 1540 | #define GEN8_PPAT_WT (2<<0) |
| 1541 | #define GEN8_PPAT_WB (3<<0) |
| 1542 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) |
| 1543 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ |
| 1544 | #define GEN8_PPAT_LLC (1<<2) |
| 1545 | #define GEN8_PPAT_LLCELLC (2<<2) |
| 1546 | #define GEN8_PPAT_LLCeLLC (3<<2) |
| 1547 | #define GEN8_PPAT_AGE(x) (x<<4) |
| 1548 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) |
| 1549 | uint64_t pat; |
| 1550 | |
| 1551 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ |
| 1552 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ |
| 1553 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ |
| 1554 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ |
| 1555 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | |
| 1556 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | |
| 1557 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | |
| 1558 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); |
| 1559 | |
| 1560 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
| 1561 | * write would work. */ |
| 1562 | I915_WRITE(GEN8_PRIVATE_PAT, pat); |
| 1563 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); |
| 1564 | } |
| 1565 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1566 | static int gen8_gmch_probe(struct drm_device *dev, |
| 1567 | size_t *gtt_total, |
| 1568 | size_t *stolen, |
| 1569 | phys_addr_t *mappable_base, |
| 1570 | unsigned long *mappable_end) |
| 1571 | { |
| 1572 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1573 | unsigned int gtt_size; |
| 1574 | u16 snb_gmch_ctl; |
| 1575 | int ret; |
| 1576 | |
| 1577 | /* TODO: We're not aware of mappable constraints on gen8 yet */ |
| 1578 | *mappable_base = pci_resource_start(dev->pdev, 2); |
| 1579 | *mappable_end = pci_resource_len(dev->pdev, 2); |
| 1580 | |
| 1581 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) |
| 1582 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); |
| 1583 | |
| 1584 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
| 1585 | |
| 1586 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); |
| 1587 | |
| 1588 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); |
Ben Widawsky | d31eb10 | 2013-11-02 21:07:17 -0700 | [diff] [blame] | 1589 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1590 | |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 1591 | gen8_setup_private_ppat(dev_priv); |
| 1592 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1593 | ret = ggtt_probe_common(dev, gtt_size); |
| 1594 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1595 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
| 1596 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1597 | |
| 1598 | return ret; |
| 1599 | } |
| 1600 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1601 | static int gen6_gmch_probe(struct drm_device *dev, |
| 1602 | size_t *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 1603 | size_t *stolen, |
| 1604 | phys_addr_t *mappable_base, |
| 1605 | unsigned long *mappable_end) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1606 | { |
| 1607 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1608 | unsigned int gtt_size; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1609 | u16 snb_gmch_ctl; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1610 | int ret; |
| 1611 | |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 1612 | *mappable_base = pci_resource_start(dev->pdev, 2); |
| 1613 | *mappable_end = pci_resource_len(dev->pdev, 2); |
| 1614 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1615 | /* 64/512MB is the current min/max we actually know of, but this is just |
| 1616 | * a coarse sanity check. |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1617 | */ |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 1618 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1619 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
| 1620 | dev_priv->gtt.mappable_end); |
| 1621 | return -ENXIO; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1622 | } |
| 1623 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1624 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
| 1625 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1626 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1627 | |
Ben Widawsky | c4ae25e | 2013-05-01 11:00:34 -0700 | [diff] [blame] | 1628 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1629 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1630 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1631 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
| 1632 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1633 | ret = ggtt_probe_common(dev, gtt_size); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1634 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1635 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
| 1636 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1637 | |
| 1638 | return ret; |
| 1639 | } |
| 1640 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1641 | static void gen6_gmch_remove(struct i915_address_space *vm) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1642 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1643 | |
| 1644 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); |
Ben Widawsky | 5ed1678 | 2013-11-25 09:54:43 -0800 | [diff] [blame] | 1645 | |
| 1646 | drm_mm_takedown(&vm->mm); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1647 | iounmap(gtt->gsm); |
| 1648 | teardown_scratch_page(vm->dev); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1649 | } |
| 1650 | |
| 1651 | static int i915_gmch_probe(struct drm_device *dev, |
| 1652 | size_t *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 1653 | size_t *stolen, |
| 1654 | phys_addr_t *mappable_base, |
| 1655 | unsigned long *mappable_end) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1656 | { |
| 1657 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1658 | int ret; |
| 1659 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1660 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
| 1661 | if (!ret) { |
| 1662 | DRM_ERROR("failed to set up gmch\n"); |
| 1663 | return -EIO; |
| 1664 | } |
| 1665 | |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 1666 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1667 | |
| 1668 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1669 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1670 | |
| 1671 | return 0; |
| 1672 | } |
| 1673 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1674 | static void i915_gmch_remove(struct i915_address_space *vm) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1675 | { |
| 1676 | intel_gmch_remove(); |
| 1677 | } |
| 1678 | |
| 1679 | int i915_gem_gtt_init(struct drm_device *dev) |
| 1680 | { |
| 1681 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1682 | struct i915_gtt *gtt = &dev_priv->gtt; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1683 | int ret; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1684 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1685 | if (INTEL_INFO(dev)->gen <= 5) { |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 1686 | gtt->gtt_probe = i915_gmch_probe; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1687 | gtt->base.cleanup = i915_gmch_remove; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1688 | } else if (INTEL_INFO(dev)->gen < 8) { |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 1689 | gtt->gtt_probe = gen6_gmch_probe; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1690 | gtt->base.cleanup = gen6_gmch_remove; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 1691 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1692 | gtt->base.pte_encode = iris_pte_encode; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 1693 | else if (IS_HASWELL(dev)) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1694 | gtt->base.pte_encode = hsw_pte_encode; |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 1695 | else if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1696 | gtt->base.pte_encode = byt_pte_encode; |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 1697 | else if (INTEL_INFO(dev)->gen >= 7) |
| 1698 | gtt->base.pte_encode = ivb_pte_encode; |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 1699 | else |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 1700 | gtt->base.pte_encode = snb_pte_encode; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1701 | } else { |
| 1702 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; |
| 1703 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1704 | } |
| 1705 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1706 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 1707 | >t->mappable_base, >t->mappable_end); |
Ben Widawsky | a54c0c2 | 2013-01-24 14:45:00 -0800 | [diff] [blame] | 1708 | if (ret) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1709 | return ret; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1710 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1711 | gtt->base.dev = dev; |
| 1712 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1713 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1714 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
| 1715 | gtt->base.total >> 20); |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 1716 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
| 1717 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1718 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1719 | return 0; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1720 | } |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1721 | |
| 1722 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, |
| 1723 | struct i915_address_space *vm) |
| 1724 | { |
| 1725 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
| 1726 | if (vma == NULL) |
| 1727 | return ERR_PTR(-ENOMEM); |
| 1728 | |
| 1729 | INIT_LIST_HEAD(&vma->vma_link); |
| 1730 | INIT_LIST_HEAD(&vma->mm_list); |
| 1731 | INIT_LIST_HEAD(&vma->exec_list); |
| 1732 | vma->vm = vm; |
| 1733 | vma->obj = obj; |
| 1734 | |
| 1735 | switch (INTEL_INFO(vm->dev)->gen) { |
| 1736 | case 8: |
| 1737 | case 7: |
| 1738 | case 6: |
| 1739 | vma->unbind_vma = ggtt_unbind_vma; |
| 1740 | vma->bind_vma = ggtt_bind_vma; |
| 1741 | break; |
| 1742 | case 5: |
| 1743 | case 4: |
| 1744 | case 3: |
| 1745 | case 2: |
| 1746 | BUG_ON(!i915_is_ggtt(vm)); |
| 1747 | vma->unbind_vma = i915_ggtt_unbind_vma; |
| 1748 | vma->bind_vma = i915_ggtt_bind_vma; |
| 1749 | break; |
| 1750 | default: |
| 1751 | BUG(); |
| 1752 | } |
| 1753 | |
| 1754 | /* Keep GGTT vmas first to make debug easier */ |
| 1755 | if (i915_is_ggtt(vm)) |
| 1756 | list_add(&vma->vma_link, &obj->vma_list); |
| 1757 | else |
| 1758 | list_add_tail(&vma->vma_link, &obj->vma_list); |
| 1759 | |
| 1760 | return vma; |
| 1761 | } |
| 1762 | |
| 1763 | struct i915_vma * |
| 1764 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
| 1765 | struct i915_address_space *vm) |
| 1766 | { |
| 1767 | struct i915_vma *vma; |
| 1768 | |
| 1769 | vma = i915_gem_obj_to_vma(obj, vm); |
| 1770 | if (!vma) |
| 1771 | vma = __i915_gem_vma_create(obj, vm); |
| 1772 | |
| 1773 | return vma; |
| 1774 | } |