Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 28 | #include <linux/dma-fence-array.h> |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 29 | #include <linux/interval_tree_generic.h> |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 30 | #include <drm/drmP.h> |
| 31 | #include <drm/amdgpu_drm.h> |
| 32 | #include "amdgpu.h" |
| 33 | #include "amdgpu_trace.h" |
| 34 | |
| 35 | /* |
| 36 | * GPUVM |
| 37 | * GPUVM is similar to the legacy gart on older asics, however |
| 38 | * rather than there being a single global gart table |
| 39 | * for the entire GPU, there are multiple VM page tables active |
| 40 | * at any given time. The VM page tables can contain a mix |
| 41 | * vram pages and system memory pages and system memory pages |
| 42 | * can be mapped as snooped (cached system pages) or unsnooped |
| 43 | * (uncached system pages). |
| 44 | * Each VM has an ID associated with it and there is a page table |
| 45 | * associated with each VMID. When execting a command buffer, |
| 46 | * the kernel tells the the ring what VMID to use for that command |
| 47 | * buffer. VMIDs are allocated dynamically as commands are submitted. |
| 48 | * The userspace drivers maintain their own address space and the kernel |
| 49 | * sets up their pages tables accordingly when they submit their |
| 50 | * command buffers and a VMID is assigned. |
| 51 | * Cayman/Trinity support up to 8 active VMs at any given time; |
| 52 | * SI supports 16. |
| 53 | */ |
| 54 | |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 55 | #define START(node) ((node)->start) |
| 56 | #define LAST(node) ((node)->last) |
| 57 | |
| 58 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, |
| 59 | START, LAST, static, amdgpu_vm_it) |
| 60 | |
| 61 | #undef START |
| 62 | #undef LAST |
| 63 | |
Harish Kasiviswanathan | f4833c4 | 2016-04-21 10:40:18 -0400 | [diff] [blame] | 64 | /* Local structure. Encapsulate some VM table update parameters to reduce |
| 65 | * the number of function parameters |
| 66 | */ |
Christian König | 29efc4f | 2016-08-04 14:52:50 +0200 | [diff] [blame] | 67 | struct amdgpu_pte_update_params { |
Christian König | 27c5f36 | 2016-08-04 15:02:49 +0200 | [diff] [blame] | 68 | /* amdgpu device we do this update for */ |
| 69 | struct amdgpu_device *adev; |
Christian König | 49ac8a2 | 2016-10-13 15:09:08 +0200 | [diff] [blame] | 70 | /* optional amdgpu_vm we do this update for */ |
| 71 | struct amdgpu_vm *vm; |
Harish Kasiviswanathan | f4833c4 | 2016-04-21 10:40:18 -0400 | [diff] [blame] | 72 | /* address where to copy page table entries from */ |
| 73 | uint64_t src; |
Harish Kasiviswanathan | f4833c4 | 2016-04-21 10:40:18 -0400 | [diff] [blame] | 74 | /* indirect buffer to fill with commands */ |
| 75 | struct amdgpu_ib *ib; |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 76 | /* Function which actually does the update */ |
| 77 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, |
| 78 | uint64_t addr, unsigned count, uint32_t incr, |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 79 | uint64_t flags); |
Harish Kasiviswanathan | b4d4251 | 2017-05-11 19:47:22 -0400 | [diff] [blame] | 80 | /* The next two are used during VM update by CPU |
| 81 | * DMA addresses to use for mapping |
| 82 | * Kernel pointer of PD/PT BO that needs to be updated |
| 83 | */ |
| 84 | dma_addr_t *pages_addr; |
| 85 | void *kptr; |
Harish Kasiviswanathan | f4833c4 | 2016-04-21 10:40:18 -0400 | [diff] [blame] | 86 | }; |
| 87 | |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 88 | /* Helper to disable partial resident texture feature from a fence callback */ |
| 89 | struct amdgpu_prt_cb { |
| 90 | struct amdgpu_device *adev; |
| 91 | struct dma_fence_cb cb; |
| 92 | }; |
| 93 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 94 | /** |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 95 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 96 | * |
| 97 | * @adev: amdgpu_device pointer |
| 98 | * |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 99 | * Calculate the number of entries in a page directory or page table. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 100 | */ |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 101 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
| 102 | unsigned level) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 103 | { |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 104 | if (level == 0) |
| 105 | /* For the root directory */ |
| 106 | return adev->vm_manager.max_pfn >> |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 107 | (adev->vm_manager.block_size * |
| 108 | adev->vm_manager.num_level); |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 109 | else if (level == adev->vm_manager.num_level) |
| 110 | /* For the page tables on the leaves */ |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 111 | return AMDGPU_VM_PTE_COUNT(adev); |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 112 | else |
| 113 | /* Everything in between */ |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 114 | return 1 << adev->vm_manager.block_size; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | /** |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 118 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 119 | * |
| 120 | * @adev: amdgpu_device pointer |
| 121 | * |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 122 | * Calculate the size of the BO for a page directory or page table in bytes. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 123 | */ |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 124 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 125 | { |
Christian König | 72a7ec5 | 2016-10-19 11:03:57 +0200 | [diff] [blame] | 126 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | /** |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 130 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 131 | * |
| 132 | * @vm: vm providing the BOs |
Christian König | 3c0eea6 | 2015-12-11 14:39:05 +0100 | [diff] [blame] | 133 | * @validated: head of validation list |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 134 | * @entry: entry to add |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 135 | * |
| 136 | * Add the page directory to the list of BOs to |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 137 | * validate for command submission. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 138 | */ |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 139 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
| 140 | struct list_head *validated, |
| 141 | struct amdgpu_bo_list_entry *entry) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 142 | { |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 143 | entry->robj = vm->root.bo; |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 144 | entry->priority = 0; |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 145 | entry->tv.bo = &entry->robj->tbo; |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 146 | entry->tv.shared = true; |
Christian König | 2f568db | 2016-02-23 12:36:59 +0100 | [diff] [blame] | 147 | entry->user_pages = NULL; |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 148 | list_add(&entry->tv.head, validated); |
| 149 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 150 | |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 151 | /** |
Christian König | 670fecc | 2016-10-12 15:36:57 +0200 | [diff] [blame] | 152 | * amdgpu_vm_validate_layer - validate a single page table level |
| 153 | * |
| 154 | * @parent: parent page table level |
| 155 | * @validate: callback to do the validation |
| 156 | * @param: parameter for the validation callback |
| 157 | * |
| 158 | * Validate the page table BOs on command submission if neccessary. |
| 159 | */ |
| 160 | static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, |
| 161 | int (*validate)(void *, struct amdgpu_bo *), |
Christian König | b636922 | 2017-08-03 11:44:01 -0400 | [diff] [blame^] | 162 | void *param, bool use_cpu_for_update, |
| 163 | struct ttm_bo_global *glob) |
Christian König | 670fecc | 2016-10-12 15:36:57 +0200 | [diff] [blame] | 164 | { |
| 165 | unsigned i; |
| 166 | int r; |
| 167 | |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 168 | if (use_cpu_for_update) { |
| 169 | r = amdgpu_bo_kmap(parent->bo, NULL); |
| 170 | if (r) |
| 171 | return r; |
| 172 | } |
| 173 | |
Christian König | 670fecc | 2016-10-12 15:36:57 +0200 | [diff] [blame] | 174 | if (!parent->entries) |
| 175 | return 0; |
| 176 | |
| 177 | for (i = 0; i <= parent->last_entry_used; ++i) { |
| 178 | struct amdgpu_vm_pt *entry = &parent->entries[i]; |
| 179 | |
| 180 | if (!entry->bo) |
| 181 | continue; |
| 182 | |
| 183 | r = validate(param, entry->bo); |
| 184 | if (r) |
| 185 | return r; |
| 186 | |
Christian König | b636922 | 2017-08-03 11:44:01 -0400 | [diff] [blame^] | 187 | spin_lock(&glob->lru_lock); |
| 188 | ttm_bo_move_to_lru_tail(&entry->bo->tbo); |
| 189 | if (entry->bo->shadow) |
| 190 | ttm_bo_move_to_lru_tail(&entry->bo->shadow->tbo); |
| 191 | spin_unlock(&glob->lru_lock); |
| 192 | |
Christian König | 670fecc | 2016-10-12 15:36:57 +0200 | [diff] [blame] | 193 | /* |
| 194 | * Recurse into the sub directory. This is harmless because we |
| 195 | * have only a maximum of 5 layers. |
| 196 | */ |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 197 | r = amdgpu_vm_validate_level(entry, validate, param, |
Christian König | b636922 | 2017-08-03 11:44:01 -0400 | [diff] [blame^] | 198 | use_cpu_for_update, glob); |
Christian König | 670fecc | 2016-10-12 15:36:57 +0200 | [diff] [blame] | 199 | if (r) |
| 200 | return r; |
| 201 | } |
| 202 | |
| 203 | return r; |
| 204 | } |
| 205 | |
| 206 | /** |
Christian König | f7da30d | 2016-09-28 12:03:04 +0200 | [diff] [blame] | 207 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 208 | * |
Christian König | 5a712a8 | 2016-06-21 16:28:15 +0200 | [diff] [blame] | 209 | * @adev: amdgpu device pointer |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 210 | * @vm: vm providing the BOs |
Christian König | f7da30d | 2016-09-28 12:03:04 +0200 | [diff] [blame] | 211 | * @validate: callback to do the validation |
| 212 | * @param: parameter for the validation callback |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 213 | * |
Christian König | f7da30d | 2016-09-28 12:03:04 +0200 | [diff] [blame] | 214 | * Validate the page table BOs on command submission if neccessary. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 215 | */ |
Christian König | f7da30d | 2016-09-28 12:03:04 +0200 | [diff] [blame] | 216 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
| 217 | int (*validate)(void *p, struct amdgpu_bo *bo), |
| 218 | void *param) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 219 | { |
Christian König | 5a712a8 | 2016-06-21 16:28:15 +0200 | [diff] [blame] | 220 | uint64_t num_evictions; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 221 | |
Christian König | 5a712a8 | 2016-06-21 16:28:15 +0200 | [diff] [blame] | 222 | /* We only need to validate the page tables |
| 223 | * if they aren't already valid. |
| 224 | */ |
| 225 | num_evictions = atomic64_read(&adev->num_evictions); |
| 226 | if (num_evictions == vm->last_eviction_counter) |
Christian König | f7da30d | 2016-09-28 12:03:04 +0200 | [diff] [blame] | 227 | return 0; |
Christian König | 5a712a8 | 2016-06-21 16:28:15 +0200 | [diff] [blame] | 228 | |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 229 | return amdgpu_vm_validate_level(&vm->root, validate, param, |
Christian König | b636922 | 2017-08-03 11:44:01 -0400 | [diff] [blame^] | 230 | vm->use_cpu_for_update, |
| 231 | adev->mman.bdev.glob); |
Christian König | eceb8a1 | 2016-01-11 15:35:21 +0100 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | /** |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 235 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels |
| 236 | * |
| 237 | * @adev: amdgpu_device pointer |
| 238 | * @vm: requested vm |
| 239 | * @saddr: start of the address range |
| 240 | * @eaddr: end of the address range |
| 241 | * |
| 242 | * Make sure the page directories and page tables are allocated |
| 243 | */ |
| 244 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, |
| 245 | struct amdgpu_vm *vm, |
| 246 | struct amdgpu_vm_pt *parent, |
| 247 | uint64_t saddr, uint64_t eaddr, |
| 248 | unsigned level) |
| 249 | { |
| 250 | unsigned shift = (adev->vm_manager.num_level - level) * |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 251 | adev->vm_manager.block_size; |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 252 | unsigned pt_idx, from, to; |
| 253 | int r; |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 254 | u64 flags; |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 255 | uint64_t init_value = 0; |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 256 | |
| 257 | if (!parent->entries) { |
| 258 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); |
| 259 | |
Michal Hocko | 2098105 | 2017-05-17 14:23:12 +0200 | [diff] [blame] | 260 | parent->entries = kvmalloc_array(num_entries, |
| 261 | sizeof(struct amdgpu_vm_pt), |
| 262 | GFP_KERNEL | __GFP_ZERO); |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 263 | if (!parent->entries) |
| 264 | return -ENOMEM; |
| 265 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); |
| 266 | } |
| 267 | |
Felix Kuehling | 1866bac | 2017-03-28 20:36:12 -0400 | [diff] [blame] | 268 | from = saddr >> shift; |
| 269 | to = eaddr >> shift; |
| 270 | if (from >= amdgpu_vm_num_entries(adev, level) || |
| 271 | to >= amdgpu_vm_num_entries(adev, level)) |
| 272 | return -EINVAL; |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 273 | |
| 274 | if (to > parent->last_entry_used) |
| 275 | parent->last_entry_used = to; |
| 276 | |
| 277 | ++level; |
Felix Kuehling | 1866bac | 2017-03-28 20:36:12 -0400 | [diff] [blame] | 278 | saddr = saddr & ((1 << shift) - 1); |
| 279 | eaddr = eaddr & ((1 << shift) - 1); |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 280 | |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 281 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
| 282 | AMDGPU_GEM_CREATE_VRAM_CLEARED; |
| 283 | if (vm->use_cpu_for_update) |
| 284 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; |
| 285 | else |
| 286 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
| 287 | AMDGPU_GEM_CREATE_SHADOW); |
| 288 | |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 289 | if (vm->pte_support_ats) { |
| 290 | init_value = AMDGPU_PTE_SYSTEM; |
| 291 | if (level != adev->vm_manager.num_level - 1) |
| 292 | init_value |= AMDGPU_PDE_PTE; |
| 293 | } |
| 294 | |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 295 | /* walk over the address space and allocate the page tables */ |
| 296 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { |
| 297 | struct reservation_object *resv = vm->root.bo->tbo.resv; |
| 298 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
| 299 | struct amdgpu_bo *pt; |
| 300 | |
| 301 | if (!entry->bo) { |
| 302 | r = amdgpu_bo_create(adev, |
| 303 | amdgpu_vm_bo_size(adev, level), |
| 304 | AMDGPU_GPU_PAGE_SIZE, true, |
| 305 | AMDGPU_GEM_DOMAIN_VRAM, |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 306 | flags, |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 307 | NULL, resv, init_value, &pt); |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 308 | if (r) |
| 309 | return r; |
| 310 | |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 311 | if (vm->use_cpu_for_update) { |
| 312 | r = amdgpu_bo_kmap(pt, NULL); |
| 313 | if (r) { |
| 314 | amdgpu_bo_unref(&pt); |
| 315 | return r; |
| 316 | } |
| 317 | } |
| 318 | |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 319 | /* Keep a reference to the root directory to avoid |
| 320 | * freeing them up in the wrong order. |
| 321 | */ |
| 322 | pt->parent = amdgpu_bo_ref(vm->root.bo); |
| 323 | |
| 324 | entry->bo = pt; |
| 325 | entry->addr = 0; |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 326 | entry->huge_page = false; |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | if (level < adev->vm_manager.num_level) { |
Felix Kuehling | 1866bac | 2017-03-28 20:36:12 -0400 | [diff] [blame] | 330 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
| 331 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : |
| 332 | ((1 << shift) - 1); |
| 333 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, |
| 334 | sub_eaddr, level); |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 335 | if (r) |
| 336 | return r; |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
Christian König | 663e457 | 2017-03-13 10:13:37 +0100 | [diff] [blame] | 343 | /** |
| 344 | * amdgpu_vm_alloc_pts - Allocate page tables. |
| 345 | * |
| 346 | * @adev: amdgpu_device pointer |
| 347 | * @vm: VM to allocate page tables for |
| 348 | * @saddr: Start address which needs to be allocated |
| 349 | * @size: Size from start address we need. |
| 350 | * |
| 351 | * Make sure the page tables are allocated. |
| 352 | */ |
| 353 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
| 354 | struct amdgpu_vm *vm, |
| 355 | uint64_t saddr, uint64_t size) |
| 356 | { |
Felix Kuehling | 22770e5 | 2017-03-28 20:24:53 -0400 | [diff] [blame] | 357 | uint64_t last_pfn; |
Christian König | 663e457 | 2017-03-13 10:13:37 +0100 | [diff] [blame] | 358 | uint64_t eaddr; |
Christian König | 663e457 | 2017-03-13 10:13:37 +0100 | [diff] [blame] | 359 | |
| 360 | /* validate the parameters */ |
| 361 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) |
| 362 | return -EINVAL; |
| 363 | |
| 364 | eaddr = saddr + size - 1; |
| 365 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; |
| 366 | if (last_pfn >= adev->vm_manager.max_pfn) { |
Felix Kuehling | 22770e5 | 2017-03-28 20:24:53 -0400 | [diff] [blame] | 367 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
Christian König | 663e457 | 2017-03-13 10:13:37 +0100 | [diff] [blame] | 368 | last_pfn, adev->vm_manager.max_pfn); |
| 369 | return -EINVAL; |
| 370 | } |
| 371 | |
| 372 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
| 373 | eaddr /= AMDGPU_GPU_PAGE_SIZE; |
| 374 | |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 375 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
Christian König | 663e457 | 2017-03-13 10:13:37 +0100 | [diff] [blame] | 376 | } |
| 377 | |
Christian König | 641e940 | 2017-04-03 13:59:25 +0200 | [diff] [blame] | 378 | /** |
| 379 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use |
| 380 | * |
| 381 | * @adev: amdgpu_device pointer |
| 382 | * @id: VMID structure |
| 383 | * |
| 384 | * Check if GPU reset occured since last use of the VMID. |
| 385 | */ |
| 386 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, |
| 387 | struct amdgpu_vm_id *id) |
Chunming Zhou | 192b7dc | 2016-06-29 14:01:15 +0800 | [diff] [blame] | 388 | { |
| 389 | return id->current_gpu_reset_count != |
Christian König | 641e940 | 2017-04-03 13:59:25 +0200 | [diff] [blame] | 390 | atomic_read(&adev->gpu_reset_counter); |
Chunming Zhou | 192b7dc | 2016-06-29 14:01:15 +0800 | [diff] [blame] | 391 | } |
| 392 | |
Chunming Zhou | 7a63eb2 | 2017-04-21 11:13:56 +0800 | [diff] [blame] | 393 | static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) |
| 394 | { |
| 395 | return !!vm->reserved_vmid[vmhub]; |
| 396 | } |
| 397 | |
| 398 | /* idr_mgr->lock must be held */ |
| 399 | static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, |
| 400 | struct amdgpu_ring *ring, |
| 401 | struct amdgpu_sync *sync, |
| 402 | struct dma_fence *fence, |
| 403 | struct amdgpu_job *job) |
| 404 | { |
| 405 | struct amdgpu_device *adev = ring->adev; |
| 406 | unsigned vmhub = ring->funcs->vmhub; |
| 407 | uint64_t fence_context = adev->fence_context + ring->idx; |
| 408 | struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; |
| 409 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
| 410 | struct dma_fence *updates = sync->last_vm_update; |
| 411 | int r = 0; |
| 412 | struct dma_fence *flushed, *tmp; |
Christian König | 6f1ceab | 2017-07-11 16:59:21 +0200 | [diff] [blame] | 413 | bool needs_flush = vm->use_cpu_for_update; |
Chunming Zhou | 7a63eb2 | 2017-04-21 11:13:56 +0800 | [diff] [blame] | 414 | |
| 415 | flushed = id->flushed_updates; |
| 416 | if ((amdgpu_vm_had_gpu_reset(adev, id)) || |
| 417 | (atomic64_read(&id->owner) != vm->client_id) || |
| 418 | (job->vm_pd_addr != id->pd_gpu_addr) || |
| 419 | (updates && (!flushed || updates->context != flushed->context || |
| 420 | dma_fence_is_later(updates, flushed))) || |
| 421 | (!id->last_flush || (id->last_flush->context != fence_context && |
| 422 | !dma_fence_is_signaled(id->last_flush)))) { |
| 423 | needs_flush = true; |
| 424 | /* to prevent one context starved by another context */ |
| 425 | id->pd_gpu_addr = 0; |
| 426 | tmp = amdgpu_sync_peek_fence(&id->active, ring); |
| 427 | if (tmp) { |
| 428 | r = amdgpu_sync_fence(adev, sync, tmp); |
| 429 | return r; |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | /* Good we can use this VMID. Remember this submission as |
| 434 | * user of the VMID. |
| 435 | */ |
| 436 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
| 437 | if (r) |
| 438 | goto out; |
| 439 | |
| 440 | if (updates && (!flushed || updates->context != flushed->context || |
| 441 | dma_fence_is_later(updates, flushed))) { |
| 442 | dma_fence_put(id->flushed_updates); |
| 443 | id->flushed_updates = dma_fence_get(updates); |
| 444 | } |
| 445 | id->pd_gpu_addr = job->vm_pd_addr; |
Chunming Zhou | 7a63eb2 | 2017-04-21 11:13:56 +0800 | [diff] [blame] | 446 | atomic64_set(&id->owner, vm->client_id); |
| 447 | job->vm_needs_flush = needs_flush; |
| 448 | if (needs_flush) { |
| 449 | dma_fence_put(id->last_flush); |
| 450 | id->last_flush = NULL; |
| 451 | } |
| 452 | job->vm_id = id - id_mgr->ids; |
| 453 | trace_amdgpu_vm_grab_id(vm, ring, job); |
| 454 | out: |
| 455 | return r; |
| 456 | } |
| 457 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 458 | /** |
| 459 | * amdgpu_vm_grab_id - allocate the next free VMID |
| 460 | * |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 461 | * @vm: vm to allocate id for |
Christian König | 7f8a529 | 2015-07-20 16:09:40 +0200 | [diff] [blame] | 462 | * @ring: ring we want to submit job to |
| 463 | * @sync: sync object where we add dependencies |
Christian König | 94dd0a4 | 2016-01-18 17:01:42 +0100 | [diff] [blame] | 464 | * @fence: fence protecting ID from reuse |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 465 | * |
Christian König | 7f8a529 | 2015-07-20 16:09:40 +0200 | [diff] [blame] | 466 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 467 | */ |
Christian König | 7f8a529 | 2015-07-20 16:09:40 +0200 | [diff] [blame] | 468 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 469 | struct amdgpu_sync *sync, struct dma_fence *fence, |
Chunming Zhou | fd53be3 | 2016-07-01 17:59:01 +0800 | [diff] [blame] | 470 | struct amdgpu_job *job) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 471 | { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 472 | struct amdgpu_device *adev = ring->adev; |
Christian König | 2e81984 | 2017-03-30 16:50:47 +0200 | [diff] [blame] | 473 | unsigned vmhub = ring->funcs->vmhub; |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 474 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
Christian König | 090b767 | 2016-07-08 10:21:02 +0200 | [diff] [blame] | 475 | uint64_t fence_context = adev->fence_context + ring->idx; |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 476 | struct dma_fence *updates = sync->last_vm_update; |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 477 | struct amdgpu_vm_id *id, *idle; |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 478 | struct dma_fence **fences; |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 479 | unsigned i; |
| 480 | int r = 0; |
| 481 | |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 482 | mutex_lock(&id_mgr->lock); |
Chunming Zhou | 7a63eb2 | 2017-04-21 11:13:56 +0800 | [diff] [blame] | 483 | if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { |
| 484 | r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); |
| 485 | mutex_unlock(&id_mgr->lock); |
| 486 | return r; |
| 487 | } |
| 488 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
| 489 | if (!fences) { |
| 490 | mutex_unlock(&id_mgr->lock); |
| 491 | return -ENOMEM; |
| 492 | } |
Christian König | 36fd7c5 | 2016-05-23 15:30:08 +0200 | [diff] [blame] | 493 | /* Check if we have an idle VMID */ |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 494 | i = 0; |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 495 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 496 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
| 497 | if (!fences[i]) |
Christian König | 36fd7c5 | 2016-05-23 15:30:08 +0200 | [diff] [blame] | 498 | break; |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 499 | ++i; |
Christian König | 36fd7c5 | 2016-05-23 15:30:08 +0200 | [diff] [blame] | 500 | } |
Christian König | bcb1ba3 | 2016-03-08 15:40:11 +0100 | [diff] [blame] | 501 | |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 502 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 503 | if (&idle->list == &id_mgr->ids_lru) { |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 504 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
| 505 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 506 | struct dma_fence_array *array; |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 507 | unsigned j; |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 508 | |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 509 | for (j = 0; j < i; ++j) |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 510 | dma_fence_get(fences[j]); |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 511 | |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 512 | array = dma_fence_array_create(i, fences, fence_context, |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 513 | seqno, true); |
| 514 | if (!array) { |
| 515 | for (j = 0; j < i; ++j) |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 516 | dma_fence_put(fences[j]); |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 517 | kfree(fences); |
| 518 | r = -ENOMEM; |
| 519 | goto error; |
| 520 | } |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 521 | |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 522 | |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 523 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 524 | dma_fence_put(&array->base); |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 525 | if (r) |
| 526 | goto error; |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 527 | |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 528 | mutex_unlock(&id_mgr->lock); |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 529 | return 0; |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 530 | |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 531 | } |
| 532 | kfree(fences); |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 533 | |
Christian König | 6f1ceab | 2017-07-11 16:59:21 +0200 | [diff] [blame] | 534 | job->vm_needs_flush = vm->use_cpu_for_update; |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 535 | /* Check if we can use a VMID already assigned to this VM */ |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 536 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 537 | struct dma_fence *flushed; |
Christian König | 6f1ceab | 2017-07-11 16:59:21 +0200 | [diff] [blame] | 538 | bool needs_flush = vm->use_cpu_for_update; |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 539 | |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 540 | /* Check all the prerequisites to using this VMID */ |
Christian König | 641e940 | 2017-04-03 13:59:25 +0200 | [diff] [blame] | 541 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
Chunming Zhou | 6adb051 | 2016-06-27 17:06:01 +0800 | [diff] [blame] | 542 | continue; |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 543 | |
| 544 | if (atomic64_read(&id->owner) != vm->client_id) |
| 545 | continue; |
| 546 | |
Chunming Zhou | fd53be3 | 2016-07-01 17:59:01 +0800 | [diff] [blame] | 547 | if (job->vm_pd_addr != id->pd_gpu_addr) |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 548 | continue; |
| 549 | |
Christian König | 87c910d | 2017-03-30 16:56:20 +0200 | [diff] [blame] | 550 | if (!id->last_flush || |
| 551 | (id->last_flush->context != fence_context && |
| 552 | !dma_fence_is_signaled(id->last_flush))) |
| 553 | needs_flush = true; |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 554 | |
| 555 | flushed = id->flushed_updates; |
Christian König | 87c910d | 2017-03-30 16:56:20 +0200 | [diff] [blame] | 556 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
| 557 | needs_flush = true; |
| 558 | |
| 559 | /* Concurrent flushes are only possible starting with Vega10 */ |
| 560 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 561 | continue; |
| 562 | |
Christian König | 3dab83b | 2016-06-01 13:31:17 +0200 | [diff] [blame] | 563 | /* Good we can use this VMID. Remember this submission as |
| 564 | * user of the VMID. |
| 565 | */ |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 566 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
| 567 | if (r) |
| 568 | goto error; |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 569 | |
Christian König | 87c910d | 2017-03-30 16:56:20 +0200 | [diff] [blame] | 570 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
| 571 | dma_fence_put(id->flushed_updates); |
| 572 | id->flushed_updates = dma_fence_get(updates); |
| 573 | } |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 574 | |
Christian König | 87c910d | 2017-03-30 16:56:20 +0200 | [diff] [blame] | 575 | if (needs_flush) |
| 576 | goto needs_flush; |
| 577 | else |
| 578 | goto no_flush_needed; |
Christian König | 8d76001e | 2016-05-23 16:00:32 +0200 | [diff] [blame] | 579 | |
Christian König | 4f618e7 | 2017-04-06 15:18:21 +0200 | [diff] [blame] | 580 | }; |
Chunming Zhou | 8e9fbeb | 2016-03-17 11:41:37 +0800 | [diff] [blame] | 581 | |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 582 | /* Still no ID to use? Then use the idle one found earlier */ |
| 583 | id = idle; |
| 584 | |
| 585 | /* Remember this submission as user of the VMID */ |
| 586 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
Christian König | 832a902 | 2016-02-15 12:33:02 +0100 | [diff] [blame] | 587 | if (r) |
| 588 | goto error; |
Christian König | 4ff37a8 | 2016-02-26 16:18:26 +0100 | [diff] [blame] | 589 | |
Christian König | 87c910d | 2017-03-30 16:56:20 +0200 | [diff] [blame] | 590 | id->pd_gpu_addr = job->vm_pd_addr; |
| 591 | dma_fence_put(id->flushed_updates); |
| 592 | id->flushed_updates = dma_fence_get(updates); |
Christian König | 87c910d | 2017-03-30 16:56:20 +0200 | [diff] [blame] | 593 | atomic64_set(&id->owner, vm->client_id); |
| 594 | |
| 595 | needs_flush: |
| 596 | job->vm_needs_flush = true; |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 597 | dma_fence_put(id->last_flush); |
Christian König | 41d9eb2 | 2016-03-01 16:46:18 +0100 | [diff] [blame] | 598 | id->last_flush = NULL; |
| 599 | |
Christian König | 87c910d | 2017-03-30 16:56:20 +0200 | [diff] [blame] | 600 | no_flush_needed: |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 601 | list_move_tail(&id->list, &id_mgr->ids_lru); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 602 | |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 603 | job->vm_id = id - id_mgr->ids; |
Christian König | c5296d1 | 2017-04-07 15:31:13 +0200 | [diff] [blame] | 604 | trace_amdgpu_vm_grab_id(vm, ring, job); |
Christian König | 832a902 | 2016-02-15 12:33:02 +0100 | [diff] [blame] | 605 | |
| 606 | error: |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 607 | mutex_unlock(&id_mgr->lock); |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 608 | return r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 609 | } |
| 610 | |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 611 | static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, |
| 612 | struct amdgpu_vm *vm, |
| 613 | unsigned vmhub) |
Alex Deucher | 93dcc37 | 2016-06-17 17:05:15 -0400 | [diff] [blame] | 614 | { |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 615 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
Alex Deucher | 93dcc37 | 2016-06-17 17:05:15 -0400 | [diff] [blame] | 616 | |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 617 | mutex_lock(&id_mgr->lock); |
| 618 | if (vm->reserved_vmid[vmhub]) { |
| 619 | list_add(&vm->reserved_vmid[vmhub]->list, |
| 620 | &id_mgr->ids_lru); |
| 621 | vm->reserved_vmid[vmhub] = NULL; |
Chunming Zhou | c350577 | 2017-04-21 15:51:04 +0800 | [diff] [blame] | 622 | atomic_dec(&id_mgr->reserved_vmid_num); |
Alex Deucher | 93dcc37 | 2016-06-17 17:05:15 -0400 | [diff] [blame] | 623 | } |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 624 | mutex_unlock(&id_mgr->lock); |
Alex Deucher | 93dcc37 | 2016-06-17 17:05:15 -0400 | [diff] [blame] | 625 | } |
| 626 | |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 627 | static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, |
| 628 | struct amdgpu_vm *vm, |
| 629 | unsigned vmhub) |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 630 | { |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 631 | struct amdgpu_vm_id_manager *id_mgr; |
| 632 | struct amdgpu_vm_id *idle; |
| 633 | int r = 0; |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 634 | |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 635 | id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
| 636 | mutex_lock(&id_mgr->lock); |
| 637 | if (vm->reserved_vmid[vmhub]) |
| 638 | goto unlock; |
Chunming Zhou | c350577 | 2017-04-21 15:51:04 +0800 | [diff] [blame] | 639 | if (atomic_inc_return(&id_mgr->reserved_vmid_num) > |
| 640 | AMDGPU_VM_MAX_RESERVED_VMID) { |
| 641 | DRM_ERROR("Over limitation of reserved vmid\n"); |
| 642 | atomic_dec(&id_mgr->reserved_vmid_num); |
| 643 | r = -EINVAL; |
| 644 | goto unlock; |
| 645 | } |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 646 | /* Select the first entry VMID */ |
| 647 | idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); |
| 648 | list_del_init(&idle->list); |
| 649 | vm->reserved_vmid[vmhub] = idle; |
| 650 | mutex_unlock(&id_mgr->lock); |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 651 | |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 652 | return 0; |
| 653 | unlock: |
| 654 | mutex_unlock(&id_mgr->lock); |
| 655 | return r; |
| 656 | } |
| 657 | |
Alex Xie | e59c020 | 2017-06-01 09:42:59 -0400 | [diff] [blame] | 658 | /** |
| 659 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug |
| 660 | * |
| 661 | * @adev: amdgpu_device pointer |
| 662 | */ |
| 663 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) |
| 664 | { |
| 665 | const struct amdgpu_ip_block *ip_block; |
| 666 | bool has_compute_vm_bug; |
| 667 | struct amdgpu_ring *ring; |
| 668 | int i; |
| 669 | |
| 670 | has_compute_vm_bug = false; |
| 671 | |
| 672 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
| 673 | if (ip_block) { |
| 674 | /* Compute has a VM bug for GFX version < 7. |
| 675 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ |
| 676 | if (ip_block->version->major <= 7) |
| 677 | has_compute_vm_bug = true; |
| 678 | else if (ip_block->version->major == 8) |
| 679 | if (adev->gfx.mec_fw_version < 673) |
| 680 | has_compute_vm_bug = true; |
| 681 | } |
| 682 | |
| 683 | for (i = 0; i < adev->num_rings; i++) { |
| 684 | ring = adev->rings[i]; |
| 685 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) |
| 686 | /* only compute rings */ |
| 687 | ring->has_compute_vm_bug = has_compute_vm_bug; |
| 688 | else |
| 689 | ring->has_compute_vm_bug = false; |
| 690 | } |
| 691 | } |
| 692 | |
Chunming Zhou | b9bf33d | 2017-05-11 14:52:48 -0400 | [diff] [blame] | 693 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
| 694 | struct amdgpu_job *job) |
| 695 | { |
| 696 | struct amdgpu_device *adev = ring->adev; |
| 697 | unsigned vmhub = ring->funcs->vmhub; |
| 698 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
| 699 | struct amdgpu_vm_id *id; |
| 700 | bool gds_switch_needed; |
Alex Xie | e59c020 | 2017-06-01 09:42:59 -0400 | [diff] [blame] | 701 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
Chunming Zhou | b9bf33d | 2017-05-11 14:52:48 -0400 | [diff] [blame] | 702 | |
| 703 | if (job->vm_id == 0) |
| 704 | return false; |
| 705 | id = &id_mgr->ids[job->vm_id]; |
| 706 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
| 707 | id->gds_base != job->gds_base || |
| 708 | id->gds_size != job->gds_size || |
| 709 | id->gws_base != job->gws_base || |
| 710 | id->gws_size != job->gws_size || |
| 711 | id->oa_base != job->oa_base || |
| 712 | id->oa_size != job->oa_size); |
| 713 | |
| 714 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
| 715 | return true; |
Alex Xie | bb37b67 | 2017-05-30 23:50:10 -0400 | [diff] [blame] | 716 | |
| 717 | return vm_flush_needed || gds_switch_needed; |
Chunming Zhou | b9bf33d | 2017-05-11 14:52:48 -0400 | [diff] [blame] | 718 | } |
| 719 | |
Harish Kasiviswanathan | 9a4b7d4 | 2017-06-09 11:26:57 -0400 | [diff] [blame] | 720 | static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) |
| 721 | { |
| 722 | return (adev->mc.real_vram_size == adev->mc.visible_vram_size); |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 723 | } |
| 724 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 725 | /** |
| 726 | * amdgpu_vm_flush - hardware flush the vm |
| 727 | * |
| 728 | * @ring: ring to use for flush |
Christian König | cffadc8 | 2016-03-01 13:34:49 +0100 | [diff] [blame] | 729 | * @vm_id: vmid number to use |
Christian König | 4ff37a8 | 2016-02-26 16:18:26 +0100 | [diff] [blame] | 730 | * @pd_addr: address of the page directory |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 731 | * |
Christian König | 4ff37a8 | 2016-02-26 16:18:26 +0100 | [diff] [blame] | 732 | * Emit a VM flush when it is necessary. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 733 | */ |
Monk Liu | 8fdf074 | 2017-06-06 17:25:13 +0800 | [diff] [blame] | 734 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 735 | { |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 736 | struct amdgpu_device *adev = ring->adev; |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 737 | unsigned vmhub = ring->funcs->vmhub; |
| 738 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
| 739 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; |
Christian König | d564a06 | 2016-03-01 15:51:53 +0100 | [diff] [blame] | 740 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
Chunming Zhou | fd53be3 | 2016-07-01 17:59:01 +0800 | [diff] [blame] | 741 | id->gds_base != job->gds_base || |
| 742 | id->gds_size != job->gds_size || |
| 743 | id->gws_base != job->gws_base || |
| 744 | id->gws_size != job->gws_size || |
| 745 | id->oa_base != job->oa_base || |
| 746 | id->oa_size != job->oa_size); |
Flora Cui | de37e68 | 2017-05-18 13:56:22 +0800 | [diff] [blame] | 747 | bool vm_flush_needed = job->vm_needs_flush; |
Christian König | c0e5193 | 2017-04-03 14:16:07 +0200 | [diff] [blame] | 748 | unsigned patch_offset = 0; |
Christian König | 41d9eb2 | 2016-03-01 16:46:18 +0100 | [diff] [blame] | 749 | int r; |
Christian König | d564a06 | 2016-03-01 15:51:53 +0100 | [diff] [blame] | 750 | |
Christian König | f7d015b | 2017-04-03 14:28:26 +0200 | [diff] [blame] | 751 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
| 752 | gds_switch_needed = true; |
| 753 | vm_flush_needed = true; |
| 754 | } |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 755 | |
Monk Liu | 8fdf074 | 2017-06-06 17:25:13 +0800 | [diff] [blame] | 756 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
Christian König | f7d015b | 2017-04-03 14:28:26 +0200 | [diff] [blame] | 757 | return 0; |
Christian König | 41d9eb2 | 2016-03-01 16:46:18 +0100 | [diff] [blame] | 758 | |
Christian König | c0e5193 | 2017-04-03 14:16:07 +0200 | [diff] [blame] | 759 | if (ring->funcs->init_cond_exec) |
| 760 | patch_offset = amdgpu_ring_init_cond_exec(ring); |
Christian König | 41d9eb2 | 2016-03-01 16:46:18 +0100 | [diff] [blame] | 761 | |
Monk Liu | 8fdf074 | 2017-06-06 17:25:13 +0800 | [diff] [blame] | 762 | if (need_pipe_sync) |
| 763 | amdgpu_ring_emit_pipeline_sync(ring); |
| 764 | |
Christian König | f7d015b | 2017-04-03 14:28:26 +0200 | [diff] [blame] | 765 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
Christian König | c0e5193 | 2017-04-03 14:16:07 +0200 | [diff] [blame] | 766 | struct dma_fence *fence; |
Monk Liu | e9d672b | 2017-03-15 12:18:57 +0800 | [diff] [blame] | 767 | |
Christian König | 9a94f5a | 2017-05-12 14:46:23 +0200 | [diff] [blame] | 768 | trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); |
| 769 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); |
Monk Liu | e9d672b | 2017-03-15 12:18:57 +0800 | [diff] [blame] | 770 | |
Christian König | c0e5193 | 2017-04-03 14:16:07 +0200 | [diff] [blame] | 771 | r = amdgpu_fence_emit(ring, &fence); |
| 772 | if (r) |
| 773 | return r; |
Monk Liu | e9d672b | 2017-03-15 12:18:57 +0800 | [diff] [blame] | 774 | |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 775 | mutex_lock(&id_mgr->lock); |
Christian König | c0e5193 | 2017-04-03 14:16:07 +0200 | [diff] [blame] | 776 | dma_fence_put(id->last_flush); |
| 777 | id->last_flush = fence; |
Chunming Zhou | bea39672 | 2017-05-10 13:02:39 +0800 | [diff] [blame] | 778 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 779 | mutex_unlock(&id_mgr->lock); |
Christian König | c0e5193 | 2017-04-03 14:16:07 +0200 | [diff] [blame] | 780 | } |
Monk Liu | e9d672b | 2017-03-15 12:18:57 +0800 | [diff] [blame] | 781 | |
Chunming Zhou | 7c4378f | 2017-05-11 18:22:17 +0800 | [diff] [blame] | 782 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
Christian König | c0e5193 | 2017-04-03 14:16:07 +0200 | [diff] [blame] | 783 | id->gds_base = job->gds_base; |
| 784 | id->gds_size = job->gds_size; |
| 785 | id->gws_base = job->gws_base; |
| 786 | id->gws_size = job->gws_size; |
| 787 | id->oa_base = job->oa_base; |
| 788 | id->oa_size = job->oa_size; |
| 789 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, |
| 790 | job->gds_size, job->gws_base, |
| 791 | job->gws_size, job->oa_base, |
| 792 | job->oa_size); |
| 793 | } |
| 794 | |
| 795 | if (ring->funcs->patch_cond_exec) |
| 796 | amdgpu_ring_patch_cond_exec(ring, patch_offset); |
| 797 | |
| 798 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ |
| 799 | if (ring->funcs->emit_switch_buffer) { |
| 800 | amdgpu_ring_emit_switch_buffer(ring); |
| 801 | amdgpu_ring_emit_switch_buffer(ring); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 802 | } |
Christian König | 41d9eb2 | 2016-03-01 16:46:18 +0100 | [diff] [blame] | 803 | return 0; |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 804 | } |
| 805 | |
| 806 | /** |
| 807 | * amdgpu_vm_reset_id - reset VMID to zero |
| 808 | * |
| 809 | * @adev: amdgpu device structure |
| 810 | * @vm_id: vmid number to use |
| 811 | * |
| 812 | * Reset saved GDW, GWS and OA to force switch on next flush. |
| 813 | */ |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 814 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
| 815 | unsigned vmid) |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 816 | { |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 817 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
| 818 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 819 | |
Christian König | b3c85a0 | 2017-05-10 20:06:58 +0200 | [diff] [blame] | 820 | atomic64_set(&id->owner, 0); |
Christian König | bcb1ba3 | 2016-03-08 15:40:11 +0100 | [diff] [blame] | 821 | id->gds_base = 0; |
| 822 | id->gds_size = 0; |
| 823 | id->gws_base = 0; |
| 824 | id->gws_size = 0; |
| 825 | id->oa_base = 0; |
| 826 | id->oa_size = 0; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 827 | } |
| 828 | |
| 829 | /** |
Christian König | b3c85a0 | 2017-05-10 20:06:58 +0200 | [diff] [blame] | 830 | * amdgpu_vm_reset_all_id - reset VMID to zero |
| 831 | * |
| 832 | * @adev: amdgpu device structure |
| 833 | * |
| 834 | * Reset VMID to force flush on next use |
| 835 | */ |
| 836 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev) |
| 837 | { |
| 838 | unsigned i, j; |
| 839 | |
| 840 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
| 841 | struct amdgpu_vm_id_manager *id_mgr = |
| 842 | &adev->vm_manager.id_mgr[i]; |
| 843 | |
| 844 | for (j = 1; j < id_mgr->num_ids; ++j) |
| 845 | amdgpu_vm_reset_id(adev, i, j); |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | /** |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 850 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo |
| 851 | * |
| 852 | * @vm: requested vm |
| 853 | * @bo: requested buffer object |
| 854 | * |
Christian König | 8843dbb | 2016-01-26 12:17:11 +0100 | [diff] [blame] | 855 | * Find @bo inside the requested vm. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 856 | * Search inside the @bos vm list for the requested vm |
| 857 | * Returns the found bo_va or NULL if none is found |
| 858 | * |
| 859 | * Object has to be reserved! |
| 860 | */ |
| 861 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, |
| 862 | struct amdgpu_bo *bo) |
| 863 | { |
| 864 | struct amdgpu_bo_va *bo_va; |
| 865 | |
| 866 | list_for_each_entry(bo_va, &bo->va, bo_list) { |
| 867 | if (bo_va->vm == vm) { |
| 868 | return bo_va; |
| 869 | } |
| 870 | } |
| 871 | return NULL; |
| 872 | } |
| 873 | |
| 874 | /** |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 875 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 876 | * |
Christian König | 29efc4f | 2016-08-04 14:52:50 +0200 | [diff] [blame] | 877 | * @params: see amdgpu_pte_update_params definition |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 878 | * @pe: addr of the page entry |
| 879 | * @addr: dst addr to write into pe |
| 880 | * @count: number of page entries to update |
| 881 | * @incr: increase next addr by incr bytes |
| 882 | * @flags: hw access flags |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 883 | * |
| 884 | * Traces the parameters and calls the right asic functions |
| 885 | * to setup the page table using the DMA. |
| 886 | */ |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 887 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
| 888 | uint64_t pe, uint64_t addr, |
| 889 | unsigned count, uint32_t incr, |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 890 | uint64_t flags) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 891 | { |
Christian König | ec2f05f | 2016-09-25 16:11:52 +0200 | [diff] [blame] | 892 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 893 | |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 894 | if (count < 3) { |
Christian König | de9ea7b | 2016-08-12 11:33:30 +0200 | [diff] [blame] | 895 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
| 896 | addr | flags, count, incr); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 897 | |
| 898 | } else { |
Christian König | 27c5f36 | 2016-08-04 15:02:49 +0200 | [diff] [blame] | 899 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 900 | count, incr, flags); |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | /** |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 905 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART |
| 906 | * |
| 907 | * @params: see amdgpu_pte_update_params definition |
| 908 | * @pe: addr of the page entry |
| 909 | * @addr: dst addr to write into pe |
| 910 | * @count: number of page entries to update |
| 911 | * @incr: increase next addr by incr bytes |
| 912 | * @flags: hw access flags |
| 913 | * |
| 914 | * Traces the parameters and calls the DMA function to copy the PTEs. |
| 915 | */ |
| 916 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, |
| 917 | uint64_t pe, uint64_t addr, |
| 918 | unsigned count, uint32_t incr, |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 919 | uint64_t flags) |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 920 | { |
Christian König | ec2f05f | 2016-09-25 16:11:52 +0200 | [diff] [blame] | 921 | uint64_t src = (params->src + (addr >> 12) * 8); |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 922 | |
Christian König | ec2f05f | 2016-09-25 16:11:52 +0200 | [diff] [blame] | 923 | |
| 924 | trace_amdgpu_vm_copy_ptes(pe, src, count); |
| 925 | |
| 926 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 927 | } |
| 928 | |
| 929 | /** |
Christian König | b07c9d2 | 2015-11-30 13:26:07 +0100 | [diff] [blame] | 930 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 931 | * |
Christian König | b07c9d2 | 2015-11-30 13:26:07 +0100 | [diff] [blame] | 932 | * @pages_addr: optional DMA address to use for lookup |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 933 | * @addr: the unmapped addr |
| 934 | * |
| 935 | * Look up the physical address of the page that the pte resolves |
Christian König | b07c9d2 | 2015-11-30 13:26:07 +0100 | [diff] [blame] | 936 | * to and return the pointer for the page table entry. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 937 | */ |
Christian König | de9ea7b | 2016-08-12 11:33:30 +0200 | [diff] [blame] | 938 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 939 | { |
| 940 | uint64_t result; |
| 941 | |
Christian König | de9ea7b | 2016-08-12 11:33:30 +0200 | [diff] [blame] | 942 | /* page table offset */ |
| 943 | result = pages_addr[addr >> PAGE_SHIFT]; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 944 | |
Christian König | de9ea7b | 2016-08-12 11:33:30 +0200 | [diff] [blame] | 945 | /* in case cpu page size != gpu page size*/ |
| 946 | result |= addr & (~PAGE_MASK); |
Christian König | b07c9d2 | 2015-11-30 13:26:07 +0100 | [diff] [blame] | 947 | |
| 948 | result &= 0xFFFFFFFFFFFFF000ULL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 949 | |
| 950 | return result; |
| 951 | } |
| 952 | |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 953 | /** |
| 954 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU |
| 955 | * |
| 956 | * @params: see amdgpu_pte_update_params definition |
| 957 | * @pe: kmap addr of the page entry |
| 958 | * @addr: dst addr to write into pe |
| 959 | * @count: number of page entries to update |
| 960 | * @incr: increase next addr by incr bytes |
| 961 | * @flags: hw access flags |
| 962 | * |
| 963 | * Write count number of PT/PD entries directly. |
| 964 | */ |
| 965 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, |
| 966 | uint64_t pe, uint64_t addr, |
| 967 | unsigned count, uint32_t incr, |
| 968 | uint64_t flags) |
| 969 | { |
| 970 | unsigned int i; |
Harish Kasiviswanathan | b4d4251 | 2017-05-11 19:47:22 -0400 | [diff] [blame] | 971 | uint64_t value; |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 972 | |
Christian König | 03918b3 | 2017-07-11 17:15:37 +0200 | [diff] [blame] | 973 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
| 974 | |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 975 | for (i = 0; i < count; i++) { |
Harish Kasiviswanathan | b4d4251 | 2017-05-11 19:47:22 -0400 | [diff] [blame] | 976 | value = params->pages_addr ? |
| 977 | amdgpu_vm_map_gart(params->pages_addr, addr) : |
| 978 | addr; |
Harish Kasiviswanathan | a1924005 | 2017-06-09 17:47:28 -0400 | [diff] [blame] | 979 | amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
Harish Kasiviswanathan | b4d4251 | 2017-05-11 19:47:22 -0400 | [diff] [blame] | 980 | i, value, flags); |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 981 | addr += incr; |
| 982 | } |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 983 | } |
| 984 | |
Christian König | a33cab7 | 2017-07-11 17:13:00 +0200 | [diff] [blame] | 985 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
| 986 | void *owner) |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 987 | { |
| 988 | struct amdgpu_sync sync; |
| 989 | int r; |
| 990 | |
| 991 | amdgpu_sync_create(&sync); |
Christian König | a33cab7 | 2017-07-11 17:13:00 +0200 | [diff] [blame] | 992 | amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.resv, owner); |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 993 | r = amdgpu_sync_wait(&sync, true); |
| 994 | amdgpu_sync_free(&sync); |
| 995 | |
| 996 | return r; |
| 997 | } |
| 998 | |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 999 | /* |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1000 | * amdgpu_vm_update_level - update a single level in the hierarchy |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1001 | * |
| 1002 | * @adev: amdgpu_device pointer |
| 1003 | * @vm: requested vm |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1004 | * @parent: parent directory |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1005 | * |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1006 | * Makes sure all entries in @parent are up to date. |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1007 | * Returns 0 for success, error for failure. |
| 1008 | */ |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1009 | static int amdgpu_vm_update_level(struct amdgpu_device *adev, |
| 1010 | struct amdgpu_vm *vm, |
| 1011 | struct amdgpu_vm_pt *parent, |
| 1012 | unsigned level) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1013 | { |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1014 | struct amdgpu_bo *shadow; |
Harish Kasiviswanathan | a1924005 | 2017-06-09 17:47:28 -0400 | [diff] [blame] | 1015 | struct amdgpu_ring *ring = NULL; |
| 1016 | uint64_t pd_addr, shadow_addr = 0; |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1017 | uint32_t incr = amdgpu_vm_bo_size(adev, level + 1); |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1018 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
Harish Kasiviswanathan | a1924005 | 2017-06-09 17:47:28 -0400 | [diff] [blame] | 1019 | unsigned count = 0, pt_idx, ndw = 0; |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 1020 | struct amdgpu_job *job; |
Christian König | 29efc4f | 2016-08-04 14:52:50 +0200 | [diff] [blame] | 1021 | struct amdgpu_pte_update_params params; |
Dave Airlie | 220196b | 2016-10-28 11:33:52 +1000 | [diff] [blame] | 1022 | struct dma_fence *fence = NULL; |
Chunming Zhou | d5fc5e8 | 2015-07-21 16:52:10 +0800 | [diff] [blame] | 1023 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1024 | int r; |
| 1025 | |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1026 | if (!parent->entries) |
| 1027 | return 0; |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 1028 | |
Christian König | 27c5f36 | 2016-08-04 15:02:49 +0200 | [diff] [blame] | 1029 | memset(¶ms, 0, sizeof(params)); |
| 1030 | params.adev = adev; |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 1031 | shadow = parent->bo->shadow; |
| 1032 | |
Alex Deucher | 6927798 | 2017-07-13 15:37:11 -0400 | [diff] [blame] | 1033 | if (vm->use_cpu_for_update) { |
Christian König | f5e1c74 | 2017-07-20 23:45:18 +0200 | [diff] [blame] | 1034 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo); |
Christian König | a33cab7 | 2017-07-11 17:13:00 +0200 | [diff] [blame] | 1035 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 1036 | if (unlikely(r)) |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 1037 | return r; |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 1038 | |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 1039 | params.func = amdgpu_vm_cpu_set_ptes; |
| 1040 | } else { |
| 1041 | if (shadow) { |
| 1042 | r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); |
| 1043 | if (r) |
| 1044 | return r; |
| 1045 | } |
| 1046 | ring = container_of(vm->entity.sched, struct amdgpu_ring, |
| 1047 | sched); |
| 1048 | |
| 1049 | /* padding, etc. */ |
| 1050 | ndw = 64; |
| 1051 | |
| 1052 | /* assume the worst case */ |
| 1053 | ndw += parent->last_entry_used * 6; |
| 1054 | |
| 1055 | pd_addr = amdgpu_bo_gpu_offset(parent->bo); |
| 1056 | |
| 1057 | if (shadow) { |
| 1058 | shadow_addr = amdgpu_bo_gpu_offset(shadow); |
| 1059 | ndw *= 2; |
| 1060 | } else { |
| 1061 | shadow_addr = 0; |
| 1062 | } |
| 1063 | |
| 1064 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
| 1065 | if (r) |
| 1066 | return r; |
| 1067 | |
| 1068 | params.ib = &job->ibs[0]; |
| 1069 | params.func = amdgpu_vm_do_set_ptes; |
| 1070 | } |
| 1071 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1072 | |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1073 | /* walk over the address space and update the directory */ |
| 1074 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { |
| 1075 | struct amdgpu_bo *bo = parent->entries[pt_idx].bo; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1076 | uint64_t pde, pt; |
| 1077 | |
| 1078 | if (bo == NULL) |
| 1079 | continue; |
| 1080 | |
Christian König | 0fc8683 | 2016-09-16 11:46:23 +0200 | [diff] [blame] | 1081 | if (bo->shadow) { |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1082 | struct amdgpu_bo *pt_shadow = bo->shadow; |
Christian König | 0fc8683 | 2016-09-16 11:46:23 +0200 | [diff] [blame] | 1083 | |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1084 | r = amdgpu_ttm_bind(&pt_shadow->tbo, |
| 1085 | &pt_shadow->tbo.mem); |
Christian König | 0fc8683 | 2016-09-16 11:46:23 +0200 | [diff] [blame] | 1086 | if (r) |
| 1087 | return r; |
| 1088 | } |
| 1089 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1090 | pt = amdgpu_bo_gpu_offset(bo); |
Christian König | 53e2e91 | 2017-05-15 15:19:10 +0200 | [diff] [blame] | 1091 | pt = amdgpu_gart_get_vm_pde(adev, pt); |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1092 | if (parent->entries[pt_idx].addr == pt || |
| 1093 | parent->entries[pt_idx].huge_page) |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1094 | continue; |
| 1095 | |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1096 | parent->entries[pt_idx].addr = pt; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1097 | |
| 1098 | pde = pd_addr + pt_idx * 8; |
| 1099 | if (((last_pde + 8 * count) != pde) || |
Christian König | 96105e5 | 2016-08-12 12:59:59 +0200 | [diff] [blame] | 1100 | ((last_pt + incr * count) != pt) || |
| 1101 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1102 | |
| 1103 | if (count) { |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1104 | if (shadow) |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 1105 | params.func(¶ms, |
| 1106 | last_shadow, |
| 1107 | last_pt, count, |
| 1108 | incr, |
| 1109 | AMDGPU_PTE_VALID); |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1110 | |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 1111 | params.func(¶ms, last_pde, |
| 1112 | last_pt, count, incr, |
| 1113 | AMDGPU_PTE_VALID); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1114 | } |
| 1115 | |
| 1116 | count = 1; |
| 1117 | last_pde = pde; |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1118 | last_shadow = shadow_addr + pt_idx * 8; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1119 | last_pt = pt; |
| 1120 | } else { |
| 1121 | ++count; |
| 1122 | } |
| 1123 | } |
| 1124 | |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1125 | if (count) { |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 1126 | if (vm->root.bo->shadow) |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 1127 | params.func(¶ms, last_shadow, last_pt, |
| 1128 | count, incr, AMDGPU_PTE_VALID); |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1129 | |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 1130 | params.func(¶ms, last_pde, last_pt, |
| 1131 | count, incr, AMDGPU_PTE_VALID); |
Chunming Zhou | d5fc5e8 | 2015-07-21 16:52:10 +0800 | [diff] [blame] | 1132 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1133 | |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 1134 | if (!vm->use_cpu_for_update) { |
| 1135 | if (params.ib->length_dw == 0) { |
| 1136 | amdgpu_job_free(job); |
| 1137 | } else { |
| 1138 | amdgpu_ring_pad_ib(ring, params.ib); |
| 1139 | amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv, |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1140 | AMDGPU_FENCE_OWNER_VM); |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 1141 | if (shadow) |
| 1142 | amdgpu_sync_resv(adev, &job->sync, |
| 1143 | shadow->tbo.resv, |
| 1144 | AMDGPU_FENCE_OWNER_VM); |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1145 | |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 1146 | WARN_ON(params.ib->length_dw > ndw); |
| 1147 | r = amdgpu_job_submit(job, ring, &vm->entity, |
| 1148 | AMDGPU_FENCE_OWNER_VM, &fence); |
| 1149 | if (r) |
| 1150 | goto error_free; |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1151 | |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 1152 | amdgpu_bo_fence(parent->bo, fence, true); |
| 1153 | dma_fence_put(vm->last_dir_update); |
| 1154 | vm->last_dir_update = dma_fence_get(fence); |
| 1155 | dma_fence_put(fence); |
| 1156 | } |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1157 | } |
| 1158 | /* |
| 1159 | * Recurse into the subdirectories. This recursion is harmless because |
| 1160 | * we only have a maximum of 5 layers. |
| 1161 | */ |
| 1162 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { |
| 1163 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
| 1164 | |
| 1165 | if (!entry->bo) |
| 1166 | continue; |
| 1167 | |
| 1168 | r = amdgpu_vm_update_level(adev, vm, entry, level + 1); |
| 1169 | if (r) |
| 1170 | return r; |
| 1171 | } |
Christian König | f8991ba | 2016-09-16 15:36:49 +0200 | [diff] [blame] | 1172 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1173 | return 0; |
Chunming Zhou | d5fc5e8 | 2015-07-21 16:52:10 +0800 | [diff] [blame] | 1174 | |
| 1175 | error_free: |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 1176 | amdgpu_job_free(job); |
Chunming Zhou | 4af9f07 | 2015-08-03 12:57:31 +0800 | [diff] [blame] | 1177 | return r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1178 | } |
| 1179 | |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1180 | /* |
Christian König | 92456b9 | 2017-05-12 16:09:26 +0200 | [diff] [blame] | 1181 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid |
| 1182 | * |
| 1183 | * @parent: parent PD |
| 1184 | * |
| 1185 | * Mark all PD level as invalid after an error. |
| 1186 | */ |
| 1187 | static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent) |
| 1188 | { |
| 1189 | unsigned pt_idx; |
| 1190 | |
| 1191 | /* |
| 1192 | * Recurse into the subdirectories. This recursion is harmless because |
| 1193 | * we only have a maximum of 5 layers. |
| 1194 | */ |
| 1195 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { |
| 1196 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
| 1197 | |
| 1198 | if (!entry->bo) |
| 1199 | continue; |
| 1200 | |
| 1201 | entry->addr = ~0ULL; |
| 1202 | amdgpu_vm_invalidate_level(entry); |
| 1203 | } |
| 1204 | } |
| 1205 | |
| 1206 | /* |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1207 | * amdgpu_vm_update_directories - make sure that all directories are valid |
| 1208 | * |
| 1209 | * @adev: amdgpu_device pointer |
| 1210 | * @vm: requested vm |
| 1211 | * |
| 1212 | * Makes sure all directories are up to date. |
| 1213 | * Returns 0 for success, error for failure. |
| 1214 | */ |
| 1215 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, |
| 1216 | struct amdgpu_vm *vm) |
| 1217 | { |
Christian König | 92456b9 | 2017-05-12 16:09:26 +0200 | [diff] [blame] | 1218 | int r; |
| 1219 | |
| 1220 | r = amdgpu_vm_update_level(adev, vm, &vm->root, 0); |
| 1221 | if (r) |
| 1222 | amdgpu_vm_invalidate_level(&vm->root); |
| 1223 | |
Christian König | 68c6230 | 2017-07-11 17:23:29 +0200 | [diff] [blame] | 1224 | if (vm->use_cpu_for_update) { |
| 1225 | /* Flush HDP */ |
| 1226 | mb(); |
| 1227 | amdgpu_gart_flush_gpu_tlb(adev, 0); |
| 1228 | } |
| 1229 | |
Christian König | 92456b9 | 2017-05-12 16:09:26 +0200 | [diff] [blame] | 1230 | return r; |
Christian König | 194d216 | 2016-10-12 15:13:52 +0200 | [diff] [blame] | 1231 | } |
| 1232 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1233 | /** |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1234 | * amdgpu_vm_find_entry - find the entry for an address |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1235 | * |
| 1236 | * @p: see amdgpu_pte_update_params definition |
| 1237 | * @addr: virtual address in question |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1238 | * @entry: resulting entry or NULL |
| 1239 | * @parent: parent entry |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1240 | * |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1241 | * Find the vm_pt entry and it's parent for the given address. |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1242 | */ |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1243 | void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, |
| 1244 | struct amdgpu_vm_pt **entry, |
| 1245 | struct amdgpu_vm_pt **parent) |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1246 | { |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1247 | unsigned idx, level = p->adev->vm_manager.num_level; |
| 1248 | |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1249 | *parent = NULL; |
| 1250 | *entry = &p->vm->root; |
| 1251 | while ((*entry)->entries) { |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 1252 | idx = addr >> (p->adev->vm_manager.block_size * level--); |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1253 | idx %= amdgpu_bo_size((*entry)->bo) / 8; |
| 1254 | *parent = *entry; |
| 1255 | *entry = &(*entry)->entries[idx]; |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1256 | } |
| 1257 | |
| 1258 | if (level) |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1259 | *entry = NULL; |
| 1260 | } |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1261 | |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1262 | /** |
| 1263 | * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages |
| 1264 | * |
| 1265 | * @p: see amdgpu_pte_update_params definition |
| 1266 | * @entry: vm_pt entry to check |
| 1267 | * @parent: parent entry |
| 1268 | * @nptes: number of PTEs updated with this operation |
| 1269 | * @dst: destination address where the PTEs should point to |
| 1270 | * @flags: access flags fro the PTEs |
| 1271 | * |
| 1272 | * Check if we can update the PD with a huge page. |
| 1273 | */ |
| 1274 | static int amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, |
| 1275 | struct amdgpu_vm_pt *entry, |
| 1276 | struct amdgpu_vm_pt *parent, |
| 1277 | unsigned nptes, uint64_t dst, |
| 1278 | uint64_t flags) |
| 1279 | { |
| 1280 | bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes); |
| 1281 | uint64_t pd_addr, pde; |
| 1282 | int r; |
| 1283 | |
| 1284 | /* In the case of a mixed PT the PDE must point to it*/ |
| 1285 | if (p->adev->asic_type < CHIP_VEGA10 || |
| 1286 | nptes != AMDGPU_VM_PTE_COUNT(p->adev) || |
| 1287 | p->func == amdgpu_vm_do_copy_ptes || |
| 1288 | !(flags & AMDGPU_PTE_VALID)) { |
| 1289 | |
| 1290 | dst = amdgpu_bo_gpu_offset(entry->bo); |
| 1291 | dst = amdgpu_gart_get_vm_pde(p->adev, dst); |
| 1292 | flags = AMDGPU_PTE_VALID; |
| 1293 | } else { |
| 1294 | flags |= AMDGPU_PDE_PTE; |
| 1295 | } |
| 1296 | |
| 1297 | if (entry->addr == dst && |
| 1298 | entry->huge_page == !!(flags & AMDGPU_PDE_PTE)) |
| 1299 | return 0; |
| 1300 | |
| 1301 | entry->addr = dst; |
| 1302 | entry->huge_page = !!(flags & AMDGPU_PDE_PTE); |
| 1303 | |
| 1304 | if (use_cpu_update) { |
| 1305 | r = amdgpu_bo_kmap(parent->bo, (void *)&pd_addr); |
| 1306 | if (r) |
| 1307 | return r; |
| 1308 | |
| 1309 | pde = pd_addr + (entry - parent->entries) * 8; |
| 1310 | amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags); |
| 1311 | } else { |
| 1312 | if (parent->bo->shadow) { |
| 1313 | pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow); |
| 1314 | pde = pd_addr + (entry - parent->entries) * 8; |
| 1315 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); |
| 1316 | } |
| 1317 | pd_addr = amdgpu_bo_gpu_offset(parent->bo); |
| 1318 | pde = pd_addr + (entry - parent->entries) * 8; |
| 1319 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); |
| 1320 | } |
| 1321 | |
| 1322 | return 0; |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1323 | } |
| 1324 | |
| 1325 | /** |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1326 | * amdgpu_vm_update_ptes - make sure that page tables are valid |
| 1327 | * |
| 1328 | * @params: see amdgpu_pte_update_params definition |
| 1329 | * @vm: requested vm |
| 1330 | * @start: start of GPU address range |
| 1331 | * @end: end of GPU address range |
| 1332 | * @dst: destination address to map to, the next dst inside the function |
| 1333 | * @flags: mapping flags |
| 1334 | * |
| 1335 | * Update the page tables in the range @start - @end. |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1336 | * Returns 0 for success, -EINVAL for failure. |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1337 | */ |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1338 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1339 | uint64_t start, uint64_t end, |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 1340 | uint64_t dst, uint64_t flags) |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1341 | { |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 1342 | struct amdgpu_device *adev = params->adev; |
| 1343 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1344 | |
Christian König | 301654a | 2017-05-16 14:30:27 +0200 | [diff] [blame] | 1345 | uint64_t addr, pe_start; |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1346 | struct amdgpu_bo *pt; |
Christian König | 301654a | 2017-05-16 14:30:27 +0200 | [diff] [blame] | 1347 | unsigned nptes; |
Harish Kasiviswanathan | 370f092 | 2017-06-09 17:47:27 -0400 | [diff] [blame] | 1348 | bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1349 | int r; |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1350 | |
| 1351 | /* walk over the address space and update the page tables */ |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1352 | for (addr = start; addr < end; addr += nptes, |
| 1353 | dst += nptes * AMDGPU_GPU_PAGE_SIZE) { |
| 1354 | struct amdgpu_vm_pt *entry, *parent; |
| 1355 | |
| 1356 | amdgpu_vm_get_entry(params, addr, &entry, &parent); |
| 1357 | if (!entry) |
| 1358 | return -ENOENT; |
Christian König | 4e2cb64 | 2016-10-25 15:52:28 +0200 | [diff] [blame] | 1359 | |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1360 | if ((addr & ~mask) == (end & ~mask)) |
| 1361 | nptes = end - addr; |
| 1362 | else |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 1363 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1364 | |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1365 | r = amdgpu_vm_handle_huge_pages(params, entry, parent, |
| 1366 | nptes, dst, flags); |
| 1367 | if (r) |
| 1368 | return r; |
| 1369 | |
| 1370 | if (entry->huge_page) |
| 1371 | continue; |
| 1372 | |
| 1373 | pt = entry->bo; |
Harish Kasiviswanathan | 370f092 | 2017-06-09 17:47:27 -0400 | [diff] [blame] | 1374 | if (use_cpu_update) { |
Christian König | f5e1c74 | 2017-07-20 23:45:18 +0200 | [diff] [blame] | 1375 | pe_start = (unsigned long)amdgpu_bo_kptr(pt); |
Christian König | dd0792c | 2017-06-27 14:48:15 -0400 | [diff] [blame] | 1376 | } else { |
| 1377 | if (pt->shadow) { |
| 1378 | pe_start = amdgpu_bo_gpu_offset(pt->shadow); |
| 1379 | pe_start += (addr & mask) * 8; |
| 1380 | params->func(params, pe_start, dst, nptes, |
| 1381 | AMDGPU_GPU_PAGE_SIZE, flags); |
| 1382 | } |
Harish Kasiviswanathan | 370f092 | 2017-06-09 17:47:27 -0400 | [diff] [blame] | 1383 | pe_start = amdgpu_bo_gpu_offset(pt); |
Christian König | dd0792c | 2017-06-27 14:48:15 -0400 | [diff] [blame] | 1384 | } |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1385 | |
Christian König | 301654a | 2017-05-16 14:30:27 +0200 | [diff] [blame] | 1386 | pe_start += (addr & mask) * 8; |
Christian König | 301654a | 2017-05-16 14:30:27 +0200 | [diff] [blame] | 1387 | params->func(params, pe_start, dst, nptes, |
| 1388 | AMDGPU_GPU_PAGE_SIZE, flags); |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1389 | } |
| 1390 | |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1391 | return 0; |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1392 | } |
| 1393 | |
| 1394 | /* |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1395 | * amdgpu_vm_frag_ptes - add fragment information to PTEs |
| 1396 | * |
Christian König | 29efc4f | 2016-08-04 14:52:50 +0200 | [diff] [blame] | 1397 | * @params: see amdgpu_pte_update_params definition |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1398 | * @vm: requested vm |
| 1399 | * @start: first PTE to handle |
| 1400 | * @end: last PTE to handle |
| 1401 | * @dst: addr those PTEs should point to |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1402 | * @flags: hw mapping flags |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1403 | * Returns 0 for success, -EINVAL for failure. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1404 | */ |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1405 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1406 | uint64_t start, uint64_t end, |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 1407 | uint64_t dst, uint64_t flags) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1408 | { |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1409 | int r; |
| 1410 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1411 | /** |
| 1412 | * The MC L1 TLB supports variable sized pages, based on a fragment |
| 1413 | * field in the PTE. When this field is set to a non-zero value, page |
| 1414 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE |
| 1415 | * flags are considered valid for all PTEs within the fragment range |
| 1416 | * and corresponding mappings are assumed to be physically contiguous. |
| 1417 | * |
| 1418 | * The L1 TLB can store a single PTE for the whole fragment, |
| 1419 | * significantly increasing the space available for translation |
| 1420 | * caching. This leads to large improvements in throughput when the |
| 1421 | * TLB is under pressure. |
| 1422 | * |
| 1423 | * The L2 TLB distributes small and large fragments into two |
| 1424 | * asymmetric partitions. The large fragment cache is significantly |
| 1425 | * larger. Thus, we try to use large fragments wherever possible. |
| 1426 | * Userspace can support this by aligning virtual base address and |
| 1427 | * allocation size to the fragment size. |
| 1428 | */ |
| 1429 | |
Christian König | 8036617 | 2016-10-04 13:39:43 +0200 | [diff] [blame] | 1430 | /* SI and newer are optimized for 64KB */ |
Christian König | 6be7adb | 2017-05-23 18:35:22 +0200 | [diff] [blame] | 1431 | unsigned pages_per_frag = AMDGPU_LOG2_PAGES_PER_FRAG(params->adev); |
| 1432 | uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag); |
| 1433 | uint64_t frag_align = 1 << pages_per_frag; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1434 | |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1435 | uint64_t frag_start = ALIGN(start, frag_align); |
| 1436 | uint64_t frag_end = end & ~(frag_align - 1); |
Christian König | 31f6c1f | 2016-01-26 12:37:49 +0100 | [diff] [blame] | 1437 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1438 | /* system pages are non continuously */ |
Christian König | b7fc2cb | 2016-08-11 16:44:15 +0200 | [diff] [blame] | 1439 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1440 | (frag_start >= frag_end)) |
| 1441 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1442 | |
| 1443 | /* handle the 4K area at the beginning */ |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1444 | if (start != frag_start) { |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1445 | r = amdgpu_vm_update_ptes(params, start, frag_start, |
| 1446 | dst, flags); |
| 1447 | if (r) |
| 1448 | return r; |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1449 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1450 | } |
| 1451 | |
| 1452 | /* handle the area in the middle */ |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1453 | r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, |
| 1454 | flags | frag_flags); |
| 1455 | if (r) |
| 1456 | return r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1457 | |
| 1458 | /* handle the 4K area at the end */ |
Christian König | 92696dd | 2016-08-05 13:56:35 +0200 | [diff] [blame] | 1459 | if (frag_end != end) { |
| 1460 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1461 | r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1462 | } |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1463 | return r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1464 | } |
| 1465 | |
| 1466 | /** |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1467 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table |
| 1468 | * |
| 1469 | * @adev: amdgpu_device pointer |
Christian König | 3cabaa5 | 2016-06-06 10:17:58 +0200 | [diff] [blame] | 1470 | * @exclusive: fence we need to sync to |
Christian König | fa3ab3c | 2016-03-18 21:00:35 +0100 | [diff] [blame] | 1471 | * @src: address where to copy page table entries from |
| 1472 | * @pages_addr: DMA addresses to use for mapping |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1473 | * @vm: requested vm |
| 1474 | * @start: start of mapped range |
| 1475 | * @last: last mapped entry |
| 1476 | * @flags: flags for the entries |
| 1477 | * @addr: addr to set the area to |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1478 | * @fence: optional resulting fence |
| 1479 | * |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1480 | * Fill in the page table entries between @start and @last. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1481 | * Returns 0 for success, -EINVAL for failure. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1482 | */ |
| 1483 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1484 | struct dma_fence *exclusive, |
Christian König | fa3ab3c | 2016-03-18 21:00:35 +0100 | [diff] [blame] | 1485 | uint64_t src, |
| 1486 | dma_addr_t *pages_addr, |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1487 | struct amdgpu_vm *vm, |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1488 | uint64_t start, uint64_t last, |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 1489 | uint64_t flags, uint64_t addr, |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1490 | struct dma_fence **fence) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1491 | { |
Christian König | 2d55e45 | 2016-02-08 17:37:38 +0100 | [diff] [blame] | 1492 | struct amdgpu_ring *ring; |
Christian König | a1e08d3 | 2016-01-26 11:40:46 +0100 | [diff] [blame] | 1493 | void *owner = AMDGPU_FENCE_OWNER_VM; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1494 | unsigned nptes, ncmds, ndw; |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 1495 | struct amdgpu_job *job; |
Christian König | 29efc4f | 2016-08-04 14:52:50 +0200 | [diff] [blame] | 1496 | struct amdgpu_pte_update_params params; |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1497 | struct dma_fence *f = NULL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1498 | int r; |
| 1499 | |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 1500 | memset(¶ms, 0, sizeof(params)); |
| 1501 | params.adev = adev; |
Christian König | 49ac8a2 | 2016-10-13 15:09:08 +0200 | [diff] [blame] | 1502 | params.vm = vm; |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 1503 | params.src = src; |
| 1504 | |
Christian König | a33cab7 | 2017-07-11 17:13:00 +0200 | [diff] [blame] | 1505 | /* sync to everything on unmapping */ |
| 1506 | if (!(flags & AMDGPU_PTE_VALID)) |
| 1507 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; |
| 1508 | |
Harish Kasiviswanathan | b4d4251 | 2017-05-11 19:47:22 -0400 | [diff] [blame] | 1509 | if (vm->use_cpu_for_update) { |
| 1510 | /* params.src is used as flag to indicate system Memory */ |
| 1511 | if (pages_addr) |
| 1512 | params.src = ~0; |
| 1513 | |
| 1514 | /* Wait for PT BOs to be free. PTs share the same resv. object |
| 1515 | * as the root PD BO |
| 1516 | */ |
Christian König | a33cab7 | 2017-07-11 17:13:00 +0200 | [diff] [blame] | 1517 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
Harish Kasiviswanathan | b4d4251 | 2017-05-11 19:47:22 -0400 | [diff] [blame] | 1518 | if (unlikely(r)) |
| 1519 | return r; |
| 1520 | |
| 1521 | params.func = amdgpu_vm_cpu_set_ptes; |
| 1522 | params.pages_addr = pages_addr; |
Harish Kasiviswanathan | b4d4251 | 2017-05-11 19:47:22 -0400 | [diff] [blame] | 1523 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
| 1524 | addr, flags); |
| 1525 | } |
| 1526 | |
Christian König | 2d55e45 | 2016-02-08 17:37:38 +0100 | [diff] [blame] | 1527 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
Christian König | 27c5f36 | 2016-08-04 15:02:49 +0200 | [diff] [blame] | 1528 | |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1529 | nptes = last - start + 1; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1530 | |
| 1531 | /* |
| 1532 | * reserve space for one command every (1 << BLOCK_SIZE) |
| 1533 | * entries or 2k dwords (whatever is smaller) |
| 1534 | */ |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 1535 | ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1536 | |
| 1537 | /* padding, etc. */ |
| 1538 | ndw = 64; |
| 1539 | |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1540 | /* one PDE write for each huge page */ |
| 1541 | ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6; |
| 1542 | |
Christian König | b0456f9 | 2016-08-11 14:06:54 +0200 | [diff] [blame] | 1543 | if (src) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1544 | /* only copy commands needed */ |
| 1545 | ndw += ncmds * 7; |
| 1546 | |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 1547 | params.func = amdgpu_vm_do_copy_ptes; |
| 1548 | |
Christian König | b0456f9 | 2016-08-11 14:06:54 +0200 | [diff] [blame] | 1549 | } else if (pages_addr) { |
| 1550 | /* copy commands needed */ |
| 1551 | ndw += ncmds * 7; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1552 | |
Christian König | b0456f9 | 2016-08-11 14:06:54 +0200 | [diff] [blame] | 1553 | /* and also PTEs */ |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1554 | ndw += nptes * 2; |
| 1555 | |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 1556 | params.func = amdgpu_vm_do_copy_ptes; |
| 1557 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1558 | } else { |
| 1559 | /* set page commands needed */ |
| 1560 | ndw += ncmds * 10; |
| 1561 | |
| 1562 | /* two extra commands for begin/end of fragment */ |
| 1563 | ndw += 2 * 10; |
Christian König | afef8b8 | 2016-08-12 13:29:18 +0200 | [diff] [blame] | 1564 | |
| 1565 | params.func = amdgpu_vm_do_set_ptes; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1566 | } |
| 1567 | |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 1568 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
| 1569 | if (r) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1570 | return r; |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 1571 | |
Christian König | 29efc4f | 2016-08-04 14:52:50 +0200 | [diff] [blame] | 1572 | params.ib = &job->ibs[0]; |
Chunming Zhou | d5fc5e8 | 2015-07-21 16:52:10 +0800 | [diff] [blame] | 1573 | |
Christian König | b0456f9 | 2016-08-11 14:06:54 +0200 | [diff] [blame] | 1574 | if (!src && pages_addr) { |
| 1575 | uint64_t *pte; |
| 1576 | unsigned i; |
| 1577 | |
| 1578 | /* Put the PTEs at the end of the IB. */ |
| 1579 | i = ndw - nptes * 2; |
| 1580 | pte= (uint64_t *)&(job->ibs->ptr[i]); |
| 1581 | params.src = job->ibs->gpu_addr + i * 4; |
| 1582 | |
| 1583 | for (i = 0; i < nptes; ++i) { |
| 1584 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * |
| 1585 | AMDGPU_GPU_PAGE_SIZE); |
| 1586 | pte[i] |= flags; |
| 1587 | } |
Christian König | d7a4ac6 | 2016-09-25 11:54:00 +0200 | [diff] [blame] | 1588 | addr = 0; |
Christian König | b0456f9 | 2016-08-11 14:06:54 +0200 | [diff] [blame] | 1589 | } |
| 1590 | |
Christian König | 3cabaa5 | 2016-06-06 10:17:58 +0200 | [diff] [blame] | 1591 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
| 1592 | if (r) |
| 1593 | goto error_free; |
| 1594 | |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 1595 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, |
Christian König | a1e08d3 | 2016-01-26 11:40:46 +0100 | [diff] [blame] | 1596 | owner); |
| 1597 | if (r) |
| 1598 | goto error_free; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1599 | |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 1600 | r = reservation_object_reserve_shared(vm->root.bo->tbo.resv); |
Christian König | a1e08d3 | 2016-01-26 11:40:46 +0100 | [diff] [blame] | 1601 | if (r) |
| 1602 | goto error_free; |
| 1603 | |
Harish Kasiviswanathan | cc28c4e | 2017-05-11 22:39:31 -0400 | [diff] [blame] | 1604 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
| 1605 | if (r) |
| 1606 | goto error_free; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1607 | |
Christian König | 29efc4f | 2016-08-04 14:52:50 +0200 | [diff] [blame] | 1608 | amdgpu_ring_pad_ib(ring, params.ib); |
| 1609 | WARN_ON(params.ib->length_dw > ndw); |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 1610 | r = amdgpu_job_submit(job, ring, &vm->entity, |
| 1611 | AMDGPU_FENCE_OWNER_VM, &f); |
Chunming Zhou | 4af9f07 | 2015-08-03 12:57:31 +0800 | [diff] [blame] | 1612 | if (r) |
| 1613 | goto error_free; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1614 | |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 1615 | amdgpu_bo_fence(vm->root.bo, f, true); |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1616 | dma_fence_put(*fence); |
| 1617 | *fence = f; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1618 | return 0; |
Chunming Zhou | d5fc5e8 | 2015-07-21 16:52:10 +0800 | [diff] [blame] | 1619 | |
| 1620 | error_free: |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 1621 | amdgpu_job_free(job); |
Alex Deucher | cf2f0a3 | 2017-07-25 16:35:38 -0400 | [diff] [blame] | 1622 | amdgpu_vm_invalidate_level(&vm->root); |
Chunming Zhou | 4af9f07 | 2015-08-03 12:57:31 +0800 | [diff] [blame] | 1623 | return r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1624 | } |
| 1625 | |
| 1626 | /** |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1627 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks |
| 1628 | * |
| 1629 | * @adev: amdgpu_device pointer |
Christian König | 3cabaa5 | 2016-06-06 10:17:58 +0200 | [diff] [blame] | 1630 | * @exclusive: fence we need to sync to |
Christian König | 8358dce | 2016-03-30 10:50:25 +0200 | [diff] [blame] | 1631 | * @gtt_flags: flags as they are used for GTT |
| 1632 | * @pages_addr: DMA addresses to use for mapping |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1633 | * @vm: requested vm |
| 1634 | * @mapping: mapped range and flags to use for the update |
Christian König | 8358dce | 2016-03-30 10:50:25 +0200 | [diff] [blame] | 1635 | * @flags: HW flags for the mapping |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1636 | * @nodes: array of drm_mm_nodes with the MC addresses |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1637 | * @fence: optional resulting fence |
| 1638 | * |
| 1639 | * Split the mapping into smaller chunks so that each update fits |
| 1640 | * into a SDMA IB. |
| 1641 | * Returns 0 for success, -EINVAL for failure. |
| 1642 | */ |
| 1643 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1644 | struct dma_fence *exclusive, |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 1645 | uint64_t gtt_flags, |
Christian König | 8358dce | 2016-03-30 10:50:25 +0200 | [diff] [blame] | 1646 | dma_addr_t *pages_addr, |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1647 | struct amdgpu_vm *vm, |
| 1648 | struct amdgpu_bo_va_mapping *mapping, |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 1649 | uint64_t flags, |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1650 | struct drm_mm_node *nodes, |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1651 | struct dma_fence **fence) |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1652 | { |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 1653 | uint64_t pfn, src = 0, start = mapping->start; |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1654 | int r; |
| 1655 | |
| 1656 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here |
| 1657 | * but in case of something, we filter the flags in first place |
| 1658 | */ |
| 1659 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) |
| 1660 | flags &= ~AMDGPU_PTE_READABLE; |
| 1661 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) |
| 1662 | flags &= ~AMDGPU_PTE_WRITEABLE; |
| 1663 | |
Alex Xie | 15b31c5 | 2017-03-03 16:47:11 -0500 | [diff] [blame] | 1664 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
| 1665 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; |
| 1666 | |
Alex Xie | b0fd18b | 2017-03-03 16:49:39 -0500 | [diff] [blame] | 1667 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
| 1668 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); |
| 1669 | |
Zhang, Jerry | d0766e9 | 2017-04-19 09:53:29 +0800 | [diff] [blame] | 1670 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
| 1671 | (adev->asic_type >= CHIP_VEGA10)) { |
| 1672 | flags |= AMDGPU_PTE_PRT; |
| 1673 | flags &= ~AMDGPU_PTE_VALID; |
| 1674 | } |
| 1675 | |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1676 | trace_amdgpu_vm_bo_update(mapping); |
| 1677 | |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1678 | pfn = mapping->offset >> PAGE_SHIFT; |
| 1679 | if (nodes) { |
| 1680 | while (pfn >= nodes->size) { |
| 1681 | pfn -= nodes->size; |
| 1682 | ++nodes; |
| 1683 | } |
Christian König | fa3ab3c | 2016-03-18 21:00:35 +0100 | [diff] [blame] | 1684 | } |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1685 | |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1686 | do { |
| 1687 | uint64_t max_entries; |
| 1688 | uint64_t addr, last; |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1689 | |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1690 | if (nodes) { |
| 1691 | addr = nodes->start << PAGE_SHIFT; |
| 1692 | max_entries = (nodes->size - pfn) * |
| 1693 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); |
| 1694 | } else { |
| 1695 | addr = 0; |
| 1696 | max_entries = S64_MAX; |
| 1697 | } |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1698 | |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1699 | if (pages_addr) { |
| 1700 | if (flags == gtt_flags) |
| 1701 | src = adev->gart.table_addr + |
| 1702 | (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; |
| 1703 | else |
| 1704 | max_entries = min(max_entries, 16ull * 1024ull); |
| 1705 | addr = 0; |
| 1706 | } else if (flags & AMDGPU_PTE_VALID) { |
| 1707 | addr += adev->vm_manager.vram_base_offset; |
| 1708 | } |
| 1709 | addr += pfn << PAGE_SHIFT; |
| 1710 | |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 1711 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
Christian König | 3cabaa5 | 2016-06-06 10:17:58 +0200 | [diff] [blame] | 1712 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
| 1713 | src, pages_addr, vm, |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1714 | start, last, flags, addr, |
| 1715 | fence); |
| 1716 | if (r) |
| 1717 | return r; |
| 1718 | |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1719 | pfn += last - start + 1; |
| 1720 | if (nodes && nodes->size == pfn) { |
| 1721 | pfn = 0; |
| 1722 | ++nodes; |
| 1723 | } |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1724 | start = last + 1; |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1725 | |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 1726 | } while (unlikely(start != mapping->last + 1)); |
Christian König | a14faa6 | 2016-01-25 14:27:31 +0100 | [diff] [blame] | 1727 | |
| 1728 | return 0; |
| 1729 | } |
| 1730 | |
| 1731 | /** |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1732 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table |
| 1733 | * |
| 1734 | * @adev: amdgpu_device pointer |
| 1735 | * @bo_va: requested BO and VM object |
Christian König | 99e124f | 2016-08-16 14:43:17 +0200 | [diff] [blame] | 1736 | * @clear: if true clear the entries |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1737 | * |
| 1738 | * Fill in the page table entries for @bo_va. |
| 1739 | * Returns 0 for success, -EINVAL for failure. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1740 | */ |
| 1741 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, |
| 1742 | struct amdgpu_bo_va *bo_va, |
Christian König | 99e124f | 2016-08-16 14:43:17 +0200 | [diff] [blame] | 1743 | bool clear) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1744 | { |
| 1745 | struct amdgpu_vm *vm = bo_va->vm; |
| 1746 | struct amdgpu_bo_va_mapping *mapping; |
Christian König | 8358dce | 2016-03-30 10:50:25 +0200 | [diff] [blame] | 1747 | dma_addr_t *pages_addr = NULL; |
Chunming Zhou | 6b77760 | 2016-09-21 16:19:19 +0800 | [diff] [blame] | 1748 | uint64_t gtt_flags, flags; |
Christian König | 99e124f | 2016-08-16 14:43:17 +0200 | [diff] [blame] | 1749 | struct ttm_mem_reg *mem; |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1750 | struct drm_mm_node *nodes; |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1751 | struct dma_fence *exclusive; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1752 | int r; |
| 1753 | |
Christian König | a5f6b5b | 2017-01-30 11:01:38 +0100 | [diff] [blame] | 1754 | if (clear || !bo_va->bo) { |
Christian König | 99e124f | 2016-08-16 14:43:17 +0200 | [diff] [blame] | 1755 | mem = NULL; |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1756 | nodes = NULL; |
Christian König | 99e124f | 2016-08-16 14:43:17 +0200 | [diff] [blame] | 1757 | exclusive = NULL; |
| 1758 | } else { |
Christian König | 8358dce | 2016-03-30 10:50:25 +0200 | [diff] [blame] | 1759 | struct ttm_dma_tt *ttm; |
| 1760 | |
Christian König | 99e124f | 2016-08-16 14:43:17 +0200 | [diff] [blame] | 1761 | mem = &bo_va->bo->tbo.mem; |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1762 | nodes = mem->mm_node; |
| 1763 | if (mem->mem_type == TTM_PL_TT) { |
Christian König | 8358dce | 2016-03-30 10:50:25 +0200 | [diff] [blame] | 1764 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
| 1765 | ttm_dma_tt, ttm); |
| 1766 | pages_addr = ttm->dma_address; |
Christian König | 9ab2146 | 2015-11-30 14:19:26 +0100 | [diff] [blame] | 1767 | } |
Christian König | 3cabaa5 | 2016-06-06 10:17:58 +0200 | [diff] [blame] | 1768 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1769 | } |
| 1770 | |
Christian König | a5f6b5b | 2017-01-30 11:01:38 +0100 | [diff] [blame] | 1771 | if (bo_va->bo) { |
| 1772 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
| 1773 | gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && |
| 1774 | adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? |
| 1775 | flags : 0; |
| 1776 | } else { |
| 1777 | flags = 0x0; |
| 1778 | gtt_flags = ~0x0; |
| 1779 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1780 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 1781 | spin_lock(&vm->status_lock); |
| 1782 | if (!list_empty(&bo_va->vm_status)) |
| 1783 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
| 1784 | spin_unlock(&vm->status_lock); |
| 1785 | |
| 1786 | list_for_each_entry(mapping, &bo_va->invalids, list) { |
Christian König | 3cabaa5 | 2016-06-06 10:17:58 +0200 | [diff] [blame] | 1787 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
| 1788 | gtt_flags, pages_addr, vm, |
Christian König | 63e0ba4 | 2016-08-16 17:38:37 +0200 | [diff] [blame] | 1789 | mapping, flags, nodes, |
Christian König | 8358dce | 2016-03-30 10:50:25 +0200 | [diff] [blame] | 1790 | &bo_va->last_pt_update); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1791 | if (r) |
| 1792 | return r; |
| 1793 | } |
| 1794 | |
Christian König | d6c10f6 | 2015-09-28 12:00:23 +0200 | [diff] [blame] | 1795 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
| 1796 | list_for_each_entry(mapping, &bo_va->valids, list) |
| 1797 | trace_amdgpu_vm_bo_mapping(mapping); |
| 1798 | |
| 1799 | list_for_each_entry(mapping, &bo_va->invalids, list) |
| 1800 | trace_amdgpu_vm_bo_mapping(mapping); |
| 1801 | } |
| 1802 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1803 | spin_lock(&vm->status_lock); |
monk.liu | 6d1d0ef | 2015-08-14 13:36:41 +0800 | [diff] [blame] | 1804 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1805 | list_del_init(&bo_va->vm_status); |
Christian König | 99e124f | 2016-08-16 14:43:17 +0200 | [diff] [blame] | 1806 | if (clear) |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 1807 | list_add(&bo_va->vm_status, &vm->cleared); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1808 | spin_unlock(&vm->status_lock); |
| 1809 | |
Christian König | 68c6230 | 2017-07-11 17:23:29 +0200 | [diff] [blame] | 1810 | if (vm->use_cpu_for_update) { |
| 1811 | /* Flush HDP */ |
| 1812 | mb(); |
| 1813 | amdgpu_gart_flush_gpu_tlb(adev, 0); |
| 1814 | } |
| 1815 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1816 | return 0; |
| 1817 | } |
| 1818 | |
| 1819 | /** |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1820 | * amdgpu_vm_update_prt_state - update the global PRT state |
| 1821 | */ |
| 1822 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) |
| 1823 | { |
| 1824 | unsigned long flags; |
| 1825 | bool enable; |
| 1826 | |
| 1827 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1828 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1829 | adev->gart.gart_funcs->set_prt(adev, enable); |
| 1830 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
| 1831 | } |
| 1832 | |
| 1833 | /** |
Christian König | 4388fc2 | 2017-03-13 10:13:36 +0100 | [diff] [blame] | 1834 | * amdgpu_vm_prt_get - add a PRT user |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1835 | */ |
| 1836 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) |
| 1837 | { |
Christian König | 4388fc2 | 2017-03-13 10:13:36 +0100 | [diff] [blame] | 1838 | if (!adev->gart.gart_funcs->set_prt) |
| 1839 | return; |
| 1840 | |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1841 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
| 1842 | amdgpu_vm_update_prt_state(adev); |
| 1843 | } |
| 1844 | |
| 1845 | /** |
Christian König | 0b15f2f | 2017-02-14 15:47:03 +0100 | [diff] [blame] | 1846 | * amdgpu_vm_prt_put - drop a PRT user |
| 1847 | */ |
| 1848 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) |
| 1849 | { |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1850 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
Christian König | 0b15f2f | 2017-02-14 15:47:03 +0100 | [diff] [blame] | 1851 | amdgpu_vm_update_prt_state(adev); |
| 1852 | } |
| 1853 | |
| 1854 | /** |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1855 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1856 | */ |
| 1857 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) |
| 1858 | { |
| 1859 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); |
| 1860 | |
Christian König | 0b15f2f | 2017-02-14 15:47:03 +0100 | [diff] [blame] | 1861 | amdgpu_vm_prt_put(cb->adev); |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1862 | kfree(cb); |
| 1863 | } |
| 1864 | |
| 1865 | /** |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1866 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status |
| 1867 | */ |
| 1868 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, |
| 1869 | struct dma_fence *fence) |
| 1870 | { |
Christian König | 4388fc2 | 2017-03-13 10:13:36 +0100 | [diff] [blame] | 1871 | struct amdgpu_prt_cb *cb; |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1872 | |
Christian König | 4388fc2 | 2017-03-13 10:13:36 +0100 | [diff] [blame] | 1873 | if (!adev->gart.gart_funcs->set_prt) |
| 1874 | return; |
| 1875 | |
| 1876 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1877 | if (!cb) { |
| 1878 | /* Last resort when we are OOM */ |
| 1879 | if (fence) |
| 1880 | dma_fence_wait(fence, false); |
| 1881 | |
Dan Carpenter | 486a68f | 2017-04-03 21:41:39 +0300 | [diff] [blame] | 1882 | amdgpu_vm_prt_put(adev); |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1883 | } else { |
| 1884 | cb->adev = adev; |
| 1885 | if (!fence || dma_fence_add_callback(fence, &cb->cb, |
| 1886 | amdgpu_vm_prt_cb)) |
| 1887 | amdgpu_vm_prt_cb(fence, &cb->cb); |
| 1888 | } |
| 1889 | } |
| 1890 | |
| 1891 | /** |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1892 | * amdgpu_vm_free_mapping - free a mapping |
| 1893 | * |
| 1894 | * @adev: amdgpu_device pointer |
| 1895 | * @vm: requested vm |
| 1896 | * @mapping: mapping to be freed |
| 1897 | * @fence: fence of the unmap operation |
| 1898 | * |
| 1899 | * Free a mapping and make sure we decrease the PRT usage count if applicable. |
| 1900 | */ |
| 1901 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, |
| 1902 | struct amdgpu_vm *vm, |
| 1903 | struct amdgpu_bo_va_mapping *mapping, |
| 1904 | struct dma_fence *fence) |
| 1905 | { |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1906 | if (mapping->flags & AMDGPU_PTE_PRT) |
| 1907 | amdgpu_vm_add_prt_cb(adev, fence); |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1908 | kfree(mapping); |
| 1909 | } |
| 1910 | |
| 1911 | /** |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1912 | * amdgpu_vm_prt_fini - finish all prt mappings |
| 1913 | * |
| 1914 | * @adev: amdgpu_device pointer |
| 1915 | * @vm: requested vm |
| 1916 | * |
| 1917 | * Register a cleanup callback to disable PRT support after VM dies. |
| 1918 | */ |
| 1919 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) |
| 1920 | { |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 1921 | struct reservation_object *resv = vm->root.bo->tbo.resv; |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 1922 | struct dma_fence *excl, **shared; |
| 1923 | unsigned i, shared_count; |
| 1924 | int r; |
| 1925 | |
| 1926 | r = reservation_object_get_fences_rcu(resv, &excl, |
| 1927 | &shared_count, &shared); |
| 1928 | if (r) { |
| 1929 | /* Not enough memory to grab the fence list, as last resort |
| 1930 | * block for all the fences to complete. |
| 1931 | */ |
| 1932 | reservation_object_wait_timeout_rcu(resv, true, false, |
| 1933 | MAX_SCHEDULE_TIMEOUT); |
| 1934 | return; |
| 1935 | } |
| 1936 | |
| 1937 | /* Add a callback for each fence in the reservation object */ |
| 1938 | amdgpu_vm_prt_get(adev); |
| 1939 | amdgpu_vm_add_prt_cb(adev, excl); |
| 1940 | |
| 1941 | for (i = 0; i < shared_count; ++i) { |
| 1942 | amdgpu_vm_prt_get(adev); |
| 1943 | amdgpu_vm_add_prt_cb(adev, shared[i]); |
| 1944 | } |
| 1945 | |
| 1946 | kfree(shared); |
| 1947 | } |
| 1948 | |
| 1949 | /** |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1950 | * amdgpu_vm_clear_freed - clear freed BOs in the PT |
| 1951 | * |
| 1952 | * @adev: amdgpu_device pointer |
| 1953 | * @vm: requested vm |
Nicolai Hähnle | f346781 | 2017-03-23 19:36:31 +0100 | [diff] [blame] | 1954 | * @fence: optional resulting fence (unchanged if no work needed to be done |
| 1955 | * or if an error occurred) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1956 | * |
| 1957 | * Make sure all freed BOs are cleared in the PT. |
| 1958 | * Returns 0 for success. |
| 1959 | * |
| 1960 | * PTs have to be reserved and mutex must be locked! |
| 1961 | */ |
| 1962 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, |
Nicolai Hähnle | f346781 | 2017-03-23 19:36:31 +0100 | [diff] [blame] | 1963 | struct amdgpu_vm *vm, |
| 1964 | struct dma_fence **fence) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1965 | { |
| 1966 | struct amdgpu_bo_va_mapping *mapping; |
Nicolai Hähnle | f346781 | 2017-03-23 19:36:31 +0100 | [diff] [blame] | 1967 | struct dma_fence *f = NULL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1968 | int r; |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 1969 | uint64_t init_pte_value = 0; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1970 | |
| 1971 | while (!list_empty(&vm->freed)) { |
| 1972 | mapping = list_first_entry(&vm->freed, |
| 1973 | struct amdgpu_bo_va_mapping, list); |
| 1974 | list_del(&mapping->list); |
Christian König | e17841b | 2016-03-08 17:52:01 +0100 | [diff] [blame] | 1975 | |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 1976 | if (vm->pte_support_ats) |
| 1977 | init_pte_value = AMDGPU_PTE_SYSTEM; |
| 1978 | |
Christian König | fc6aa33 | 2017-04-19 14:41:19 +0200 | [diff] [blame] | 1979 | r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm, |
| 1980 | mapping->start, mapping->last, |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 1981 | init_pte_value, 0, &f); |
Nicolai Hähnle | f346781 | 2017-03-23 19:36:31 +0100 | [diff] [blame] | 1982 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1983 | if (r) { |
Nicolai Hähnle | f346781 | 2017-03-23 19:36:31 +0100 | [diff] [blame] | 1984 | dma_fence_put(f); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1985 | return r; |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 1986 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1987 | } |
Nicolai Hähnle | f346781 | 2017-03-23 19:36:31 +0100 | [diff] [blame] | 1988 | |
| 1989 | if (fence && f) { |
| 1990 | dma_fence_put(*fence); |
| 1991 | *fence = f; |
| 1992 | } else { |
| 1993 | dma_fence_put(f); |
| 1994 | } |
| 1995 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1996 | return 0; |
| 1997 | |
| 1998 | } |
| 1999 | |
| 2000 | /** |
| 2001 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT |
| 2002 | * |
| 2003 | * @adev: amdgpu_device pointer |
| 2004 | * @vm: requested vm |
| 2005 | * |
| 2006 | * Make sure all invalidated BOs are cleared in the PT. |
| 2007 | * Returns 0 for success. |
| 2008 | * |
| 2009 | * PTs have to be reserved and mutex must be locked! |
| 2010 | */ |
| 2011 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, |
monk.liu | cfe2c97 | 2015-05-26 15:01:54 +0800 | [diff] [blame] | 2012 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2013 | { |
monk.liu | cfe2c97 | 2015-05-26 15:01:54 +0800 | [diff] [blame] | 2014 | struct amdgpu_bo_va *bo_va = NULL; |
Christian König | 91e1a52 | 2015-07-06 22:06:40 +0200 | [diff] [blame] | 2015 | int r = 0; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2016 | |
| 2017 | spin_lock(&vm->status_lock); |
| 2018 | while (!list_empty(&vm->invalidated)) { |
| 2019 | bo_va = list_first_entry(&vm->invalidated, |
| 2020 | struct amdgpu_bo_va, vm_status); |
| 2021 | spin_unlock(&vm->status_lock); |
Christian König | 32b41ac | 2016-03-08 18:03:27 +0100 | [diff] [blame] | 2022 | |
Christian König | 99e124f | 2016-08-16 14:43:17 +0200 | [diff] [blame] | 2023 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2024 | if (r) |
| 2025 | return r; |
| 2026 | |
| 2027 | spin_lock(&vm->status_lock); |
| 2028 | } |
| 2029 | spin_unlock(&vm->status_lock); |
| 2030 | |
monk.liu | cfe2c97 | 2015-05-26 15:01:54 +0800 | [diff] [blame] | 2031 | if (bo_va) |
Chunming Zhou | bb1e38a4 | 2015-08-03 18:19:38 +0800 | [diff] [blame] | 2032 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
Christian König | 91e1a52 | 2015-07-06 22:06:40 +0200 | [diff] [blame] | 2033 | |
| 2034 | return r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2035 | } |
| 2036 | |
| 2037 | /** |
| 2038 | * amdgpu_vm_bo_add - add a bo to a specific vm |
| 2039 | * |
| 2040 | * @adev: amdgpu_device pointer |
| 2041 | * @vm: requested vm |
| 2042 | * @bo: amdgpu buffer object |
| 2043 | * |
Christian König | 8843dbb | 2016-01-26 12:17:11 +0100 | [diff] [blame] | 2044 | * Add @bo into the requested vm. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2045 | * Add @bo to the list of bos associated with the vm |
| 2046 | * Returns newly added bo_va or NULL for failure |
| 2047 | * |
| 2048 | * Object has to be reserved! |
| 2049 | */ |
| 2050 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, |
| 2051 | struct amdgpu_vm *vm, |
| 2052 | struct amdgpu_bo *bo) |
| 2053 | { |
| 2054 | struct amdgpu_bo_va *bo_va; |
| 2055 | |
| 2056 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); |
| 2057 | if (bo_va == NULL) { |
| 2058 | return NULL; |
| 2059 | } |
| 2060 | bo_va->vm = vm; |
| 2061 | bo_va->bo = bo; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2062 | bo_va->ref_count = 1; |
| 2063 | INIT_LIST_HEAD(&bo_va->bo_list); |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2064 | INIT_LIST_HEAD(&bo_va->valids); |
| 2065 | INIT_LIST_HEAD(&bo_va->invalids); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2066 | INIT_LIST_HEAD(&bo_va->vm_status); |
Christian König | 32b41ac | 2016-03-08 18:03:27 +0100 | [diff] [blame] | 2067 | |
Christian König | a5f6b5b | 2017-01-30 11:01:38 +0100 | [diff] [blame] | 2068 | if (bo) |
| 2069 | list_add_tail(&bo_va->bo_list, &bo->va); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2070 | |
| 2071 | return bo_va; |
| 2072 | } |
| 2073 | |
| 2074 | /** |
| 2075 | * amdgpu_vm_bo_map - map bo inside a vm |
| 2076 | * |
| 2077 | * @adev: amdgpu_device pointer |
| 2078 | * @bo_va: bo_va to store the address |
| 2079 | * @saddr: where to map the BO |
| 2080 | * @offset: requested offset in the BO |
| 2081 | * @flags: attributes of pages (read/write/valid/etc.) |
| 2082 | * |
| 2083 | * Add a mapping of the BO at the specefied addr into the VM. |
| 2084 | * Returns 0 for success, error for failure. |
| 2085 | * |
Chunming Zhou | 49b02b1 | 2015-11-13 14:18:38 +0800 | [diff] [blame] | 2086 | * Object has to be reserved and unreserved outside! |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2087 | */ |
| 2088 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, |
| 2089 | struct amdgpu_bo_va *bo_va, |
| 2090 | uint64_t saddr, uint64_t offset, |
Christian König | 268c300 | 2017-01-18 14:49:43 +0100 | [diff] [blame] | 2091 | uint64_t size, uint64_t flags) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2092 | { |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2093 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2094 | struct amdgpu_vm *vm = bo_va->vm; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2095 | uint64_t eaddr; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2096 | |
Christian König | 0be52de | 2015-05-18 14:37:27 +0200 | [diff] [blame] | 2097 | /* validate the parameters */ |
| 2098 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || |
Chunming Zhou | 49b02b1 | 2015-11-13 14:18:38 +0800 | [diff] [blame] | 2099 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
Christian König | 0be52de | 2015-05-18 14:37:27 +0200 | [diff] [blame] | 2100 | return -EINVAL; |
Christian König | 0be52de | 2015-05-18 14:37:27 +0200 | [diff] [blame] | 2101 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2102 | /* make sure object fit at this offset */ |
Felix Kuehling | 005ae95 | 2015-11-23 17:43:48 -0500 | [diff] [blame] | 2103 | eaddr = saddr + size - 1; |
Christian König | a5f6b5b | 2017-01-30 11:01:38 +0100 | [diff] [blame] | 2104 | if (saddr >= eaddr || |
| 2105 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2106 | return -EINVAL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2107 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2108 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
| 2109 | eaddr /= AMDGPU_GPU_PAGE_SIZE; |
| 2110 | |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2111 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
| 2112 | if (tmp) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2113 | /* bo and tmp overlap, invalid addr */ |
| 2114 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2115 | "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr, |
| 2116 | tmp->start, tmp->last + 1); |
Christian König | 663e457 | 2017-03-13 10:13:37 +0100 | [diff] [blame] | 2117 | return -EINVAL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2118 | } |
| 2119 | |
| 2120 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); |
Christian König | 663e457 | 2017-03-13 10:13:37 +0100 | [diff] [blame] | 2121 | if (!mapping) |
| 2122 | return -ENOMEM; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2123 | |
| 2124 | INIT_LIST_HEAD(&mapping->list); |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2125 | mapping->start = saddr; |
| 2126 | mapping->last = eaddr; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2127 | mapping->offset = offset; |
| 2128 | mapping->flags = flags; |
| 2129 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2130 | list_add(&mapping->list, &bo_va->invalids); |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2131 | amdgpu_vm_it_insert(mapping, &vm->va); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2132 | |
Christian König | 4388fc2 | 2017-03-13 10:13:36 +0100 | [diff] [blame] | 2133 | if (flags & AMDGPU_PTE_PRT) |
| 2134 | amdgpu_vm_prt_get(adev); |
| 2135 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2136 | return 0; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2137 | } |
| 2138 | |
| 2139 | /** |
Christian König | 80f95c5 | 2017-03-13 10:13:39 +0100 | [diff] [blame] | 2140 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings |
| 2141 | * |
| 2142 | * @adev: amdgpu_device pointer |
| 2143 | * @bo_va: bo_va to store the address |
| 2144 | * @saddr: where to map the BO |
| 2145 | * @offset: requested offset in the BO |
| 2146 | * @flags: attributes of pages (read/write/valid/etc.) |
| 2147 | * |
| 2148 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing |
| 2149 | * mappings as we do so. |
| 2150 | * Returns 0 for success, error for failure. |
| 2151 | * |
| 2152 | * Object has to be reserved and unreserved outside! |
| 2153 | */ |
| 2154 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, |
| 2155 | struct amdgpu_bo_va *bo_va, |
| 2156 | uint64_t saddr, uint64_t offset, |
| 2157 | uint64_t size, uint64_t flags) |
| 2158 | { |
| 2159 | struct amdgpu_bo_va_mapping *mapping; |
| 2160 | struct amdgpu_vm *vm = bo_va->vm; |
| 2161 | uint64_t eaddr; |
| 2162 | int r; |
| 2163 | |
| 2164 | /* validate the parameters */ |
| 2165 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || |
| 2166 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
| 2167 | return -EINVAL; |
| 2168 | |
| 2169 | /* make sure object fit at this offset */ |
| 2170 | eaddr = saddr + size - 1; |
| 2171 | if (saddr >= eaddr || |
| 2172 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) |
| 2173 | return -EINVAL; |
| 2174 | |
| 2175 | /* Allocate all the needed memory */ |
| 2176 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); |
| 2177 | if (!mapping) |
| 2178 | return -ENOMEM; |
| 2179 | |
| 2180 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); |
| 2181 | if (r) { |
| 2182 | kfree(mapping); |
| 2183 | return r; |
| 2184 | } |
| 2185 | |
| 2186 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
| 2187 | eaddr /= AMDGPU_GPU_PAGE_SIZE; |
| 2188 | |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2189 | mapping->start = saddr; |
| 2190 | mapping->last = eaddr; |
Christian König | 80f95c5 | 2017-03-13 10:13:39 +0100 | [diff] [blame] | 2191 | mapping->offset = offset; |
| 2192 | mapping->flags = flags; |
| 2193 | |
| 2194 | list_add(&mapping->list, &bo_va->invalids); |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2195 | amdgpu_vm_it_insert(mapping, &vm->va); |
Christian König | 80f95c5 | 2017-03-13 10:13:39 +0100 | [diff] [blame] | 2196 | |
| 2197 | if (flags & AMDGPU_PTE_PRT) |
| 2198 | amdgpu_vm_prt_get(adev); |
| 2199 | |
| 2200 | return 0; |
| 2201 | } |
| 2202 | |
| 2203 | /** |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2204 | * amdgpu_vm_bo_unmap - remove bo mapping from vm |
| 2205 | * |
| 2206 | * @adev: amdgpu_device pointer |
| 2207 | * @bo_va: bo_va to remove the address from |
| 2208 | * @saddr: where to the BO is mapped |
| 2209 | * |
| 2210 | * Remove a mapping of the BO at the specefied addr from the VM. |
| 2211 | * Returns 0 for success, error for failure. |
| 2212 | * |
Chunming Zhou | 49b02b1 | 2015-11-13 14:18:38 +0800 | [diff] [blame] | 2213 | * Object has to be reserved and unreserved outside! |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2214 | */ |
| 2215 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, |
| 2216 | struct amdgpu_bo_va *bo_va, |
| 2217 | uint64_t saddr) |
| 2218 | { |
| 2219 | struct amdgpu_bo_va_mapping *mapping; |
| 2220 | struct amdgpu_vm *vm = bo_va->vm; |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2221 | bool valid = true; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2222 | |
Christian König | 6c7fc50 | 2015-06-05 20:56:17 +0200 | [diff] [blame] | 2223 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
Christian König | 32b41ac | 2016-03-08 18:03:27 +0100 | [diff] [blame] | 2224 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2225 | list_for_each_entry(mapping, &bo_va->valids, list) { |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2226 | if (mapping->start == saddr) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2227 | break; |
| 2228 | } |
| 2229 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2230 | if (&mapping->list == &bo_va->valids) { |
| 2231 | valid = false; |
| 2232 | |
| 2233 | list_for_each_entry(mapping, &bo_va->invalids, list) { |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2234 | if (mapping->start == saddr) |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2235 | break; |
| 2236 | } |
| 2237 | |
Christian König | 32b41ac | 2016-03-08 18:03:27 +0100 | [diff] [blame] | 2238 | if (&mapping->list == &bo_va->invalids) |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2239 | return -ENOENT; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2240 | } |
Christian König | 32b41ac | 2016-03-08 18:03:27 +0100 | [diff] [blame] | 2241 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2242 | list_del(&mapping->list); |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2243 | amdgpu_vm_it_remove(mapping, &vm->va); |
Christian König | 93e3e43 | 2015-06-09 16:58:33 +0200 | [diff] [blame] | 2244 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2245 | |
Christian König | e17841b | 2016-03-08 17:52:01 +0100 | [diff] [blame] | 2246 | if (valid) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2247 | list_add(&mapping->list, &vm->freed); |
Christian König | e17841b | 2016-03-08 17:52:01 +0100 | [diff] [blame] | 2248 | else |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 2249 | amdgpu_vm_free_mapping(adev, vm, mapping, |
| 2250 | bo_va->last_pt_update); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2251 | |
| 2252 | return 0; |
| 2253 | } |
| 2254 | |
| 2255 | /** |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2256 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range |
| 2257 | * |
| 2258 | * @adev: amdgpu_device pointer |
| 2259 | * @vm: VM structure to use |
| 2260 | * @saddr: start of the range |
| 2261 | * @size: size of the range |
| 2262 | * |
| 2263 | * Remove all mappings in a range, split them as appropriate. |
| 2264 | * Returns 0 for success, error for failure. |
| 2265 | */ |
| 2266 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, |
| 2267 | struct amdgpu_vm *vm, |
| 2268 | uint64_t saddr, uint64_t size) |
| 2269 | { |
| 2270 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2271 | LIST_HEAD(removed); |
| 2272 | uint64_t eaddr; |
| 2273 | |
| 2274 | eaddr = saddr + size - 1; |
| 2275 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
| 2276 | eaddr /= AMDGPU_GPU_PAGE_SIZE; |
| 2277 | |
| 2278 | /* Allocate all the needed memory */ |
| 2279 | before = kzalloc(sizeof(*before), GFP_KERNEL); |
| 2280 | if (!before) |
| 2281 | return -ENOMEM; |
Junwei Zhang | 27f6d61 | 2017-03-16 16:09:24 +0800 | [diff] [blame] | 2282 | INIT_LIST_HEAD(&before->list); |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2283 | |
| 2284 | after = kzalloc(sizeof(*after), GFP_KERNEL); |
| 2285 | if (!after) { |
| 2286 | kfree(before); |
| 2287 | return -ENOMEM; |
| 2288 | } |
Junwei Zhang | 27f6d61 | 2017-03-16 16:09:24 +0800 | [diff] [blame] | 2289 | INIT_LIST_HEAD(&after->list); |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2290 | |
| 2291 | /* Now gather all removed mappings */ |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2292 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
| 2293 | while (tmp) { |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2294 | /* Remember mapping split at the start */ |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2295 | if (tmp->start < saddr) { |
| 2296 | before->start = tmp->start; |
| 2297 | before->last = saddr - 1; |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2298 | before->offset = tmp->offset; |
| 2299 | before->flags = tmp->flags; |
| 2300 | list_add(&before->list, &tmp->list); |
| 2301 | } |
| 2302 | |
| 2303 | /* Remember mapping split at the end */ |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2304 | if (tmp->last > eaddr) { |
| 2305 | after->start = eaddr + 1; |
| 2306 | after->last = tmp->last; |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2307 | after->offset = tmp->offset; |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2308 | after->offset += after->start - tmp->start; |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2309 | after->flags = tmp->flags; |
| 2310 | list_add(&after->list, &tmp->list); |
| 2311 | } |
| 2312 | |
| 2313 | list_del(&tmp->list); |
| 2314 | list_add(&tmp->list, &removed); |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2315 | |
| 2316 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2317 | } |
| 2318 | |
| 2319 | /* And free them up */ |
| 2320 | list_for_each_entry_safe(tmp, next, &removed, list) { |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2321 | amdgpu_vm_it_remove(tmp, &vm->va); |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2322 | list_del(&tmp->list); |
| 2323 | |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2324 | if (tmp->start < saddr) |
| 2325 | tmp->start = saddr; |
| 2326 | if (tmp->last > eaddr) |
| 2327 | tmp->last = eaddr; |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2328 | |
| 2329 | list_add(&tmp->list, &vm->freed); |
| 2330 | trace_amdgpu_vm_bo_unmap(NULL, tmp); |
| 2331 | } |
| 2332 | |
Junwei Zhang | 27f6d61 | 2017-03-16 16:09:24 +0800 | [diff] [blame] | 2333 | /* Insert partial mapping before the range */ |
| 2334 | if (!list_empty(&before->list)) { |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2335 | amdgpu_vm_it_insert(before, &vm->va); |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2336 | if (before->flags & AMDGPU_PTE_PRT) |
| 2337 | amdgpu_vm_prt_get(adev); |
| 2338 | } else { |
| 2339 | kfree(before); |
| 2340 | } |
| 2341 | |
| 2342 | /* Insert partial mapping after the range */ |
Junwei Zhang | 27f6d61 | 2017-03-16 16:09:24 +0800 | [diff] [blame] | 2343 | if (!list_empty(&after->list)) { |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2344 | amdgpu_vm_it_insert(after, &vm->va); |
Christian König | dc54d3d | 2017-03-13 10:13:38 +0100 | [diff] [blame] | 2345 | if (after->flags & AMDGPU_PTE_PRT) |
| 2346 | amdgpu_vm_prt_get(adev); |
| 2347 | } else { |
| 2348 | kfree(after); |
| 2349 | } |
| 2350 | |
| 2351 | return 0; |
| 2352 | } |
| 2353 | |
| 2354 | /** |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2355 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm |
| 2356 | * |
| 2357 | * @adev: amdgpu_device pointer |
| 2358 | * @bo_va: requested bo_va |
| 2359 | * |
Christian König | 8843dbb | 2016-01-26 12:17:11 +0100 | [diff] [blame] | 2360 | * Remove @bo_va->bo from the requested vm. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2361 | * |
| 2362 | * Object have to be reserved! |
| 2363 | */ |
| 2364 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, |
| 2365 | struct amdgpu_bo_va *bo_va) |
| 2366 | { |
| 2367 | struct amdgpu_bo_va_mapping *mapping, *next; |
| 2368 | struct amdgpu_vm *vm = bo_va->vm; |
| 2369 | |
| 2370 | list_del(&bo_va->bo_list); |
| 2371 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2372 | spin_lock(&vm->status_lock); |
| 2373 | list_del(&bo_va->vm_status); |
| 2374 | spin_unlock(&vm->status_lock); |
| 2375 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2376 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2377 | list_del(&mapping->list); |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2378 | amdgpu_vm_it_remove(mapping, &vm->va); |
Christian König | 93e3e43 | 2015-06-09 16:58:33 +0200 | [diff] [blame] | 2379 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2380 | list_add(&mapping->list, &vm->freed); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2381 | } |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2382 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { |
| 2383 | list_del(&mapping->list); |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2384 | amdgpu_vm_it_remove(mapping, &vm->va); |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 2385 | amdgpu_vm_free_mapping(adev, vm, mapping, |
| 2386 | bo_va->last_pt_update); |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2387 | } |
Christian König | 32b41ac | 2016-03-08 18:03:27 +0100 | [diff] [blame] | 2388 | |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 2389 | dma_fence_put(bo_va->last_pt_update); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2390 | kfree(bo_va); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2391 | } |
| 2392 | |
| 2393 | /** |
| 2394 | * amdgpu_vm_bo_invalidate - mark the bo as invalid |
| 2395 | * |
| 2396 | * @adev: amdgpu_device pointer |
| 2397 | * @vm: requested vm |
| 2398 | * @bo: amdgpu buffer object |
| 2399 | * |
Christian König | 8843dbb | 2016-01-26 12:17:11 +0100 | [diff] [blame] | 2400 | * Mark @bo as invalid. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2401 | */ |
| 2402 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, |
| 2403 | struct amdgpu_bo *bo) |
| 2404 | { |
| 2405 | struct amdgpu_bo_va *bo_va; |
| 2406 | |
| 2407 | list_for_each_entry(bo_va, &bo->va, bo_list) { |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2408 | spin_lock(&bo_va->vm->status_lock); |
| 2409 | if (list_empty(&bo_va->vm_status)) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2410 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2411 | spin_unlock(&bo_va->vm->status_lock); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2412 | } |
| 2413 | } |
| 2414 | |
Junwei Zhang | bab4fee | 2017-04-05 13:54:56 +0800 | [diff] [blame] | 2415 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
| 2416 | { |
| 2417 | /* Total bits covered by PD + PTs */ |
| 2418 | unsigned bits = ilog2(vm_size) + 18; |
| 2419 | |
| 2420 | /* Make sure the PD is 4K in size up to 8GB address space. |
| 2421 | Above that split equal between PD and PTs */ |
| 2422 | if (vm_size <= 8) |
| 2423 | return (bits - 9); |
| 2424 | else |
| 2425 | return ((bits + 3) / 2); |
| 2426 | } |
| 2427 | |
| 2428 | /** |
| 2429 | * amdgpu_vm_adjust_size - adjust vm size and block size |
| 2430 | * |
| 2431 | * @adev: amdgpu_device pointer |
| 2432 | * @vm_size: the default vm size if it's set auto |
| 2433 | */ |
| 2434 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) |
| 2435 | { |
| 2436 | /* adjust vm size firstly */ |
| 2437 | if (amdgpu_vm_size == -1) |
| 2438 | adev->vm_manager.vm_size = vm_size; |
| 2439 | else |
| 2440 | adev->vm_manager.vm_size = amdgpu_vm_size; |
| 2441 | |
| 2442 | /* block size depends on vm size */ |
| 2443 | if (amdgpu_vm_block_size == -1) |
| 2444 | adev->vm_manager.block_size = |
| 2445 | amdgpu_vm_get_block_size(adev->vm_manager.vm_size); |
| 2446 | else |
| 2447 | adev->vm_manager.block_size = amdgpu_vm_block_size; |
| 2448 | |
| 2449 | DRM_INFO("vm size is %llu GB, block size is %u-bit\n", |
| 2450 | adev->vm_manager.vm_size, adev->vm_manager.block_size); |
| 2451 | } |
| 2452 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2453 | /** |
| 2454 | * amdgpu_vm_init - initialize a vm instance |
| 2455 | * |
| 2456 | * @adev: amdgpu_device pointer |
| 2457 | * @vm: requested vm |
Harish Kasiviswanathan | 9a4b7d4 | 2017-06-09 11:26:57 -0400 | [diff] [blame] | 2458 | * @vm_context: Indicates if it GFX or Compute context |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2459 | * |
Christian König | 8843dbb | 2016-01-26 12:17:11 +0100 | [diff] [blame] | 2460 | * Init @vm fields. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2461 | */ |
Harish Kasiviswanathan | 9a4b7d4 | 2017-06-09 11:26:57 -0400 | [diff] [blame] | 2462 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
| 2463 | int vm_context) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2464 | { |
| 2465 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 2466 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
Christian König | 2d55e45 | 2016-02-08 17:37:38 +0100 | [diff] [blame] | 2467 | unsigned ring_instance; |
| 2468 | struct amdgpu_ring *ring; |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2469 | struct amd_sched_rq *rq; |
Chunming Zhou | 36bbf3b | 2017-04-20 16:17:34 +0800 | [diff] [blame] | 2470 | int r, i; |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 2471 | u64 flags; |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 2472 | uint64_t init_pde_value = 0; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2473 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2474 | vm->va = RB_ROOT; |
Chunming Zhou | 031e298 | 2016-04-25 10:19:13 +0800 | [diff] [blame] | 2475 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
Chunming Zhou | 36bbf3b | 2017-04-20 16:17:34 +0800 | [diff] [blame] | 2476 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
| 2477 | vm->reserved_vmid[i] = NULL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2478 | spin_lock_init(&vm->status_lock); |
| 2479 | INIT_LIST_HEAD(&vm->invalidated); |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 2480 | INIT_LIST_HEAD(&vm->cleared); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2481 | INIT_LIST_HEAD(&vm->freed); |
Christian König | 2025021 | 2016-03-08 17:58:35 +0100 | [diff] [blame] | 2482 | |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2483 | /* create scheduler entity for page table updates */ |
Christian König | 2d55e45 | 2016-02-08 17:37:38 +0100 | [diff] [blame] | 2484 | |
| 2485 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); |
| 2486 | ring_instance %= adev->vm_manager.vm_pte_num_rings; |
| 2487 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2488 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
| 2489 | r = amd_sched_entity_init(&ring->sched, &vm->entity, |
| 2490 | rq, amdgpu_sched_jobs); |
| 2491 | if (r) |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 2492 | return r; |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2493 | |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 2494 | vm->pte_support_ats = false; |
| 2495 | |
| 2496 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { |
Harish Kasiviswanathan | 9a4b7d4 | 2017-06-09 11:26:57 -0400 | [diff] [blame] | 2497 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
| 2498 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 2499 | |
| 2500 | if (adev->asic_type == CHIP_RAVEN) { |
| 2501 | vm->pte_support_ats = true; |
| 2502 | init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE; |
| 2503 | } |
| 2504 | } else |
Harish Kasiviswanathan | 9a4b7d4 | 2017-06-09 11:26:57 -0400 | [diff] [blame] | 2505 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
| 2506 | AMDGPU_VM_USE_CPU_FOR_GFX); |
| 2507 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
| 2508 | vm->use_cpu_for_update ? "CPU" : "SDMA"); |
| 2509 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), |
| 2510 | "CPU update of VM recommended only for large BAR system\n"); |
Christian König | a24960f | 2016-10-12 13:20:52 +0200 | [diff] [blame] | 2511 | vm->last_dir_update = NULL; |
Bas Nieuwenhuizen | 05906de | 2015-08-14 20:08:40 +0200 | [diff] [blame] | 2512 | |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 2513 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
| 2514 | AMDGPU_GEM_CREATE_VRAM_CLEARED; |
| 2515 | if (vm->use_cpu_for_update) |
| 2516 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; |
| 2517 | else |
| 2518 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
| 2519 | AMDGPU_GEM_CREATE_SHADOW); |
| 2520 | |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 2521 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
Alex Deucher | 857d913 | 2015-08-27 00:14:16 -0400 | [diff] [blame] | 2522 | AMDGPU_GEM_DOMAIN_VRAM, |
Harish Kasiviswanathan | 3c82417 | 2017-05-11 15:50:08 -0400 | [diff] [blame] | 2523 | flags, |
Yong Zhao | 51ac7ee | 2017-07-27 12:48:22 -0400 | [diff] [blame] | 2524 | NULL, NULL, init_pde_value, &vm->root.bo); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2525 | if (r) |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2526 | goto error_free_sched_entity; |
| 2527 | |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 2528 | r = amdgpu_bo_reserve(vm->root.bo, false); |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2529 | if (r) |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 2530 | goto error_free_root; |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2531 | |
Christian König | 5a712a8 | 2016-06-21 16:28:15 +0200 | [diff] [blame] | 2532 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
Christian König | 0a096fb | 2017-07-12 10:01:48 +0200 | [diff] [blame] | 2533 | |
| 2534 | if (vm->use_cpu_for_update) { |
| 2535 | r = amdgpu_bo_kmap(vm->root.bo, NULL); |
| 2536 | if (r) |
| 2537 | goto error_free_root; |
| 2538 | } |
| 2539 | |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 2540 | amdgpu_bo_unreserve(vm->root.bo); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2541 | |
| 2542 | return 0; |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2543 | |
Christian König | 67003a1 | 2016-10-12 14:46:26 +0200 | [diff] [blame] | 2544 | error_free_root: |
| 2545 | amdgpu_bo_unref(&vm->root.bo->shadow); |
| 2546 | amdgpu_bo_unref(&vm->root.bo); |
| 2547 | vm->root.bo = NULL; |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2548 | |
| 2549 | error_free_sched_entity: |
| 2550 | amd_sched_entity_fini(&ring->sched, &vm->entity); |
| 2551 | |
| 2552 | return r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2553 | } |
| 2554 | |
| 2555 | /** |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 2556 | * amdgpu_vm_free_levels - free PD/PT levels |
| 2557 | * |
| 2558 | * @level: PD/PT starting level to free |
| 2559 | * |
| 2560 | * Free the page directory or page table level and all sub levels. |
| 2561 | */ |
| 2562 | static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) |
| 2563 | { |
| 2564 | unsigned i; |
| 2565 | |
| 2566 | if (level->bo) { |
| 2567 | amdgpu_bo_unref(&level->bo->shadow); |
| 2568 | amdgpu_bo_unref(&level->bo); |
| 2569 | } |
| 2570 | |
| 2571 | if (level->entries) |
| 2572 | for (i = 0; i <= level->last_entry_used; i++) |
| 2573 | amdgpu_vm_free_levels(&level->entries[i]); |
| 2574 | |
Michal Hocko | 2098105 | 2017-05-17 14:23:12 +0200 | [diff] [blame] | 2575 | kvfree(level->entries); |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 2576 | } |
| 2577 | |
| 2578 | /** |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2579 | * amdgpu_vm_fini - tear down a vm instance |
| 2580 | * |
| 2581 | * @adev: amdgpu_device pointer |
| 2582 | * @vm: requested vm |
| 2583 | * |
Christian König | 8843dbb | 2016-01-26 12:17:11 +0100 | [diff] [blame] | 2584 | * Tear down @vm. |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2585 | * Unbind the VM and remove all bos from the vm bo list |
| 2586 | */ |
| 2587 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) |
| 2588 | { |
| 2589 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
Christian König | 4388fc2 | 2017-03-13 10:13:36 +0100 | [diff] [blame] | 2590 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
Chunming Zhou | 36bbf3b | 2017-04-20 16:17:34 +0800 | [diff] [blame] | 2591 | int i; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2592 | |
Christian König | 2d55e45 | 2016-02-08 17:37:38 +0100 | [diff] [blame] | 2593 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 2594 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2595 | if (!RB_EMPTY_ROOT(&vm->va)) { |
| 2596 | dev_err(adev->dev, "still active bo inside vm\n"); |
| 2597 | } |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2598 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2599 | list_del(&mapping->list); |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 2600 | amdgpu_vm_it_remove(mapping, &vm->va); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2601 | kfree(mapping); |
| 2602 | } |
| 2603 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { |
Christian König | 4388fc2 | 2017-03-13 10:13:36 +0100 | [diff] [blame] | 2604 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 2605 | amdgpu_vm_prt_fini(adev, vm); |
Christian König | 4388fc2 | 2017-03-13 10:13:36 +0100 | [diff] [blame] | 2606 | prt_fini_needed = false; |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 2607 | } |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 2608 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2609 | list_del(&mapping->list); |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 2610 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2611 | } |
| 2612 | |
Christian König | f566ceb | 2016-10-27 20:04:38 +0200 | [diff] [blame] | 2613 | amdgpu_vm_free_levels(&vm->root); |
Christian König | a24960f | 2016-10-12 13:20:52 +0200 | [diff] [blame] | 2614 | dma_fence_put(vm->last_dir_update); |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 2615 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
| 2616 | amdgpu_vm_free_reserved_vmid(adev, vm, i); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 2617 | } |
Christian König | ea89f8c | 2015-11-15 20:52:06 +0100 | [diff] [blame] | 2618 | |
| 2619 | /** |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 2620 | * amdgpu_vm_manager_init - init the VM manager |
| 2621 | * |
| 2622 | * @adev: amdgpu_device pointer |
| 2623 | * |
| 2624 | * Initialize the VM manager structures |
| 2625 | */ |
| 2626 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) |
| 2627 | { |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 2628 | unsigned i, j; |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 2629 | |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 2630 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
| 2631 | struct amdgpu_vm_id_manager *id_mgr = |
| 2632 | &adev->vm_manager.id_mgr[i]; |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 2633 | |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 2634 | mutex_init(&id_mgr->lock); |
| 2635 | INIT_LIST_HEAD(&id_mgr->ids_lru); |
Chunming Zhou | c350577 | 2017-04-21 15:51:04 +0800 | [diff] [blame] | 2636 | atomic_set(&id_mgr->reserved_vmid_num, 0); |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 2637 | |
| 2638 | /* skip over VMID 0, since it is the system VM */ |
| 2639 | for (j = 1; j < id_mgr->num_ids; ++j) { |
| 2640 | amdgpu_vm_reset_id(adev, i, j); |
| 2641 | amdgpu_sync_create(&id_mgr->ids[i].active); |
| 2642 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); |
| 2643 | } |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 2644 | } |
Christian König | 2d55e45 | 2016-02-08 17:37:38 +0100 | [diff] [blame] | 2645 | |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 2646 | adev->vm_manager.fence_context = |
| 2647 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
Christian König | 1fbb2e9 | 2016-06-01 10:47:36 +0200 | [diff] [blame] | 2648 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
| 2649 | adev->vm_manager.seqno[i] = 0; |
| 2650 | |
Christian König | 2d55e45 | 2016-02-08 17:37:38 +0100 | [diff] [blame] | 2651 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
Christian König | b1c8a81 | 2016-05-04 10:34:03 +0200 | [diff] [blame] | 2652 | atomic64_set(&adev->vm_manager.client_counter, 0); |
Christian König | 284710f | 2017-01-30 11:09:31 +0100 | [diff] [blame] | 2653 | spin_lock_init(&adev->vm_manager.prt_lock); |
Christian König | 451bc8e | 2017-02-14 16:02:52 +0100 | [diff] [blame] | 2654 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
Harish Kasiviswanathan | 9a4b7d4 | 2017-06-09 11:26:57 -0400 | [diff] [blame] | 2655 | |
| 2656 | /* If not overridden by the user, by default, only in large BAR systems |
| 2657 | * Compute VM tables will be updated by CPU |
| 2658 | */ |
| 2659 | #ifdef CONFIG_X86_64 |
| 2660 | if (amdgpu_vm_update_mode == -1) { |
| 2661 | if (amdgpu_vm_is_large_bar(adev)) |
| 2662 | adev->vm_manager.vm_update_mode = |
| 2663 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; |
| 2664 | else |
| 2665 | adev->vm_manager.vm_update_mode = 0; |
| 2666 | } else |
| 2667 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; |
| 2668 | #else |
| 2669 | adev->vm_manager.vm_update_mode = 0; |
| 2670 | #endif |
| 2671 | |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 2672 | } |
| 2673 | |
| 2674 | /** |
Christian König | ea89f8c | 2015-11-15 20:52:06 +0100 | [diff] [blame] | 2675 | * amdgpu_vm_manager_fini - cleanup VM manager |
| 2676 | * |
| 2677 | * @adev: amdgpu_device pointer |
| 2678 | * |
| 2679 | * Cleanup the VM manager and free resources. |
| 2680 | */ |
| 2681 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) |
| 2682 | { |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 2683 | unsigned i, j; |
Christian König | ea89f8c | 2015-11-15 20:52:06 +0100 | [diff] [blame] | 2684 | |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 2685 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
| 2686 | struct amdgpu_vm_id_manager *id_mgr = |
| 2687 | &adev->vm_manager.id_mgr[i]; |
Christian König | bcb1ba3 | 2016-03-08 15:40:11 +0100 | [diff] [blame] | 2688 | |
Christian König | 7645670 | 2017-04-06 17:52:39 +0200 | [diff] [blame] | 2689 | mutex_destroy(&id_mgr->lock); |
| 2690 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { |
| 2691 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; |
| 2692 | |
| 2693 | amdgpu_sync_free(&id->active); |
| 2694 | dma_fence_put(id->flushed_updates); |
| 2695 | dma_fence_put(id->last_flush); |
| 2696 | } |
Christian König | bcb1ba3 | 2016-03-08 15:40:11 +0100 | [diff] [blame] | 2697 | } |
Christian König | ea89f8c | 2015-11-15 20:52:06 +0100 | [diff] [blame] | 2698 | } |
Chunming Zhou | cfbcacf | 2017-04-24 11:09:04 +0800 | [diff] [blame] | 2699 | |
| 2700 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
| 2701 | { |
| 2702 | union drm_amdgpu_vm *args = data; |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 2703 | struct amdgpu_device *adev = dev->dev_private; |
| 2704 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
| 2705 | int r; |
Chunming Zhou | cfbcacf | 2017-04-24 11:09:04 +0800 | [diff] [blame] | 2706 | |
| 2707 | switch (args->in.op) { |
| 2708 | case AMDGPU_VM_OP_RESERVE_VMID: |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 2709 | /* current, we only have requirement to reserve vmid from gfxhub */ |
| 2710 | r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, |
| 2711 | AMDGPU_GFXHUB); |
| 2712 | if (r) |
| 2713 | return r; |
| 2714 | break; |
Chunming Zhou | cfbcacf | 2017-04-24 11:09:04 +0800 | [diff] [blame] | 2715 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
Chunming Zhou | 1e9ef26 | 2017-04-20 16:18:48 +0800 | [diff] [blame] | 2716 | amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); |
Chunming Zhou | cfbcacf | 2017-04-24 11:09:04 +0800 | [diff] [blame] | 2717 | break; |
| 2718 | default: |
| 2719 | return -EINVAL; |
| 2720 | } |
| 2721 | |
| 2722 | return 0; |
| 2723 | } |