blob: ff8ab2074a594981523a907978e3c369a4e0eb5d [file] [log] [blame]
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
Chris Wilsonf54d1862016-10-25 13:00:45 +010028#include <linux/dma-fence-array.h>
Christian Königa9f87f62017-03-30 14:03:59 +020029#include <linux/interval_tree_generic.h>
Alex Deucherd38ceaf2015-04-20 16:55:21 -040030#include <drm/drmP.h>
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33#include "amdgpu_trace.h"
34
35/*
36 * GPUVM
37 * GPUVM is similar to the legacy gart on older asics, however
38 * rather than there being a single global gart table
39 * for the entire GPU, there are multiple VM page tables active
40 * at any given time. The VM page tables can contain a mix
41 * vram pages and system memory pages and system memory pages
42 * can be mapped as snooped (cached system pages) or unsnooped
43 * (uncached system pages).
44 * Each VM has an ID associated with it and there is a page table
45 * associated with each VMID. When execting a command buffer,
46 * the kernel tells the the ring what VMID to use for that command
47 * buffer. VMIDs are allocated dynamically as commands are submitted.
48 * The userspace drivers maintain their own address space and the kernel
49 * sets up their pages tables accordingly when they submit their
50 * command buffers and a VMID is assigned.
51 * Cayman/Trinity support up to 8 active VMs at any given time;
52 * SI supports 16.
53 */
54
Christian Königa9f87f62017-03-30 14:03:59 +020055#define START(node) ((node)->start)
56#define LAST(node) ((node)->last)
57
58INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
59 START, LAST, static, amdgpu_vm_it)
60
61#undef START
62#undef LAST
63
Harish Kasiviswanathanf4833c42016-04-21 10:40:18 -040064/* Local structure. Encapsulate some VM table update parameters to reduce
65 * the number of function parameters
66 */
Christian König29efc4f2016-08-04 14:52:50 +020067struct amdgpu_pte_update_params {
Christian König27c5f362016-08-04 15:02:49 +020068 /* amdgpu device we do this update for */
69 struct amdgpu_device *adev;
Christian König49ac8a22016-10-13 15:09:08 +020070 /* optional amdgpu_vm we do this update for */
71 struct amdgpu_vm *vm;
Harish Kasiviswanathanf4833c42016-04-21 10:40:18 -040072 /* address where to copy page table entries from */
73 uint64_t src;
Harish Kasiviswanathanf4833c42016-04-21 10:40:18 -040074 /* indirect buffer to fill with commands */
75 struct amdgpu_ib *ib;
Christian Königafef8b82016-08-12 13:29:18 +020076 /* Function which actually does the update */
77 void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
78 uint64_t addr, unsigned count, uint32_t incr,
Chunming Zhou6b777602016-09-21 16:19:19 +080079 uint64_t flags);
Harish Kasiviswanathanb4d42512017-05-11 19:47:22 -040080 /* The next two are used during VM update by CPU
81 * DMA addresses to use for mapping
82 * Kernel pointer of PD/PT BO that needs to be updated
83 */
84 dma_addr_t *pages_addr;
85 void *kptr;
Harish Kasiviswanathanf4833c42016-04-21 10:40:18 -040086};
87
Christian König284710f2017-01-30 11:09:31 +010088/* Helper to disable partial resident texture feature from a fence callback */
89struct amdgpu_prt_cb {
90 struct amdgpu_device *adev;
91 struct dma_fence_cb cb;
92};
93
Alex Deucherd38ceaf2015-04-20 16:55:21 -040094/**
Christian König72a7ec52016-10-19 11:03:57 +020095 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
Alex Deucherd38ceaf2015-04-20 16:55:21 -040096 *
97 * @adev: amdgpu_device pointer
98 *
Christian König72a7ec52016-10-19 11:03:57 +020099 * Calculate the number of entries in a page directory or page table.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400100 */
Christian König72a7ec52016-10-19 11:03:57 +0200101static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
102 unsigned level)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400103{
Christian König72a7ec52016-10-19 11:03:57 +0200104 if (level == 0)
105 /* For the root directory */
106 return adev->vm_manager.max_pfn >>
Zhang, Jerry36b32a62017-03-29 16:08:32 +0800107 (adev->vm_manager.block_size *
108 adev->vm_manager.num_level);
Christian König72a7ec52016-10-19 11:03:57 +0200109 else if (level == adev->vm_manager.num_level)
110 /* For the page tables on the leaves */
Zhang, Jerry36b32a62017-03-29 16:08:32 +0800111 return AMDGPU_VM_PTE_COUNT(adev);
Christian König72a7ec52016-10-19 11:03:57 +0200112 else
113 /* Everything in between */
Zhang, Jerry36b32a62017-03-29 16:08:32 +0800114 return 1 << adev->vm_manager.block_size;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400115}
116
117/**
Christian König72a7ec52016-10-19 11:03:57 +0200118 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400119 *
120 * @adev: amdgpu_device pointer
121 *
Christian König72a7ec52016-10-19 11:03:57 +0200122 * Calculate the size of the BO for a page directory or page table in bytes.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400123 */
Christian König72a7ec52016-10-19 11:03:57 +0200124static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400125{
Christian König72a7ec52016-10-19 11:03:57 +0200126 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400127}
128
129/**
Christian König56467eb2015-12-11 15:16:32 +0100130 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400131 *
132 * @vm: vm providing the BOs
Christian König3c0eea62015-12-11 14:39:05 +0100133 * @validated: head of validation list
Christian König56467eb2015-12-11 15:16:32 +0100134 * @entry: entry to add
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400135 *
136 * Add the page directory to the list of BOs to
Christian König56467eb2015-12-11 15:16:32 +0100137 * validate for command submission.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400138 */
Christian König56467eb2015-12-11 15:16:32 +0100139void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
140 struct list_head *validated,
141 struct amdgpu_bo_list_entry *entry)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400142{
Christian König67003a12016-10-12 14:46:26 +0200143 entry->robj = vm->root.bo;
Christian König56467eb2015-12-11 15:16:32 +0100144 entry->priority = 0;
Christian König67003a12016-10-12 14:46:26 +0200145 entry->tv.bo = &entry->robj->tbo;
Christian König56467eb2015-12-11 15:16:32 +0100146 entry->tv.shared = true;
Christian König2f568db2016-02-23 12:36:59 +0100147 entry->user_pages = NULL;
Christian König56467eb2015-12-11 15:16:32 +0100148 list_add(&entry->tv.head, validated);
149}
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400150
Christian König56467eb2015-12-11 15:16:32 +0100151/**
Christian König670fecc2016-10-12 15:36:57 +0200152 * amdgpu_vm_validate_layer - validate a single page table level
153 *
154 * @parent: parent page table level
155 * @validate: callback to do the validation
156 * @param: parameter for the validation callback
157 *
158 * Validate the page table BOs on command submission if neccessary.
159 */
160static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
161 int (*validate)(void *, struct amdgpu_bo *),
Christian Königb6369222017-08-03 11:44:01 -0400162 void *param, bool use_cpu_for_update,
163 struct ttm_bo_global *glob)
Christian König670fecc2016-10-12 15:36:57 +0200164{
165 unsigned i;
166 int r;
167
Christian König0a096fb2017-07-12 10:01:48 +0200168 if (use_cpu_for_update) {
169 r = amdgpu_bo_kmap(parent->bo, NULL);
170 if (r)
171 return r;
172 }
173
Christian König670fecc2016-10-12 15:36:57 +0200174 if (!parent->entries)
175 return 0;
176
177 for (i = 0; i <= parent->last_entry_used; ++i) {
178 struct amdgpu_vm_pt *entry = &parent->entries[i];
179
180 if (!entry->bo)
181 continue;
182
183 r = validate(param, entry->bo);
184 if (r)
185 return r;
186
Christian Königb6369222017-08-03 11:44:01 -0400187 spin_lock(&glob->lru_lock);
188 ttm_bo_move_to_lru_tail(&entry->bo->tbo);
189 if (entry->bo->shadow)
190 ttm_bo_move_to_lru_tail(&entry->bo->shadow->tbo);
191 spin_unlock(&glob->lru_lock);
192
Christian König670fecc2016-10-12 15:36:57 +0200193 /*
194 * Recurse into the sub directory. This is harmless because we
195 * have only a maximum of 5 layers.
196 */
Christian König0a096fb2017-07-12 10:01:48 +0200197 r = amdgpu_vm_validate_level(entry, validate, param,
Christian Königb6369222017-08-03 11:44:01 -0400198 use_cpu_for_update, glob);
Christian König670fecc2016-10-12 15:36:57 +0200199 if (r)
200 return r;
201 }
202
203 return r;
204}
205
206/**
Christian Königf7da30d2016-09-28 12:03:04 +0200207 * amdgpu_vm_validate_pt_bos - validate the page table BOs
Christian König56467eb2015-12-11 15:16:32 +0100208 *
Christian König5a712a82016-06-21 16:28:15 +0200209 * @adev: amdgpu device pointer
Christian König56467eb2015-12-11 15:16:32 +0100210 * @vm: vm providing the BOs
Christian Königf7da30d2016-09-28 12:03:04 +0200211 * @validate: callback to do the validation
212 * @param: parameter for the validation callback
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400213 *
Christian Königf7da30d2016-09-28 12:03:04 +0200214 * Validate the page table BOs on command submission if neccessary.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400215 */
Christian Königf7da30d2016-09-28 12:03:04 +0200216int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
217 int (*validate)(void *p, struct amdgpu_bo *bo),
218 void *param)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400219{
Christian König5a712a82016-06-21 16:28:15 +0200220 uint64_t num_evictions;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400221
Christian König5a712a82016-06-21 16:28:15 +0200222 /* We only need to validate the page tables
223 * if they aren't already valid.
224 */
225 num_evictions = atomic64_read(&adev->num_evictions);
226 if (num_evictions == vm->last_eviction_counter)
Christian Königf7da30d2016-09-28 12:03:04 +0200227 return 0;
Christian König5a712a82016-06-21 16:28:15 +0200228
Christian König0a096fb2017-07-12 10:01:48 +0200229 return amdgpu_vm_validate_level(&vm->root, validate, param,
Christian Königb6369222017-08-03 11:44:01 -0400230 vm->use_cpu_for_update,
231 adev->mman.bdev.glob);
Christian Königeceb8a12016-01-11 15:35:21 +0100232}
233
234/**
Christian Königf566ceb2016-10-27 20:04:38 +0200235 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
236 *
237 * @adev: amdgpu_device pointer
238 * @vm: requested vm
239 * @saddr: start of the address range
240 * @eaddr: end of the address range
241 *
242 * Make sure the page directories and page tables are allocated
243 */
244static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
245 struct amdgpu_vm *vm,
246 struct amdgpu_vm_pt *parent,
247 uint64_t saddr, uint64_t eaddr,
248 unsigned level)
249{
250 unsigned shift = (adev->vm_manager.num_level - level) *
Zhang, Jerry36b32a62017-03-29 16:08:32 +0800251 adev->vm_manager.block_size;
Christian Königf566ceb2016-10-27 20:04:38 +0200252 unsigned pt_idx, from, to;
253 int r;
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400254 u64 flags;
Yong Zhao51ac7ee2017-07-27 12:48:22 -0400255 uint64_t init_value = 0;
Christian Königf566ceb2016-10-27 20:04:38 +0200256
257 if (!parent->entries) {
258 unsigned num_entries = amdgpu_vm_num_entries(adev, level);
259
Michal Hocko20981052017-05-17 14:23:12 +0200260 parent->entries = kvmalloc_array(num_entries,
261 sizeof(struct amdgpu_vm_pt),
262 GFP_KERNEL | __GFP_ZERO);
Christian Königf566ceb2016-10-27 20:04:38 +0200263 if (!parent->entries)
264 return -ENOMEM;
265 memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
266 }
267
Felix Kuehling1866bac2017-03-28 20:36:12 -0400268 from = saddr >> shift;
269 to = eaddr >> shift;
270 if (from >= amdgpu_vm_num_entries(adev, level) ||
271 to >= amdgpu_vm_num_entries(adev, level))
272 return -EINVAL;
Christian Königf566ceb2016-10-27 20:04:38 +0200273
274 if (to > parent->last_entry_used)
275 parent->last_entry_used = to;
276
277 ++level;
Felix Kuehling1866bac2017-03-28 20:36:12 -0400278 saddr = saddr & ((1 << shift) - 1);
279 eaddr = eaddr & ((1 << shift) - 1);
Christian Königf566ceb2016-10-27 20:04:38 +0200280
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400281 flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
282 AMDGPU_GEM_CREATE_VRAM_CLEARED;
283 if (vm->use_cpu_for_update)
284 flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
285 else
286 flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
287 AMDGPU_GEM_CREATE_SHADOW);
288
Yong Zhao51ac7ee2017-07-27 12:48:22 -0400289 if (vm->pte_support_ats) {
290 init_value = AMDGPU_PTE_SYSTEM;
291 if (level != adev->vm_manager.num_level - 1)
292 init_value |= AMDGPU_PDE_PTE;
293 }
294
Christian Königf566ceb2016-10-27 20:04:38 +0200295 /* walk over the address space and allocate the page tables */
296 for (pt_idx = from; pt_idx <= to; ++pt_idx) {
297 struct reservation_object *resv = vm->root.bo->tbo.resv;
298 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
299 struct amdgpu_bo *pt;
300
301 if (!entry->bo) {
302 r = amdgpu_bo_create(adev,
303 amdgpu_vm_bo_size(adev, level),
304 AMDGPU_GPU_PAGE_SIZE, true,
305 AMDGPU_GEM_DOMAIN_VRAM,
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400306 flags,
Yong Zhao51ac7ee2017-07-27 12:48:22 -0400307 NULL, resv, init_value, &pt);
Christian Königf566ceb2016-10-27 20:04:38 +0200308 if (r)
309 return r;
310
Christian König0a096fb2017-07-12 10:01:48 +0200311 if (vm->use_cpu_for_update) {
312 r = amdgpu_bo_kmap(pt, NULL);
313 if (r) {
314 amdgpu_bo_unref(&pt);
315 return r;
316 }
317 }
318
Christian Königf566ceb2016-10-27 20:04:38 +0200319 /* Keep a reference to the root directory to avoid
320 * freeing them up in the wrong order.
321 */
322 pt->parent = amdgpu_bo_ref(vm->root.bo);
323
324 entry->bo = pt;
325 entry->addr = 0;
Alex Deuchercf2f0a32017-07-25 16:35:38 -0400326 entry->huge_page = false;
Christian Königf566ceb2016-10-27 20:04:38 +0200327 }
328
329 if (level < adev->vm_manager.num_level) {
Felix Kuehling1866bac2017-03-28 20:36:12 -0400330 uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
331 uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
332 ((1 << shift) - 1);
333 r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
334 sub_eaddr, level);
Christian Königf566ceb2016-10-27 20:04:38 +0200335 if (r)
336 return r;
337 }
338 }
339
340 return 0;
341}
342
Christian König663e4572017-03-13 10:13:37 +0100343/**
344 * amdgpu_vm_alloc_pts - Allocate page tables.
345 *
346 * @adev: amdgpu_device pointer
347 * @vm: VM to allocate page tables for
348 * @saddr: Start address which needs to be allocated
349 * @size: Size from start address we need.
350 *
351 * Make sure the page tables are allocated.
352 */
353int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
354 struct amdgpu_vm *vm,
355 uint64_t saddr, uint64_t size)
356{
Felix Kuehling22770e52017-03-28 20:24:53 -0400357 uint64_t last_pfn;
Christian König663e4572017-03-13 10:13:37 +0100358 uint64_t eaddr;
Christian König663e4572017-03-13 10:13:37 +0100359
360 /* validate the parameters */
361 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
362 return -EINVAL;
363
364 eaddr = saddr + size - 1;
365 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
366 if (last_pfn >= adev->vm_manager.max_pfn) {
Felix Kuehling22770e52017-03-28 20:24:53 -0400367 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
Christian König663e4572017-03-13 10:13:37 +0100368 last_pfn, adev->vm_manager.max_pfn);
369 return -EINVAL;
370 }
371
372 saddr /= AMDGPU_GPU_PAGE_SIZE;
373 eaddr /= AMDGPU_GPU_PAGE_SIZE;
374
Christian Königf566ceb2016-10-27 20:04:38 +0200375 return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
Christian König663e4572017-03-13 10:13:37 +0100376}
377
Christian König641e9402017-04-03 13:59:25 +0200378/**
379 * amdgpu_vm_had_gpu_reset - check if reset occured since last use
380 *
381 * @adev: amdgpu_device pointer
382 * @id: VMID structure
383 *
384 * Check if GPU reset occured since last use of the VMID.
385 */
386static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev,
387 struct amdgpu_vm_id *id)
Chunming Zhou192b7dc2016-06-29 14:01:15 +0800388{
389 return id->current_gpu_reset_count !=
Christian König641e9402017-04-03 13:59:25 +0200390 atomic_read(&adev->gpu_reset_counter);
Chunming Zhou192b7dc2016-06-29 14:01:15 +0800391}
392
Chunming Zhou7a63eb22017-04-21 11:13:56 +0800393static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub)
394{
395 return !!vm->reserved_vmid[vmhub];
396}
397
398/* idr_mgr->lock must be held */
399static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm,
400 struct amdgpu_ring *ring,
401 struct amdgpu_sync *sync,
402 struct dma_fence *fence,
403 struct amdgpu_job *job)
404{
405 struct amdgpu_device *adev = ring->adev;
406 unsigned vmhub = ring->funcs->vmhub;
407 uint64_t fence_context = adev->fence_context + ring->idx;
408 struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub];
409 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
410 struct dma_fence *updates = sync->last_vm_update;
411 int r = 0;
412 struct dma_fence *flushed, *tmp;
Christian König6f1ceab2017-07-11 16:59:21 +0200413 bool needs_flush = vm->use_cpu_for_update;
Chunming Zhou7a63eb22017-04-21 11:13:56 +0800414
415 flushed = id->flushed_updates;
416 if ((amdgpu_vm_had_gpu_reset(adev, id)) ||
417 (atomic64_read(&id->owner) != vm->client_id) ||
418 (job->vm_pd_addr != id->pd_gpu_addr) ||
419 (updates && (!flushed || updates->context != flushed->context ||
420 dma_fence_is_later(updates, flushed))) ||
421 (!id->last_flush || (id->last_flush->context != fence_context &&
422 !dma_fence_is_signaled(id->last_flush)))) {
423 needs_flush = true;
424 /* to prevent one context starved by another context */
425 id->pd_gpu_addr = 0;
426 tmp = amdgpu_sync_peek_fence(&id->active, ring);
427 if (tmp) {
428 r = amdgpu_sync_fence(adev, sync, tmp);
429 return r;
430 }
431 }
432
433 /* Good we can use this VMID. Remember this submission as
434 * user of the VMID.
435 */
436 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
437 if (r)
438 goto out;
439
440 if (updates && (!flushed || updates->context != flushed->context ||
441 dma_fence_is_later(updates, flushed))) {
442 dma_fence_put(id->flushed_updates);
443 id->flushed_updates = dma_fence_get(updates);
444 }
445 id->pd_gpu_addr = job->vm_pd_addr;
Chunming Zhou7a63eb22017-04-21 11:13:56 +0800446 atomic64_set(&id->owner, vm->client_id);
447 job->vm_needs_flush = needs_flush;
448 if (needs_flush) {
449 dma_fence_put(id->last_flush);
450 id->last_flush = NULL;
451 }
452 job->vm_id = id - id_mgr->ids;
453 trace_amdgpu_vm_grab_id(vm, ring, job);
454out:
455 return r;
456}
457
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400458/**
459 * amdgpu_vm_grab_id - allocate the next free VMID
460 *
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400461 * @vm: vm to allocate id for
Christian König7f8a5292015-07-20 16:09:40 +0200462 * @ring: ring we want to submit job to
463 * @sync: sync object where we add dependencies
Christian König94dd0a42016-01-18 17:01:42 +0100464 * @fence: fence protecting ID from reuse
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400465 *
Christian König7f8a5292015-07-20 16:09:40 +0200466 * Allocate an id for the vm, adding fences to the sync obj as necessary.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400467 */
Christian König7f8a5292015-07-20 16:09:40 +0200468int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100469 struct amdgpu_sync *sync, struct dma_fence *fence,
Chunming Zhoufd53be32016-07-01 17:59:01 +0800470 struct amdgpu_job *job)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400471{
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400472 struct amdgpu_device *adev = ring->adev;
Christian König2e819842017-03-30 16:50:47 +0200473 unsigned vmhub = ring->funcs->vmhub;
Christian König76456702017-04-06 17:52:39 +0200474 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
Christian König090b7672016-07-08 10:21:02 +0200475 uint64_t fence_context = adev->fence_context + ring->idx;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100476 struct dma_fence *updates = sync->last_vm_update;
Christian König8d76001e2016-05-23 16:00:32 +0200477 struct amdgpu_vm_id *id, *idle;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100478 struct dma_fence **fences;
Christian König1fbb2e92016-06-01 10:47:36 +0200479 unsigned i;
480 int r = 0;
481
Christian König76456702017-04-06 17:52:39 +0200482 mutex_lock(&id_mgr->lock);
Chunming Zhou7a63eb22017-04-21 11:13:56 +0800483 if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) {
484 r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job);
485 mutex_unlock(&id_mgr->lock);
486 return r;
487 }
488 fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
489 if (!fences) {
490 mutex_unlock(&id_mgr->lock);
491 return -ENOMEM;
492 }
Christian König36fd7c52016-05-23 15:30:08 +0200493 /* Check if we have an idle VMID */
Christian König1fbb2e92016-06-01 10:47:36 +0200494 i = 0;
Christian König76456702017-04-06 17:52:39 +0200495 list_for_each_entry(idle, &id_mgr->ids_lru, list) {
Christian König1fbb2e92016-06-01 10:47:36 +0200496 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
497 if (!fences[i])
Christian König36fd7c52016-05-23 15:30:08 +0200498 break;
Christian König1fbb2e92016-06-01 10:47:36 +0200499 ++i;
Christian König36fd7c52016-05-23 15:30:08 +0200500 }
Christian Königbcb1ba32016-03-08 15:40:11 +0100501
Christian König1fbb2e92016-06-01 10:47:36 +0200502 /* If we can't find a idle VMID to use, wait till one becomes available */
Christian König76456702017-04-06 17:52:39 +0200503 if (&idle->list == &id_mgr->ids_lru) {
Christian König1fbb2e92016-06-01 10:47:36 +0200504 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
505 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
Chris Wilsonf54d1862016-10-25 13:00:45 +0100506 struct dma_fence_array *array;
Christian König1fbb2e92016-06-01 10:47:36 +0200507 unsigned j;
Christian König8d76001e2016-05-23 16:00:32 +0200508
Christian König1fbb2e92016-06-01 10:47:36 +0200509 for (j = 0; j < i; ++j)
Chris Wilsonf54d1862016-10-25 13:00:45 +0100510 dma_fence_get(fences[j]);
Christian König8d76001e2016-05-23 16:00:32 +0200511
Chris Wilsonf54d1862016-10-25 13:00:45 +0100512 array = dma_fence_array_create(i, fences, fence_context,
Christian König1fbb2e92016-06-01 10:47:36 +0200513 seqno, true);
514 if (!array) {
515 for (j = 0; j < i; ++j)
Chris Wilsonf54d1862016-10-25 13:00:45 +0100516 dma_fence_put(fences[j]);
Christian König1fbb2e92016-06-01 10:47:36 +0200517 kfree(fences);
518 r = -ENOMEM;
519 goto error;
520 }
Christian König8d76001e2016-05-23 16:00:32 +0200521
Christian König8d76001e2016-05-23 16:00:32 +0200522
Christian König1fbb2e92016-06-01 10:47:36 +0200523 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
Chris Wilsonf54d1862016-10-25 13:00:45 +0100524 dma_fence_put(&array->base);
Christian König1fbb2e92016-06-01 10:47:36 +0200525 if (r)
526 goto error;
Christian König8d76001e2016-05-23 16:00:32 +0200527
Christian König76456702017-04-06 17:52:39 +0200528 mutex_unlock(&id_mgr->lock);
Christian König1fbb2e92016-06-01 10:47:36 +0200529 return 0;
Christian König8d76001e2016-05-23 16:00:32 +0200530
Christian König1fbb2e92016-06-01 10:47:36 +0200531 }
532 kfree(fences);
Christian König8d76001e2016-05-23 16:00:32 +0200533
Christian König6f1ceab2017-07-11 16:59:21 +0200534 job->vm_needs_flush = vm->use_cpu_for_update;
Christian König1fbb2e92016-06-01 10:47:36 +0200535 /* Check if we can use a VMID already assigned to this VM */
Christian König76456702017-04-06 17:52:39 +0200536 list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
Chris Wilsonf54d1862016-10-25 13:00:45 +0100537 struct dma_fence *flushed;
Christian König6f1ceab2017-07-11 16:59:21 +0200538 bool needs_flush = vm->use_cpu_for_update;
Christian König8d76001e2016-05-23 16:00:32 +0200539
Christian König1fbb2e92016-06-01 10:47:36 +0200540 /* Check all the prerequisites to using this VMID */
Christian König641e9402017-04-03 13:59:25 +0200541 if (amdgpu_vm_had_gpu_reset(adev, id))
Chunming Zhou6adb0512016-06-27 17:06:01 +0800542 continue;
Christian König1fbb2e92016-06-01 10:47:36 +0200543
544 if (atomic64_read(&id->owner) != vm->client_id)
545 continue;
546
Chunming Zhoufd53be32016-07-01 17:59:01 +0800547 if (job->vm_pd_addr != id->pd_gpu_addr)
Christian König1fbb2e92016-06-01 10:47:36 +0200548 continue;
549
Christian König87c910d2017-03-30 16:56:20 +0200550 if (!id->last_flush ||
551 (id->last_flush->context != fence_context &&
552 !dma_fence_is_signaled(id->last_flush)))
553 needs_flush = true;
Christian König1fbb2e92016-06-01 10:47:36 +0200554
555 flushed = id->flushed_updates;
Christian König87c910d2017-03-30 16:56:20 +0200556 if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
557 needs_flush = true;
558
559 /* Concurrent flushes are only possible starting with Vega10 */
560 if (adev->asic_type < CHIP_VEGA10 && needs_flush)
Christian König1fbb2e92016-06-01 10:47:36 +0200561 continue;
562
Christian König3dab83b2016-06-01 13:31:17 +0200563 /* Good we can use this VMID. Remember this submission as
564 * user of the VMID.
565 */
Christian König1fbb2e92016-06-01 10:47:36 +0200566 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
567 if (r)
568 goto error;
Christian König8d76001e2016-05-23 16:00:32 +0200569
Christian König87c910d2017-03-30 16:56:20 +0200570 if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
571 dma_fence_put(id->flushed_updates);
572 id->flushed_updates = dma_fence_get(updates);
573 }
Christian König8d76001e2016-05-23 16:00:32 +0200574
Christian König87c910d2017-03-30 16:56:20 +0200575 if (needs_flush)
576 goto needs_flush;
577 else
578 goto no_flush_needed;
Christian König8d76001e2016-05-23 16:00:32 +0200579
Christian König4f618e72017-04-06 15:18:21 +0200580 };
Chunming Zhou8e9fbeb2016-03-17 11:41:37 +0800581
Christian König1fbb2e92016-06-01 10:47:36 +0200582 /* Still no ID to use? Then use the idle one found earlier */
583 id = idle;
584
585 /* Remember this submission as user of the VMID */
586 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
Christian König832a9022016-02-15 12:33:02 +0100587 if (r)
588 goto error;
Christian König4ff37a82016-02-26 16:18:26 +0100589
Christian König87c910d2017-03-30 16:56:20 +0200590 id->pd_gpu_addr = job->vm_pd_addr;
591 dma_fence_put(id->flushed_updates);
592 id->flushed_updates = dma_fence_get(updates);
Christian König87c910d2017-03-30 16:56:20 +0200593 atomic64_set(&id->owner, vm->client_id);
594
595needs_flush:
596 job->vm_needs_flush = true;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100597 dma_fence_put(id->last_flush);
Christian König41d9eb22016-03-01 16:46:18 +0100598 id->last_flush = NULL;
599
Christian König87c910d2017-03-30 16:56:20 +0200600no_flush_needed:
Christian König76456702017-04-06 17:52:39 +0200601 list_move_tail(&id->list, &id_mgr->ids_lru);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400602
Christian König76456702017-04-06 17:52:39 +0200603 job->vm_id = id - id_mgr->ids;
Christian Königc5296d12017-04-07 15:31:13 +0200604 trace_amdgpu_vm_grab_id(vm, ring, job);
Christian König832a9022016-02-15 12:33:02 +0100605
606error:
Christian König76456702017-04-06 17:52:39 +0200607 mutex_unlock(&id_mgr->lock);
Christian Königa9a78b32016-01-21 10:19:11 +0100608 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400609}
610
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800611static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev,
612 struct amdgpu_vm *vm,
613 unsigned vmhub)
Alex Deucher93dcc372016-06-17 17:05:15 -0400614{
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800615 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
Alex Deucher93dcc372016-06-17 17:05:15 -0400616
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800617 mutex_lock(&id_mgr->lock);
618 if (vm->reserved_vmid[vmhub]) {
619 list_add(&vm->reserved_vmid[vmhub]->list,
620 &id_mgr->ids_lru);
621 vm->reserved_vmid[vmhub] = NULL;
Chunming Zhouc3505772017-04-21 15:51:04 +0800622 atomic_dec(&id_mgr->reserved_vmid_num);
Alex Deucher93dcc372016-06-17 17:05:15 -0400623 }
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800624 mutex_unlock(&id_mgr->lock);
Alex Deucher93dcc372016-06-17 17:05:15 -0400625}
626
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800627static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev,
628 struct amdgpu_vm *vm,
629 unsigned vmhub)
Alex Xiee60f8db2017-03-09 11:36:26 -0500630{
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800631 struct amdgpu_vm_id_manager *id_mgr;
632 struct amdgpu_vm_id *idle;
633 int r = 0;
Alex Xiee60f8db2017-03-09 11:36:26 -0500634
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800635 id_mgr = &adev->vm_manager.id_mgr[vmhub];
636 mutex_lock(&id_mgr->lock);
637 if (vm->reserved_vmid[vmhub])
638 goto unlock;
Chunming Zhouc3505772017-04-21 15:51:04 +0800639 if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
640 AMDGPU_VM_MAX_RESERVED_VMID) {
641 DRM_ERROR("Over limitation of reserved vmid\n");
642 atomic_dec(&id_mgr->reserved_vmid_num);
643 r = -EINVAL;
644 goto unlock;
645 }
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800646 /* Select the first entry VMID */
647 idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list);
648 list_del_init(&idle->list);
649 vm->reserved_vmid[vmhub] = idle;
650 mutex_unlock(&id_mgr->lock);
Alex Xiee60f8db2017-03-09 11:36:26 -0500651
Chunming Zhou1e9ef262017-04-20 16:18:48 +0800652 return 0;
653unlock:
654 mutex_unlock(&id_mgr->lock);
655 return r;
656}
657
Alex Xiee59c0202017-06-01 09:42:59 -0400658/**
659 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
660 *
661 * @adev: amdgpu_device pointer
662 */
663void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
664{
665 const struct amdgpu_ip_block *ip_block;
666 bool has_compute_vm_bug;
667 struct amdgpu_ring *ring;
668 int i;
669
670 has_compute_vm_bug = false;
671
672 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
673 if (ip_block) {
674 /* Compute has a VM bug for GFX version < 7.
675 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
676 if (ip_block->version->major <= 7)
677 has_compute_vm_bug = true;
678 else if (ip_block->version->major == 8)
679 if (adev->gfx.mec_fw_version < 673)
680 has_compute_vm_bug = true;
681 }
682
683 for (i = 0; i < adev->num_rings; i++) {
684 ring = adev->rings[i];
685 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
686 /* only compute rings */
687 ring->has_compute_vm_bug = has_compute_vm_bug;
688 else
689 ring->has_compute_vm_bug = false;
690 }
691}
692
Chunming Zhoub9bf33d2017-05-11 14:52:48 -0400693bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
694 struct amdgpu_job *job)
695{
696 struct amdgpu_device *adev = ring->adev;
697 unsigned vmhub = ring->funcs->vmhub;
698 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
699 struct amdgpu_vm_id *id;
700 bool gds_switch_needed;
Alex Xiee59c0202017-06-01 09:42:59 -0400701 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
Chunming Zhoub9bf33d2017-05-11 14:52:48 -0400702
703 if (job->vm_id == 0)
704 return false;
705 id = &id_mgr->ids[job->vm_id];
706 gds_switch_needed = ring->funcs->emit_gds_switch && (
707 id->gds_base != job->gds_base ||
708 id->gds_size != job->gds_size ||
709 id->gws_base != job->gws_base ||
710 id->gws_size != job->gws_size ||
711 id->oa_base != job->oa_base ||
712 id->oa_size != job->oa_size);
713
714 if (amdgpu_vm_had_gpu_reset(adev, id))
715 return true;
Alex Xiebb37b672017-05-30 23:50:10 -0400716
717 return vm_flush_needed || gds_switch_needed;
Chunming Zhoub9bf33d2017-05-11 14:52:48 -0400718}
719
Harish Kasiviswanathan9a4b7d42017-06-09 11:26:57 -0400720static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
721{
722 return (adev->mc.real_vram_size == adev->mc.visible_vram_size);
Alex Xiee60f8db2017-03-09 11:36:26 -0500723}
724
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400725/**
726 * amdgpu_vm_flush - hardware flush the vm
727 *
728 * @ring: ring to use for flush
Christian Königcffadc82016-03-01 13:34:49 +0100729 * @vm_id: vmid number to use
Christian König4ff37a82016-02-26 16:18:26 +0100730 * @pd_addr: address of the page directory
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400731 *
Christian König4ff37a82016-02-26 16:18:26 +0100732 * Emit a VM flush when it is necessary.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400733 */
Monk Liu8fdf0742017-06-06 17:25:13 +0800734int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400735{
Christian König971fe9a92016-03-01 15:09:25 +0100736 struct amdgpu_device *adev = ring->adev;
Christian König76456702017-04-06 17:52:39 +0200737 unsigned vmhub = ring->funcs->vmhub;
738 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
739 struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id];
Christian Königd564a062016-03-01 15:51:53 +0100740 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
Chunming Zhoufd53be32016-07-01 17:59:01 +0800741 id->gds_base != job->gds_base ||
742 id->gds_size != job->gds_size ||
743 id->gws_base != job->gws_base ||
744 id->gws_size != job->gws_size ||
745 id->oa_base != job->oa_base ||
746 id->oa_size != job->oa_size);
Flora Cuide37e682017-05-18 13:56:22 +0800747 bool vm_flush_needed = job->vm_needs_flush;
Christian Königc0e51932017-04-03 14:16:07 +0200748 unsigned patch_offset = 0;
Christian König41d9eb22016-03-01 16:46:18 +0100749 int r;
Christian Königd564a062016-03-01 15:51:53 +0100750
Christian Königf7d015b2017-04-03 14:28:26 +0200751 if (amdgpu_vm_had_gpu_reset(adev, id)) {
752 gds_switch_needed = true;
753 vm_flush_needed = true;
754 }
Christian König971fe9a92016-03-01 15:09:25 +0100755
Monk Liu8fdf0742017-06-06 17:25:13 +0800756 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
Christian Königf7d015b2017-04-03 14:28:26 +0200757 return 0;
Christian König41d9eb22016-03-01 16:46:18 +0100758
Christian Königc0e51932017-04-03 14:16:07 +0200759 if (ring->funcs->init_cond_exec)
760 patch_offset = amdgpu_ring_init_cond_exec(ring);
Christian König41d9eb22016-03-01 16:46:18 +0100761
Monk Liu8fdf0742017-06-06 17:25:13 +0800762 if (need_pipe_sync)
763 amdgpu_ring_emit_pipeline_sync(ring);
764
Christian Königf7d015b2017-04-03 14:28:26 +0200765 if (ring->funcs->emit_vm_flush && vm_flush_needed) {
Christian Königc0e51932017-04-03 14:16:07 +0200766 struct dma_fence *fence;
Monk Liue9d672b2017-03-15 12:18:57 +0800767
Christian König9a94f5a2017-05-12 14:46:23 +0200768 trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr);
769 amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);
Monk Liue9d672b2017-03-15 12:18:57 +0800770
Christian Königc0e51932017-04-03 14:16:07 +0200771 r = amdgpu_fence_emit(ring, &fence);
772 if (r)
773 return r;
Monk Liue9d672b2017-03-15 12:18:57 +0800774
Christian König76456702017-04-06 17:52:39 +0200775 mutex_lock(&id_mgr->lock);
Christian Königc0e51932017-04-03 14:16:07 +0200776 dma_fence_put(id->last_flush);
777 id->last_flush = fence;
Chunming Zhoubea396722017-05-10 13:02:39 +0800778 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
Christian König76456702017-04-06 17:52:39 +0200779 mutex_unlock(&id_mgr->lock);
Christian Königc0e51932017-04-03 14:16:07 +0200780 }
Monk Liue9d672b2017-03-15 12:18:57 +0800781
Chunming Zhou7c4378f2017-05-11 18:22:17 +0800782 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
Christian Königc0e51932017-04-03 14:16:07 +0200783 id->gds_base = job->gds_base;
784 id->gds_size = job->gds_size;
785 id->gws_base = job->gws_base;
786 id->gws_size = job->gws_size;
787 id->oa_base = job->oa_base;
788 id->oa_size = job->oa_size;
789 amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
790 job->gds_size, job->gws_base,
791 job->gws_size, job->oa_base,
792 job->oa_size);
793 }
794
795 if (ring->funcs->patch_cond_exec)
796 amdgpu_ring_patch_cond_exec(ring, patch_offset);
797
798 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
799 if (ring->funcs->emit_switch_buffer) {
800 amdgpu_ring_emit_switch_buffer(ring);
801 amdgpu_ring_emit_switch_buffer(ring);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400802 }
Christian König41d9eb22016-03-01 16:46:18 +0100803 return 0;
Christian König971fe9a92016-03-01 15:09:25 +0100804}
805
806/**
807 * amdgpu_vm_reset_id - reset VMID to zero
808 *
809 * @adev: amdgpu device structure
810 * @vm_id: vmid number to use
811 *
812 * Reset saved GDW, GWS and OA to force switch on next flush.
813 */
Christian König76456702017-04-06 17:52:39 +0200814void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
815 unsigned vmid)
Christian König971fe9a92016-03-01 15:09:25 +0100816{
Christian König76456702017-04-06 17:52:39 +0200817 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
818 struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
Christian König971fe9a92016-03-01 15:09:25 +0100819
Christian Königb3c85a02017-05-10 20:06:58 +0200820 atomic64_set(&id->owner, 0);
Christian Königbcb1ba32016-03-08 15:40:11 +0100821 id->gds_base = 0;
822 id->gds_size = 0;
823 id->gws_base = 0;
824 id->gws_size = 0;
825 id->oa_base = 0;
826 id->oa_size = 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400827}
828
829/**
Christian Königb3c85a02017-05-10 20:06:58 +0200830 * amdgpu_vm_reset_all_id - reset VMID to zero
831 *
832 * @adev: amdgpu device structure
833 *
834 * Reset VMID to force flush on next use
835 */
836void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev)
837{
838 unsigned i, j;
839
840 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
841 struct amdgpu_vm_id_manager *id_mgr =
842 &adev->vm_manager.id_mgr[i];
843
844 for (j = 1; j < id_mgr->num_ids; ++j)
845 amdgpu_vm_reset_id(adev, i, j);
846 }
847}
848
849/**
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400850 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
851 *
852 * @vm: requested vm
853 * @bo: requested buffer object
854 *
Christian König8843dbb2016-01-26 12:17:11 +0100855 * Find @bo inside the requested vm.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400856 * Search inside the @bos vm list for the requested vm
857 * Returns the found bo_va or NULL if none is found
858 *
859 * Object has to be reserved!
860 */
861struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
862 struct amdgpu_bo *bo)
863{
864 struct amdgpu_bo_va *bo_va;
865
866 list_for_each_entry(bo_va, &bo->va, bo_list) {
867 if (bo_va->vm == vm) {
868 return bo_va;
869 }
870 }
871 return NULL;
872}
873
874/**
Christian Königafef8b82016-08-12 13:29:18 +0200875 * amdgpu_vm_do_set_ptes - helper to call the right asic function
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400876 *
Christian König29efc4f2016-08-04 14:52:50 +0200877 * @params: see amdgpu_pte_update_params definition
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400878 * @pe: addr of the page entry
879 * @addr: dst addr to write into pe
880 * @count: number of page entries to update
881 * @incr: increase next addr by incr bytes
882 * @flags: hw access flags
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400883 *
884 * Traces the parameters and calls the right asic functions
885 * to setup the page table using the DMA.
886 */
Christian Königafef8b82016-08-12 13:29:18 +0200887static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
888 uint64_t pe, uint64_t addr,
889 unsigned count, uint32_t incr,
Chunming Zhou6b777602016-09-21 16:19:19 +0800890 uint64_t flags)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400891{
Christian Königec2f05f2016-09-25 16:11:52 +0200892 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400893
Christian Königafef8b82016-08-12 13:29:18 +0200894 if (count < 3) {
Christian Königde9ea7b2016-08-12 11:33:30 +0200895 amdgpu_vm_write_pte(params->adev, params->ib, pe,
896 addr | flags, count, incr);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400897
898 } else {
Christian König27c5f362016-08-04 15:02:49 +0200899 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400900 count, incr, flags);
901 }
902}
903
904/**
Christian Königafef8b82016-08-12 13:29:18 +0200905 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
906 *
907 * @params: see amdgpu_pte_update_params definition
908 * @pe: addr of the page entry
909 * @addr: dst addr to write into pe
910 * @count: number of page entries to update
911 * @incr: increase next addr by incr bytes
912 * @flags: hw access flags
913 *
914 * Traces the parameters and calls the DMA function to copy the PTEs.
915 */
916static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
917 uint64_t pe, uint64_t addr,
918 unsigned count, uint32_t incr,
Chunming Zhou6b777602016-09-21 16:19:19 +0800919 uint64_t flags)
Christian Königafef8b82016-08-12 13:29:18 +0200920{
Christian Königec2f05f2016-09-25 16:11:52 +0200921 uint64_t src = (params->src + (addr >> 12) * 8);
Christian Königafef8b82016-08-12 13:29:18 +0200922
Christian Königec2f05f2016-09-25 16:11:52 +0200923
924 trace_amdgpu_vm_copy_ptes(pe, src, count);
925
926 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
Christian Königafef8b82016-08-12 13:29:18 +0200927}
928
929/**
Christian Königb07c9d22015-11-30 13:26:07 +0100930 * amdgpu_vm_map_gart - Resolve gart mapping of addr
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400931 *
Christian Königb07c9d22015-11-30 13:26:07 +0100932 * @pages_addr: optional DMA address to use for lookup
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400933 * @addr: the unmapped addr
934 *
935 * Look up the physical address of the page that the pte resolves
Christian Königb07c9d22015-11-30 13:26:07 +0100936 * to and return the pointer for the page table entry.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400937 */
Christian Königde9ea7b2016-08-12 11:33:30 +0200938static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400939{
940 uint64_t result;
941
Christian Königde9ea7b2016-08-12 11:33:30 +0200942 /* page table offset */
943 result = pages_addr[addr >> PAGE_SHIFT];
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400944
Christian Königde9ea7b2016-08-12 11:33:30 +0200945 /* in case cpu page size != gpu page size*/
946 result |= addr & (~PAGE_MASK);
Christian Königb07c9d22015-11-30 13:26:07 +0100947
948 result &= 0xFFFFFFFFFFFFF000ULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400949
950 return result;
951}
952
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400953/**
954 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
955 *
956 * @params: see amdgpu_pte_update_params definition
957 * @pe: kmap addr of the page entry
958 * @addr: dst addr to write into pe
959 * @count: number of page entries to update
960 * @incr: increase next addr by incr bytes
961 * @flags: hw access flags
962 *
963 * Write count number of PT/PD entries directly.
964 */
965static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
966 uint64_t pe, uint64_t addr,
967 unsigned count, uint32_t incr,
968 uint64_t flags)
969{
970 unsigned int i;
Harish Kasiviswanathanb4d42512017-05-11 19:47:22 -0400971 uint64_t value;
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400972
Christian König03918b32017-07-11 17:15:37 +0200973 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
974
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400975 for (i = 0; i < count; i++) {
Harish Kasiviswanathanb4d42512017-05-11 19:47:22 -0400976 value = params->pages_addr ?
977 amdgpu_vm_map_gart(params->pages_addr, addr) :
978 addr;
Harish Kasiviswanathana19240052017-06-09 17:47:28 -0400979 amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
Harish Kasiviswanathanb4d42512017-05-11 19:47:22 -0400980 i, value, flags);
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400981 addr += incr;
982 }
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400983}
984
Christian Königa33cab72017-07-11 17:13:00 +0200985static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
986 void *owner)
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400987{
988 struct amdgpu_sync sync;
989 int r;
990
991 amdgpu_sync_create(&sync);
Christian Königa33cab72017-07-11 17:13:00 +0200992 amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.resv, owner);
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -0400993 r = amdgpu_sync_wait(&sync, true);
994 amdgpu_sync_free(&sync);
995
996 return r;
997}
998
Christian Königf8991ba2016-09-16 15:36:49 +0200999/*
Christian König194d2162016-10-12 15:13:52 +02001000 * amdgpu_vm_update_level - update a single level in the hierarchy
Christian Königf8991ba2016-09-16 15:36:49 +02001001 *
1002 * @adev: amdgpu_device pointer
1003 * @vm: requested vm
Christian König194d2162016-10-12 15:13:52 +02001004 * @parent: parent directory
Christian Königf8991ba2016-09-16 15:36:49 +02001005 *
Christian König194d2162016-10-12 15:13:52 +02001006 * Makes sure all entries in @parent are up to date.
Christian Königf8991ba2016-09-16 15:36:49 +02001007 * Returns 0 for success, error for failure.
1008 */
Christian König194d2162016-10-12 15:13:52 +02001009static int amdgpu_vm_update_level(struct amdgpu_device *adev,
1010 struct amdgpu_vm *vm,
1011 struct amdgpu_vm_pt *parent,
1012 unsigned level)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001013{
Christian Königf8991ba2016-09-16 15:36:49 +02001014 struct amdgpu_bo *shadow;
Harish Kasiviswanathana19240052017-06-09 17:47:28 -04001015 struct amdgpu_ring *ring = NULL;
1016 uint64_t pd_addr, shadow_addr = 0;
Christian König194d2162016-10-12 15:13:52 +02001017 uint32_t incr = amdgpu_vm_bo_size(adev, level + 1);
Christian Königf8991ba2016-09-16 15:36:49 +02001018 uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
Harish Kasiviswanathana19240052017-06-09 17:47:28 -04001019 unsigned count = 0, pt_idx, ndw = 0;
Christian Königd71518b2016-02-01 12:20:25 +01001020 struct amdgpu_job *job;
Christian König29efc4f2016-08-04 14:52:50 +02001021 struct amdgpu_pte_update_params params;
Dave Airlie220196b2016-10-28 11:33:52 +10001022 struct dma_fence *fence = NULL;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001023
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001024 int r;
1025
Christian König194d2162016-10-12 15:13:52 +02001026 if (!parent->entries)
1027 return 0;
Christian Königd71518b2016-02-01 12:20:25 +01001028
Christian König27c5f362016-08-04 15:02:49 +02001029 memset(&params, 0, sizeof(params));
1030 params.adev = adev;
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04001031 shadow = parent->bo->shadow;
1032
Alex Deucher69277982017-07-13 15:37:11 -04001033 if (vm->use_cpu_for_update) {
Christian Königf5e1c742017-07-20 23:45:18 +02001034 pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo);
Christian Königa33cab72017-07-11 17:13:00 +02001035 r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
Christian König0a096fb2017-07-12 10:01:48 +02001036 if (unlikely(r))
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04001037 return r;
Christian König0a096fb2017-07-12 10:01:48 +02001038
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04001039 params.func = amdgpu_vm_cpu_set_ptes;
1040 } else {
1041 if (shadow) {
1042 r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
1043 if (r)
1044 return r;
1045 }
1046 ring = container_of(vm->entity.sched, struct amdgpu_ring,
1047 sched);
1048
1049 /* padding, etc. */
1050 ndw = 64;
1051
1052 /* assume the worst case */
1053 ndw += parent->last_entry_used * 6;
1054
1055 pd_addr = amdgpu_bo_gpu_offset(parent->bo);
1056
1057 if (shadow) {
1058 shadow_addr = amdgpu_bo_gpu_offset(shadow);
1059 ndw *= 2;
1060 } else {
1061 shadow_addr = 0;
1062 }
1063
1064 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1065 if (r)
1066 return r;
1067
1068 params.ib = &job->ibs[0];
1069 params.func = amdgpu_vm_do_set_ptes;
1070 }
1071
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001072
Christian König194d2162016-10-12 15:13:52 +02001073 /* walk over the address space and update the directory */
1074 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
1075 struct amdgpu_bo *bo = parent->entries[pt_idx].bo;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001076 uint64_t pde, pt;
1077
1078 if (bo == NULL)
1079 continue;
1080
Christian König0fc86832016-09-16 11:46:23 +02001081 if (bo->shadow) {
Christian Königf8991ba2016-09-16 15:36:49 +02001082 struct amdgpu_bo *pt_shadow = bo->shadow;
Christian König0fc86832016-09-16 11:46:23 +02001083
Christian Königf8991ba2016-09-16 15:36:49 +02001084 r = amdgpu_ttm_bind(&pt_shadow->tbo,
1085 &pt_shadow->tbo.mem);
Christian König0fc86832016-09-16 11:46:23 +02001086 if (r)
1087 return r;
1088 }
1089
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001090 pt = amdgpu_bo_gpu_offset(bo);
Christian König53e2e912017-05-15 15:19:10 +02001091 pt = amdgpu_gart_get_vm_pde(adev, pt);
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001092 if (parent->entries[pt_idx].addr == pt ||
1093 parent->entries[pt_idx].huge_page)
Christian Königf8991ba2016-09-16 15:36:49 +02001094 continue;
1095
Christian König194d2162016-10-12 15:13:52 +02001096 parent->entries[pt_idx].addr = pt;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001097
1098 pde = pd_addr + pt_idx * 8;
1099 if (((last_pde + 8 * count) != pde) ||
Christian König96105e52016-08-12 12:59:59 +02001100 ((last_pt + incr * count) != pt) ||
1101 (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001102
1103 if (count) {
Christian Königf8991ba2016-09-16 15:36:49 +02001104 if (shadow)
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04001105 params.func(&params,
1106 last_shadow,
1107 last_pt, count,
1108 incr,
1109 AMDGPU_PTE_VALID);
Christian Königf8991ba2016-09-16 15:36:49 +02001110
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04001111 params.func(&params, last_pde,
1112 last_pt, count, incr,
1113 AMDGPU_PTE_VALID);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001114 }
1115
1116 count = 1;
1117 last_pde = pde;
Christian Königf8991ba2016-09-16 15:36:49 +02001118 last_shadow = shadow_addr + pt_idx * 8;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001119 last_pt = pt;
1120 } else {
1121 ++count;
1122 }
1123 }
1124
Christian Königf8991ba2016-09-16 15:36:49 +02001125 if (count) {
Christian König67003a12016-10-12 14:46:26 +02001126 if (vm->root.bo->shadow)
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04001127 params.func(&params, last_shadow, last_pt,
1128 count, incr, AMDGPU_PTE_VALID);
Christian Königf8991ba2016-09-16 15:36:49 +02001129
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04001130 params.func(&params, last_pde, last_pt,
1131 count, incr, AMDGPU_PTE_VALID);
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001132 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001133
Christian König0a096fb2017-07-12 10:01:48 +02001134 if (!vm->use_cpu_for_update) {
1135 if (params.ib->length_dw == 0) {
1136 amdgpu_job_free(job);
1137 } else {
1138 amdgpu_ring_pad_ib(ring, params.ib);
1139 amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv,
Christian König194d2162016-10-12 15:13:52 +02001140 AMDGPU_FENCE_OWNER_VM);
Christian König0a096fb2017-07-12 10:01:48 +02001141 if (shadow)
1142 amdgpu_sync_resv(adev, &job->sync,
1143 shadow->tbo.resv,
1144 AMDGPU_FENCE_OWNER_VM);
Christian Königf8991ba2016-09-16 15:36:49 +02001145
Christian König0a096fb2017-07-12 10:01:48 +02001146 WARN_ON(params.ib->length_dw > ndw);
1147 r = amdgpu_job_submit(job, ring, &vm->entity,
1148 AMDGPU_FENCE_OWNER_VM, &fence);
1149 if (r)
1150 goto error_free;
Christian Königf8991ba2016-09-16 15:36:49 +02001151
Christian König0a096fb2017-07-12 10:01:48 +02001152 amdgpu_bo_fence(parent->bo, fence, true);
1153 dma_fence_put(vm->last_dir_update);
1154 vm->last_dir_update = dma_fence_get(fence);
1155 dma_fence_put(fence);
1156 }
Christian König194d2162016-10-12 15:13:52 +02001157 }
1158 /*
1159 * Recurse into the subdirectories. This recursion is harmless because
1160 * we only have a maximum of 5 layers.
1161 */
1162 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
1163 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
1164
1165 if (!entry->bo)
1166 continue;
1167
1168 r = amdgpu_vm_update_level(adev, vm, entry, level + 1);
1169 if (r)
1170 return r;
1171 }
Christian Königf8991ba2016-09-16 15:36:49 +02001172
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001173 return 0;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001174
1175error_free:
Christian Königd71518b2016-02-01 12:20:25 +01001176 amdgpu_job_free(job);
Chunming Zhou4af9f072015-08-03 12:57:31 +08001177 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001178}
1179
Christian König194d2162016-10-12 15:13:52 +02001180/*
Christian König92456b92017-05-12 16:09:26 +02001181 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
1182 *
1183 * @parent: parent PD
1184 *
1185 * Mark all PD level as invalid after an error.
1186 */
1187static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent)
1188{
1189 unsigned pt_idx;
1190
1191 /*
1192 * Recurse into the subdirectories. This recursion is harmless because
1193 * we only have a maximum of 5 layers.
1194 */
1195 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
1196 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
1197
1198 if (!entry->bo)
1199 continue;
1200
1201 entry->addr = ~0ULL;
1202 amdgpu_vm_invalidate_level(entry);
1203 }
1204}
1205
1206/*
Christian König194d2162016-10-12 15:13:52 +02001207 * amdgpu_vm_update_directories - make sure that all directories are valid
1208 *
1209 * @adev: amdgpu_device pointer
1210 * @vm: requested vm
1211 *
1212 * Makes sure all directories are up to date.
1213 * Returns 0 for success, error for failure.
1214 */
1215int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1216 struct amdgpu_vm *vm)
1217{
Christian König92456b92017-05-12 16:09:26 +02001218 int r;
1219
1220 r = amdgpu_vm_update_level(adev, vm, &vm->root, 0);
1221 if (r)
1222 amdgpu_vm_invalidate_level(&vm->root);
1223
Christian König68c62302017-07-11 17:23:29 +02001224 if (vm->use_cpu_for_update) {
1225 /* Flush HDP */
1226 mb();
1227 amdgpu_gart_flush_gpu_tlb(adev, 0);
1228 }
1229
Christian König92456b92017-05-12 16:09:26 +02001230 return r;
Christian König194d2162016-10-12 15:13:52 +02001231}
1232
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001233/**
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001234 * amdgpu_vm_find_entry - find the entry for an address
Christian König4e2cb642016-10-25 15:52:28 +02001235 *
1236 * @p: see amdgpu_pte_update_params definition
1237 * @addr: virtual address in question
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001238 * @entry: resulting entry or NULL
1239 * @parent: parent entry
Christian König4e2cb642016-10-25 15:52:28 +02001240 *
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001241 * Find the vm_pt entry and it's parent for the given address.
Christian König4e2cb642016-10-25 15:52:28 +02001242 */
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001243void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
1244 struct amdgpu_vm_pt **entry,
1245 struct amdgpu_vm_pt **parent)
Christian König4e2cb642016-10-25 15:52:28 +02001246{
Christian König4e2cb642016-10-25 15:52:28 +02001247 unsigned idx, level = p->adev->vm_manager.num_level;
1248
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001249 *parent = NULL;
1250 *entry = &p->vm->root;
1251 while ((*entry)->entries) {
Zhang, Jerry36b32a62017-03-29 16:08:32 +08001252 idx = addr >> (p->adev->vm_manager.block_size * level--);
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001253 idx %= amdgpu_bo_size((*entry)->bo) / 8;
1254 *parent = *entry;
1255 *entry = &(*entry)->entries[idx];
Christian König4e2cb642016-10-25 15:52:28 +02001256 }
1257
1258 if (level)
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001259 *entry = NULL;
1260}
Christian König4e2cb642016-10-25 15:52:28 +02001261
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001262/**
1263 * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
1264 *
1265 * @p: see amdgpu_pte_update_params definition
1266 * @entry: vm_pt entry to check
1267 * @parent: parent entry
1268 * @nptes: number of PTEs updated with this operation
1269 * @dst: destination address where the PTEs should point to
1270 * @flags: access flags fro the PTEs
1271 *
1272 * Check if we can update the PD with a huge page.
1273 */
1274static int amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
1275 struct amdgpu_vm_pt *entry,
1276 struct amdgpu_vm_pt *parent,
1277 unsigned nptes, uint64_t dst,
1278 uint64_t flags)
1279{
1280 bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes);
1281 uint64_t pd_addr, pde;
1282 int r;
1283
1284 /* In the case of a mixed PT the PDE must point to it*/
1285 if (p->adev->asic_type < CHIP_VEGA10 ||
1286 nptes != AMDGPU_VM_PTE_COUNT(p->adev) ||
1287 p->func == amdgpu_vm_do_copy_ptes ||
1288 !(flags & AMDGPU_PTE_VALID)) {
1289
1290 dst = amdgpu_bo_gpu_offset(entry->bo);
1291 dst = amdgpu_gart_get_vm_pde(p->adev, dst);
1292 flags = AMDGPU_PTE_VALID;
1293 } else {
1294 flags |= AMDGPU_PDE_PTE;
1295 }
1296
1297 if (entry->addr == dst &&
1298 entry->huge_page == !!(flags & AMDGPU_PDE_PTE))
1299 return 0;
1300
1301 entry->addr = dst;
1302 entry->huge_page = !!(flags & AMDGPU_PDE_PTE);
1303
1304 if (use_cpu_update) {
1305 r = amdgpu_bo_kmap(parent->bo, (void *)&pd_addr);
1306 if (r)
1307 return r;
1308
1309 pde = pd_addr + (entry - parent->entries) * 8;
1310 amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags);
1311 } else {
1312 if (parent->bo->shadow) {
1313 pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow);
1314 pde = pd_addr + (entry - parent->entries) * 8;
1315 amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
1316 }
1317 pd_addr = amdgpu_bo_gpu_offset(parent->bo);
1318 pde = pd_addr + (entry - parent->entries) * 8;
1319 amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
1320 }
1321
1322 return 0;
Christian König4e2cb642016-10-25 15:52:28 +02001323}
1324
1325/**
Christian König92696dd2016-08-05 13:56:35 +02001326 * amdgpu_vm_update_ptes - make sure that page tables are valid
1327 *
1328 * @params: see amdgpu_pte_update_params definition
1329 * @vm: requested vm
1330 * @start: start of GPU address range
1331 * @end: end of GPU address range
1332 * @dst: destination address to map to, the next dst inside the function
1333 * @flags: mapping flags
1334 *
1335 * Update the page tables in the range @start - @end.
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001336 * Returns 0 for success, -EINVAL for failure.
Christian König92696dd2016-08-05 13:56:35 +02001337 */
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001338static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
Christian König92696dd2016-08-05 13:56:35 +02001339 uint64_t start, uint64_t end,
Chunming Zhou6b777602016-09-21 16:19:19 +08001340 uint64_t dst, uint64_t flags)
Christian König92696dd2016-08-05 13:56:35 +02001341{
Zhang, Jerry36b32a62017-03-29 16:08:32 +08001342 struct amdgpu_device *adev = params->adev;
1343 const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
Christian König92696dd2016-08-05 13:56:35 +02001344
Christian König301654a2017-05-16 14:30:27 +02001345 uint64_t addr, pe_start;
Christian König92696dd2016-08-05 13:56:35 +02001346 struct amdgpu_bo *pt;
Christian König301654a2017-05-16 14:30:27 +02001347 unsigned nptes;
Harish Kasiviswanathan370f0922017-06-09 17:47:27 -04001348 bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes);
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001349 int r;
Christian König92696dd2016-08-05 13:56:35 +02001350
1351 /* walk over the address space and update the page tables */
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001352 for (addr = start; addr < end; addr += nptes,
1353 dst += nptes * AMDGPU_GPU_PAGE_SIZE) {
1354 struct amdgpu_vm_pt *entry, *parent;
1355
1356 amdgpu_vm_get_entry(params, addr, &entry, &parent);
1357 if (!entry)
1358 return -ENOENT;
Christian König4e2cb642016-10-25 15:52:28 +02001359
Christian König92696dd2016-08-05 13:56:35 +02001360 if ((addr & ~mask) == (end & ~mask))
1361 nptes = end - addr;
1362 else
Zhang, Jerry36b32a62017-03-29 16:08:32 +08001363 nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
Christian König92696dd2016-08-05 13:56:35 +02001364
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001365 r = amdgpu_vm_handle_huge_pages(params, entry, parent,
1366 nptes, dst, flags);
1367 if (r)
1368 return r;
1369
1370 if (entry->huge_page)
1371 continue;
1372
1373 pt = entry->bo;
Harish Kasiviswanathan370f0922017-06-09 17:47:27 -04001374 if (use_cpu_update) {
Christian Königf5e1c742017-07-20 23:45:18 +02001375 pe_start = (unsigned long)amdgpu_bo_kptr(pt);
Christian Königdd0792c2017-06-27 14:48:15 -04001376 } else {
1377 if (pt->shadow) {
1378 pe_start = amdgpu_bo_gpu_offset(pt->shadow);
1379 pe_start += (addr & mask) * 8;
1380 params->func(params, pe_start, dst, nptes,
1381 AMDGPU_GPU_PAGE_SIZE, flags);
1382 }
Harish Kasiviswanathan370f0922017-06-09 17:47:27 -04001383 pe_start = amdgpu_bo_gpu_offset(pt);
Christian Königdd0792c2017-06-27 14:48:15 -04001384 }
Christian König92696dd2016-08-05 13:56:35 +02001385
Christian König301654a2017-05-16 14:30:27 +02001386 pe_start += (addr & mask) * 8;
Christian König301654a2017-05-16 14:30:27 +02001387 params->func(params, pe_start, dst, nptes,
1388 AMDGPU_GPU_PAGE_SIZE, flags);
Christian König92696dd2016-08-05 13:56:35 +02001389 }
1390
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001391 return 0;
Christian König92696dd2016-08-05 13:56:35 +02001392}
1393
1394/*
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001395 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1396 *
Christian König29efc4f2016-08-04 14:52:50 +02001397 * @params: see amdgpu_pte_update_params definition
Christian König92696dd2016-08-05 13:56:35 +02001398 * @vm: requested vm
1399 * @start: first PTE to handle
1400 * @end: last PTE to handle
1401 * @dst: addr those PTEs should point to
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001402 * @flags: hw mapping flags
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001403 * Returns 0 for success, -EINVAL for failure.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001404 */
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001405static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
Christian König92696dd2016-08-05 13:56:35 +02001406 uint64_t start, uint64_t end,
Chunming Zhou6b777602016-09-21 16:19:19 +08001407 uint64_t dst, uint64_t flags)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001408{
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001409 int r;
1410
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001411 /**
1412 * The MC L1 TLB supports variable sized pages, based on a fragment
1413 * field in the PTE. When this field is set to a non-zero value, page
1414 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1415 * flags are considered valid for all PTEs within the fragment range
1416 * and corresponding mappings are assumed to be physically contiguous.
1417 *
1418 * The L1 TLB can store a single PTE for the whole fragment,
1419 * significantly increasing the space available for translation
1420 * caching. This leads to large improvements in throughput when the
1421 * TLB is under pressure.
1422 *
1423 * The L2 TLB distributes small and large fragments into two
1424 * asymmetric partitions. The large fragment cache is significantly
1425 * larger. Thus, we try to use large fragments wherever possible.
1426 * Userspace can support this by aligning virtual base address and
1427 * allocation size to the fragment size.
1428 */
1429
Christian König80366172016-10-04 13:39:43 +02001430 /* SI and newer are optimized for 64KB */
Christian König6be7adb2017-05-23 18:35:22 +02001431 unsigned pages_per_frag = AMDGPU_LOG2_PAGES_PER_FRAG(params->adev);
1432 uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag);
1433 uint64_t frag_align = 1 << pages_per_frag;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001434
Christian König92696dd2016-08-05 13:56:35 +02001435 uint64_t frag_start = ALIGN(start, frag_align);
1436 uint64_t frag_end = end & ~(frag_align - 1);
Christian König31f6c1f2016-01-26 12:37:49 +01001437
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001438 /* system pages are non continuously */
Christian Königb7fc2cb2016-08-11 16:44:15 +02001439 if (params->src || !(flags & AMDGPU_PTE_VALID) ||
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001440 (frag_start >= frag_end))
1441 return amdgpu_vm_update_ptes(params, start, end, dst, flags);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001442
1443 /* handle the 4K area at the beginning */
Christian König92696dd2016-08-05 13:56:35 +02001444 if (start != frag_start) {
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001445 r = amdgpu_vm_update_ptes(params, start, frag_start,
1446 dst, flags);
1447 if (r)
1448 return r;
Christian König92696dd2016-08-05 13:56:35 +02001449 dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001450 }
1451
1452 /* handle the area in the middle */
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001453 r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
1454 flags | frag_flags);
1455 if (r)
1456 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001457
1458 /* handle the 4K area at the end */
Christian König92696dd2016-08-05 13:56:35 +02001459 if (frag_end != end) {
1460 dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001461 r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001462 }
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001463 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001464}
1465
1466/**
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001467 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1468 *
1469 * @adev: amdgpu_device pointer
Christian König3cabaa52016-06-06 10:17:58 +02001470 * @exclusive: fence we need to sync to
Christian Königfa3ab3c2016-03-18 21:00:35 +01001471 * @src: address where to copy page table entries from
1472 * @pages_addr: DMA addresses to use for mapping
Christian Königa14faa62016-01-25 14:27:31 +01001473 * @vm: requested vm
1474 * @start: start of mapped range
1475 * @last: last mapped entry
1476 * @flags: flags for the entries
1477 * @addr: addr to set the area to
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001478 * @fence: optional resulting fence
1479 *
Christian Königa14faa62016-01-25 14:27:31 +01001480 * Fill in the page table entries between @start and @last.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001481 * Returns 0 for success, -EINVAL for failure.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001482 */
1483static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
Chris Wilsonf54d1862016-10-25 13:00:45 +01001484 struct dma_fence *exclusive,
Christian Königfa3ab3c2016-03-18 21:00:35 +01001485 uint64_t src,
1486 dma_addr_t *pages_addr,
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001487 struct amdgpu_vm *vm,
Christian Königa14faa62016-01-25 14:27:31 +01001488 uint64_t start, uint64_t last,
Chunming Zhou6b777602016-09-21 16:19:19 +08001489 uint64_t flags, uint64_t addr,
Chris Wilsonf54d1862016-10-25 13:00:45 +01001490 struct dma_fence **fence)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001491{
Christian König2d55e452016-02-08 17:37:38 +01001492 struct amdgpu_ring *ring;
Christian Königa1e08d32016-01-26 11:40:46 +01001493 void *owner = AMDGPU_FENCE_OWNER_VM;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001494 unsigned nptes, ncmds, ndw;
Christian Königd71518b2016-02-01 12:20:25 +01001495 struct amdgpu_job *job;
Christian König29efc4f2016-08-04 14:52:50 +02001496 struct amdgpu_pte_update_params params;
Chris Wilsonf54d1862016-10-25 13:00:45 +01001497 struct dma_fence *f = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001498 int r;
1499
Christian Königafef8b82016-08-12 13:29:18 +02001500 memset(&params, 0, sizeof(params));
1501 params.adev = adev;
Christian König49ac8a22016-10-13 15:09:08 +02001502 params.vm = vm;
Christian Königafef8b82016-08-12 13:29:18 +02001503 params.src = src;
1504
Christian Königa33cab72017-07-11 17:13:00 +02001505 /* sync to everything on unmapping */
1506 if (!(flags & AMDGPU_PTE_VALID))
1507 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1508
Harish Kasiviswanathanb4d42512017-05-11 19:47:22 -04001509 if (vm->use_cpu_for_update) {
1510 /* params.src is used as flag to indicate system Memory */
1511 if (pages_addr)
1512 params.src = ~0;
1513
1514 /* Wait for PT BOs to be free. PTs share the same resv. object
1515 * as the root PD BO
1516 */
Christian Königa33cab72017-07-11 17:13:00 +02001517 r = amdgpu_vm_wait_pd(adev, vm, owner);
Harish Kasiviswanathanb4d42512017-05-11 19:47:22 -04001518 if (unlikely(r))
1519 return r;
1520
1521 params.func = amdgpu_vm_cpu_set_ptes;
1522 params.pages_addr = pages_addr;
Harish Kasiviswanathanb4d42512017-05-11 19:47:22 -04001523 return amdgpu_vm_frag_ptes(&params, start, last + 1,
1524 addr, flags);
1525 }
1526
Christian König2d55e452016-02-08 17:37:38 +01001527 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
Christian König27c5f362016-08-04 15:02:49 +02001528
Christian Königa14faa62016-01-25 14:27:31 +01001529 nptes = last - start + 1;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001530
1531 /*
1532 * reserve space for one command every (1 << BLOCK_SIZE)
1533 * entries or 2k dwords (whatever is smaller)
1534 */
Zhang, Jerry36b32a62017-03-29 16:08:32 +08001535 ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001536
1537 /* padding, etc. */
1538 ndw = 64;
1539
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001540 /* one PDE write for each huge page */
1541 ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6;
1542
Christian Königb0456f92016-08-11 14:06:54 +02001543 if (src) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001544 /* only copy commands needed */
1545 ndw += ncmds * 7;
1546
Christian Königafef8b82016-08-12 13:29:18 +02001547 params.func = amdgpu_vm_do_copy_ptes;
1548
Christian Königb0456f92016-08-11 14:06:54 +02001549 } else if (pages_addr) {
1550 /* copy commands needed */
1551 ndw += ncmds * 7;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001552
Christian Königb0456f92016-08-11 14:06:54 +02001553 /* and also PTEs */
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001554 ndw += nptes * 2;
1555
Christian Königafef8b82016-08-12 13:29:18 +02001556 params.func = amdgpu_vm_do_copy_ptes;
1557
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001558 } else {
1559 /* set page commands needed */
1560 ndw += ncmds * 10;
1561
1562 /* two extra commands for begin/end of fragment */
1563 ndw += 2 * 10;
Christian Königafef8b82016-08-12 13:29:18 +02001564
1565 params.func = amdgpu_vm_do_set_ptes;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001566 }
1567
Christian Königd71518b2016-02-01 12:20:25 +01001568 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1569 if (r)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001570 return r;
Christian Königd71518b2016-02-01 12:20:25 +01001571
Christian König29efc4f2016-08-04 14:52:50 +02001572 params.ib = &job->ibs[0];
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001573
Christian Königb0456f92016-08-11 14:06:54 +02001574 if (!src && pages_addr) {
1575 uint64_t *pte;
1576 unsigned i;
1577
1578 /* Put the PTEs at the end of the IB. */
1579 i = ndw - nptes * 2;
1580 pte= (uint64_t *)&(job->ibs->ptr[i]);
1581 params.src = job->ibs->gpu_addr + i * 4;
1582
1583 for (i = 0; i < nptes; ++i) {
1584 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1585 AMDGPU_GPU_PAGE_SIZE);
1586 pte[i] |= flags;
1587 }
Christian Königd7a4ac62016-09-25 11:54:00 +02001588 addr = 0;
Christian Königb0456f92016-08-11 14:06:54 +02001589 }
1590
Christian König3cabaa52016-06-06 10:17:58 +02001591 r = amdgpu_sync_fence(adev, &job->sync, exclusive);
1592 if (r)
1593 goto error_free;
1594
Christian König67003a12016-10-12 14:46:26 +02001595 r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
Christian Königa1e08d32016-01-26 11:40:46 +01001596 owner);
1597 if (r)
1598 goto error_free;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001599
Christian König67003a12016-10-12 14:46:26 +02001600 r = reservation_object_reserve_shared(vm->root.bo->tbo.resv);
Christian Königa1e08d32016-01-26 11:40:46 +01001601 if (r)
1602 goto error_free;
1603
Harish Kasiviswanathancc28c4e2017-05-11 22:39:31 -04001604 r = amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags);
1605 if (r)
1606 goto error_free;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001607
Christian König29efc4f2016-08-04 14:52:50 +02001608 amdgpu_ring_pad_ib(ring, params.ib);
1609 WARN_ON(params.ib->length_dw > ndw);
Christian König2bd9ccf2016-02-01 12:53:58 +01001610 r = amdgpu_job_submit(job, ring, &vm->entity,
1611 AMDGPU_FENCE_OWNER_VM, &f);
Chunming Zhou4af9f072015-08-03 12:57:31 +08001612 if (r)
1613 goto error_free;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001614
Christian König67003a12016-10-12 14:46:26 +02001615 amdgpu_bo_fence(vm->root.bo, f, true);
Christian König284710f2017-01-30 11:09:31 +01001616 dma_fence_put(*fence);
1617 *fence = f;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001618 return 0;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001619
1620error_free:
Christian Königd71518b2016-02-01 12:20:25 +01001621 amdgpu_job_free(job);
Alex Deuchercf2f0a32017-07-25 16:35:38 -04001622 amdgpu_vm_invalidate_level(&vm->root);
Chunming Zhou4af9f072015-08-03 12:57:31 +08001623 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001624}
1625
1626/**
Christian Königa14faa62016-01-25 14:27:31 +01001627 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1628 *
1629 * @adev: amdgpu_device pointer
Christian König3cabaa52016-06-06 10:17:58 +02001630 * @exclusive: fence we need to sync to
Christian König8358dce2016-03-30 10:50:25 +02001631 * @gtt_flags: flags as they are used for GTT
1632 * @pages_addr: DMA addresses to use for mapping
Christian Königa14faa62016-01-25 14:27:31 +01001633 * @vm: requested vm
1634 * @mapping: mapped range and flags to use for the update
Christian König8358dce2016-03-30 10:50:25 +02001635 * @flags: HW flags for the mapping
Christian König63e0ba42016-08-16 17:38:37 +02001636 * @nodes: array of drm_mm_nodes with the MC addresses
Christian Königa14faa62016-01-25 14:27:31 +01001637 * @fence: optional resulting fence
1638 *
1639 * Split the mapping into smaller chunks so that each update fits
1640 * into a SDMA IB.
1641 * Returns 0 for success, -EINVAL for failure.
1642 */
1643static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
Chris Wilsonf54d1862016-10-25 13:00:45 +01001644 struct dma_fence *exclusive,
Chunming Zhou6b777602016-09-21 16:19:19 +08001645 uint64_t gtt_flags,
Christian König8358dce2016-03-30 10:50:25 +02001646 dma_addr_t *pages_addr,
Christian Königa14faa62016-01-25 14:27:31 +01001647 struct amdgpu_vm *vm,
1648 struct amdgpu_bo_va_mapping *mapping,
Chunming Zhou6b777602016-09-21 16:19:19 +08001649 uint64_t flags,
Christian König63e0ba42016-08-16 17:38:37 +02001650 struct drm_mm_node *nodes,
Chris Wilsonf54d1862016-10-25 13:00:45 +01001651 struct dma_fence **fence)
Christian Königa14faa62016-01-25 14:27:31 +01001652{
Christian Königa9f87f62017-03-30 14:03:59 +02001653 uint64_t pfn, src = 0, start = mapping->start;
Christian Königa14faa62016-01-25 14:27:31 +01001654 int r;
1655
1656 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1657 * but in case of something, we filter the flags in first place
1658 */
1659 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1660 flags &= ~AMDGPU_PTE_READABLE;
1661 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1662 flags &= ~AMDGPU_PTE_WRITEABLE;
1663
Alex Xie15b31c52017-03-03 16:47:11 -05001664 flags &= ~AMDGPU_PTE_EXECUTABLE;
1665 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1666
Alex Xieb0fd18b2017-03-03 16:49:39 -05001667 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1668 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1669
Zhang, Jerryd0766e92017-04-19 09:53:29 +08001670 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1671 (adev->asic_type >= CHIP_VEGA10)) {
1672 flags |= AMDGPU_PTE_PRT;
1673 flags &= ~AMDGPU_PTE_VALID;
1674 }
1675
Christian Königa14faa62016-01-25 14:27:31 +01001676 trace_amdgpu_vm_bo_update(mapping);
1677
Christian König63e0ba42016-08-16 17:38:37 +02001678 pfn = mapping->offset >> PAGE_SHIFT;
1679 if (nodes) {
1680 while (pfn >= nodes->size) {
1681 pfn -= nodes->size;
1682 ++nodes;
1683 }
Christian Königfa3ab3c2016-03-18 21:00:35 +01001684 }
Christian Königa14faa62016-01-25 14:27:31 +01001685
Christian König63e0ba42016-08-16 17:38:37 +02001686 do {
1687 uint64_t max_entries;
1688 uint64_t addr, last;
Christian Königa14faa62016-01-25 14:27:31 +01001689
Christian König63e0ba42016-08-16 17:38:37 +02001690 if (nodes) {
1691 addr = nodes->start << PAGE_SHIFT;
1692 max_entries = (nodes->size - pfn) *
1693 (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1694 } else {
1695 addr = 0;
1696 max_entries = S64_MAX;
1697 }
Christian Königa14faa62016-01-25 14:27:31 +01001698
Christian König63e0ba42016-08-16 17:38:37 +02001699 if (pages_addr) {
1700 if (flags == gtt_flags)
1701 src = adev->gart.table_addr +
1702 (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
1703 else
1704 max_entries = min(max_entries, 16ull * 1024ull);
1705 addr = 0;
1706 } else if (flags & AMDGPU_PTE_VALID) {
1707 addr += adev->vm_manager.vram_base_offset;
1708 }
1709 addr += pfn << PAGE_SHIFT;
1710
Christian Königa9f87f62017-03-30 14:03:59 +02001711 last = min((uint64_t)mapping->last, start + max_entries - 1);
Christian König3cabaa52016-06-06 10:17:58 +02001712 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1713 src, pages_addr, vm,
Christian Königa14faa62016-01-25 14:27:31 +01001714 start, last, flags, addr,
1715 fence);
1716 if (r)
1717 return r;
1718
Christian König63e0ba42016-08-16 17:38:37 +02001719 pfn += last - start + 1;
1720 if (nodes && nodes->size == pfn) {
1721 pfn = 0;
1722 ++nodes;
1723 }
Christian Königa14faa62016-01-25 14:27:31 +01001724 start = last + 1;
Christian König63e0ba42016-08-16 17:38:37 +02001725
Christian Königa9f87f62017-03-30 14:03:59 +02001726 } while (unlikely(start != mapping->last + 1));
Christian Königa14faa62016-01-25 14:27:31 +01001727
1728 return 0;
1729}
1730
1731/**
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001732 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1733 *
1734 * @adev: amdgpu_device pointer
1735 * @bo_va: requested BO and VM object
Christian König99e124f2016-08-16 14:43:17 +02001736 * @clear: if true clear the entries
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001737 *
1738 * Fill in the page table entries for @bo_va.
1739 * Returns 0 for success, -EINVAL for failure.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001740 */
1741int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1742 struct amdgpu_bo_va *bo_va,
Christian König99e124f2016-08-16 14:43:17 +02001743 bool clear)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001744{
1745 struct amdgpu_vm *vm = bo_va->vm;
1746 struct amdgpu_bo_va_mapping *mapping;
Christian König8358dce2016-03-30 10:50:25 +02001747 dma_addr_t *pages_addr = NULL;
Chunming Zhou6b777602016-09-21 16:19:19 +08001748 uint64_t gtt_flags, flags;
Christian König99e124f2016-08-16 14:43:17 +02001749 struct ttm_mem_reg *mem;
Christian König63e0ba42016-08-16 17:38:37 +02001750 struct drm_mm_node *nodes;
Chris Wilsonf54d1862016-10-25 13:00:45 +01001751 struct dma_fence *exclusive;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001752 int r;
1753
Christian Königa5f6b5b2017-01-30 11:01:38 +01001754 if (clear || !bo_va->bo) {
Christian König99e124f2016-08-16 14:43:17 +02001755 mem = NULL;
Christian König63e0ba42016-08-16 17:38:37 +02001756 nodes = NULL;
Christian König99e124f2016-08-16 14:43:17 +02001757 exclusive = NULL;
1758 } else {
Christian König8358dce2016-03-30 10:50:25 +02001759 struct ttm_dma_tt *ttm;
1760
Christian König99e124f2016-08-16 14:43:17 +02001761 mem = &bo_va->bo->tbo.mem;
Christian König63e0ba42016-08-16 17:38:37 +02001762 nodes = mem->mm_node;
1763 if (mem->mem_type == TTM_PL_TT) {
Christian König8358dce2016-03-30 10:50:25 +02001764 ttm = container_of(bo_va->bo->tbo.ttm, struct
1765 ttm_dma_tt, ttm);
1766 pages_addr = ttm->dma_address;
Christian König9ab21462015-11-30 14:19:26 +01001767 }
Christian König3cabaa52016-06-06 10:17:58 +02001768 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001769 }
1770
Christian Königa5f6b5b2017-01-30 11:01:38 +01001771 if (bo_va->bo) {
1772 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1773 gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
1774 adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
1775 flags : 0;
1776 } else {
1777 flags = 0x0;
1778 gtt_flags = ~0x0;
1779 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001780
Christian König7fc11952015-07-30 11:53:42 +02001781 spin_lock(&vm->status_lock);
1782 if (!list_empty(&bo_va->vm_status))
1783 list_splice_init(&bo_va->valids, &bo_va->invalids);
1784 spin_unlock(&vm->status_lock);
1785
1786 list_for_each_entry(mapping, &bo_va->invalids, list) {
Christian König3cabaa52016-06-06 10:17:58 +02001787 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1788 gtt_flags, pages_addr, vm,
Christian König63e0ba42016-08-16 17:38:37 +02001789 mapping, flags, nodes,
Christian König8358dce2016-03-30 10:50:25 +02001790 &bo_va->last_pt_update);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001791 if (r)
1792 return r;
1793 }
1794
Christian Königd6c10f62015-09-28 12:00:23 +02001795 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1796 list_for_each_entry(mapping, &bo_va->valids, list)
1797 trace_amdgpu_vm_bo_mapping(mapping);
1798
1799 list_for_each_entry(mapping, &bo_va->invalids, list)
1800 trace_amdgpu_vm_bo_mapping(mapping);
1801 }
1802
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001803 spin_lock(&vm->status_lock);
monk.liu6d1d0ef2015-08-14 13:36:41 +08001804 list_splice_init(&bo_va->invalids, &bo_va->valids);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001805 list_del_init(&bo_va->vm_status);
Christian König99e124f2016-08-16 14:43:17 +02001806 if (clear)
Christian König7fc11952015-07-30 11:53:42 +02001807 list_add(&bo_va->vm_status, &vm->cleared);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001808 spin_unlock(&vm->status_lock);
1809
Christian König68c62302017-07-11 17:23:29 +02001810 if (vm->use_cpu_for_update) {
1811 /* Flush HDP */
1812 mb();
1813 amdgpu_gart_flush_gpu_tlb(adev, 0);
1814 }
1815
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001816 return 0;
1817}
1818
1819/**
Christian König284710f2017-01-30 11:09:31 +01001820 * amdgpu_vm_update_prt_state - update the global PRT state
1821 */
1822static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1823{
1824 unsigned long flags;
1825 bool enable;
1826
1827 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
Christian König451bc8e2017-02-14 16:02:52 +01001828 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
Christian König284710f2017-01-30 11:09:31 +01001829 adev->gart.gart_funcs->set_prt(adev, enable);
1830 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1831}
1832
1833/**
Christian König4388fc22017-03-13 10:13:36 +01001834 * amdgpu_vm_prt_get - add a PRT user
Christian König451bc8e2017-02-14 16:02:52 +01001835 */
1836static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1837{
Christian König4388fc22017-03-13 10:13:36 +01001838 if (!adev->gart.gart_funcs->set_prt)
1839 return;
1840
Christian König451bc8e2017-02-14 16:02:52 +01001841 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1842 amdgpu_vm_update_prt_state(adev);
1843}
1844
1845/**
Christian König0b15f2f2017-02-14 15:47:03 +01001846 * amdgpu_vm_prt_put - drop a PRT user
1847 */
1848static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1849{
Christian König451bc8e2017-02-14 16:02:52 +01001850 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
Christian König0b15f2f2017-02-14 15:47:03 +01001851 amdgpu_vm_update_prt_state(adev);
1852}
1853
1854/**
Christian König451bc8e2017-02-14 16:02:52 +01001855 * amdgpu_vm_prt_cb - callback for updating the PRT status
Christian König284710f2017-01-30 11:09:31 +01001856 */
1857static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1858{
1859 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1860
Christian König0b15f2f2017-02-14 15:47:03 +01001861 amdgpu_vm_prt_put(cb->adev);
Christian König284710f2017-01-30 11:09:31 +01001862 kfree(cb);
1863}
1864
1865/**
Christian König451bc8e2017-02-14 16:02:52 +01001866 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1867 */
1868static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1869 struct dma_fence *fence)
1870{
Christian König4388fc22017-03-13 10:13:36 +01001871 struct amdgpu_prt_cb *cb;
Christian König451bc8e2017-02-14 16:02:52 +01001872
Christian König4388fc22017-03-13 10:13:36 +01001873 if (!adev->gart.gart_funcs->set_prt)
1874 return;
1875
1876 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
Christian König451bc8e2017-02-14 16:02:52 +01001877 if (!cb) {
1878 /* Last resort when we are OOM */
1879 if (fence)
1880 dma_fence_wait(fence, false);
1881
Dan Carpenter486a68f2017-04-03 21:41:39 +03001882 amdgpu_vm_prt_put(adev);
Christian König451bc8e2017-02-14 16:02:52 +01001883 } else {
1884 cb->adev = adev;
1885 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1886 amdgpu_vm_prt_cb))
1887 amdgpu_vm_prt_cb(fence, &cb->cb);
1888 }
1889}
1890
1891/**
Christian König284710f2017-01-30 11:09:31 +01001892 * amdgpu_vm_free_mapping - free a mapping
1893 *
1894 * @adev: amdgpu_device pointer
1895 * @vm: requested vm
1896 * @mapping: mapping to be freed
1897 * @fence: fence of the unmap operation
1898 *
1899 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1900 */
1901static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1902 struct amdgpu_vm *vm,
1903 struct amdgpu_bo_va_mapping *mapping,
1904 struct dma_fence *fence)
1905{
Christian König451bc8e2017-02-14 16:02:52 +01001906 if (mapping->flags & AMDGPU_PTE_PRT)
1907 amdgpu_vm_add_prt_cb(adev, fence);
Christian König284710f2017-01-30 11:09:31 +01001908 kfree(mapping);
1909}
1910
1911/**
Christian König451bc8e2017-02-14 16:02:52 +01001912 * amdgpu_vm_prt_fini - finish all prt mappings
1913 *
1914 * @adev: amdgpu_device pointer
1915 * @vm: requested vm
1916 *
1917 * Register a cleanup callback to disable PRT support after VM dies.
1918 */
1919static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1920{
Christian König67003a12016-10-12 14:46:26 +02001921 struct reservation_object *resv = vm->root.bo->tbo.resv;
Christian König451bc8e2017-02-14 16:02:52 +01001922 struct dma_fence *excl, **shared;
1923 unsigned i, shared_count;
1924 int r;
1925
1926 r = reservation_object_get_fences_rcu(resv, &excl,
1927 &shared_count, &shared);
1928 if (r) {
1929 /* Not enough memory to grab the fence list, as last resort
1930 * block for all the fences to complete.
1931 */
1932 reservation_object_wait_timeout_rcu(resv, true, false,
1933 MAX_SCHEDULE_TIMEOUT);
1934 return;
1935 }
1936
1937 /* Add a callback for each fence in the reservation object */
1938 amdgpu_vm_prt_get(adev);
1939 amdgpu_vm_add_prt_cb(adev, excl);
1940
1941 for (i = 0; i < shared_count; ++i) {
1942 amdgpu_vm_prt_get(adev);
1943 amdgpu_vm_add_prt_cb(adev, shared[i]);
1944 }
1945
1946 kfree(shared);
1947}
1948
1949/**
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001950 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1951 *
1952 * @adev: amdgpu_device pointer
1953 * @vm: requested vm
Nicolai Hähnlef3467812017-03-23 19:36:31 +01001954 * @fence: optional resulting fence (unchanged if no work needed to be done
1955 * or if an error occurred)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001956 *
1957 * Make sure all freed BOs are cleared in the PT.
1958 * Returns 0 for success.
1959 *
1960 * PTs have to be reserved and mutex must be locked!
1961 */
1962int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
Nicolai Hähnlef3467812017-03-23 19:36:31 +01001963 struct amdgpu_vm *vm,
1964 struct dma_fence **fence)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001965{
1966 struct amdgpu_bo_va_mapping *mapping;
Nicolai Hähnlef3467812017-03-23 19:36:31 +01001967 struct dma_fence *f = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001968 int r;
Yong Zhao51ac7ee2017-07-27 12:48:22 -04001969 uint64_t init_pte_value = 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001970
1971 while (!list_empty(&vm->freed)) {
1972 mapping = list_first_entry(&vm->freed,
1973 struct amdgpu_bo_va_mapping, list);
1974 list_del(&mapping->list);
Christian Könige17841b2016-03-08 17:52:01 +01001975
Yong Zhao51ac7ee2017-07-27 12:48:22 -04001976 if (vm->pte_support_ats)
1977 init_pte_value = AMDGPU_PTE_SYSTEM;
1978
Christian Königfc6aa332017-04-19 14:41:19 +02001979 r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm,
1980 mapping->start, mapping->last,
Yong Zhao51ac7ee2017-07-27 12:48:22 -04001981 init_pte_value, 0, &f);
Nicolai Hähnlef3467812017-03-23 19:36:31 +01001982 amdgpu_vm_free_mapping(adev, vm, mapping, f);
Christian König284710f2017-01-30 11:09:31 +01001983 if (r) {
Nicolai Hähnlef3467812017-03-23 19:36:31 +01001984 dma_fence_put(f);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001985 return r;
Christian König284710f2017-01-30 11:09:31 +01001986 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001987 }
Nicolai Hähnlef3467812017-03-23 19:36:31 +01001988
1989 if (fence && f) {
1990 dma_fence_put(*fence);
1991 *fence = f;
1992 } else {
1993 dma_fence_put(f);
1994 }
1995
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001996 return 0;
1997
1998}
1999
2000/**
2001 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
2002 *
2003 * @adev: amdgpu_device pointer
2004 * @vm: requested vm
2005 *
2006 * Make sure all invalidated BOs are cleared in the PT.
2007 * Returns 0 for success.
2008 *
2009 * PTs have to be reserved and mutex must be locked!
2010 */
2011int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
monk.liucfe2c972015-05-26 15:01:54 +08002012 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002013{
monk.liucfe2c972015-05-26 15:01:54 +08002014 struct amdgpu_bo_va *bo_va = NULL;
Christian König91e1a522015-07-06 22:06:40 +02002015 int r = 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002016
2017 spin_lock(&vm->status_lock);
2018 while (!list_empty(&vm->invalidated)) {
2019 bo_va = list_first_entry(&vm->invalidated,
2020 struct amdgpu_bo_va, vm_status);
2021 spin_unlock(&vm->status_lock);
Christian König32b41ac2016-03-08 18:03:27 +01002022
Christian König99e124f2016-08-16 14:43:17 +02002023 r = amdgpu_vm_bo_update(adev, bo_va, true);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002024 if (r)
2025 return r;
2026
2027 spin_lock(&vm->status_lock);
2028 }
2029 spin_unlock(&vm->status_lock);
2030
monk.liucfe2c972015-05-26 15:01:54 +08002031 if (bo_va)
Chunming Zhoubb1e38a42015-08-03 18:19:38 +08002032 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
Christian König91e1a522015-07-06 22:06:40 +02002033
2034 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002035}
2036
2037/**
2038 * amdgpu_vm_bo_add - add a bo to a specific vm
2039 *
2040 * @adev: amdgpu_device pointer
2041 * @vm: requested vm
2042 * @bo: amdgpu buffer object
2043 *
Christian König8843dbb2016-01-26 12:17:11 +01002044 * Add @bo into the requested vm.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002045 * Add @bo to the list of bos associated with the vm
2046 * Returns newly added bo_va or NULL for failure
2047 *
2048 * Object has to be reserved!
2049 */
2050struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2051 struct amdgpu_vm *vm,
2052 struct amdgpu_bo *bo)
2053{
2054 struct amdgpu_bo_va *bo_va;
2055
2056 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2057 if (bo_va == NULL) {
2058 return NULL;
2059 }
2060 bo_va->vm = vm;
2061 bo_va->bo = bo;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002062 bo_va->ref_count = 1;
2063 INIT_LIST_HEAD(&bo_va->bo_list);
Christian König7fc11952015-07-30 11:53:42 +02002064 INIT_LIST_HEAD(&bo_va->valids);
2065 INIT_LIST_HEAD(&bo_va->invalids);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002066 INIT_LIST_HEAD(&bo_va->vm_status);
Christian König32b41ac2016-03-08 18:03:27 +01002067
Christian Königa5f6b5b2017-01-30 11:01:38 +01002068 if (bo)
2069 list_add_tail(&bo_va->bo_list, &bo->va);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002070
2071 return bo_va;
2072}
2073
2074/**
2075 * amdgpu_vm_bo_map - map bo inside a vm
2076 *
2077 * @adev: amdgpu_device pointer
2078 * @bo_va: bo_va to store the address
2079 * @saddr: where to map the BO
2080 * @offset: requested offset in the BO
2081 * @flags: attributes of pages (read/write/valid/etc.)
2082 *
2083 * Add a mapping of the BO at the specefied addr into the VM.
2084 * Returns 0 for success, error for failure.
2085 *
Chunming Zhou49b02b12015-11-13 14:18:38 +08002086 * Object has to be reserved and unreserved outside!
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002087 */
2088int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2089 struct amdgpu_bo_va *bo_va,
2090 uint64_t saddr, uint64_t offset,
Christian König268c3002017-01-18 14:49:43 +01002091 uint64_t size, uint64_t flags)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002092{
Christian Königa9f87f62017-03-30 14:03:59 +02002093 struct amdgpu_bo_va_mapping *mapping, *tmp;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002094 struct amdgpu_vm *vm = bo_va->vm;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002095 uint64_t eaddr;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002096
Christian König0be52de2015-05-18 14:37:27 +02002097 /* validate the parameters */
2098 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
Chunming Zhou49b02b12015-11-13 14:18:38 +08002099 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
Christian König0be52de2015-05-18 14:37:27 +02002100 return -EINVAL;
Christian König0be52de2015-05-18 14:37:27 +02002101
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002102 /* make sure object fit at this offset */
Felix Kuehling005ae952015-11-23 17:43:48 -05002103 eaddr = saddr + size - 1;
Christian Königa5f6b5b2017-01-30 11:01:38 +01002104 if (saddr >= eaddr ||
2105 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002106 return -EINVAL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002107
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002108 saddr /= AMDGPU_GPU_PAGE_SIZE;
2109 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2110
Christian Königa9f87f62017-03-30 14:03:59 +02002111 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2112 if (tmp) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002113 /* bo and tmp overlap, invalid addr */
2114 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
Christian Königa9f87f62017-03-30 14:03:59 +02002115 "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr,
2116 tmp->start, tmp->last + 1);
Christian König663e4572017-03-13 10:13:37 +01002117 return -EINVAL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002118 }
2119
2120 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
Christian König663e4572017-03-13 10:13:37 +01002121 if (!mapping)
2122 return -ENOMEM;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002123
2124 INIT_LIST_HEAD(&mapping->list);
Christian Königa9f87f62017-03-30 14:03:59 +02002125 mapping->start = saddr;
2126 mapping->last = eaddr;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002127 mapping->offset = offset;
2128 mapping->flags = flags;
2129
Christian König7fc11952015-07-30 11:53:42 +02002130 list_add(&mapping->list, &bo_va->invalids);
Christian Königa9f87f62017-03-30 14:03:59 +02002131 amdgpu_vm_it_insert(mapping, &vm->va);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002132
Christian König4388fc22017-03-13 10:13:36 +01002133 if (flags & AMDGPU_PTE_PRT)
2134 amdgpu_vm_prt_get(adev);
2135
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002136 return 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002137}
2138
2139/**
Christian König80f95c52017-03-13 10:13:39 +01002140 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2141 *
2142 * @adev: amdgpu_device pointer
2143 * @bo_va: bo_va to store the address
2144 * @saddr: where to map the BO
2145 * @offset: requested offset in the BO
2146 * @flags: attributes of pages (read/write/valid/etc.)
2147 *
2148 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2149 * mappings as we do so.
2150 * Returns 0 for success, error for failure.
2151 *
2152 * Object has to be reserved and unreserved outside!
2153 */
2154int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2155 struct amdgpu_bo_va *bo_va,
2156 uint64_t saddr, uint64_t offset,
2157 uint64_t size, uint64_t flags)
2158{
2159 struct amdgpu_bo_va_mapping *mapping;
2160 struct amdgpu_vm *vm = bo_va->vm;
2161 uint64_t eaddr;
2162 int r;
2163
2164 /* validate the parameters */
2165 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2166 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2167 return -EINVAL;
2168
2169 /* make sure object fit at this offset */
2170 eaddr = saddr + size - 1;
2171 if (saddr >= eaddr ||
2172 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
2173 return -EINVAL;
2174
2175 /* Allocate all the needed memory */
2176 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2177 if (!mapping)
2178 return -ENOMEM;
2179
2180 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size);
2181 if (r) {
2182 kfree(mapping);
2183 return r;
2184 }
2185
2186 saddr /= AMDGPU_GPU_PAGE_SIZE;
2187 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2188
Christian Königa9f87f62017-03-30 14:03:59 +02002189 mapping->start = saddr;
2190 mapping->last = eaddr;
Christian König80f95c52017-03-13 10:13:39 +01002191 mapping->offset = offset;
2192 mapping->flags = flags;
2193
2194 list_add(&mapping->list, &bo_va->invalids);
Christian Königa9f87f62017-03-30 14:03:59 +02002195 amdgpu_vm_it_insert(mapping, &vm->va);
Christian König80f95c52017-03-13 10:13:39 +01002196
2197 if (flags & AMDGPU_PTE_PRT)
2198 amdgpu_vm_prt_get(adev);
2199
2200 return 0;
2201}
2202
2203/**
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002204 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2205 *
2206 * @adev: amdgpu_device pointer
2207 * @bo_va: bo_va to remove the address from
2208 * @saddr: where to the BO is mapped
2209 *
2210 * Remove a mapping of the BO at the specefied addr from the VM.
2211 * Returns 0 for success, error for failure.
2212 *
Chunming Zhou49b02b12015-11-13 14:18:38 +08002213 * Object has to be reserved and unreserved outside!
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002214 */
2215int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2216 struct amdgpu_bo_va *bo_va,
2217 uint64_t saddr)
2218{
2219 struct amdgpu_bo_va_mapping *mapping;
2220 struct amdgpu_vm *vm = bo_va->vm;
Christian König7fc11952015-07-30 11:53:42 +02002221 bool valid = true;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002222
Christian König6c7fc502015-06-05 20:56:17 +02002223 saddr /= AMDGPU_GPU_PAGE_SIZE;
Christian König32b41ac2016-03-08 18:03:27 +01002224
Christian König7fc11952015-07-30 11:53:42 +02002225 list_for_each_entry(mapping, &bo_va->valids, list) {
Christian Königa9f87f62017-03-30 14:03:59 +02002226 if (mapping->start == saddr)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002227 break;
2228 }
2229
Christian König7fc11952015-07-30 11:53:42 +02002230 if (&mapping->list == &bo_va->valids) {
2231 valid = false;
2232
2233 list_for_each_entry(mapping, &bo_va->invalids, list) {
Christian Königa9f87f62017-03-30 14:03:59 +02002234 if (mapping->start == saddr)
Christian König7fc11952015-07-30 11:53:42 +02002235 break;
2236 }
2237
Christian König32b41ac2016-03-08 18:03:27 +01002238 if (&mapping->list == &bo_va->invalids)
Christian König7fc11952015-07-30 11:53:42 +02002239 return -ENOENT;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002240 }
Christian König32b41ac2016-03-08 18:03:27 +01002241
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002242 list_del(&mapping->list);
Christian Königa9f87f62017-03-30 14:03:59 +02002243 amdgpu_vm_it_remove(mapping, &vm->va);
Christian König93e3e432015-06-09 16:58:33 +02002244 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002245
Christian Könige17841b2016-03-08 17:52:01 +01002246 if (valid)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002247 list_add(&mapping->list, &vm->freed);
Christian Könige17841b2016-03-08 17:52:01 +01002248 else
Christian König284710f2017-01-30 11:09:31 +01002249 amdgpu_vm_free_mapping(adev, vm, mapping,
2250 bo_va->last_pt_update);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002251
2252 return 0;
2253}
2254
2255/**
Christian Königdc54d3d2017-03-13 10:13:38 +01002256 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2257 *
2258 * @adev: amdgpu_device pointer
2259 * @vm: VM structure to use
2260 * @saddr: start of the range
2261 * @size: size of the range
2262 *
2263 * Remove all mappings in a range, split them as appropriate.
2264 * Returns 0 for success, error for failure.
2265 */
2266int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2267 struct amdgpu_vm *vm,
2268 uint64_t saddr, uint64_t size)
2269{
2270 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
Christian Königdc54d3d2017-03-13 10:13:38 +01002271 LIST_HEAD(removed);
2272 uint64_t eaddr;
2273
2274 eaddr = saddr + size - 1;
2275 saddr /= AMDGPU_GPU_PAGE_SIZE;
2276 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2277
2278 /* Allocate all the needed memory */
2279 before = kzalloc(sizeof(*before), GFP_KERNEL);
2280 if (!before)
2281 return -ENOMEM;
Junwei Zhang27f6d612017-03-16 16:09:24 +08002282 INIT_LIST_HEAD(&before->list);
Christian Königdc54d3d2017-03-13 10:13:38 +01002283
2284 after = kzalloc(sizeof(*after), GFP_KERNEL);
2285 if (!after) {
2286 kfree(before);
2287 return -ENOMEM;
2288 }
Junwei Zhang27f6d612017-03-16 16:09:24 +08002289 INIT_LIST_HEAD(&after->list);
Christian Königdc54d3d2017-03-13 10:13:38 +01002290
2291 /* Now gather all removed mappings */
Christian Königa9f87f62017-03-30 14:03:59 +02002292 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2293 while (tmp) {
Christian Königdc54d3d2017-03-13 10:13:38 +01002294 /* Remember mapping split at the start */
Christian Königa9f87f62017-03-30 14:03:59 +02002295 if (tmp->start < saddr) {
2296 before->start = tmp->start;
2297 before->last = saddr - 1;
Christian Königdc54d3d2017-03-13 10:13:38 +01002298 before->offset = tmp->offset;
2299 before->flags = tmp->flags;
2300 list_add(&before->list, &tmp->list);
2301 }
2302
2303 /* Remember mapping split at the end */
Christian Königa9f87f62017-03-30 14:03:59 +02002304 if (tmp->last > eaddr) {
2305 after->start = eaddr + 1;
2306 after->last = tmp->last;
Christian Königdc54d3d2017-03-13 10:13:38 +01002307 after->offset = tmp->offset;
Christian Königa9f87f62017-03-30 14:03:59 +02002308 after->offset += after->start - tmp->start;
Christian Königdc54d3d2017-03-13 10:13:38 +01002309 after->flags = tmp->flags;
2310 list_add(&after->list, &tmp->list);
2311 }
2312
2313 list_del(&tmp->list);
2314 list_add(&tmp->list, &removed);
Christian Königa9f87f62017-03-30 14:03:59 +02002315
2316 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
Christian Königdc54d3d2017-03-13 10:13:38 +01002317 }
2318
2319 /* And free them up */
2320 list_for_each_entry_safe(tmp, next, &removed, list) {
Christian Königa9f87f62017-03-30 14:03:59 +02002321 amdgpu_vm_it_remove(tmp, &vm->va);
Christian Königdc54d3d2017-03-13 10:13:38 +01002322 list_del(&tmp->list);
2323
Christian Königa9f87f62017-03-30 14:03:59 +02002324 if (tmp->start < saddr)
2325 tmp->start = saddr;
2326 if (tmp->last > eaddr)
2327 tmp->last = eaddr;
Christian Königdc54d3d2017-03-13 10:13:38 +01002328
2329 list_add(&tmp->list, &vm->freed);
2330 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2331 }
2332
Junwei Zhang27f6d612017-03-16 16:09:24 +08002333 /* Insert partial mapping before the range */
2334 if (!list_empty(&before->list)) {
Christian Königa9f87f62017-03-30 14:03:59 +02002335 amdgpu_vm_it_insert(before, &vm->va);
Christian Königdc54d3d2017-03-13 10:13:38 +01002336 if (before->flags & AMDGPU_PTE_PRT)
2337 amdgpu_vm_prt_get(adev);
2338 } else {
2339 kfree(before);
2340 }
2341
2342 /* Insert partial mapping after the range */
Junwei Zhang27f6d612017-03-16 16:09:24 +08002343 if (!list_empty(&after->list)) {
Christian Königa9f87f62017-03-30 14:03:59 +02002344 amdgpu_vm_it_insert(after, &vm->va);
Christian Königdc54d3d2017-03-13 10:13:38 +01002345 if (after->flags & AMDGPU_PTE_PRT)
2346 amdgpu_vm_prt_get(adev);
2347 } else {
2348 kfree(after);
2349 }
2350
2351 return 0;
2352}
2353
2354/**
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002355 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2356 *
2357 * @adev: amdgpu_device pointer
2358 * @bo_va: requested bo_va
2359 *
Christian König8843dbb2016-01-26 12:17:11 +01002360 * Remove @bo_va->bo from the requested vm.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002361 *
2362 * Object have to be reserved!
2363 */
2364void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2365 struct amdgpu_bo_va *bo_va)
2366{
2367 struct amdgpu_bo_va_mapping *mapping, *next;
2368 struct amdgpu_vm *vm = bo_va->vm;
2369
2370 list_del(&bo_va->bo_list);
2371
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002372 spin_lock(&vm->status_lock);
2373 list_del(&bo_va->vm_status);
2374 spin_unlock(&vm->status_lock);
2375
Christian König7fc11952015-07-30 11:53:42 +02002376 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002377 list_del(&mapping->list);
Christian Königa9f87f62017-03-30 14:03:59 +02002378 amdgpu_vm_it_remove(mapping, &vm->va);
Christian König93e3e432015-06-09 16:58:33 +02002379 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
Christian König7fc11952015-07-30 11:53:42 +02002380 list_add(&mapping->list, &vm->freed);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002381 }
Christian König7fc11952015-07-30 11:53:42 +02002382 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2383 list_del(&mapping->list);
Christian Königa9f87f62017-03-30 14:03:59 +02002384 amdgpu_vm_it_remove(mapping, &vm->va);
Christian König284710f2017-01-30 11:09:31 +01002385 amdgpu_vm_free_mapping(adev, vm, mapping,
2386 bo_va->last_pt_update);
Christian König7fc11952015-07-30 11:53:42 +02002387 }
Christian König32b41ac2016-03-08 18:03:27 +01002388
Chris Wilsonf54d1862016-10-25 13:00:45 +01002389 dma_fence_put(bo_va->last_pt_update);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002390 kfree(bo_va);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002391}
2392
2393/**
2394 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2395 *
2396 * @adev: amdgpu_device pointer
2397 * @vm: requested vm
2398 * @bo: amdgpu buffer object
2399 *
Christian König8843dbb2016-01-26 12:17:11 +01002400 * Mark @bo as invalid.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002401 */
2402void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2403 struct amdgpu_bo *bo)
2404{
2405 struct amdgpu_bo_va *bo_va;
2406
2407 list_for_each_entry(bo_va, &bo->va, bo_list) {
Christian König7fc11952015-07-30 11:53:42 +02002408 spin_lock(&bo_va->vm->status_lock);
2409 if (list_empty(&bo_va->vm_status))
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002410 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
Christian König7fc11952015-07-30 11:53:42 +02002411 spin_unlock(&bo_va->vm->status_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002412 }
2413}
2414
Junwei Zhangbab4fee2017-04-05 13:54:56 +08002415static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2416{
2417 /* Total bits covered by PD + PTs */
2418 unsigned bits = ilog2(vm_size) + 18;
2419
2420 /* Make sure the PD is 4K in size up to 8GB address space.
2421 Above that split equal between PD and PTs */
2422 if (vm_size <= 8)
2423 return (bits - 9);
2424 else
2425 return ((bits + 3) / 2);
2426}
2427
2428/**
2429 * amdgpu_vm_adjust_size - adjust vm size and block size
2430 *
2431 * @adev: amdgpu_device pointer
2432 * @vm_size: the default vm size if it's set auto
2433 */
2434void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size)
2435{
2436 /* adjust vm size firstly */
2437 if (amdgpu_vm_size == -1)
2438 adev->vm_manager.vm_size = vm_size;
2439 else
2440 adev->vm_manager.vm_size = amdgpu_vm_size;
2441
2442 /* block size depends on vm size */
2443 if (amdgpu_vm_block_size == -1)
2444 adev->vm_manager.block_size =
2445 amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
2446 else
2447 adev->vm_manager.block_size = amdgpu_vm_block_size;
2448
2449 DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
2450 adev->vm_manager.vm_size, adev->vm_manager.block_size);
2451}
2452
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002453/**
2454 * amdgpu_vm_init - initialize a vm instance
2455 *
2456 * @adev: amdgpu_device pointer
2457 * @vm: requested vm
Harish Kasiviswanathan9a4b7d42017-06-09 11:26:57 -04002458 * @vm_context: Indicates if it GFX or Compute context
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002459 *
Christian König8843dbb2016-01-26 12:17:11 +01002460 * Init @vm fields.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002461 */
Harish Kasiviswanathan9a4b7d42017-06-09 11:26:57 -04002462int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2463 int vm_context)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002464{
2465 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
Zhang, Jerry36b32a62017-03-29 16:08:32 +08002466 AMDGPU_VM_PTE_COUNT(adev) * 8);
Christian König2d55e452016-02-08 17:37:38 +01002467 unsigned ring_instance;
2468 struct amdgpu_ring *ring;
Christian König2bd9ccf2016-02-01 12:53:58 +01002469 struct amd_sched_rq *rq;
Chunming Zhou36bbf3b2017-04-20 16:17:34 +08002470 int r, i;
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04002471 u64 flags;
Yong Zhao51ac7ee2017-07-27 12:48:22 -04002472 uint64_t init_pde_value = 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002473
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002474 vm->va = RB_ROOT;
Chunming Zhou031e2982016-04-25 10:19:13 +08002475 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
Chunming Zhou36bbf3b2017-04-20 16:17:34 +08002476 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2477 vm->reserved_vmid[i] = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002478 spin_lock_init(&vm->status_lock);
2479 INIT_LIST_HEAD(&vm->invalidated);
Christian König7fc11952015-07-30 11:53:42 +02002480 INIT_LIST_HEAD(&vm->cleared);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002481 INIT_LIST_HEAD(&vm->freed);
Christian König20250212016-03-08 17:58:35 +01002482
Christian König2bd9ccf2016-02-01 12:53:58 +01002483 /* create scheduler entity for page table updates */
Christian König2d55e452016-02-08 17:37:38 +01002484
2485 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
2486 ring_instance %= adev->vm_manager.vm_pte_num_rings;
2487 ring = adev->vm_manager.vm_pte_rings[ring_instance];
Christian König2bd9ccf2016-02-01 12:53:58 +01002488 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
2489 r = amd_sched_entity_init(&ring->sched, &vm->entity,
2490 rq, amdgpu_sched_jobs);
2491 if (r)
Christian Königf566ceb2016-10-27 20:04:38 +02002492 return r;
Christian König2bd9ccf2016-02-01 12:53:58 +01002493
Yong Zhao51ac7ee2017-07-27 12:48:22 -04002494 vm->pte_support_ats = false;
2495
2496 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
Harish Kasiviswanathan9a4b7d42017-06-09 11:26:57 -04002497 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2498 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
Yong Zhao51ac7ee2017-07-27 12:48:22 -04002499
2500 if (adev->asic_type == CHIP_RAVEN) {
2501 vm->pte_support_ats = true;
2502 init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE;
2503 }
2504 } else
Harish Kasiviswanathan9a4b7d42017-06-09 11:26:57 -04002505 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2506 AMDGPU_VM_USE_CPU_FOR_GFX);
2507 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2508 vm->use_cpu_for_update ? "CPU" : "SDMA");
2509 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
2510 "CPU update of VM recommended only for large BAR system\n");
Christian Königa24960f2016-10-12 13:20:52 +02002511 vm->last_dir_update = NULL;
Bas Nieuwenhuizen05906de2015-08-14 20:08:40 +02002512
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04002513 flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
2514 AMDGPU_GEM_CREATE_VRAM_CLEARED;
2515 if (vm->use_cpu_for_update)
2516 flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
2517 else
2518 flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
2519 AMDGPU_GEM_CREATE_SHADOW);
2520
Christian Königf566ceb2016-10-27 20:04:38 +02002521 r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
Alex Deucher857d9132015-08-27 00:14:16 -04002522 AMDGPU_GEM_DOMAIN_VRAM,
Harish Kasiviswanathan3c824172017-05-11 15:50:08 -04002523 flags,
Yong Zhao51ac7ee2017-07-27 12:48:22 -04002524 NULL, NULL, init_pde_value, &vm->root.bo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002525 if (r)
Christian König2bd9ccf2016-02-01 12:53:58 +01002526 goto error_free_sched_entity;
2527
Christian König67003a12016-10-12 14:46:26 +02002528 r = amdgpu_bo_reserve(vm->root.bo, false);
Christian König2bd9ccf2016-02-01 12:53:58 +01002529 if (r)
Christian König67003a12016-10-12 14:46:26 +02002530 goto error_free_root;
Christian König2bd9ccf2016-02-01 12:53:58 +01002531
Christian König5a712a82016-06-21 16:28:15 +02002532 vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
Christian König0a096fb2017-07-12 10:01:48 +02002533
2534 if (vm->use_cpu_for_update) {
2535 r = amdgpu_bo_kmap(vm->root.bo, NULL);
2536 if (r)
2537 goto error_free_root;
2538 }
2539
Christian König67003a12016-10-12 14:46:26 +02002540 amdgpu_bo_unreserve(vm->root.bo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002541
2542 return 0;
Christian König2bd9ccf2016-02-01 12:53:58 +01002543
Christian König67003a12016-10-12 14:46:26 +02002544error_free_root:
2545 amdgpu_bo_unref(&vm->root.bo->shadow);
2546 amdgpu_bo_unref(&vm->root.bo);
2547 vm->root.bo = NULL;
Christian König2bd9ccf2016-02-01 12:53:58 +01002548
2549error_free_sched_entity:
2550 amd_sched_entity_fini(&ring->sched, &vm->entity);
2551
2552 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002553}
2554
2555/**
Christian Königf566ceb2016-10-27 20:04:38 +02002556 * amdgpu_vm_free_levels - free PD/PT levels
2557 *
2558 * @level: PD/PT starting level to free
2559 *
2560 * Free the page directory or page table level and all sub levels.
2561 */
2562static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
2563{
2564 unsigned i;
2565
2566 if (level->bo) {
2567 amdgpu_bo_unref(&level->bo->shadow);
2568 amdgpu_bo_unref(&level->bo);
2569 }
2570
2571 if (level->entries)
2572 for (i = 0; i <= level->last_entry_used; i++)
2573 amdgpu_vm_free_levels(&level->entries[i]);
2574
Michal Hocko20981052017-05-17 14:23:12 +02002575 kvfree(level->entries);
Christian Königf566ceb2016-10-27 20:04:38 +02002576}
2577
2578/**
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002579 * amdgpu_vm_fini - tear down a vm instance
2580 *
2581 * @adev: amdgpu_device pointer
2582 * @vm: requested vm
2583 *
Christian König8843dbb2016-01-26 12:17:11 +01002584 * Tear down @vm.
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002585 * Unbind the VM and remove all bos from the vm bo list
2586 */
2587void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2588{
2589 struct amdgpu_bo_va_mapping *mapping, *tmp;
Christian König4388fc22017-03-13 10:13:36 +01002590 bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
Chunming Zhou36bbf3b2017-04-20 16:17:34 +08002591 int i;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002592
Christian König2d55e452016-02-08 17:37:38 +01002593 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
Christian König2bd9ccf2016-02-01 12:53:58 +01002594
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002595 if (!RB_EMPTY_ROOT(&vm->va)) {
2596 dev_err(adev->dev, "still active bo inside vm\n");
2597 }
Christian Königa9f87f62017-03-30 14:03:59 +02002598 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002599 list_del(&mapping->list);
Christian Königa9f87f62017-03-30 14:03:59 +02002600 amdgpu_vm_it_remove(mapping, &vm->va);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002601 kfree(mapping);
2602 }
2603 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
Christian König4388fc22017-03-13 10:13:36 +01002604 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
Christian König451bc8e2017-02-14 16:02:52 +01002605 amdgpu_vm_prt_fini(adev, vm);
Christian König4388fc22017-03-13 10:13:36 +01002606 prt_fini_needed = false;
Christian König451bc8e2017-02-14 16:02:52 +01002607 }
Christian König284710f2017-01-30 11:09:31 +01002608
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002609 list_del(&mapping->list);
Christian König451bc8e2017-02-14 16:02:52 +01002610 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002611 }
2612
Christian Königf566ceb2016-10-27 20:04:38 +02002613 amdgpu_vm_free_levels(&vm->root);
Christian Königa24960f2016-10-12 13:20:52 +02002614 dma_fence_put(vm->last_dir_update);
Chunming Zhou1e9ef262017-04-20 16:18:48 +08002615 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2616 amdgpu_vm_free_reserved_vmid(adev, vm, i);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04002617}
Christian Königea89f8c2015-11-15 20:52:06 +01002618
2619/**
Christian Königa9a78b32016-01-21 10:19:11 +01002620 * amdgpu_vm_manager_init - init the VM manager
2621 *
2622 * @adev: amdgpu_device pointer
2623 *
2624 * Initialize the VM manager structures
2625 */
2626void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2627{
Christian König76456702017-04-06 17:52:39 +02002628 unsigned i, j;
Christian Königa9a78b32016-01-21 10:19:11 +01002629
Christian König76456702017-04-06 17:52:39 +02002630 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2631 struct amdgpu_vm_id_manager *id_mgr =
2632 &adev->vm_manager.id_mgr[i];
Christian Königa9a78b32016-01-21 10:19:11 +01002633
Christian König76456702017-04-06 17:52:39 +02002634 mutex_init(&id_mgr->lock);
2635 INIT_LIST_HEAD(&id_mgr->ids_lru);
Chunming Zhouc3505772017-04-21 15:51:04 +08002636 atomic_set(&id_mgr->reserved_vmid_num, 0);
Christian König76456702017-04-06 17:52:39 +02002637
2638 /* skip over VMID 0, since it is the system VM */
2639 for (j = 1; j < id_mgr->num_ids; ++j) {
2640 amdgpu_vm_reset_id(adev, i, j);
2641 amdgpu_sync_create(&id_mgr->ids[i].active);
2642 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
2643 }
Christian König971fe9a92016-03-01 15:09:25 +01002644 }
Christian König2d55e452016-02-08 17:37:38 +01002645
Chris Wilsonf54d1862016-10-25 13:00:45 +01002646 adev->vm_manager.fence_context =
2647 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
Christian König1fbb2e92016-06-01 10:47:36 +02002648 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2649 adev->vm_manager.seqno[i] = 0;
2650
Christian König2d55e452016-02-08 17:37:38 +01002651 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
Christian Königb1c8a812016-05-04 10:34:03 +02002652 atomic64_set(&adev->vm_manager.client_counter, 0);
Christian König284710f2017-01-30 11:09:31 +01002653 spin_lock_init(&adev->vm_manager.prt_lock);
Christian König451bc8e2017-02-14 16:02:52 +01002654 atomic_set(&adev->vm_manager.num_prt_users, 0);
Harish Kasiviswanathan9a4b7d42017-06-09 11:26:57 -04002655
2656 /* If not overridden by the user, by default, only in large BAR systems
2657 * Compute VM tables will be updated by CPU
2658 */
2659#ifdef CONFIG_X86_64
2660 if (amdgpu_vm_update_mode == -1) {
2661 if (amdgpu_vm_is_large_bar(adev))
2662 adev->vm_manager.vm_update_mode =
2663 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2664 else
2665 adev->vm_manager.vm_update_mode = 0;
2666 } else
2667 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2668#else
2669 adev->vm_manager.vm_update_mode = 0;
2670#endif
2671
Christian Königa9a78b32016-01-21 10:19:11 +01002672}
2673
2674/**
Christian Königea89f8c2015-11-15 20:52:06 +01002675 * amdgpu_vm_manager_fini - cleanup VM manager
2676 *
2677 * @adev: amdgpu_device pointer
2678 *
2679 * Cleanup the VM manager and free resources.
2680 */
2681void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2682{
Christian König76456702017-04-06 17:52:39 +02002683 unsigned i, j;
Christian Königea89f8c2015-11-15 20:52:06 +01002684
Christian König76456702017-04-06 17:52:39 +02002685 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2686 struct amdgpu_vm_id_manager *id_mgr =
2687 &adev->vm_manager.id_mgr[i];
Christian Königbcb1ba32016-03-08 15:40:11 +01002688
Christian König76456702017-04-06 17:52:39 +02002689 mutex_destroy(&id_mgr->lock);
2690 for (j = 0; j < AMDGPU_NUM_VM; ++j) {
2691 struct amdgpu_vm_id *id = &id_mgr->ids[j];
2692
2693 amdgpu_sync_free(&id->active);
2694 dma_fence_put(id->flushed_updates);
2695 dma_fence_put(id->last_flush);
2696 }
Christian Königbcb1ba32016-03-08 15:40:11 +01002697 }
Christian Königea89f8c2015-11-15 20:52:06 +01002698}
Chunming Zhoucfbcacf2017-04-24 11:09:04 +08002699
2700int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2701{
2702 union drm_amdgpu_vm *args = data;
Chunming Zhou1e9ef262017-04-20 16:18:48 +08002703 struct amdgpu_device *adev = dev->dev_private;
2704 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2705 int r;
Chunming Zhoucfbcacf2017-04-24 11:09:04 +08002706
2707 switch (args->in.op) {
2708 case AMDGPU_VM_OP_RESERVE_VMID:
Chunming Zhou1e9ef262017-04-20 16:18:48 +08002709 /* current, we only have requirement to reserve vmid from gfxhub */
2710 r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm,
2711 AMDGPU_GFXHUB);
2712 if (r)
2713 return r;
2714 break;
Chunming Zhoucfbcacf2017-04-24 11:09:04 +08002715 case AMDGPU_VM_OP_UNRESERVE_VMID:
Chunming Zhou1e9ef262017-04-20 16:18:48 +08002716 amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB);
Chunming Zhoucfbcacf2017-04-24 11:09:04 +08002717 break;
2718 default:
2719 return -EINVAL;
2720 }
2721
2722 return 0;
2723}