Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/linux/mtd/nand.h |
| 3 | * |
David Woodhouse | a1452a3 | 2010-08-08 20:58:20 +0100 | [diff] [blame] | 4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
| 5 | * Steven J. Hill <sjhill@realitydiluted.com> |
| 6 | * Thomas Gleixner <tglx@linutronix.de> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
Thomas Gleixner | 2c0a2be | 2006-05-23 11:50:56 +0200 | [diff] [blame] | 12 | * Info: |
| 13 | * Contains standard defines and IDs for NAND flash devices |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | * |
Thomas Gleixner | 2c0a2be | 2006-05-23 11:50:56 +0200 | [diff] [blame] | 15 | * Changelog: |
| 16 | * See git changelog. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | */ |
| 18 | #ifndef __LINUX_MTD_NAND_H |
| 19 | #define __LINUX_MTD_NAND_H |
| 20 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <linux/wait.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/mtd/mtd.h> |
Alessandro Rubini | 30631cb | 2009-09-20 23:28:14 +0200 | [diff] [blame] | 24 | #include <linux/mtd/flashchip.h> |
Alessandro Rubini | c62d81b | 2009-09-20 23:28:04 +0200 | [diff] [blame] | 25 | #include <linux/mtd/bbm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | |
| 27 | struct mtd_info; |
David Woodhouse | 5e81e88 | 2010-02-26 18:32:56 +0000 | [diff] [blame] | 28 | struct nand_flash_dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | /* Scan and identify a NAND device */ |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 30 | extern int nand_scan(struct mtd_info *mtd, int max_chips); |
| 31 | /* |
| 32 | * Separate phases of nand_scan(), allowing board driver to intervene |
| 33 | * and override command or ECC setup according to flash type. |
| 34 | */ |
David Woodhouse | 5e81e88 | 2010-02-26 18:32:56 +0000 | [diff] [blame] | 35 | extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
| 36 | struct nand_flash_dev *table); |
David Woodhouse | 3b85c32 | 2006-09-25 17:06:53 +0100 | [diff] [blame] | 37 | extern int nand_scan_tail(struct mtd_info *mtd); |
| 38 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | /* Free resources held by the NAND device */ |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 40 | extern void nand_release(struct mtd_info *mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
David Woodhouse | b77d95c | 2006-09-25 21:58:50 +0100 | [diff] [blame] | 42 | /* Internal helper for board drivers which need to override command function */ |
| 43 | extern void nand_wait_ready(struct mtd_info *mtd); |
| 44 | |
Vimal Singh | 7d70f33 | 2010-02-08 15:50:49 +0530 | [diff] [blame] | 45 | /* locks all blockes present in the device */ |
| 46 | extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
| 47 | |
| 48 | /* unlocks specified locked blockes */ |
| 49 | extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
| 50 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | /* The maximum number of NAND chips in an array */ |
| 52 | #define NAND_MAX_CHIPS 8 |
| 53 | |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 54 | /* |
| 55 | * This constant declares the max. oobsize / page, which |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | * is supported now. If you add a chip with bigger oobsize/page |
| 57 | * adjust this accordingly. |
| 58 | */ |
Brian Norris | 5c709ee | 2010-08-20 12:36:13 -0700 | [diff] [blame] | 59 | #define NAND_MAX_OOBSIZE 576 |
| 60 | #define NAND_MAX_PAGESIZE 8192 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | |
| 62 | /* |
| 63 | * Constants for hardware specific CLE/ALE/NCE function |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 64 | * |
| 65 | * These are bits which can be or'ed to set/clear multiple |
| 66 | * bits in one go. |
| 67 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | /* Select the chip by setting nCE to low */ |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 69 | #define NAND_NCE 0x01 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | /* Select the command latch by setting CLE to high */ |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 71 | #define NAND_CLE 0x02 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | /* Select the address latch by setting ALE to high */ |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 73 | #define NAND_ALE 0x04 |
| 74 | |
| 75 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) |
| 76 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) |
| 77 | #define NAND_CTRL_CHANGE 0x80 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | |
| 79 | /* |
| 80 | * Standard NAND flash commands |
| 81 | */ |
| 82 | #define NAND_CMD_READ0 0 |
| 83 | #define NAND_CMD_READ1 1 |
Thomas Gleixner | 7bc3312 | 2006-06-20 20:05:05 +0200 | [diff] [blame] | 84 | #define NAND_CMD_RNDOUT 5 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | #define NAND_CMD_PAGEPROG 0x10 |
| 86 | #define NAND_CMD_READOOB 0x50 |
| 87 | #define NAND_CMD_ERASE1 0x60 |
| 88 | #define NAND_CMD_STATUS 0x70 |
| 89 | #define NAND_CMD_STATUS_MULTI 0x71 |
| 90 | #define NAND_CMD_SEQIN 0x80 |
Thomas Gleixner | 7bc3312 | 2006-06-20 20:05:05 +0200 | [diff] [blame] | 91 | #define NAND_CMD_RNDIN 0x85 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | #define NAND_CMD_READID 0x90 |
| 93 | #define NAND_CMD_ERASE2 0xd0 |
Florian Fainelli | caa4b6f | 2010-08-30 18:32:14 +0200 | [diff] [blame] | 94 | #define NAND_CMD_PARAM 0xec |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | #define NAND_CMD_RESET 0xff |
| 96 | |
Vimal Singh | 7d70f33 | 2010-02-08 15:50:49 +0530 | [diff] [blame] | 97 | #define NAND_CMD_LOCK 0x2a |
| 98 | #define NAND_CMD_UNLOCK1 0x23 |
| 99 | #define NAND_CMD_UNLOCK2 0x24 |
| 100 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | /* Extended commands for large page devices */ |
| 102 | #define NAND_CMD_READSTART 0x30 |
Thomas Gleixner | 7bc3312 | 2006-06-20 20:05:05 +0200 | [diff] [blame] | 103 | #define NAND_CMD_RNDOUTSTART 0xE0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | #define NAND_CMD_CACHEDPROG 0x15 |
| 105 | |
David A. Marlin | 28a48de | 2005-01-17 18:29:21 +0000 | [diff] [blame] | 106 | /* Extended commands for AG-AND device */ |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 107 | /* |
| 108 | * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but |
David A. Marlin | 28a48de | 2005-01-17 18:29:21 +0000 | [diff] [blame] | 109 | * there is no way to distinguish that from NAND_CMD_READ0 |
| 110 | * until the remaining sequence of commands has been completed |
| 111 | * so add a high order bit and mask it off in the command. |
| 112 | */ |
| 113 | #define NAND_CMD_DEPLETE1 0x100 |
| 114 | #define NAND_CMD_DEPLETE2 0x38 |
| 115 | #define NAND_CMD_STATUS_MULTI 0x71 |
| 116 | #define NAND_CMD_STATUS_ERROR 0x72 |
| 117 | /* multi-bank error status (banks 0-3) */ |
| 118 | #define NAND_CMD_STATUS_ERROR0 0x73 |
| 119 | #define NAND_CMD_STATUS_ERROR1 0x74 |
| 120 | #define NAND_CMD_STATUS_ERROR2 0x75 |
| 121 | #define NAND_CMD_STATUS_ERROR3 0x76 |
| 122 | #define NAND_CMD_STATUS_RESET 0x7f |
| 123 | #define NAND_CMD_STATUS_CLEAR 0xff |
| 124 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 125 | #define NAND_CMD_NONE -1 |
| 126 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | /* Status bits */ |
| 128 | #define NAND_STATUS_FAIL 0x01 |
| 129 | #define NAND_STATUS_FAIL_N1 0x02 |
| 130 | #define NAND_STATUS_TRUE_READY 0x20 |
| 131 | #define NAND_STATUS_READY 0x40 |
| 132 | #define NAND_STATUS_WP 0x80 |
| 133 | |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 134 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | * Constants for ECC_MODES |
| 136 | */ |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 137 | typedef enum { |
| 138 | NAND_ECC_NONE, |
| 139 | NAND_ECC_SOFT, |
| 140 | NAND_ECC_HW, |
| 141 | NAND_ECC_HW_SYNDROME, |
Sneha Narnakaje | 6e0cb13 | 2009-09-18 12:51:47 -0700 | [diff] [blame] | 142 | NAND_ECC_HW_OOB_FIRST, |
Ivan Djelic | 193bd40 | 2011-03-11 11:05:33 +0100 | [diff] [blame] | 143 | NAND_ECC_SOFT_BCH, |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 144 | } nand_ecc_modes_t; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | |
| 146 | /* |
| 147 | * Constants for Hardware ECC |
David A. Marlin | 068e3c0 | 2005-01-24 03:07:46 +0000 | [diff] [blame] | 148 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | /* Reset Hardware ECC for read */ |
| 150 | #define NAND_ECC_READ 0 |
| 151 | /* Reset Hardware ECC for write */ |
| 152 | #define NAND_ECC_WRITE 1 |
| 153 | /* Enable Hardware ECC before syndrom is read back from flash */ |
| 154 | #define NAND_ECC_READSYN 2 |
| 155 | |
David A. Marlin | 068e3c0 | 2005-01-24 03:07:46 +0000 | [diff] [blame] | 156 | /* Bit mask for flags passed to do_nand_read_ecc */ |
| 157 | #define NAND_GET_DEVICE 0x80 |
| 158 | |
| 159 | |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 160 | /* |
| 161 | * Option constants for bizarre disfunctionality and real |
| 162 | * features. |
| 163 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | /* Chip can not auto increment pages */ |
| 165 | #define NAND_NO_AUTOINCR 0x00000001 |
| 166 | /* Buswitdh is 16 bit */ |
| 167 | #define NAND_BUSWIDTH_16 0x00000002 |
| 168 | /* Device supports partial programming without padding */ |
| 169 | #define NAND_NO_PADDING 0x00000004 |
| 170 | /* Chip has cache program function */ |
| 171 | #define NAND_CACHEPRG 0x00000008 |
| 172 | /* Chip has copy back function */ |
| 173 | #define NAND_COPYBACK 0x00000010 |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 174 | /* |
| 175 | * AND Chip which has 4 banks and a confusing page / block |
| 176 | * assignment. See Renesas datasheet for further information. |
| 177 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 178 | #define NAND_IS_AND 0x00000020 |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 179 | /* |
| 180 | * Chip has a array of 4 pages which can be read without |
| 181 | * additional ready /busy waits. |
| 182 | */ |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 183 | #define NAND_4PAGE_ARRAY 0x00000040 |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 184 | /* |
| 185 | * Chip requires that BBT is periodically rewritten to prevent |
David A. Marlin | 28a48de | 2005-01-17 18:29:21 +0000 | [diff] [blame] | 186 | * bits from adjacent blocks from 'leaking' in altering data. |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 187 | * This happens with the Renesas AG-AND chips, possibly others. |
| 188 | */ |
David A. Marlin | 28a48de | 2005-01-17 18:29:21 +0000 | [diff] [blame] | 189 | #define BBT_AUTO_REFRESH 0x00000080 |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 190 | /* |
| 191 | * Chip does not require ready check on read. True |
Thomas Gleixner | 7a30601 | 2006-05-25 09:50:16 +0200 | [diff] [blame] | 192 | * for all large page devices, as they do not support |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 193 | * autoincrement. |
| 194 | */ |
Thomas Gleixner | 7a30601 | 2006-05-25 09:50:16 +0200 | [diff] [blame] | 195 | #define NAND_NO_READRDY 0x00000100 |
Thomas Gleixner | 29072b9 | 2006-09-28 15:38:36 +0200 | [diff] [blame] | 196 | /* Chip does not allow subpage writes */ |
| 197 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 |
| 198 | |
Maxim Levitsky | 93edbad | 2010-02-22 20:39:40 +0200 | [diff] [blame] | 199 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
| 200 | #define NAND_BROKEN_XD 0x00000400 |
| 201 | |
| 202 | /* Device behaves just like nand, but is readonly */ |
| 203 | #define NAND_ROM 0x00000800 |
| 204 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | /* Options valid for Samsung large page devices */ |
| 206 | #define NAND_SAMSUNG_LP_OPTIONS \ |
| 207 | (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) |
| 208 | |
| 209 | /* Macros to identify the above */ |
| 210 | #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) |
| 211 | #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) |
| 212 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
| 213 | #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) |
Alexey Korolev | 96d8b64 | 2008-07-29 13:54:11 +0100 | [diff] [blame] | 214 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
| 215 | #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ |
| 216 | && (chip->page_shift > 9)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | |
| 218 | /* Mask to zero out the chip options, which come from the id table */ |
| 219 | #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) |
| 220 | |
| 221 | /* Non chip related options */ |
Thomas Gleixner | 0040bf3 | 2005-02-09 12:20:00 +0000 | [diff] [blame] | 222 | /* This option skips the bbt scan during initialization. */ |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 223 | #define NAND_SKIP_BBTSCAN 0x00020000 |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 224 | /* |
| 225 | * This option is defined if the board driver allocates its own buffers |
| 226 | * (e.g. because it needs them DMA-coherent). |
| 227 | */ |
David Woodhouse | 4bf63fc | 2006-09-25 17:08:04 +0100 | [diff] [blame] | 228 | #define NAND_OWN_BUFFERS 0x00040000 |
Ben Dooks | b1c6e6d | 2009-11-02 18:12:33 +0000 | [diff] [blame] | 229 | /* Chip may not exist, so silence any errors in scan */ |
| 230 | #define NAND_SCAN_SILENT_NODEV 0x00080000 |
Sebastian Andrzej Siewior | 453281a | 2010-10-01 21:37:37 +0200 | [diff] [blame] | 231 | /* Create an empty BBT with no vendor information if the BBT is available */ |
Brian Norris | a626743 | 2011-03-18 21:53:41 -0700 | [diff] [blame] | 232 | #define NAND_CREATE_EMPTY_BBT 0x01000000 |
Ben Dooks | b1c6e6d | 2009-11-02 18:12:33 +0000 | [diff] [blame] | 233 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | /* Options set by nand scan */ |
Thomas Gleixner | a36ed29 | 2006-05-23 11:37:03 +0200 | [diff] [blame] | 235 | /* Nand scan has allocated controller struct */ |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 236 | #define NAND_CONTROLLER_ALLOC 0x80000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | |
Thomas Gleixner | 29072b9 | 2006-09-28 15:38:36 +0200 | [diff] [blame] | 238 | /* Cell info constants */ |
| 239 | #define NAND_CI_CHIPNR_MSK 0x03 |
| 240 | #define NAND_CI_CELLTYPE_MSK 0x0C |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | /* Keep gcc happy */ |
| 243 | struct nand_chip; |
| 244 | |
Florian Fainelli | d1e1f4e | 2010-08-30 18:32:24 +0200 | [diff] [blame] | 245 | struct nand_onfi_params { |
| 246 | /* rev info and features block */ |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 247 | /* 'O' 'N' 'F' 'I' */ |
| 248 | u8 sig[4]; |
| 249 | __le16 revision; |
| 250 | __le16 features; |
| 251 | __le16 opt_cmd; |
| 252 | u8 reserved[22]; |
Florian Fainelli | d1e1f4e | 2010-08-30 18:32:24 +0200 | [diff] [blame] | 253 | |
| 254 | /* manufacturer information block */ |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 255 | char manufacturer[12]; |
| 256 | char model[20]; |
| 257 | u8 jedec_id; |
| 258 | __le16 date_code; |
| 259 | u8 reserved2[13]; |
Florian Fainelli | d1e1f4e | 2010-08-30 18:32:24 +0200 | [diff] [blame] | 260 | |
| 261 | /* memory organization block */ |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 262 | __le32 byte_per_page; |
| 263 | __le16 spare_bytes_per_page; |
| 264 | __le32 data_bytes_per_ppage; |
| 265 | __le16 spare_bytes_per_ppage; |
| 266 | __le32 pages_per_block; |
| 267 | __le32 blocks_per_lun; |
| 268 | u8 lun_count; |
| 269 | u8 addr_cycles; |
| 270 | u8 bits_per_cell; |
| 271 | __le16 bb_per_lun; |
| 272 | __le16 block_endurance; |
| 273 | u8 guaranteed_good_blocks; |
| 274 | __le16 guaranteed_block_endurance; |
| 275 | u8 programs_per_page; |
| 276 | u8 ppage_attr; |
| 277 | u8 ecc_bits; |
| 278 | u8 interleaved_bits; |
| 279 | u8 interleaved_ops; |
| 280 | u8 reserved3[13]; |
Florian Fainelli | d1e1f4e | 2010-08-30 18:32:24 +0200 | [diff] [blame] | 281 | |
| 282 | /* electrical parameter block */ |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 283 | u8 io_pin_capacitance_max; |
| 284 | __le16 async_timing_mode; |
| 285 | __le16 program_cache_timing_mode; |
| 286 | __le16 t_prog; |
| 287 | __le16 t_bers; |
| 288 | __le16 t_r; |
| 289 | __le16 t_ccs; |
| 290 | __le16 src_sync_timing_mode; |
| 291 | __le16 src_ssync_features; |
| 292 | __le16 clk_pin_capacitance_typ; |
| 293 | __le16 io_pin_capacitance_typ; |
| 294 | __le16 input_pin_capacitance_typ; |
| 295 | u8 input_pin_capacitance_max; |
| 296 | u8 driver_strenght_support; |
| 297 | __le16 t_int_r; |
| 298 | __le16 t_ald; |
| 299 | u8 reserved4[7]; |
Florian Fainelli | d1e1f4e | 2010-08-30 18:32:24 +0200 | [diff] [blame] | 300 | |
| 301 | /* vendor */ |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 302 | u8 reserved5[90]; |
Florian Fainelli | d1e1f4e | 2010-08-30 18:32:24 +0200 | [diff] [blame] | 303 | |
| 304 | __le16 crc; |
| 305 | } __attribute__((packed)); |
| 306 | |
| 307 | #define ONFI_CRC_BASE 0x4F4E |
| 308 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 309 | /** |
Randy Dunlap | 844d3b4 | 2006-06-28 21:48:27 -0700 | [diff] [blame] | 310 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 311 | * @lock: protection lock |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | * @active: the mtd device which holds the controller currently |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 313 | * @wq: wait queue to sleep on if a NAND operation is in |
| 314 | * progress used instead of the per chip wait queue |
| 315 | * when a hw controller is available. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | */ |
| 317 | struct nand_hw_control { |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 318 | spinlock_t lock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 319 | struct nand_chip *active; |
Thomas Gleixner | 0dfc624 | 2005-05-31 20:39:20 +0100 | [diff] [blame] | 320 | wait_queue_head_t wq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | }; |
| 322 | |
| 323 | /** |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 324 | * struct nand_ecc_ctrl - Control structure for ecc |
| 325 | * @mode: ecc mode |
| 326 | * @steps: number of ecc steps per page |
| 327 | * @size: data bytes per ecc step |
| 328 | * @bytes: ecc bytes per step |
Thomas Gleixner | 9577f44 | 2006-05-25 10:04:31 +0200 | [diff] [blame] | 329 | * @total: total number of ecc bytes per page |
| 330 | * @prepad: padding information for syndrome based ecc generators |
| 331 | * @postpad: padding information for syndrome based ecc generators |
Randy Dunlap | 844d3b4 | 2006-06-28 21:48:27 -0700 | [diff] [blame] | 332 | * @layout: ECC layout control struct pointer |
Ivan Djelic | 193bd40 | 2011-03-11 11:05:33 +0100 | [diff] [blame] | 333 | * @priv: pointer to private ecc control data |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 334 | * @hwctl: function to control hardware ecc generator. Must only |
| 335 | * be provided if an hardware ECC is available |
| 336 | * @calculate: function for ecc calculation or readback from ecc hardware |
| 337 | * @correct: function for ecc correction, matching to ecc generator (sw/hw) |
David Woodhouse | 956e944 | 2006-09-25 17:12:39 +0100 | [diff] [blame] | 338 | * @read_page_raw: function to read a raw page without ECC |
| 339 | * @write_page_raw: function to write a raw page without ECC |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 340 | * @read_page: function to read a page according to the ecc generator |
| 341 | * requirements. |
Alexey Korolev | 17c1d2be | 2008-08-20 22:32:08 +0100 | [diff] [blame] | 342 | * @read_subpage: function to read parts of the page covered by ECC. |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 343 | * @write_page: function to write a page according to the ecc generator |
| 344 | * requirements. |
Randy Dunlap | 844d3b4 | 2006-06-28 21:48:27 -0700 | [diff] [blame] | 345 | * @read_oob: function to read chip OOB data |
| 346 | * @write_oob: function to write chip OOB data |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 347 | */ |
| 348 | struct nand_ecc_ctrl { |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 349 | nand_ecc_modes_t mode; |
| 350 | int steps; |
| 351 | int size; |
| 352 | int bytes; |
| 353 | int total; |
| 354 | int prepad; |
| 355 | int postpad; |
Thomas Gleixner | 5bd34c0 | 2006-05-27 22:16:10 +0200 | [diff] [blame] | 356 | struct nand_ecclayout *layout; |
Ivan Djelic | 193bd40 | 2011-03-11 11:05:33 +0100 | [diff] [blame] | 357 | void *priv; |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 358 | void (*hwctl)(struct mtd_info *mtd, int mode); |
| 359 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, |
| 360 | uint8_t *ecc_code); |
| 361 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, |
| 362 | uint8_t *calc_ecc); |
| 363 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
| 364 | uint8_t *buf, int page); |
| 365 | void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
| 366 | const uint8_t *buf); |
| 367 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
| 368 | uint8_t *buf, int page); |
| 369 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
| 370 | uint32_t offs, uint32_t len, uint8_t *buf); |
| 371 | void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
| 372 | const uint8_t *buf); |
| 373 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page, |
| 374 | int sndcmd); |
| 375 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, |
| 376 | int page); |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 377 | }; |
| 378 | |
| 379 | /** |
| 380 | * struct nand_buffers - buffer structure for read/write |
| 381 | * @ecccalc: buffer for calculated ecc |
| 382 | * @ecccode: buffer for ecc read from flash |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 383 | * @databuf: buffer for data - dynamically sized |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 384 | * |
| 385 | * Do not change the order of buffers. databuf and oobrbuf must be in |
| 386 | * consecutive order. |
| 387 | */ |
| 388 | struct nand_buffers { |
| 389 | uint8_t ecccalc[NAND_MAX_OOBSIZE]; |
| 390 | uint8_t ecccode[NAND_MAX_OOBSIZE]; |
David Woodhouse | 7dcdcbef | 2006-10-21 17:09:53 +0100 | [diff] [blame] | 391 | uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 392 | }; |
| 393 | |
| 394 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | * struct nand_chip - NAND Private Flash Chip Data |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 396 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
| 397 | * flash device |
| 398 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the |
| 399 | * flash device. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | * @read_byte: [REPLACEABLE] read one byte from the chip |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | * @read_word: [REPLACEABLE] read one word from the chip |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
| 403 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 404 | * @verify_buf: [REPLACEABLE] verify buffer contents against the chip |
| 405 | * data. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | * @select_chip: [REPLACEABLE] select chip nr |
| 407 | * @block_bad: [REPLACEABLE] check, if the block is bad |
| 408 | * @block_markbad: [REPLACEABLE] mark the block bad |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 409 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 410 | * ALE/CLE/nCE. Also used to write command and address |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 411 | * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting |
Huang Shijie | 12a40a5 | 2010-09-27 10:43:53 +0800 | [diff] [blame] | 412 | * mtd->oobsize, mtd->writesize and so on. |
| 413 | * @id_data contains the 8 bytes values of NAND_CMD_READID. |
| 414 | * Return with the bus width. |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 415 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing |
| 416 | * device ready/busy line. If set to NULL no access to |
| 417 | * ready/busy is available and the ready/busy information |
| 418 | * is read from the chip status register. |
| 419 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing |
| 420 | * commands to the chip. |
| 421 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on |
| 422 | * ready. |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 423 | * @ecc: [BOARDSPECIFIC] ecc control ctructure |
Randy Dunlap | 844d3b4 | 2006-06-28 21:48:27 -0700 | [diff] [blame] | 424 | * @buffers: buffer structure for read/write |
| 425 | * @hwcontrol: platform-specific hardware control structure |
| 426 | * @ops: oob operation operands |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 427 | * @erase_cmd: [INTERN] erase command write function, selectable due |
| 428 | * to AND support. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 430 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 431 | * data from array to read regs (tR). |
Thomas Gleixner | 2c0a2be | 2006-05-23 11:50:56 +0200 | [diff] [blame] | 432 | * @state: [INTERN] the current state of the NAND device |
Randy Dunlap | 844d3b4 | 2006-06-28 21:48:27 -0700 | [diff] [blame] | 433 | * @oob_poi: poison value buffer |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 434 | * @page_shift: [INTERN] number of address bits in a page (column |
| 435 | * address bits). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
| 437 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry |
| 438 | * @chip_shift: [INTERN] number of address bits in one chip |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 439 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
| 440 | * be set to inform nand_scan about special functionality. |
| 441 | * See the defines for further explanation. |
Brian Norris | 5fb1549 | 2011-05-31 16:31:21 -0700 | [diff] [blame] | 442 | * @bbt_options: [INTERN] bad block specific options. All options used |
| 443 | * here must come from bbm.h. By default, these options |
| 444 | * will be copied to the appropriate nand_bbt_descr's. |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 445 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
| 446 | * area. |
Randy Dunlap | 1534b8b | 2010-11-18 15:02:21 -0800 | [diff] [blame] | 447 | * @badblockbits: [INTERN] number of bits to left-shift the bad block |
| 448 | * number |
Randy Dunlap | 552a827 | 2007-02-05 16:28:59 -0800 | [diff] [blame] | 449 | * @cellinfo: [INTERN] MLC/multichip data from chip ident |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 450 | * @numchips: [INTERN] number of physical chips |
| 451 | * @chipsize: [INTERN] the size of one chip for multichip arrays |
| 452 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 453 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
| 454 | * data_buf. |
Thomas Gleixner | 29072b9 | 2006-09-28 15:38:36 +0200 | [diff] [blame] | 455 | * @subpagesize: [INTERN] holds the subpagesize |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 456 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
| 457 | * non 0 if ONFI supported. |
| 458 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is |
| 459 | * supported, 0 otherwise. |
Thomas Gleixner | 5bd34c0 | 2006-05-27 22:16:10 +0200 | [diff] [blame] | 460 | * @ecclayout: [REPLACEABLE] the default ecc placement scheme |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | * @bbt: [INTERN] bad block table pointer |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 462 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
| 463 | * lookup. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 465 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
| 466 | * bad block scan. |
| 467 | * @controller: [REPLACEABLE] a pointer to a hardware controller |
| 468 | * structure which is shared among multiple independend |
| 469 | * devices. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 470 | * @priv: [OPTIONAL] pointer to private chip date |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 471 | * @errstat: [OPTIONAL] hardware specific function to perform |
| 472 | * additional error status checks (determine if errors are |
| 473 | * correctable). |
Randy Dunlap | 351edd2 | 2006-10-29 22:46:40 -0800 | [diff] [blame] | 474 | * @write_page: [REPLACEABLE] High-level page write function |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | */ |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 476 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | struct nand_chip { |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 478 | void __iomem *IO_ADDR_R; |
| 479 | void __iomem *IO_ADDR_W; |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 480 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 481 | uint8_t (*read_byte)(struct mtd_info *mtd); |
| 482 | u16 (*read_word)(struct mtd_info *mtd); |
| 483 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
| 484 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); |
| 485 | int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
| 486 | void (*select_chip)(struct mtd_info *mtd, int chip); |
| 487 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); |
| 488 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); |
| 489 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); |
| 490 | int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, |
| 491 | u8 *id_data); |
| 492 | int (*dev_ready)(struct mtd_info *mtd); |
| 493 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, |
| 494 | int page_addr); |
| 495 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); |
| 496 | void (*erase_cmd)(struct mtd_info *mtd, int page); |
| 497 | int (*scan_bbt)(struct mtd_info *mtd); |
| 498 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, |
| 499 | int status, int page); |
| 500 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
| 501 | const uint8_t *buf, int page, int cached, int raw); |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 502 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 503 | int chip_delay; |
| 504 | unsigned int options; |
Brian Norris | 5fb1549 | 2011-05-31 16:31:21 -0700 | [diff] [blame] | 505 | unsigned int bbt_options; |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 506 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 507 | int page_shift; |
| 508 | int phys_erase_shift; |
| 509 | int bbt_erase_shift; |
| 510 | int chip_shift; |
| 511 | int numchips; |
| 512 | uint64_t chipsize; |
| 513 | int pagemask; |
| 514 | int pagebuf; |
| 515 | int subpagesize; |
| 516 | uint8_t cellinfo; |
| 517 | int badblockpos; |
| 518 | int badblockbits; |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 519 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 520 | int onfi_version; |
Florian Fainelli | d1e1f4e | 2010-08-30 18:32:24 +0200 | [diff] [blame] | 521 | struct nand_onfi_params onfi_params; |
| 522 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 523 | flstate_t state; |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 524 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 525 | uint8_t *oob_poi; |
| 526 | struct nand_hw_control *controller; |
| 527 | struct nand_ecclayout *ecclayout; |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 528 | |
| 529 | struct nand_ecc_ctrl ecc; |
David Woodhouse | 4bf63fc | 2006-09-25 17:08:04 +0100 | [diff] [blame] | 530 | struct nand_buffers *buffers; |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 531 | struct nand_hw_control hwcontrol; |
| 532 | |
Thomas Gleixner | 8593fbc | 2006-05-29 03:26:58 +0200 | [diff] [blame] | 533 | struct mtd_oob_ops ops; |
| 534 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 535 | uint8_t *bbt; |
| 536 | struct nand_bbt_descr *bbt_td; |
| 537 | struct nand_bbt_descr *bbt_md; |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 538 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 539 | struct nand_bbt_descr *badblock_pattern; |
Thomas Gleixner | f75e509 | 2006-05-26 18:52:08 +0200 | [diff] [blame] | 540 | |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 541 | void *priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 542 | }; |
| 543 | |
| 544 | /* |
| 545 | * NAND Flash Manufacturer ID Codes |
| 546 | */ |
| 547 | #define NAND_MFR_TOSHIBA 0x98 |
| 548 | #define NAND_MFR_SAMSUNG 0xec |
| 549 | #define NAND_MFR_FUJITSU 0x04 |
| 550 | #define NAND_MFR_NATIONAL 0x8f |
| 551 | #define NAND_MFR_RENESAS 0x07 |
| 552 | #define NAND_MFR_STMICRO 0x20 |
Thomas Gleixner | 2c0a2be | 2006-05-23 11:50:56 +0200 | [diff] [blame] | 553 | #define NAND_MFR_HYNIX 0xad |
sshahrom@micron.com | 8c60e54 | 2007-03-21 18:48:02 -0700 | [diff] [blame] | 554 | #define NAND_MFR_MICRON 0x2c |
Steven J. Hill | 30eb0db | 2007-07-18 23:29:46 -0500 | [diff] [blame] | 555 | #define NAND_MFR_AMD 0x01 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 556 | |
| 557 | /** |
| 558 | * struct nand_flash_dev - NAND Flash Device ID Structure |
Thomas Gleixner | 2c0a2be | 2006-05-23 11:50:56 +0200 | [diff] [blame] | 559 | * @name: Identify the device type |
| 560 | * @id: device ID code |
| 561 | * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 562 | * If the pagesize is 0, then the real pagesize |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 563 | * and the eraseize are determined from the |
| 564 | * extended id bytes in the chip |
Thomas Gleixner | 2c0a2be | 2006-05-23 11:50:56 +0200 | [diff] [blame] | 565 | * @erasesize: Size of an erase block in the flash device. |
| 566 | * @chipsize: Total chipsize in Mega Bytes |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 567 | * @options: Bitfield to store chip relevant options |
| 568 | */ |
| 569 | struct nand_flash_dev { |
| 570 | char *name; |
| 571 | int id; |
| 572 | unsigned long pagesize; |
| 573 | unsigned long chipsize; |
| 574 | unsigned long erasesize; |
| 575 | unsigned long options; |
| 576 | }; |
| 577 | |
| 578 | /** |
| 579 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure |
| 580 | * @name: Manufacturer name |
Thomas Gleixner | 2c0a2be | 2006-05-23 11:50:56 +0200 | [diff] [blame] | 581 | * @id: manufacturer ID code of device. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 582 | */ |
| 583 | struct nand_manufacturers { |
| 584 | int id; |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 585 | char *name; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 586 | }; |
| 587 | |
| 588 | extern struct nand_flash_dev nand_flash_ids[]; |
| 589 | extern struct nand_manufacturers nand_manuf_ids[]; |
| 590 | |
Thomas Gleixner | f5bbdac | 2006-05-25 10:07:16 +0200 | [diff] [blame] | 591 | extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); |
| 592 | extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); |
| 593 | extern int nand_default_bbt(struct mtd_info *mtd); |
| 594 | extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); |
| 595 | extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
| 596 | int allowbbt); |
| 597 | extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, |
Sebastian Andrzej Siewior | a0491fc | 2010-10-05 12:41:01 +0200 | [diff] [blame] | 598 | size_t *retlen, uint8_t *buf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 600 | /** |
| 601 | * struct platform_nand_chip - chip level device structure |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 602 | * @nr_chips: max. number of chips to scan for |
Randy Dunlap | 844d3b4 | 2006-06-28 21:48:27 -0700 | [diff] [blame] | 603 | * @chip_offset: chip number offset |
Thomas Gleixner | 8be834f | 2006-05-27 20:05:26 +0200 | [diff] [blame] | 604 | * @nr_partitions: number of partitions pointed to by partitions (or zero) |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 605 | * @partitions: mtd partition list |
| 606 | * @chip_delay: R/B delay value in us |
| 607 | * @options: Option flags, e.g. 16bit buswidth |
Brian Norris | a40f734 | 2011-05-31 16:31:22 -0700 | [diff] [blame^] | 608 | * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH |
Thomas Gleixner | 5bd34c0 | 2006-05-27 22:16:10 +0200 | [diff] [blame] | 609 | * @ecclayout: ecc layout info structure |
Vitaly Wool | 972edcb | 2007-05-06 18:46:57 +0400 | [diff] [blame] | 610 | * @part_probe_types: NULL-terminated array of probe types |
H Hartley Sweeten | f36e20c | 2009-05-12 13:46:59 -0700 | [diff] [blame] | 611 | * @set_parts: platform specific function to set partitions |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 612 | * @priv: hardware controller specific settings |
| 613 | */ |
| 614 | struct platform_nand_chip { |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 615 | int nr_chips; |
| 616 | int chip_offset; |
| 617 | int nr_partitions; |
| 618 | struct mtd_partition *partitions; |
| 619 | struct nand_ecclayout *ecclayout; |
| 620 | int chip_delay; |
| 621 | unsigned int options; |
Brian Norris | a40f734 | 2011-05-31 16:31:22 -0700 | [diff] [blame^] | 622 | unsigned int bbt_options; |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 623 | const char **part_probe_types; |
| 624 | void (*set_parts)(uint64_t size, struct platform_nand_chip *chip); |
| 625 | void *priv; |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 626 | }; |
| 627 | |
H Hartley Sweeten | bf95efd | 2009-05-12 13:46:58 -0700 | [diff] [blame] | 628 | /* Keep gcc happy */ |
| 629 | struct platform_device; |
| 630 | |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 631 | /** |
| 632 | * struct platform_nand_ctrl - controller level device structure |
H Hartley Sweeten | bf95efd | 2009-05-12 13:46:58 -0700 | [diff] [blame] | 633 | * @probe: platform specific function to probe/setup hardware |
| 634 | * @remove: platform specific function to remove/teardown hardware |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 635 | * @hwcontrol: platform specific hardware control structure |
| 636 | * @dev_ready: platform specific function to read ready/busy pin |
| 637 | * @select_chip: platform specific chip select function |
Vitaly Wool | 972edcb | 2007-05-06 18:46:57 +0400 | [diff] [blame] | 638 | * @cmd_ctrl: platform specific function for controlling |
| 639 | * ALE/CLE/nCE. Also used to write command and address |
Alexander Clouter | d6fed9e | 2009-05-11 19:28:01 +0100 | [diff] [blame] | 640 | * @write_buf: platform specific function for write buffer |
| 641 | * @read_buf: platform specific function for read buffer |
Randy Dunlap | 844d3b4 | 2006-06-28 21:48:27 -0700 | [diff] [blame] | 642 | * @priv: private data to transport driver specific settings |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 643 | * |
| 644 | * All fields are optional and depend on the hardware driver requirements |
| 645 | */ |
| 646 | struct platform_nand_ctrl { |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 647 | int (*probe)(struct platform_device *pdev); |
| 648 | void (*remove)(struct platform_device *pdev); |
| 649 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); |
| 650 | int (*dev_ready)(struct mtd_info *mtd); |
| 651 | void (*select_chip)(struct mtd_info *mtd, int chip); |
| 652 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); |
| 653 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
| 654 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); |
| 655 | void *priv; |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 656 | }; |
| 657 | |
Vitaly Wool | 972edcb | 2007-05-06 18:46:57 +0400 | [diff] [blame] | 658 | /** |
| 659 | * struct platform_nand_data - container structure for platform-specific data |
| 660 | * @chip: chip level chip structure |
| 661 | * @ctrl: controller level device structure |
| 662 | */ |
| 663 | struct platform_nand_data { |
Sebastian Andrzej Siewior | b46daf7 | 2010-10-07 21:48:27 +0200 | [diff] [blame] | 664 | struct platform_nand_chip chip; |
| 665 | struct platform_nand_ctrl ctrl; |
Vitaly Wool | 972edcb | 2007-05-06 18:46:57 +0400 | [diff] [blame] | 666 | }; |
| 667 | |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame] | 668 | /* Some helpers to access the data structures */ |
| 669 | static inline |
| 670 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) |
| 671 | { |
| 672 | struct nand_chip *chip = mtd->priv; |
| 673 | |
| 674 | return chip->priv; |
| 675 | } |
| 676 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 677 | #endif /* __LINUX_MTD_NAND_H */ |