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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/include/linux/mtd/nand.h
3 *
David Woodhousea1452a32010-08-08 20:58:20 +01004 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +020012 * Info:
13 * Contains standard defines and IDs for NAND flash devices
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 *
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +020015 * Changelog:
16 * See git changelog.
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 */
18#ifndef __LINUX_MTD_NAND_H
19#define __LINUX_MTD_NAND_H
20
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/mtd/mtd.h>
Alessandro Rubini30631cb2009-09-20 23:28:14 +020024#include <linux/mtd/flashchip.h>
Alessandro Rubinic62d81b2009-09-20 23:28:04 +020025#include <linux/mtd/bbm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
27struct mtd_info;
David Woodhouse5e81e882010-02-26 18:32:56 +000028struct nand_flash_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070029/* Scan and identify a NAND device */
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +020030extern int nand_scan(struct mtd_info *mtd, int max_chips);
31/*
32 * Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type.
34 */
David Woodhouse5e81e882010-02-26 18:32:56 +000035extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
36 struct nand_flash_dev *table);
David Woodhouse3b85c322006-09-25 17:06:53 +010037extern int nand_scan_tail(struct mtd_info *mtd);
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039/* Free resources held by the NAND device */
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +020040extern void nand_release(struct mtd_info *mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
David Woodhouseb77d95c2006-09-25 21:58:50 +010042/* Internal helper for board drivers which need to override command function */
43extern void nand_wait_ready(struct mtd_info *mtd);
44
Vimal Singh7d70f332010-02-08 15:50:49 +053045/* locks all blockes present in the device */
46extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
47
48/* unlocks specified locked blockes */
49extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
50
Linus Torvalds1da177e2005-04-16 15:20:36 -070051/* The maximum number of NAND chips in an array */
52#define NAND_MAX_CHIPS 8
53
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +020054/*
55 * This constant declares the max. oobsize / page, which
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 * is supported now. If you add a chip with bigger oobsize/page
57 * adjust this accordingly.
58 */
Brian Norris5c709ee2010-08-20 12:36:13 -070059#define NAND_MAX_OOBSIZE 576
60#define NAND_MAX_PAGESIZE 8192
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
62/*
63 * Constants for hardware specific CLE/ALE/NCE function
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020064 *
65 * These are bits which can be or'ed to set/clear multiple
66 * bits in one go.
67 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070068/* Select the chip by setting nCE to low */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020069#define NAND_NCE 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -070070/* Select the command latch by setting CLE to high */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020071#define NAND_CLE 0x02
Linus Torvalds1da177e2005-04-16 15:20:36 -070072/* Select the address latch by setting ALE to high */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020073#define NAND_ALE 0x04
74
75#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
76#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
77#define NAND_CTRL_CHANGE 0x80
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
79/*
80 * Standard NAND flash commands
81 */
82#define NAND_CMD_READ0 0
83#define NAND_CMD_READ1 1
Thomas Gleixner7bc33122006-06-20 20:05:05 +020084#define NAND_CMD_RNDOUT 5
Linus Torvalds1da177e2005-04-16 15:20:36 -070085#define NAND_CMD_PAGEPROG 0x10
86#define NAND_CMD_READOOB 0x50
87#define NAND_CMD_ERASE1 0x60
88#define NAND_CMD_STATUS 0x70
89#define NAND_CMD_STATUS_MULTI 0x71
90#define NAND_CMD_SEQIN 0x80
Thomas Gleixner7bc33122006-06-20 20:05:05 +020091#define NAND_CMD_RNDIN 0x85
Linus Torvalds1da177e2005-04-16 15:20:36 -070092#define NAND_CMD_READID 0x90
93#define NAND_CMD_ERASE2 0xd0
Florian Fainellicaa4b6f2010-08-30 18:32:14 +020094#define NAND_CMD_PARAM 0xec
Linus Torvalds1da177e2005-04-16 15:20:36 -070095#define NAND_CMD_RESET 0xff
96
Vimal Singh7d70f332010-02-08 15:50:49 +053097#define NAND_CMD_LOCK 0x2a
98#define NAND_CMD_UNLOCK1 0x23
99#define NAND_CMD_UNLOCK2 0x24
100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101/* Extended commands for large page devices */
102#define NAND_CMD_READSTART 0x30
Thomas Gleixner7bc33122006-06-20 20:05:05 +0200103#define NAND_CMD_RNDOUTSTART 0xE0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104#define NAND_CMD_CACHEDPROG 0x15
105
David A. Marlin28a48de2005-01-17 18:29:21 +0000106/* Extended commands for AG-AND device */
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000107/*
108 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
David A. Marlin28a48de2005-01-17 18:29:21 +0000109 * there is no way to distinguish that from NAND_CMD_READ0
110 * until the remaining sequence of commands has been completed
111 * so add a high order bit and mask it off in the command.
112 */
113#define NAND_CMD_DEPLETE1 0x100
114#define NAND_CMD_DEPLETE2 0x38
115#define NAND_CMD_STATUS_MULTI 0x71
116#define NAND_CMD_STATUS_ERROR 0x72
117/* multi-bank error status (banks 0-3) */
118#define NAND_CMD_STATUS_ERROR0 0x73
119#define NAND_CMD_STATUS_ERROR1 0x74
120#define NAND_CMD_STATUS_ERROR2 0x75
121#define NAND_CMD_STATUS_ERROR3 0x76
122#define NAND_CMD_STATUS_RESET 0x7f
123#define NAND_CMD_STATUS_CLEAR 0xff
124
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200125#define NAND_CMD_NONE -1
126
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127/* Status bits */
128#define NAND_STATUS_FAIL 0x01
129#define NAND_STATUS_FAIL_N1 0x02
130#define NAND_STATUS_TRUE_READY 0x20
131#define NAND_STATUS_READY 0x40
132#define NAND_STATUS_WP 0x80
133
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000134/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 * Constants for ECC_MODES
136 */
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200137typedef enum {
138 NAND_ECC_NONE,
139 NAND_ECC_SOFT,
140 NAND_ECC_HW,
141 NAND_ECC_HW_SYNDROME,
Sneha Narnakaje6e0cb132009-09-18 12:51:47 -0700142 NAND_ECC_HW_OOB_FIRST,
Ivan Djelic193bd402011-03-11 11:05:33 +0100143 NAND_ECC_SOFT_BCH,
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200144} nand_ecc_modes_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145
146/*
147 * Constants for Hardware ECC
David A. Marlin068e3c02005-01-24 03:07:46 +0000148 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149/* Reset Hardware ECC for read */
150#define NAND_ECC_READ 0
151/* Reset Hardware ECC for write */
152#define NAND_ECC_WRITE 1
153/* Enable Hardware ECC before syndrom is read back from flash */
154#define NAND_ECC_READSYN 2
155
David A. Marlin068e3c02005-01-24 03:07:46 +0000156/* Bit mask for flags passed to do_nand_read_ecc */
157#define NAND_GET_DEVICE 0x80
158
159
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200160/*
161 * Option constants for bizarre disfunctionality and real
162 * features.
163 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164/* Chip can not auto increment pages */
165#define NAND_NO_AUTOINCR 0x00000001
166/* Buswitdh is 16 bit */
167#define NAND_BUSWIDTH_16 0x00000002
168/* Device supports partial programming without padding */
169#define NAND_NO_PADDING 0x00000004
170/* Chip has cache program function */
171#define NAND_CACHEPRG 0x00000008
172/* Chip has copy back function */
173#define NAND_COPYBACK 0x00000010
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200174/*
175 * AND Chip which has 4 banks and a confusing page / block
176 * assignment. See Renesas datasheet for further information.
177 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178#define NAND_IS_AND 0x00000020
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200179/*
180 * Chip has a array of 4 pages which can be read without
181 * additional ready /busy waits.
182 */
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000183#define NAND_4PAGE_ARRAY 0x00000040
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200184/*
185 * Chip requires that BBT is periodically rewritten to prevent
David A. Marlin28a48de2005-01-17 18:29:21 +0000186 * bits from adjacent blocks from 'leaking' in altering data.
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200187 * This happens with the Renesas AG-AND chips, possibly others.
188 */
David A. Marlin28a48de2005-01-17 18:29:21 +0000189#define BBT_AUTO_REFRESH 0x00000080
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200190/*
191 * Chip does not require ready check on read. True
Thomas Gleixner7a306012006-05-25 09:50:16 +0200192 * for all large page devices, as they do not support
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200193 * autoincrement.
194 */
Thomas Gleixner7a306012006-05-25 09:50:16 +0200195#define NAND_NO_READRDY 0x00000100
Thomas Gleixner29072b92006-09-28 15:38:36 +0200196/* Chip does not allow subpage writes */
197#define NAND_NO_SUBPAGE_WRITE 0x00000200
198
Maxim Levitsky93edbad2010-02-22 20:39:40 +0200199/* Device is one of 'new' xD cards that expose fake nand command set */
200#define NAND_BROKEN_XD 0x00000400
201
202/* Device behaves just like nand, but is readonly */
203#define NAND_ROM 0x00000800
204
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205/* Options valid for Samsung large page devices */
206#define NAND_SAMSUNG_LP_OPTIONS \
207 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
208
209/* Macros to identify the above */
210#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
211#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
212#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
213#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
Alexey Korolev96d8b642008-07-29 13:54:11 +0100214/* Large page NAND with SOFT_ECC should support subpage reads */
215#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
216 && (chip->page_shift > 9))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217
218/* Mask to zero out the chip options, which come from the id table */
219#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
220
221/* Non chip related options */
Thomas Gleixner0040bf32005-02-09 12:20:00 +0000222/* This option skips the bbt scan during initialization. */
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200223#define NAND_SKIP_BBTSCAN 0x00020000
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200224/*
225 * This option is defined if the board driver allocates its own buffers
226 * (e.g. because it needs them DMA-coherent).
227 */
David Woodhouse4bf63fc2006-09-25 17:08:04 +0100228#define NAND_OWN_BUFFERS 0x00040000
Ben Dooksb1c6e6d2009-11-02 18:12:33 +0000229/* Chip may not exist, so silence any errors in scan */
230#define NAND_SCAN_SILENT_NODEV 0x00080000
Sebastian Andrzej Siewior453281a2010-10-01 21:37:37 +0200231/* Create an empty BBT with no vendor information if the BBT is available */
Brian Norrisa6267432011-03-18 21:53:41 -0700232#define NAND_CREATE_EMPTY_BBT 0x01000000
Ben Dooksb1c6e6d2009-11-02 18:12:33 +0000233
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234/* Options set by nand scan */
Thomas Gleixnera36ed292006-05-23 11:37:03 +0200235/* Nand scan has allocated controller struct */
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200236#define NAND_CONTROLLER_ALLOC 0x80000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237
Thomas Gleixner29072b92006-09-28 15:38:36 +0200238/* Cell info constants */
239#define NAND_CI_CHIPNR_MSK 0x03
240#define NAND_CI_CELLTYPE_MSK 0x0C
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242/* Keep gcc happy */
243struct nand_chip;
244
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200245struct nand_onfi_params {
246 /* rev info and features block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200247 /* 'O' 'N' 'F' 'I' */
248 u8 sig[4];
249 __le16 revision;
250 __le16 features;
251 __le16 opt_cmd;
252 u8 reserved[22];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200253
254 /* manufacturer information block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200255 char manufacturer[12];
256 char model[20];
257 u8 jedec_id;
258 __le16 date_code;
259 u8 reserved2[13];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200260
261 /* memory organization block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200262 __le32 byte_per_page;
263 __le16 spare_bytes_per_page;
264 __le32 data_bytes_per_ppage;
265 __le16 spare_bytes_per_ppage;
266 __le32 pages_per_block;
267 __le32 blocks_per_lun;
268 u8 lun_count;
269 u8 addr_cycles;
270 u8 bits_per_cell;
271 __le16 bb_per_lun;
272 __le16 block_endurance;
273 u8 guaranteed_good_blocks;
274 __le16 guaranteed_block_endurance;
275 u8 programs_per_page;
276 u8 ppage_attr;
277 u8 ecc_bits;
278 u8 interleaved_bits;
279 u8 interleaved_ops;
280 u8 reserved3[13];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200281
282 /* electrical parameter block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200283 u8 io_pin_capacitance_max;
284 __le16 async_timing_mode;
285 __le16 program_cache_timing_mode;
286 __le16 t_prog;
287 __le16 t_bers;
288 __le16 t_r;
289 __le16 t_ccs;
290 __le16 src_sync_timing_mode;
291 __le16 src_ssync_features;
292 __le16 clk_pin_capacitance_typ;
293 __le16 io_pin_capacitance_typ;
294 __le16 input_pin_capacitance_typ;
295 u8 input_pin_capacitance_max;
296 u8 driver_strenght_support;
297 __le16 t_int_r;
298 __le16 t_ald;
299 u8 reserved4[7];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200300
301 /* vendor */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200302 u8 reserved5[90];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200303
304 __le16 crc;
305} __attribute__((packed));
306
307#define ONFI_CRC_BASE 0x4F4E
308
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309/**
Randy Dunlap844d3b42006-06-28 21:48:27 -0700310 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000311 * @lock: protection lock
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 * @active: the mtd device which holds the controller currently
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200313 * @wq: wait queue to sleep on if a NAND operation is in
314 * progress used instead of the per chip wait queue
315 * when a hw controller is available.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316 */
317struct nand_hw_control {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200318 spinlock_t lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 struct nand_chip *active;
Thomas Gleixner0dfc6242005-05-31 20:39:20 +0100320 wait_queue_head_t wq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321};
322
323/**
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200324 * struct nand_ecc_ctrl - Control structure for ecc
325 * @mode: ecc mode
326 * @steps: number of ecc steps per page
327 * @size: data bytes per ecc step
328 * @bytes: ecc bytes per step
Thomas Gleixner9577f442006-05-25 10:04:31 +0200329 * @total: total number of ecc bytes per page
330 * @prepad: padding information for syndrome based ecc generators
331 * @postpad: padding information for syndrome based ecc generators
Randy Dunlap844d3b42006-06-28 21:48:27 -0700332 * @layout: ECC layout control struct pointer
Ivan Djelic193bd402011-03-11 11:05:33 +0100333 * @priv: pointer to private ecc control data
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200334 * @hwctl: function to control hardware ecc generator. Must only
335 * be provided if an hardware ECC is available
336 * @calculate: function for ecc calculation or readback from ecc hardware
337 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
David Woodhouse956e9442006-09-25 17:12:39 +0100338 * @read_page_raw: function to read a raw page without ECC
339 * @write_page_raw: function to write a raw page without ECC
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200340 * @read_page: function to read a page according to the ecc generator
341 * requirements.
Alexey Korolev17c1d2be2008-08-20 22:32:08 +0100342 * @read_subpage: function to read parts of the page covered by ECC.
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200343 * @write_page: function to write a page according to the ecc generator
344 * requirements.
Randy Dunlap844d3b42006-06-28 21:48:27 -0700345 * @read_oob: function to read chip OOB data
346 * @write_oob: function to write chip OOB data
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200347 */
348struct nand_ecc_ctrl {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200349 nand_ecc_modes_t mode;
350 int steps;
351 int size;
352 int bytes;
353 int total;
354 int prepad;
355 int postpad;
Thomas Gleixner5bd34c02006-05-27 22:16:10 +0200356 struct nand_ecclayout *layout;
Ivan Djelic193bd402011-03-11 11:05:33 +0100357 void *priv;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200358 void (*hwctl)(struct mtd_info *mtd, int mode);
359 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
360 uint8_t *ecc_code);
361 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
362 uint8_t *calc_ecc);
363 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
364 uint8_t *buf, int page);
365 void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
366 const uint8_t *buf);
367 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
368 uint8_t *buf, int page);
369 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
370 uint32_t offs, uint32_t len, uint8_t *buf);
371 void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
372 const uint8_t *buf);
373 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
374 int sndcmd);
375 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
376 int page);
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200377};
378
379/**
380 * struct nand_buffers - buffer structure for read/write
381 * @ecccalc: buffer for calculated ecc
382 * @ecccode: buffer for ecc read from flash
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200383 * @databuf: buffer for data - dynamically sized
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200384 *
385 * Do not change the order of buffers. databuf and oobrbuf must be in
386 * consecutive order.
387 */
388struct nand_buffers {
389 uint8_t ecccalc[NAND_MAX_OOBSIZE];
390 uint8_t ecccode[NAND_MAX_OOBSIZE];
David Woodhouse7dcdcbef2006-10-21 17:09:53 +0100391 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200392};
393
394/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 * struct nand_chip - NAND Private Flash Chip Data
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200396 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
397 * flash device
398 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
399 * flash device.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 * @read_byte: [REPLACEABLE] read one byte from the chip
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 * @read_word: [REPLACEABLE] read one word from the chip
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
403 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200404 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip
405 * data.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406 * @select_chip: [REPLACEABLE] select chip nr
407 * @block_bad: [REPLACEABLE] check, if the block is bad
408 * @block_markbad: [REPLACEABLE] mark the block bad
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300409 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200410 * ALE/CLE/nCE. Also used to write command and address
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300411 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
Huang Shijie12a40a52010-09-27 10:43:53 +0800412 * mtd->oobsize, mtd->writesize and so on.
413 * @id_data contains the 8 bytes values of NAND_CMD_READID.
414 * Return with the bus width.
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200415 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing
416 * device ready/busy line. If set to NULL no access to
417 * ready/busy is available and the ready/busy information
418 * is read from the chip status register.
419 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
420 * commands to the chip.
421 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
422 * ready.
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200423 * @ecc: [BOARDSPECIFIC] ecc control ctructure
Randy Dunlap844d3b42006-06-28 21:48:27 -0700424 * @buffers: buffer structure for read/write
425 * @hwcontrol: platform-specific hardware control structure
426 * @ops: oob operation operands
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200427 * @erase_cmd: [INTERN] erase command write function, selectable due
428 * to AND support.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429 * @scan_bbt: [REPLACEABLE] function to scan bad block table
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300430 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200431 * data from array to read regs (tR).
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200432 * @state: [INTERN] the current state of the NAND device
Randy Dunlap844d3b42006-06-28 21:48:27 -0700433 * @oob_poi: poison value buffer
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200434 * @page_shift: [INTERN] number of address bits in a page (column
435 * address bits).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
437 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
438 * @chip_shift: [INTERN] number of address bits in one chip
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200439 * @options: [BOARDSPECIFIC] various chip options. They can partly
440 * be set to inform nand_scan about special functionality.
441 * See the defines for further explanation.
Brian Norris5fb15492011-05-31 16:31:21 -0700442 * @bbt_options: [INTERN] bad block specific options. All options used
443 * here must come from bbm.h. By default, these options
444 * will be copied to the appropriate nand_bbt_descr's.
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200445 * @badblockpos: [INTERN] position of the bad block marker in the oob
446 * area.
Randy Dunlap1534b8b2010-11-18 15:02:21 -0800447 * @badblockbits: [INTERN] number of bits to left-shift the bad block
448 * number
Randy Dunlap552a8272007-02-05 16:28:59 -0800449 * @cellinfo: [INTERN] MLC/multichip data from chip ident
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 * @numchips: [INTERN] number of physical chips
451 * @chipsize: [INTERN] the size of one chip for multichip arrays
452 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200453 * @pagebuf: [INTERN] holds the pagenumber which is currently in
454 * data_buf.
Thomas Gleixner29072b92006-09-28 15:38:36 +0200455 * @subpagesize: [INTERN] holds the subpagesize
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200456 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
457 * non 0 if ONFI supported.
458 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
459 * supported, 0 otherwise.
Thomas Gleixner5bd34c02006-05-27 22:16:10 +0200460 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461 * @bbt: [INTERN] bad block table pointer
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200462 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
463 * lookup.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200465 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
466 * bad block scan.
467 * @controller: [REPLACEABLE] a pointer to a hardware controller
468 * structure which is shared among multiple independend
469 * devices.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 * @priv: [OPTIONAL] pointer to private chip date
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200471 * @errstat: [OPTIONAL] hardware specific function to perform
472 * additional error status checks (determine if errors are
473 * correctable).
Randy Dunlap351edd22006-10-29 22:46:40 -0800474 * @write_page: [REPLACEABLE] High-level page write function
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 */
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000476
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477struct nand_chip {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200478 void __iomem *IO_ADDR_R;
479 void __iomem *IO_ADDR_W;
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000480
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200481 uint8_t (*read_byte)(struct mtd_info *mtd);
482 u16 (*read_word)(struct mtd_info *mtd);
483 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
484 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
485 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
486 void (*select_chip)(struct mtd_info *mtd, int chip);
487 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
488 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
489 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
490 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
491 u8 *id_data);
492 int (*dev_ready)(struct mtd_info *mtd);
493 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
494 int page_addr);
495 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
496 void (*erase_cmd)(struct mtd_info *mtd, int page);
497 int (*scan_bbt)(struct mtd_info *mtd);
498 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
499 int status, int page);
500 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
501 const uint8_t *buf, int page, int cached, int raw);
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200502
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200503 int chip_delay;
504 unsigned int options;
Brian Norris5fb15492011-05-31 16:31:21 -0700505 unsigned int bbt_options;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200506
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200507 int page_shift;
508 int phys_erase_shift;
509 int bbt_erase_shift;
510 int chip_shift;
511 int numchips;
512 uint64_t chipsize;
513 int pagemask;
514 int pagebuf;
515 int subpagesize;
516 uint8_t cellinfo;
517 int badblockpos;
518 int badblockbits;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200519
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200520 int onfi_version;
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200521 struct nand_onfi_params onfi_params;
522
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200523 flstate_t state;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200524
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200525 uint8_t *oob_poi;
526 struct nand_hw_control *controller;
527 struct nand_ecclayout *ecclayout;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200528
529 struct nand_ecc_ctrl ecc;
David Woodhouse4bf63fc2006-09-25 17:08:04 +0100530 struct nand_buffers *buffers;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200531 struct nand_hw_control hwcontrol;
532
Thomas Gleixner8593fbc2006-05-29 03:26:58 +0200533 struct mtd_oob_ops ops;
534
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200535 uint8_t *bbt;
536 struct nand_bbt_descr *bbt_td;
537 struct nand_bbt_descr *bbt_md;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200538
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200539 struct nand_bbt_descr *badblock_pattern;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200540
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200541 void *priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542};
543
544/*
545 * NAND Flash Manufacturer ID Codes
546 */
547#define NAND_MFR_TOSHIBA 0x98
548#define NAND_MFR_SAMSUNG 0xec
549#define NAND_MFR_FUJITSU 0x04
550#define NAND_MFR_NATIONAL 0x8f
551#define NAND_MFR_RENESAS 0x07
552#define NAND_MFR_STMICRO 0x20
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200553#define NAND_MFR_HYNIX 0xad
sshahrom@micron.com8c60e542007-03-21 18:48:02 -0700554#define NAND_MFR_MICRON 0x2c
Steven J. Hill30eb0db2007-07-18 23:29:46 -0500555#define NAND_MFR_AMD 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556
557/**
558 * struct nand_flash_dev - NAND Flash Device ID Structure
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200559 * @name: Identify the device type
560 * @id: device ID code
561 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000562 * If the pagesize is 0, then the real pagesize
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563 * and the eraseize are determined from the
564 * extended id bytes in the chip
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200565 * @erasesize: Size of an erase block in the flash device.
566 * @chipsize: Total chipsize in Mega Bytes
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 * @options: Bitfield to store chip relevant options
568 */
569struct nand_flash_dev {
570 char *name;
571 int id;
572 unsigned long pagesize;
573 unsigned long chipsize;
574 unsigned long erasesize;
575 unsigned long options;
576};
577
578/**
579 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
580 * @name: Manufacturer name
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200581 * @id: manufacturer ID code of device.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582*/
583struct nand_manufacturers {
584 int id;
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200585 char *name;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586};
587
588extern struct nand_flash_dev nand_flash_ids[];
589extern struct nand_manufacturers nand_manuf_ids[];
590
Thomas Gleixnerf5bbdac2006-05-25 10:07:16 +0200591extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
592extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
593extern int nand_default_bbt(struct mtd_info *mtd);
594extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
595extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
596 int allowbbt);
597extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200598 size_t *retlen, uint8_t *buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599
Thomas Gleixner41796c22006-05-23 11:38:59 +0200600/**
601 * struct platform_nand_chip - chip level device structure
Thomas Gleixner41796c22006-05-23 11:38:59 +0200602 * @nr_chips: max. number of chips to scan for
Randy Dunlap844d3b42006-06-28 21:48:27 -0700603 * @chip_offset: chip number offset
Thomas Gleixner8be834f2006-05-27 20:05:26 +0200604 * @nr_partitions: number of partitions pointed to by partitions (or zero)
Thomas Gleixner41796c22006-05-23 11:38:59 +0200605 * @partitions: mtd partition list
606 * @chip_delay: R/B delay value in us
607 * @options: Option flags, e.g. 16bit buswidth
Brian Norrisa40f7342011-05-31 16:31:22 -0700608 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
Thomas Gleixner5bd34c02006-05-27 22:16:10 +0200609 * @ecclayout: ecc layout info structure
Vitaly Wool972edcb2007-05-06 18:46:57 +0400610 * @part_probe_types: NULL-terminated array of probe types
H Hartley Sweetenf36e20c2009-05-12 13:46:59 -0700611 * @set_parts: platform specific function to set partitions
Thomas Gleixner41796c22006-05-23 11:38:59 +0200612 * @priv: hardware controller specific settings
613 */
614struct platform_nand_chip {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200615 int nr_chips;
616 int chip_offset;
617 int nr_partitions;
618 struct mtd_partition *partitions;
619 struct nand_ecclayout *ecclayout;
620 int chip_delay;
621 unsigned int options;
Brian Norrisa40f7342011-05-31 16:31:22 -0700622 unsigned int bbt_options;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200623 const char **part_probe_types;
624 void (*set_parts)(uint64_t size, struct platform_nand_chip *chip);
625 void *priv;
Thomas Gleixner41796c22006-05-23 11:38:59 +0200626};
627
H Hartley Sweetenbf95efd2009-05-12 13:46:58 -0700628/* Keep gcc happy */
629struct platform_device;
630
Thomas Gleixner41796c22006-05-23 11:38:59 +0200631/**
632 * struct platform_nand_ctrl - controller level device structure
H Hartley Sweetenbf95efd2009-05-12 13:46:58 -0700633 * @probe: platform specific function to probe/setup hardware
634 * @remove: platform specific function to remove/teardown hardware
Thomas Gleixner41796c22006-05-23 11:38:59 +0200635 * @hwcontrol: platform specific hardware control structure
636 * @dev_ready: platform specific function to read ready/busy pin
637 * @select_chip: platform specific chip select function
Vitaly Wool972edcb2007-05-06 18:46:57 +0400638 * @cmd_ctrl: platform specific function for controlling
639 * ALE/CLE/nCE. Also used to write command and address
Alexander Clouterd6fed9e2009-05-11 19:28:01 +0100640 * @write_buf: platform specific function for write buffer
641 * @read_buf: platform specific function for read buffer
Randy Dunlap844d3b42006-06-28 21:48:27 -0700642 * @priv: private data to transport driver specific settings
Thomas Gleixner41796c22006-05-23 11:38:59 +0200643 *
644 * All fields are optional and depend on the hardware driver requirements
645 */
646struct platform_nand_ctrl {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200647 int (*probe)(struct platform_device *pdev);
648 void (*remove)(struct platform_device *pdev);
649 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
650 int (*dev_ready)(struct mtd_info *mtd);
651 void (*select_chip)(struct mtd_info *mtd, int chip);
652 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
653 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
654 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
655 void *priv;
Thomas Gleixner41796c22006-05-23 11:38:59 +0200656};
657
Vitaly Wool972edcb2007-05-06 18:46:57 +0400658/**
659 * struct platform_nand_data - container structure for platform-specific data
660 * @chip: chip level chip structure
661 * @ctrl: controller level device structure
662 */
663struct platform_nand_data {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200664 struct platform_nand_chip chip;
665 struct platform_nand_ctrl ctrl;
Vitaly Wool972edcb2007-05-06 18:46:57 +0400666};
667
Thomas Gleixner41796c22006-05-23 11:38:59 +0200668/* Some helpers to access the data structures */
669static inline
670struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
671{
672 struct nand_chip *chip = mtd->priv;
673
674 return chip->priv;
675}
676
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677#endif /* __LINUX_MTD_NAND_H */