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Adam Lee522624f2013-12-18 22:23:38 +08001#ifndef __SDHCI_PCI_H
2#define __SDHCI_PCI_H
3
4/*
5 * PCI device IDs
6 */
7
8#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
9#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
10#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
11#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
12#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
13#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
Alan Cox066173b2014-08-20 13:27:44 +030014#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
15#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
16#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
Andy Shevchenko1f64cec2016-07-12 14:03:42 +030017#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
Adam Lee522624f2013-12-18 22:23:38 +080018#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
19#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
20#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
21#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
22#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
Derek Browne43e968c2014-06-24 06:56:36 -070023#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
Adrian Hunter1f7f2652015-01-05 14:47:58 +020024#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
25#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
26#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
Adrian Hunter06bf9c52015-10-06 10:26:21 +030027#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
Adrian Hunter4fd4c062015-10-21 11:15:45 +030028#define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca
29#define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc
30#define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0
Adrian Hunter01d6b2a2016-04-04 12:40:37 +030031#define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
32#define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc
33#define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0
Adrian Hunter4fd4c062015-10-21 11:15:45 +030034#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
35#define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
36#define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
Adrian Hunter2d1956d2016-11-22 11:03:37 +020037#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
38#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
39#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
Adam Lee522624f2013-12-18 22:23:38 +080040
41/*
42 * PCI registers
43 */
44
45#define PCI_SDHCI_IFPIO 0x00
46#define PCI_SDHCI_IFDMA 0x01
47#define PCI_SDHCI_IFVENDOR 0x02
48
49#define PCI_SLOT_INFO 0x40 /* 8 bits */
50#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
51#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
52
53#define MAX_SLOTS 8
54
55struct sdhci_pci_chip;
56struct sdhci_pci_slot;
57
58struct sdhci_pci_fixes {
59 unsigned int quirks;
60 unsigned int quirks2;
61 bool allow_runtime_pm;
Adrian Hunter77a01222014-01-13 09:49:16 +020062 bool own_cd_for_runtime_pm;
Adam Lee522624f2013-12-18 22:23:38 +080063
64 int (*probe) (struct sdhci_pci_chip *);
65
66 int (*probe_slot) (struct sdhci_pci_slot *);
67 void (*remove_slot) (struct sdhci_pci_slot *, int);
68
69 int (*suspend) (struct sdhci_pci_chip *);
70 int (*resume) (struct sdhci_pci_chip *);
Adrian Hunter6bc09062016-10-05 12:11:23 +030071
72 const struct sdhci_ops *ops;
Adam Lee522624f2013-12-18 22:23:38 +080073};
74
75struct sdhci_pci_slot {
76 struct sdhci_pci_chip *chip;
77 struct sdhci_host *host;
78 struct sdhci_pci_data *data;
79
Adam Lee522624f2013-12-18 22:23:38 +080080 int rst_n_gpio;
81 int cd_gpio;
82 int cd_irq;
83
Adrian Hunterff59c522014-09-24 10:27:31 +030084 int cd_idx;
85 bool cd_override_level;
86
Adam Lee522624f2013-12-18 22:23:38 +080087 void (*hw_reset)(struct sdhci_host *host);
Adrian Huntere1bfad62015-02-06 14:13:00 +020088 int (*select_drive_strength)(struct sdhci_host *host,
89 struct mmc_card *card,
90 unsigned int max_dtr, int host_drv,
91 int card_drv, int *drv_type);
Adam Lee522624f2013-12-18 22:23:38 +080092};
93
94struct sdhci_pci_chip {
95 struct pci_dev *pdev;
96
97 unsigned int quirks;
98 unsigned int quirks2;
99 bool allow_runtime_pm;
100 const struct sdhci_pci_fixes *fixes;
101
102 int num_slots; /* Slots on controller */
103 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
104};
105
106#endif /* __SDHCI_PCI_H */