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gerrit-public.fairphone.software / kernel / msm-4.19 / b1afa7822da4b8f49f003cc3a494d524907c1d3d / . / arch / arm / boot / dts / tegra20-harmony.dts
blob: 6145f26a0ec5666a306b398cac7bc33eaa70c3e8 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]3#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]4#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]5
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +0000[diff] [blame]7 model = "NVIDIA Tegra20 Harmony evaluation board";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]8 compatible = "nvidia,harmony", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]15 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]16 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]17 };
18
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]19 host1x@50000000 {
20 hdmi@54280000 {
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]21 status = "okay";
22
23 vdd-supply = <&hdmi_vdd_reg>;
24 pll-supply = <&hdmi_pll_reg>;
25
26 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]27 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
28 GPIO_ACTIVE_HIGH>;
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]29 };
30 };
31
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]32 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]33 pinctrl-names = "default";
34 pinctrl-0 = <&state_default>;
35
36 state_default: pinmux {
37 ata {
38 nvidia,pins = "ata";
39 nvidia,function = "ide";
40 };
41 atb {
42 nvidia,pins = "atb", "gma", "gme";
43 nvidia,function = "sdio4";
44 };
45 atc {
46 nvidia,pins = "atc";
47 nvidia,function = "nand";
48 };
49 atd {
50 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
51 "spia", "spib", "spic";
52 nvidia,function = "gmi";
53 };
54 cdev1 {
55 nvidia,pins = "cdev1";
56 nvidia,function = "plla_out";
57 };
58 cdev2 {
59 nvidia,pins = "cdev2";
60 nvidia,function = "pllp_out4";
61 };
62 crtp {
63 nvidia,pins = "crtp";
64 nvidia,function = "crt";
65 };
66 csus {
67 nvidia,pins = "csus";
68 nvidia,function = "vi_sensor_clk";
69 };
70 dap1 {
71 nvidia,pins = "dap1";
72 nvidia,function = "dap1";
73 };
74 dap2 {
75 nvidia,pins = "dap2";
76 nvidia,function = "dap2";
77 };
78 dap3 {
79 nvidia,pins = "dap3";
80 nvidia,function = "dap3";
81 };
82 dap4 {
83 nvidia,pins = "dap4";
84 nvidia,function = "dap4";
85 };
86 ddc {
87 nvidia,pins = "ddc";
88 nvidia,function = "i2c2";
89 };
90 dta {
91 nvidia,pins = "dta", "dtd";
92 nvidia,function = "sdio2";
93 };
94 dtb {
95 nvidia,pins = "dtb", "dtc", "dte";
96 nvidia,function = "rsvd1";
97 };
98 dtf {
99 nvidia,pins = "dtf";
100 nvidia,function = "i2c3";
101 };
102 gmc {
103 nvidia,pins = "gmc";
104 nvidia,function = "uartd";
105 };
106 gpu7 {
107 nvidia,pins = "gpu7";
108 nvidia,function = "rtck";
109 };
110 gpv {
111 nvidia,pins = "gpv", "slxa", "slxk";
112 nvidia,function = "pcie";
113 };
114 hdint {
115 nvidia,pins = "hdint", "pta";
116 nvidia,function = "hdmi";
117 };
118 i2cp {
119 nvidia,pins = "i2cp";
120 nvidia,function = "i2cp";
121 };
122 irrx {
123 nvidia,pins = "irrx", "irtx";
124 nvidia,function = "uarta";
125 };
126 kbca {
127 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
128 "kbce", "kbcf";
129 nvidia,function = "kbc";
130 };
131 lcsn {
132 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
133 "ld3", "ld4", "ld5", "ld6", "ld7",
134 "ld8", "ld9", "ld10", "ld11", "ld12",
135 "ld13", "ld14", "ld15", "ld16", "ld17",
136 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
137 "lhs", "lm0", "lm1", "lpp", "lpw0",
138 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
139 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
140 "lvs";
141 nvidia,function = "displaya";
142 };
143 owc {
144 nvidia,pins = "owc", "spdi", "spdo", "uac";
145 nvidia,function = "rsvd2";
146 };
147 pmc {
148 nvidia,pins = "pmc";
149 nvidia,function = "pwr_on";
150 };
151 rm {
152 nvidia,pins = "rm";
153 nvidia,function = "i2c1";
154 };
155 sdb {
156 nvidia,pins = "sdb", "sdc", "sdd";
157 nvidia,function = "pwm";
158 };
159 sdio1 {
160 nvidia,pins = "sdio1";
161 nvidia,function = "sdio1";
162 };
163 slxc {
164 nvidia,pins = "slxc", "slxd";
165 nvidia,function = "spdif";
166 };
167 spid {
168 nvidia,pins = "spid", "spie", "spif";
169 nvidia,function = "spi1";
170 };
171 spig {
172 nvidia,pins = "spig", "spih";
173 nvidia,function = "spi2_alt";
174 };
175 uaa {
176 nvidia,pins = "uaa", "uab", "uda";
177 nvidia,function = "ulpi";
178 };
179 uad {
180 nvidia,pins = "uad";
181 nvidia,function = "irda";
182 };
183 uca {
184 nvidia,pins = "uca", "ucb";
185 nvidia,function = "uartc";
186 };
187 conf_ata {
188 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]189 "cdev1", "cdev2", "dap1", "dtb", "gma",
190 "gmb", "gmc", "gmd", "gme", "gpu7",
191 "gpv", "i2cp", "pta", "rm", "slxa",
192 "slxk", "spia", "spib", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]195 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]196 conf_ck32 {
197 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
198 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]199 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]200 };
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]201 conf_csus {
202 nvidia,pins = "csus", "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]203 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
204 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]205 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]206 conf_crtp {
207 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
208 "dtc", "dte", "dtf", "gpu", "sdio1",
209 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]210 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]213 };
214 conf_ddc {
215 nvidia,pins = "ddc", "dta", "dtd", "kbca",
216 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
217 "sdc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]218 nvidia,pull = <TEGRA_PIN_PULL_UP>;
219 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]220 };
221 conf_hdint {
222 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
223 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
224 "lvp0", "owc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]225 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]226 };
227 conf_irrx {
228 nvidia,pins = "irrx", "irtx", "sdd", "spic",
229 "spie", "spih", "uaa", "uab", "uad",
230 "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
232 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]233 };
234 conf_lc {
235 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]236 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]237 };
238 conf_ld0 {
239 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
240 "ld5", "ld6", "ld7", "ld8", "ld9",
241 "ld10", "ld11", "ld12", "ld13", "ld14",
242 "ld15", "ld16", "ld17", "ldi", "lhp0",
243 "lhp1", "lhp2", "lhs", "lm0", "lpp",
244 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
245 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]246 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]247 };
248 conf_ld17_0 {
249 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
250 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]251 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]252 };
253 };
254 };
255
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]256 i2s@70002800 {
257 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]258 };
259
260 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]261 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]262 };
263
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]264 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]265 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]266 clock-frequency = <400000>;
267
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]268 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]269 compatible = "wlf,wm8903";
270 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]271 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]272 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]273
274 gpio-controller;
275 #gpio-cells = <2>;
276
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]277 micdet-cfg = <0>;
278 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]279 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]280 };
281 };
282
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]283 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]284 status = "okay";
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]285 clock-frequency = <100000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]286 };
287
288 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]289 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]290 clock-frequency = <400000>;
291 };
292
293 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]294 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]295 clock-frequency = <400000>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]296
297 pmic: tps6586x@34 {
298 compatible = "ti,tps6586x";
299 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]300 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]301
Stephen Warrenbe972c32012-09-11 11:40:04 -0600[diff] [blame]302 ti,system-power-controller;
303
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]304 #gpio-cells = <2>;
305 gpio-controller;
306
307 sys-supply = <&vdd_5v0_reg>;
308 vin-sm0-supply = <&sys_reg>;
309 vin-sm1-supply = <&sys_reg>;
310 vin-sm2-supply = <&sys_reg>;
311 vinldo01-supply = <&sm2_reg>;
312 vinldo23-supply = <&sm2_reg>;
313 vinldo4-supply = <&sm2_reg>;
314 vinldo678-supply = <&sm2_reg>;
315 vinldo9-supply = <&sm2_reg>;
316
317 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]318 sys_reg: sys {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]319 regulator-name = "vdd_sys";
320 regulator-always-on;
321 };
322
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]323 sm0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]324 regulator-name = "vdd_sm0,vdd_core";
325 regulator-min-microvolt = <1200000>;
326 regulator-max-microvolt = <1200000>;
327 regulator-always-on;
328 };
329
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]330 sm1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]331 regulator-name = "vdd_sm1,vdd_cpu";
332 regulator-min-microvolt = <1000000>;
333 regulator-max-microvolt = <1000000>;
334 regulator-always-on;
335 };
336
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]337 sm2_reg: sm2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]338 regulator-name = "vdd_sm2,vin_ldo*";
339 regulator-min-microvolt = <3700000>;
340 regulator-max-microvolt = <3700000>;
341 regulator-always-on;
342 };
343
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]344 pci_clk_reg: ldo0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]345 regulator-name = "vdd_ldo0,vddio_pex_clk";
346 regulator-min-microvolt = <3300000>;
347 regulator-max-microvolt = <3300000>;
348 };
349
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]350 ldo1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]351 regulator-name = "vdd_ldo1,avdd_pll*";
352 regulator-min-microvolt = <1100000>;
353 regulator-max-microvolt = <1100000>;
354 regulator-always-on;
355 };
356
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]357 ldo2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]358 regulator-name = "vdd_ldo2,vdd_rtc";
359 regulator-min-microvolt = <1200000>;
360 regulator-max-microvolt = <1200000>;
361 };
362
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]363 ldo3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]364 regulator-name = "vdd_ldo3,avdd_usb*";
365 regulator-min-microvolt = <3300000>;
366 regulator-max-microvolt = <3300000>;
367 regulator-always-on;
368 };
369
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]370 ldo4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]371 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
372 regulator-min-microvolt = <1800000>;
373 regulator-max-microvolt = <1800000>;
374 regulator-always-on;
375 };
376
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]377 ldo5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]378 regulator-name = "vdd_ldo5,vcore_mmc";
379 regulator-min-microvolt = <2850000>;
380 regulator-max-microvolt = <2850000>;
381 regulator-always-on;
382 };
383
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]384 ldo6 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]385 regulator-name = "vdd_ldo6,avdd_vdac";
386 regulator-min-microvolt = <1800000>;
387 regulator-max-microvolt = <1800000>;
388 };
389
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]390 hdmi_vdd_reg: ldo7 {
Stephen Warren740418e2012-09-20 15:20:39 -0600[diff] [blame]391 regulator-name = "vdd_ldo7,avdd_hdmi";
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]392 regulator-min-microvolt = <3300000>;
393 regulator-max-microvolt = <3300000>;
394 };
395
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]396 hdmi_pll_reg: ldo8 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]397 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
398 regulator-min-microvolt = <1800000>;
399 regulator-max-microvolt = <1800000>;
400 };
401
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]402 ldo9 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]403 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
404 regulator-min-microvolt = <2850000>;
405 regulator-max-microvolt = <2850000>;
406 regulator-always-on;
407 };
408
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]409 ldo_rtc {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]410 regulator-name = "vdd_rtc_out,vdd_cell";
411 regulator-min-microvolt = <3300000>;
412 regulator-max-microvolt = <3300000>;
413 regulator-always-on;
414 };
415 };
416 };
Thierry Reding42d25342012-11-09 22:58:43 +0100[diff] [blame]417
418 temperature-sensor@4c {
419 compatible = "adi,adt7461";
420 reg = <0x4c>;
421 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]422 };
423
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]424 kbc@7000e200 {
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]425 status = "okay";
426 nvidia,debounce-delay-ms = <2>;
427 nvidia,repeat-delay-ms = <160>;
428 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
429 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]430 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
431 MATRIX_KEY(0x00, 0x03, KEY_S)
432 MATRIX_KEY(0x00, 0x04, KEY_A)
433 MATRIX_KEY(0x00, 0x05, KEY_Z)
434 MATRIX_KEY(0x00, 0x07, KEY_FN)
435 MATRIX_KEY(0x01, 0x07, KEY_MENU)
436 MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
437 MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
438 MATRIX_KEY(0x03, 0x00, KEY_5)
439 MATRIX_KEY(0x03, 0x01, KEY_4)
440 MATRIX_KEY(0x03, 0x02, KEY_R)
441 MATRIX_KEY(0x03, 0x03, KEY_E)
442 MATRIX_KEY(0x03, 0x04, KEY_F)
443 MATRIX_KEY(0x03, 0x05, KEY_D)
444 MATRIX_KEY(0x03, 0x06, KEY_X)
445 MATRIX_KEY(0x04, 0x00, KEY_7)
446 MATRIX_KEY(0x04, 0x01, KEY_6)
447 MATRIX_KEY(0x04, 0x02, KEY_T)
448 MATRIX_KEY(0x04, 0x03, KEY_H)
449 MATRIX_KEY(0x04, 0x04, KEY_G)
450 MATRIX_KEY(0x04, 0x05, KEY_V)
451 MATRIX_KEY(0x04, 0x06, KEY_C)
452 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
453 MATRIX_KEY(0x05, 0x00, KEY_9)
454 MATRIX_KEY(0x05, 0x01, KEY_8)
455 MATRIX_KEY(0x05, 0x02, KEY_U)
456 MATRIX_KEY(0x05, 0x03, KEY_Y)
457 MATRIX_KEY(0x05, 0x04, KEY_J)
458 MATRIX_KEY(0x05, 0x05, KEY_N)
459 MATRIX_KEY(0x05, 0x06, KEY_B)
460 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
461 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
462 MATRIX_KEY(0x06, 0x01, KEY_0)
463 MATRIX_KEY(0x06, 0x02, KEY_O)
464 MATRIX_KEY(0x06, 0x03, KEY_I)
465 MATRIX_KEY(0x06, 0x04, KEY_L)
466 MATRIX_KEY(0x06, 0x05, KEY_K)
467 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
468 MATRIX_KEY(0x06, 0x07, KEY_M)
469 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
470 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
471 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
472 MATRIX_KEY(0x07, 0x07, KEY_MENU)
473 MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
474 MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
475 MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
476 MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
477 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
478 MATRIX_KEY(0x0B, 0x01, KEY_P)
479 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
480 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
481 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
482 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
483 MATRIX_KEY(0x0C, 0x00, KEY_F10)
484 MATRIX_KEY(0x0C, 0x01, KEY_F9)
485 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
486 MATRIX_KEY(0x0C, 0x03, KEY_3)
487 MATRIX_KEY(0x0C, 0x04, KEY_2)
488 MATRIX_KEY(0x0C, 0x05, KEY_UP)
489 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
490 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
491 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
492 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
493 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
494 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
495 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
496 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
497 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
498 MATRIX_KEY(0x0E, 0x00, KEY_F11)
499 MATRIX_KEY(0x0E, 0x01, KEY_F12)
500 MATRIX_KEY(0x0E, 0x02, KEY_F8)
501 MATRIX_KEY(0x0E, 0x03, KEY_Q)
502 MATRIX_KEY(0x0E, 0x04, KEY_F4)
503 MATRIX_KEY(0x0E, 0x05, KEY_F3)
504 MATRIX_KEY(0x0E, 0x06, KEY_1)
505 MATRIX_KEY(0x0E, 0x07, KEY_F7)
506 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
507 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
508 MATRIX_KEY(0x0F, 0x02, KEY_F5)
509 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
510 MATRIX_KEY(0x0F, 0x04, KEY_F1)
511 MATRIX_KEY(0x0F, 0x05, KEY_F2)
512 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
513 MATRIX_KEY(0x0F, 0x07, KEY_F6)
514 MATRIX_KEY(0x14, 0x00, KEY_KP7)
515 MATRIX_KEY(0x15, 0x00, KEY_KP9)
516 MATRIX_KEY(0x15, 0x01, KEY_KP8)
517 MATRIX_KEY(0x15, 0x02, KEY_KP4)
518 MATRIX_KEY(0x15, 0x04, KEY_KP1)
519 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
520 MATRIX_KEY(0x16, 0x02, KEY_KP6)
521 MATRIX_KEY(0x16, 0x03, KEY_KP5)
522 MATRIX_KEY(0x16, 0x04, KEY_KP3)
523 MATRIX_KEY(0x16, 0x05, KEY_KP2)
524 MATRIX_KEY(0x16, 0x07, KEY_KP0)
525 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
526 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
527 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
528 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
529 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
530 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
531 MATRIX_KEY(0x1D, 0x04, KEY_END)
532 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
533 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
534 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
535 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
536 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
537 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
538 MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]539 };
540
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]541 pmc@7000e400 {
542 nvidia,invert-interrupt;
543 nvidia,suspend-mode = <1>;
544 nvidia,cpu-pwr-good-time = <5000>;
545 nvidia,cpu-pwr-off-time = <5000>;
546 nvidia,core-pwr-good-time = <3845 3845>;
547 nvidia,core-pwr-off-time = <3875>;
548 nvidia,sys-clock-req-active-high;
549 };
550
551 pcie-controller@80003000 {
552 pex-clk-supply = <&pci_clk_reg>;
553 vdd-supply = <&pci_vdd_reg>;
554 status = "okay";
555
556 pci@1,0 {
557 status = "okay";
558 };
559
560 pci@2,0 {
561 status = "okay";
562 };
563 };
564
565 usb@c5000000 {
566 status = "okay";
567 };
568
569 usb-phy@c5000000 {
570 status = "okay";
571 };
572
573 usb@c5004000 {
574 status = "okay";
575 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
576 GPIO_ACTIVE_LOW>;
577 };
578
579 usb-phy@c5004000 {
580 status = "okay";
581 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
582 GPIO_ACTIVE_LOW>;
583 };
584
585 usb@c5008000 {
586 status = "okay";
587 };
588
589 usb-phy@c5008000 {
590 status = "okay";
591 };
592
593 sdhci@c8000200 {
594 status = "okay";
595 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
596 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
597 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
598 bus-width = <4>;
599 };
600
601 sdhci@c8000600 {
602 status = "okay";
603 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
604 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
605 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
606 bus-width = <8>;
607 };
608
609 clocks {
610 compatible = "simple-bus";
611 #address-cells = <1>;
612 #size-cells = <0>;
613
614 clk32k_in: clock@0 {
615 compatible = "fixed-clock";
616 reg=<0>;
617 #clock-cells = <0>;
618 clock-frequency = <32768>;
619 };
620 };
621
622 gpio-keys {
623 compatible = "gpio-keys";
624
625 power {
626 label = "Power";
627 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]628 linux,code = <KEY_POWER>;
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]629 gpio-key,wakeup;
630 };
631 };
632
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]633 regulators {
634 compatible = "simple-bus";
635 #address-cells = <1>;
636 #size-cells = <0>;
637
638 vdd_5v0_reg: regulator@0 {
639 compatible = "regulator-fixed";
640 reg = <0>;
641 regulator-name = "vdd_5v0";
642 regulator-min-microvolt = <5000000>;
643 regulator-max-microvolt = <5000000>;
644 regulator-always-on;
645 };
646
647 regulator@1 {
648 compatible = "regulator-fixed";
649 reg = <1>;
650 regulator-name = "vdd_1v5";
651 regulator-min-microvolt = <1500000>;
652 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]653 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]654 };
655
656 regulator@2 {
657 compatible = "regulator-fixed";
658 reg = <2>;
659 regulator-name = "vdd_1v2";
660 regulator-min-microvolt = <1200000>;
661 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]662 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]663 enable-active-high;
664 };
665
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]666 pci_vdd_reg: regulator@3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]667 compatible = "regulator-fixed";
668 reg = <3>;
669 regulator-name = "vdd_1v05";
670 regulator-min-microvolt = <1050000>;
671 regulator-max-microvolt = <1050000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]672 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]673 enable-active-high;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]674 };
675
676 regulator@4 {
677 compatible = "regulator-fixed";
678 reg = <4>;
679 regulator-name = "vdd_pnl";
680 regulator-min-microvolt = <2800000>;
681 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]682 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]683 enable-active-high;
684 };
685
686 regulator@5 {
687 compatible = "regulator-fixed";
688 reg = <5>;
689 regulator-name = "vdd_bl";
690 regulator-min-microvolt = <2800000>;
691 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]692 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]693 enable-active-high;
694 };
695 };
696
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]697 sound {
698 compatible = "nvidia,tegra-audio-wm8903-harmony",
699 "nvidia,tegra-audio-wm8903";
700 nvidia,model = "NVIDIA Tegra Harmony";
701
702 nvidia,audio-routing =
703 "Headphone Jack", "HPOUTR",
704 "Headphone Jack", "HPOUTL",
705 "Int Spk", "ROP",
706 "Int Spk", "RON",
707 "Int Spk", "LOP",
708 "Int Spk", "LON",
709 "Mic Jack", "MICBIAS",
710 "IN1L", "Mic Jack";
711
712 nvidia,i2s-controller = <&tegra_i2s1>;
713 nvidia,audio-codec = <&wm8903>;
714
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]715 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
716 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
717 GPIO_ACTIVE_HIGH>;
718 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
719 GPIO_ACTIVE_HIGH>;
720 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
721 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]722
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300[diff] [blame]723 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
724 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
725 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]726 clock-names = "pll_a", "pll_a_out0", "mclk";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]727 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]728};