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Paul Walmsleyf2ab9972009-01-28 12:27:37 -07001/*
2 * SMS/SDRC (SDRAM controller) common code for OMAP2/3
3 *
4 * Copyright (C) 2005, 2008 Texas Instruments Inc.
5 * Copyright (C) 2005, 2008 Nokia Corporation
6 *
7 * Tony Lindgren <tony@atomide.com>
8 * Paul Walmsley
9 * Richard Woodruff <r-woodruff2@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
Paul Walmsley87246b72009-01-28 12:27:39 -070015#undef DEBUG
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070016
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/list.h>
21#include <linux/errno.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
Tony Lindgren622297f2012-10-02 14:19:52 -070026#include "../plat-omap/sram.h"
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070027
Paul Walmsleya135eaa2012-09-27 10:33:34 -060028#include "common.h"
29#include "clock.h"
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070030#include "sdrc.h"
31
Jean Pihet58cda882009-07-24 19:43:25 -060032static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
Paul Walmsley87246b72009-01-28 12:27:39 -070033
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070034void __iomem *omap2_sdrc_base;
35void __iomem *omap2_sms_base;
36
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +030037struct omap2_sms_regs {
38 u32 sms_sysconfig;
39};
40
41static struct omap2_sms_regs sms_context;
42
Paul Walmsley98cfe5a2009-05-12 17:27:09 -060043/* SDRC_POWER register bits */
44#define SDRC_POWER_EXTCLKDIS_SHIFT 3
45#define SDRC_POWER_PWDENA_SHIFT 2
46#define SDRC_POWER_PAGEPOLICY_SHIFT 0
Paul Walmsley87246b72009-01-28 12:27:39 -070047
48/**
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +030049 * omap2_sms_save_context - Save SMS registers
50 *
51 * Save SMS registers that need to be restored after off mode.
52 */
53void omap2_sms_save_context(void)
54{
55 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
56}
57
58/**
59 * omap2_sms_restore_context - Restore SMS registers
60 *
61 * Restore SMS registers that need to be Restored after off mode.
62 */
63void omap2_sms_restore_context(void)
64{
65 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
66}
67
68/**
Paul Walmsley87246b72009-01-28 12:27:39 -070069 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
70 * @r: SDRC clock rate (in Hz)
Jean Pihet58cda882009-07-24 19:43:25 -060071 * @sdrc_cs0: chip select 0 ram timings **
72 * @sdrc_cs1: chip select 1 ram timings **
Paul Walmsley87246b72009-01-28 12:27:39 -070073 *
74 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
Jean Pihet58cda882009-07-24 19:43:25 -060075 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
76 * structs,for a given SDRC clock rate 'r'.
77 * These parameters control various timing delays in the SDRAM controller
78 * that are expressed in terms of the number of SDRC clock cycles to
79 * wait; hence the clock rate dependency.
80 *
81 * Supports 2 different timing parameters for both chip selects.
82 *
83 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
84 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
85 * as sdrc_init_params_cs_0.
86 *
87 * Fills in the struct omap_sdrc_params * for each chip select.
88 * Returns 0 upon success or -1 upon failure.
Paul Walmsley87246b72009-01-28 12:27:39 -070089 */
Jean Pihet58cda882009-07-24 19:43:25 -060090int omap2_sdrc_get_params(unsigned long r,
91 struct omap_sdrc_params **sdrc_cs0,
92 struct omap_sdrc_params **sdrc_cs1)
Paul Walmsley87246b72009-01-28 12:27:39 -070093{
Jean Pihet58cda882009-07-24 19:43:25 -060094 struct omap_sdrc_params *sp0, *sp1;
Paul Walmsley87246b72009-01-28 12:27:39 -070095
Jean Pihet58cda882009-07-24 19:43:25 -060096 if (!sdrc_init_params_cs0)
97 return -1;
Kevin Hilman8bd22942009-05-28 10:56:16 -070098
Jean Pihet58cda882009-07-24 19:43:25 -060099 sp0 = sdrc_init_params_cs0;
100 sp1 = sdrc_init_params_cs1;
Paul Walmsley87246b72009-01-28 12:27:39 -0700101
Jean Pihet58cda882009-07-24 19:43:25 -0600102 while (sp0->rate && sp0->rate != r) {
103 sp0++;
104 if (sdrc_init_params_cs1)
105 sp1++;
106 }
Paul Walmsley87246b72009-01-28 12:27:39 -0700107
Jean Pihet58cda882009-07-24 19:43:25 -0600108 if (!sp0->rate)
109 return -1;
Paul Walmsley87246b72009-01-28 12:27:39 -0700110
Jean Pihet58cda882009-07-24 19:43:25 -0600111 *sdrc_cs0 = sp0;
112 *sdrc_cs1 = sp1;
113 return 0;
Paul Walmsley87246b72009-01-28 12:27:39 -0700114}
115
116
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600117void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700118{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600119 omap2_sdrc_base = sdrc;
120 omap2_sms_base = sms;
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700121}
122
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600123/**
124 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
Jean Pihet58cda882009-07-24 19:43:25 -0600125 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
126 * Support for 2 chip selects timings
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600127 *
128 * Turn on smart idle modes for SDRAM scheduler and controller.
129 * Program a known-good configuration for the SDRC to deal with buggy
130 * bootloaders.
131 */
Jean Pihet58cda882009-07-24 19:43:25 -0600132void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
133 struct omap_sdrc_params *sdrc_cs1)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700134{
135 u32 l;
136
137 l = sms_read_reg(SMS_SYSCONFIG);
138 l &= ~(0x3 << 3);
139 l |= (0x2 << 3);
140 sms_write_reg(l, SMS_SYSCONFIG);
141
142 l = sdrc_read_reg(SDRC_SYSCONFIG);
143 l &= ~(0x3 << 3);
144 l |= (0x2 << 3);
145 sdrc_write_reg(l, SDRC_SYSCONFIG);
Paul Walmsley87246b72009-01-28 12:27:39 -0700146
Jean Pihet58cda882009-07-24 19:43:25 -0600147 sdrc_init_params_cs0 = sdrc_cs0;
148 sdrc_init_params_cs1 = sdrc_cs1;
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600149
150 /* XXX Enable SRFRONIDLEREQ here also? */
Paul Walmsley75f251e2009-07-24 19:44:01 -0600151 /*
152 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
153 * can cause random memory corruption
154 */
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600155 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600156 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
157 sdrc_write_reg(l, SDRC_POWER);
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +0300158 omap2_sms_save_context();
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700159}