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Auke Kok9a799d72007-09-15 14:07:45 -07001/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Mark Rustad2d40cd12016-04-01 12:18:35 -07004 Copyright(c) 1999 - 2016 Intel Corporation.
Auke Kok9a799d72007-09-15 14:07:45 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Jacob Kellerb89aae72014-02-22 01:23:50 +000023 Linux NICS <linux.nics@intel.com>
Auke Kok9a799d72007-09-15 14:07:45 -070024 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_PHY_H_
30#define _IXGBE_PHY_H_
31
32#include "ixgbe_type.h"
Jesse Brandeburgc44ade92008-09-11 19:59:59 -070033#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
Emil Tantilov07ce8702012-12-19 07:14:17 +000034#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
Auke Kok9a799d72007-09-15 14:07:45 -070035
Jesse Brandeburgc44ade92008-09-11 19:59:59 -070036/* EEPROM byte offsets */
Don Skidmore8f583322013-07-27 06:25:38 +000037#define IXGBE_SFF_IDENTIFIER 0x0
38#define IXGBE_SFF_IDENTIFIER_SFP 0x3
39#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
40#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
41#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
42#define IXGBE_SFF_1GBE_COMP_CODES 0x6
43#define IXGBE_SFF_10GBE_COMP_CODES 0x3
44#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
45#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
46#define IXGBE_SFF_SFF_8472_SWAP 0x5C
47#define IXGBE_SFF_SFF_8472_COMP 0x5E
48#define IXGBE_SFF_SFF_8472_OSCB 0x6E
49#define IXGBE_SFF_SFF_8472_ESCB 0x76
50#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD
51#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
52#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
53#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
Emil Tantilov9a84fea2013-08-16 23:11:14 +000054#define IXGBE_SFF_QSFP_CONNECTOR 0x82
Don Skidmore8f583322013-07-27 06:25:38 +000055#define IXGBE_SFF_QSFP_10GBE_COMP 0x83
56#define IXGBE_SFF_QSFP_1GBE_COMP 0x86
Emil Tantilov9a84fea2013-08-16 23:11:14 +000057#define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92
58#define IXGBE_SFF_QSFP_DEVICE_TECH 0x93
Auke Kok9a799d72007-09-15 14:07:45 -070059
Jesse Brandeburgc44ade92008-09-11 19:59:59 -070060/* Bitmasks */
Jeff Kirsherb0007482013-10-01 04:33:53 -070061#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
62#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
63#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
64#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
65#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
66#define IXGBE_SFF_1GBASET_CAPABLE 0x8
67#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
68#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
Mark Rustad6d373a12015-08-08 16:18:28 -070069#define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
70#define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8
71#define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0
Jeff Kirsherb0007482013-10-01 04:33:53 -070072#define IXGBE_SFF_ADDRESSING_MODE 0x4
73#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
74#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
Emil Tantilov9a84fea2013-08-16 23:11:14 +000075#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23
76#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0
Jeff Kirsherb0007482013-10-01 04:33:53 -070077#define IXGBE_I2C_EEPROM_READ_MASK 0x100
78#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
79#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
80#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
81#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
82#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
Don Skidmore6a14ee02014-12-05 03:59:50 +000083#define IXGBE_CS4227 0xBE /* CS4227 address */
Mark Rustad2d40cd12016-04-01 12:18:35 -070084#define IXGBE_CS4227_GLOBAL_ID_LSB 0
85#define IXGBE_CS4227_GLOBAL_ID_MSB 1
Mark Rustad542b6ee2015-08-08 16:18:38 -070086#define IXGBE_CS4227_SCRATCH 2
Mark Rustad2d40cd12016-04-01 12:18:35 -070087#define IXGBE_CS4223_PHY_ID 0x7003 /* Quad port */
88#define IXGBE_CS4227_PHY_ID 0x3003 /* Dual port */
Mark Rustad542b6ee2015-08-08 16:18:38 -070089#define IXGBE_CS4227_RESET_PENDING 0x1357
90#define IXGBE_CS4227_RESET_COMPLETE 0x5AA5
91#define IXGBE_CS4227_RETRIES 15
92#define IXGBE_CS4227_EFUSE_STATUS 0x0181
Mark Rustade23f3332015-08-08 16:18:33 -070093#define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to set speed */
94#define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to set EDC */
95#define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to set speed */
96#define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */
Mark Rustad542b6ee2015-08-08 16:18:38 -070097#define IXGBE_CS4227_EEPROM_STATUS 0x5001
98#define IXGBE_CS4227_EEPROM_LOAD_OK 0x0001
Mark Rustade23f3332015-08-08 16:18:33 -070099#define IXGBE_CS4227_SPEED_1G 0x8000
100#define IXGBE_CS4227_SPEED_10G 0
Don Skidmore6a14ee02014-12-05 03:59:50 +0000101#define IXGBE_CS4227_EDC_MODE_CX1 0x0002
102#define IXGBE_CS4227_EDC_MODE_SR 0x0004
Mark Rustad542b6ee2015-08-08 16:18:38 -0700103#define IXGBE_CS4227_EDC_MODE_DIAG 0x0008
104#define IXGBE_CS4227_RESET_HOLD 500 /* microseconds */
105#define IXGBE_CS4227_RESET_DELAY 500 /* milliseconds */
106#define IXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */
107#define IXGBE_PE 0xE0 /* Port expander addr */
108#define IXGBE_PE_OUTPUT 1 /* Output reg offset */
109#define IXGBE_PE_CONFIG 3 /* Config reg offset */
Jacob Kellerb4f47a42016-04-13 16:08:22 -0700110#define IXGBE_PE_BIT1 BIT(1)
Don Skidmore6a14ee02014-12-05 03:59:50 +0000111
Emil Tantilov0b0c2b32011-02-26 06:40:16 +0000112/* Flow control defines */
113#define IXGBE_TAF_SYM_PAUSE 0x400
114#define IXGBE_TAF_ASM_PAUSE 0x800
115
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700116/* Bit-shift macros */
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000117#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
118#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
119#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700120
121/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
122#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
123#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
124#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000125#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700126
Donald Skidmorec4900be2008-11-20 21:11:42 -0800127/* I2C SDA and SCL timing parameters for standard mode */
128#define IXGBE_I2C_T_HD_STA 4
129#define IXGBE_I2C_T_LOW 5
130#define IXGBE_I2C_T_HIGH 4
131#define IXGBE_I2C_T_SU_STA 5
132#define IXGBE_I2C_T_HD_DATA 5
133#define IXGBE_I2C_T_SU_DATA 1
134#define IXGBE_I2C_T_RISE 1
135#define IXGBE_I2C_T_FALL 1
136#define IXGBE_I2C_T_SU_STO 4
137#define IXGBE_I2C_T_BUF 5
138
Mark Rustad56f6ed12015-08-08 16:18:22 -0700139#define IXGBE_SFP_DETECT_RETRIES 2
140
Mallikarjuna R Chilakala119fc602010-05-20 23:07:06 -0700141#define IXGBE_TN_LASI_STATUS_REG 0x9005
142#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700143
Emil Tantilov07ce8702012-12-19 07:14:17 +0000144/* SFP+ SFF-8472 Compliance code */
145#define IXGBE_SFF_SFF_8472_UNSUP 0x00
146
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700147s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
148s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
149s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000150 u32 device_type, u16 *phy_data);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700151s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000152 u32 device_type, u16 phy_data);
Emil Tantilov3dcc2f42013-05-29 06:23:05 +0000153s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
154 u32 device_type, u16 *phy_data);
155s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
156 u32 device_type, u16 phy_data);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700157s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
158s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000159 ixgbe_link_speed speed,
160 bool autoneg_wait_to_complete);
Don Skidmorea391f1d2010-11-16 19:27:15 -0800161s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000162 ixgbe_link_speed *speed,
163 bool *autoneg);
Jean Sacren6425f0f2014-03-11 05:57:56 +0000164bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
Auke Kok9a799d72007-09-15 14:07:45 -0700165
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700166/* PHY specific */
167s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000168 ixgbe_link_speed *speed,
169 bool *link_up);
Emil Tantilov9dda1732011-03-05 01:28:07 +0000170s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700171s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000172 u16 *firmware_version);
Don Skidmorefe15e8e12010-11-16 19:27:16 -0800173s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000174 u16 *firmware_version);
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700175
Donald Skidmorec4900be2008-11-20 21:11:42 -0800176s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
Don Skidmore961fac82015-06-09 16:09:47 -0700177s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
Don Skidmore8f583322013-07-27 06:25:38 +0000178s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
Donald Skidmorec4900be2008-11-20 21:11:42 -0800179s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
180s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000181 u16 *list_offset,
182 u16 *data_offset);
Mallikarjuna R Chilakala119fc602010-05-20 23:07:06 -0700183s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000184s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000185 u8 dev_addr, u8 *data);
Mark Rustadbb5ce9a2015-08-08 16:18:02 -0700186s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
187 u8 dev_addr, u8 *data);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000188s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000189 u8 dev_addr, u8 data);
Mark Rustadbb5ce9a2015-08-08 16:18:02 -0700190s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
191 u8 dev_addr, u8 data);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000192s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000193 u8 *eeprom_data);
Emil Tantilov07ce8702012-12-19 07:14:17 +0000194s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
195 u8 *sff8472_data);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000196s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000197 u8 eeprom_data);
Don Skidmore28abba02014-11-29 05:22:43 +0000198s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
199 u16 reg, u16 *val);
Mark Rustadbb5ce9a2015-08-08 16:18:02 -0700200s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
201 u16 reg, u16 *val);
Don Skidmore28abba02014-11-29 05:22:43 +0000202s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
203 u16 reg, u16 val);
Mark Rustadbb5ce9a2015-08-08 16:18:02 -0700204s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
205 u16 reg, u16 val);
Auke Kok9a799d72007-09-15 14:07:45 -0700206#endif /* _IXGBE_PHY_H_ */