Peter De Schrijver | add29e6 | 2011-10-12 14:53:05 +0300 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Laxman Dewangan | 6bccbd5 | 2013-12-02 18:39:57 +0530 | [diff] [blame] | 3 | #include <dt-bindings/input/input.h> |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 4 | #include "tegra20.dtsi" |
Peter De Schrijver | add29e6 | 2011-10-12 14:53:05 +0300 | [diff] [blame] | 5 | |
| 6 | / { |
Bryan Wu | 8fef5df | 2012-12-20 09:41:29 +0000 | [diff] [blame] | 7 | model = "NVIDIA Tegra20 Ventana evaluation board"; |
Peter De Schrijver | add29e6 | 2011-10-12 14:53:05 +0300 | [diff] [blame] | 8 | compatible = "nvidia,ventana", "nvidia,tegra20"; |
| 9 | |
Peter De Schrijver | add29e6 | 2011-10-12 14:53:05 +0300 | [diff] [blame] | 10 | memory { |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 11 | reg = <0x00000000 0x40000000>; |
Peter De Schrijver | add29e6 | 2011-10-12 14:53:05 +0300 | [diff] [blame] | 12 | }; |
| 13 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 14 | host1x@50000000 { |
| 15 | hdmi@54280000 { |
Stephen Warren | 97d5520 | 2013-01-02 14:53:21 -0700 | [diff] [blame] | 16 | status = "okay"; |
| 17 | |
| 18 | vdd-supply = <&hdmi_vdd_reg>; |
| 19 | pll-supply = <&hdmi_pll_reg>; |
| 20 | |
| 21 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 22 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 23 | GPIO_ACTIVE_HIGH>; |
Stephen Warren | 97d5520 | 2013-01-02 14:53:21 -0700 | [diff] [blame] | 24 | }; |
| 25 | }; |
| 26 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 27 | pinmux@70000014 { |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 28 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&state_default>; |
| 30 | |
| 31 | state_default: pinmux { |
| 32 | ata { |
| 33 | nvidia,pins = "ata"; |
| 34 | nvidia,function = "ide"; |
| 35 | }; |
| 36 | atb { |
| 37 | nvidia,pins = "atb", "gma", "gme"; |
| 38 | nvidia,function = "sdio4"; |
| 39 | }; |
| 40 | atc { |
| 41 | nvidia,pins = "atc"; |
| 42 | nvidia,function = "nand"; |
| 43 | }; |
| 44 | atd { |
| 45 | nvidia,pins = "atd", "ate", "gmb", "spia", |
| 46 | "spib", "spic"; |
| 47 | nvidia,function = "gmi"; |
| 48 | }; |
| 49 | cdev1 { |
| 50 | nvidia,pins = "cdev1"; |
| 51 | nvidia,function = "plla_out"; |
| 52 | }; |
| 53 | cdev2 { |
| 54 | nvidia,pins = "cdev2"; |
| 55 | nvidia,function = "pllp_out4"; |
| 56 | }; |
| 57 | crtp { |
| 58 | nvidia,pins = "crtp", "lm1"; |
| 59 | nvidia,function = "crt"; |
| 60 | }; |
| 61 | csus { |
| 62 | nvidia,pins = "csus"; |
| 63 | nvidia,function = "vi_sensor_clk"; |
| 64 | }; |
| 65 | dap1 { |
| 66 | nvidia,pins = "dap1"; |
| 67 | nvidia,function = "dap1"; |
| 68 | }; |
| 69 | dap2 { |
| 70 | nvidia,pins = "dap2"; |
| 71 | nvidia,function = "dap2"; |
| 72 | }; |
| 73 | dap3 { |
| 74 | nvidia,pins = "dap3"; |
| 75 | nvidia,function = "dap3"; |
| 76 | }; |
| 77 | dap4 { |
| 78 | nvidia,pins = "dap4"; |
| 79 | nvidia,function = "dap4"; |
| 80 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 81 | dta { |
| 82 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
| 83 | nvidia,function = "vi"; |
| 84 | }; |
| 85 | dtf { |
| 86 | nvidia,pins = "dtf"; |
| 87 | nvidia,function = "i2c3"; |
| 88 | }; |
| 89 | gmc { |
| 90 | nvidia,pins = "gmc"; |
| 91 | nvidia,function = "uartd"; |
| 92 | }; |
| 93 | gmd { |
| 94 | nvidia,pins = "gmd"; |
| 95 | nvidia,function = "sflash"; |
| 96 | }; |
| 97 | gpu { |
| 98 | nvidia,pins = "gpu"; |
| 99 | nvidia,function = "pwm"; |
| 100 | }; |
| 101 | gpu7 { |
| 102 | nvidia,pins = "gpu7"; |
| 103 | nvidia,function = "rtck"; |
| 104 | }; |
| 105 | gpv { |
| 106 | nvidia,pins = "gpv", "slxa", "slxk"; |
| 107 | nvidia,function = "pcie"; |
| 108 | }; |
| 109 | hdint { |
Mark Zhang | cf63346 | 2012-10-25 14:52:30 +0800 | [diff] [blame] | 110 | nvidia,pins = "hdint"; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 111 | nvidia,function = "hdmi"; |
| 112 | }; |
| 113 | i2cp { |
| 114 | nvidia,pins = "i2cp"; |
| 115 | nvidia,function = "i2cp"; |
| 116 | }; |
| 117 | irrx { |
| 118 | nvidia,pins = "irrx", "irtx"; |
| 119 | nvidia,function = "uartb"; |
| 120 | }; |
| 121 | kbca { |
| 122 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 123 | "kbce", "kbcf"; |
| 124 | nvidia,function = "kbc"; |
| 125 | }; |
| 126 | lcsn { |
| 127 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", |
| 128 | "lsdi", "lvp0"; |
| 129 | nvidia,function = "rsvd4"; |
| 130 | }; |
| 131 | ld0 { |
| 132 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 133 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 134 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 135 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 136 | "lhp1", "lhp2", "lhs", "lpp", "lpw0", |
| 137 | "lpw2", "lsc0", "lsc1", "lsck", "lsda", |
| 138 | "lspi", "lvp1", "lvs"; |
| 139 | nvidia,function = "displaya"; |
| 140 | }; |
Mark Zhang | cf63346 | 2012-10-25 14:52:30 +0800 | [diff] [blame] | 141 | owc { |
| 142 | nvidia,pins = "owc", "spdi", "spdo", "uac"; |
| 143 | nvidia,function = "rsvd2"; |
| 144 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 145 | pmc { |
| 146 | nvidia,pins = "pmc"; |
| 147 | nvidia,function = "pwr_on"; |
| 148 | }; |
| 149 | rm { |
| 150 | nvidia,pins = "rm"; |
| 151 | nvidia,function = "i2c1"; |
| 152 | }; |
| 153 | sdb { |
| 154 | nvidia,pins = "sdb", "sdc", "sdd", "slxc"; |
| 155 | nvidia,function = "sdio3"; |
| 156 | }; |
| 157 | sdio1 { |
| 158 | nvidia,pins = "sdio1"; |
| 159 | nvidia,function = "sdio1"; |
| 160 | }; |
| 161 | slxd { |
| 162 | nvidia,pins = "slxd"; |
| 163 | nvidia,function = "spdif"; |
| 164 | }; |
| 165 | spid { |
| 166 | nvidia,pins = "spid", "spie", "spif"; |
| 167 | nvidia,function = "spi1"; |
| 168 | }; |
| 169 | spig { |
| 170 | nvidia,pins = "spig", "spih"; |
| 171 | nvidia,function = "spi2_alt"; |
| 172 | }; |
| 173 | uaa { |
| 174 | nvidia,pins = "uaa", "uab", "uda"; |
| 175 | nvidia,function = "ulpi"; |
| 176 | }; |
| 177 | uad { |
| 178 | nvidia,pins = "uad"; |
| 179 | nvidia,function = "irda"; |
| 180 | }; |
| 181 | uca { |
| 182 | nvidia,pins = "uca", "ucb"; |
| 183 | nvidia,function = "uartc"; |
| 184 | }; |
| 185 | conf_ata { |
| 186 | nvidia,pins = "ata", "atb", "atc", "atd", |
| 187 | "cdev1", "cdev2", "dap1", "dap2", |
| 188 | "dap4", "ddc", "dtf", "gma", "gmc", |
| 189 | "gme", "gpu", "gpu7", "i2cp", "irrx", |
| 190 | "irtx", "pta", "rm", "sdc", "sdd", |
| 191 | "slxc", "slxd", "slxk", "spdi", "spdo", |
| 192 | "uac", "uad", "uca", "ucb", "uda"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 193 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 194 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 195 | }; |
| 196 | conf_ate { |
| 197 | nvidia,pins = "ate", "csus", "dap3", "gmd", |
| 198 | "gpv", "owc", "spia", "spib", "spic", |
| 199 | "spid", "spie", "spig"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 200 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 201 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 202 | }; |
| 203 | conf_ck32 { |
| 204 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 205 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 206 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 207 | }; |
| 208 | conf_crtp { |
| 209 | nvidia,pins = "crtp", "gmb", "slxa", "spih"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 210 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 211 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 212 | }; |
| 213 | conf_dta { |
| 214 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 215 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 216 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 217 | }; |
| 218 | conf_dte { |
| 219 | nvidia,pins = "dte", "spif"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 220 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 221 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 222 | }; |
| 223 | conf_hdint { |
| 224 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
| 225 | "lpw1", "lsck", "lsda", "lsdi", "lvp0"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 226 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 227 | }; |
| 228 | conf_kbca { |
| 229 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 230 | "kbce", "kbcf", "sdio1", "uaa", "uab"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 231 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 232 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 233 | }; |
| 234 | conf_lc { |
| 235 | nvidia,pins = "lc", "ls"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 236 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 237 | }; |
| 238 | conf_ld0 { |
| 239 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 240 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 241 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 242 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 243 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
| 244 | "lpw0", "lpw2", "lsc0", "lsc1", "lspi", |
| 245 | "lvp1", "lvs", "pmc", "sdb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 246 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 247 | }; |
| 248 | conf_ld17_0 { |
| 249 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 250 | "ld23_22"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 251 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 252 | }; |
Wei Ni | c729429 | 2012-09-21 16:54:58 +0800 | [diff] [blame] | 253 | drive_sdio1 { |
| 254 | nvidia,pins = "drive_sdio1"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 255 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 256 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; |
| 257 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
Wei Ni | c729429 | 2012-09-21 16:54:58 +0800 | [diff] [blame] | 258 | nvidia,pull-down-strength = <31>; |
| 259 | nvidia,pull-up-strength = <31>; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 260 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 261 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
Wei Ni | c729429 | 2012-09-21 16:54:58 +0800 | [diff] [blame] | 262 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 263 | }; |
Mark Zhang | cf63346 | 2012-10-25 14:52:30 +0800 | [diff] [blame] | 264 | |
| 265 | state_i2cmux_ddc: pinmux_i2cmux_ddc { |
| 266 | ddc { |
| 267 | nvidia,pins = "ddc"; |
| 268 | nvidia,function = "i2c2"; |
| 269 | }; |
| 270 | pta { |
| 271 | nvidia,pins = "pta"; |
| 272 | nvidia,function = "rsvd4"; |
| 273 | }; |
| 274 | }; |
| 275 | |
| 276 | state_i2cmux_pta: pinmux_i2cmux_pta { |
| 277 | ddc { |
| 278 | nvidia,pins = "ddc"; |
| 279 | nvidia,function = "rsvd4"; |
| 280 | }; |
| 281 | pta { |
| 282 | nvidia,pins = "pta"; |
| 283 | nvidia,function = "i2c2"; |
| 284 | }; |
| 285 | }; |
| 286 | |
| 287 | state_i2cmux_idle: pinmux_i2cmux_idle { |
| 288 | ddc { |
| 289 | nvidia,pins = "ddc"; |
| 290 | nvidia,function = "rsvd4"; |
| 291 | }; |
| 292 | pta { |
| 293 | nvidia,pins = "pta"; |
| 294 | nvidia,function = "rsvd4"; |
| 295 | }; |
| 296 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 297 | }; |
| 298 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 299 | i2s@70002800 { |
| 300 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 301 | }; |
| 302 | |
| 303 | serial@70006300 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 304 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 305 | }; |
| 306 | |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 307 | i2c@7000c000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 308 | status = "okay"; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 309 | clock-frequency = <400000>; |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 310 | |
| 311 | wm8903: wm8903@1a { |
| 312 | compatible = "wlf,wm8903"; |
| 313 | reg = <0x1a>; |
| 314 | interrupt-parent = <&gpio>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 315 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 316 | |
| 317 | gpio-controller; |
| 318 | #gpio-cells = <2>; |
| 319 | |
| 320 | micdet-cfg = <0>; |
| 321 | micdet-delay = <100>; |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 322 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 323 | }; |
Laxman Dewangan | b46b0b5 | 2012-04-23 17:41:36 +0530 | [diff] [blame] | 324 | |
| 325 | /* ALS and proximity sensor */ |
| 326 | isl29018@44 { |
| 327 | compatible = "isil,isl29018"; |
| 328 | reg = <0x44>; |
| 329 | interrupt-parent = <&gpio>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 330 | interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | b46b0b5 | 2012-04-23 17:41:36 +0530 | [diff] [blame] | 331 | }; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 332 | }; |
| 333 | |
| 334 | i2c@7000c400 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 335 | status = "okay"; |
Stephen Warren | 97d5520 | 2013-01-02 14:53:21 -0700 | [diff] [blame] | 336 | clock-frequency = <100000>; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 337 | }; |
| 338 | |
Mark Zhang | cf63346 | 2012-10-25 14:52:30 +0800 | [diff] [blame] | 339 | i2cmux { |
| 340 | compatible = "i2c-mux-pinctrl"; |
| 341 | #address-cells = <1>; |
| 342 | #size-cells = <0>; |
| 343 | |
| 344 | i2c-parent = <&{/i2c@7000c400}>; |
| 345 | |
| 346 | pinctrl-names = "ddc", "pta", "idle"; |
| 347 | pinctrl-0 = <&state_i2cmux_ddc>; |
| 348 | pinctrl-1 = <&state_i2cmux_pta>; |
| 349 | pinctrl-2 = <&state_i2cmux_idle>; |
| 350 | |
Stephen Warren | 97d5520 | 2013-01-02 14:53:21 -0700 | [diff] [blame] | 351 | hdmi_ddc: i2c@0 { |
Mark Zhang | cf63346 | 2012-10-25 14:52:30 +0800 | [diff] [blame] | 352 | reg = <0>; |
| 353 | #address-cells = <1>; |
| 354 | #size-cells = <0>; |
| 355 | }; |
| 356 | |
| 357 | i2c@1 { |
| 358 | reg = <1>; |
| 359 | #address-cells = <1>; |
| 360 | #size-cells = <0>; |
| 361 | }; |
| 362 | }; |
| 363 | |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 364 | i2c@7000c500 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 365 | status = "okay"; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 366 | clock-frequency = <400000>; |
| 367 | }; |
| 368 | |
| 369 | i2c@7000d000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 370 | status = "okay"; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 371 | clock-frequency = <400000>; |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 372 | |
| 373 | pmic: tps6586x@34 { |
| 374 | compatible = "ti,tps6586x"; |
| 375 | reg = <0x34>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 376 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 377 | |
Stephen Warren | 44b12ef | 2012-09-11 11:42:26 -0600 | [diff] [blame] | 378 | ti,system-power-controller; |
| 379 | |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 380 | #gpio-cells = <2>; |
| 381 | gpio-controller; |
| 382 | |
| 383 | sys-supply = <&vdd_5v0_reg>; |
| 384 | vin-sm0-supply = <&sys_reg>; |
| 385 | vin-sm1-supply = <&sys_reg>; |
| 386 | vin-sm2-supply = <&sys_reg>; |
| 387 | vinldo01-supply = <&sm2_reg>; |
| 388 | vinldo23-supply = <&sm2_reg>; |
| 389 | vinldo4-supply = <&sm2_reg>; |
| 390 | vinldo678-supply = <&sm2_reg>; |
| 391 | vinldo9-supply = <&sm2_reg>; |
| 392 | |
| 393 | regulators { |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 394 | sys_reg: sys { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 395 | regulator-name = "vdd_sys"; |
| 396 | regulator-always-on; |
| 397 | }; |
| 398 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 399 | sm0 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 400 | regulator-name = "vdd_sm0,vdd_core"; |
| 401 | regulator-min-microvolt = <1200000>; |
| 402 | regulator-max-microvolt = <1200000>; |
| 403 | regulator-always-on; |
| 404 | }; |
| 405 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 406 | sm1 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 407 | regulator-name = "vdd_sm1,vdd_cpu"; |
| 408 | regulator-min-microvolt = <1000000>; |
| 409 | regulator-max-microvolt = <1000000>; |
| 410 | regulator-always-on; |
| 411 | }; |
| 412 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 413 | sm2_reg: sm2 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 414 | regulator-name = "vdd_sm2,vin_ldo*"; |
| 415 | regulator-min-microvolt = <3700000>; |
| 416 | regulator-max-microvolt = <3700000>; |
| 417 | regulator-always-on; |
| 418 | }; |
| 419 | |
| 420 | /* LDO0 is not connected to anything */ |
| 421 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 422 | ldo1 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 423 | regulator-name = "vdd_ldo1,avdd_pll*"; |
| 424 | regulator-min-microvolt = <1100000>; |
| 425 | regulator-max-microvolt = <1100000>; |
| 426 | regulator-always-on; |
| 427 | }; |
| 428 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 429 | ldo2 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 430 | regulator-name = "vdd_ldo2,vdd_rtc"; |
| 431 | regulator-min-microvolt = <1200000>; |
| 432 | regulator-max-microvolt = <1200000>; |
| 433 | }; |
| 434 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 435 | ldo3 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 436 | regulator-name = "vdd_ldo3,avdd_usb*"; |
| 437 | regulator-min-microvolt = <3300000>; |
| 438 | regulator-max-microvolt = <3300000>; |
| 439 | regulator-always-on; |
| 440 | }; |
| 441 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 442 | ldo4 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 443 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
| 444 | regulator-min-microvolt = <1800000>; |
| 445 | regulator-max-microvolt = <1800000>; |
| 446 | regulator-always-on; |
| 447 | }; |
| 448 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 449 | ldo5 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 450 | regulator-name = "vdd_ldo5,vcore_mmc"; |
| 451 | regulator-min-microvolt = <2850000>; |
| 452 | regulator-max-microvolt = <2850000>; |
| 453 | regulator-always-on; |
| 454 | }; |
| 455 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 456 | ldo6 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 457 | regulator-name = "vdd_ldo6,avdd_vdac"; |
| 458 | regulator-min-microvolt = <1800000>; |
| 459 | regulator-max-microvolt = <1800000>; |
| 460 | }; |
| 461 | |
Stephen Warren | 97d5520 | 2013-01-02 14:53:21 -0700 | [diff] [blame] | 462 | hdmi_vdd_reg: ldo7 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 463 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
| 464 | regulator-min-microvolt = <3300000>; |
| 465 | regulator-max-microvolt = <3300000>; |
| 466 | }; |
| 467 | |
Stephen Warren | 97d5520 | 2013-01-02 14:53:21 -0700 | [diff] [blame] | 468 | hdmi_pll_reg: ldo8 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 469 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
| 470 | regulator-min-microvolt = <1800000>; |
| 471 | regulator-max-microvolt = <1800000>; |
| 472 | }; |
| 473 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 474 | ldo9 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 475 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
| 476 | regulator-min-microvolt = <2850000>; |
| 477 | regulator-max-microvolt = <2850000>; |
| 478 | regulator-always-on; |
| 479 | }; |
| 480 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 481 | ldo_rtc { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 482 | regulator-name = "vdd_rtc_out,vdd_cell"; |
| 483 | regulator-min-microvolt = <3300000>; |
| 484 | regulator-max-microvolt = <3300000>; |
| 485 | regulator-always-on; |
| 486 | }; |
| 487 | }; |
| 488 | }; |
Thierry Reding | ee9f726 | 2012-11-09 23:01:21 +0100 | [diff] [blame] | 489 | |
| 490 | temperature-sensor@4c { |
| 491 | compatible = "onnn,nct1008"; |
| 492 | reg = <0x4c>; |
| 493 | }; |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 494 | }; |
| 495 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 496 | pmc@7000e400 { |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 497 | nvidia,invert-interrupt; |
Joseph Lo | 47d2d63 | 2013-08-12 17:40:07 +0800 | [diff] [blame] | 498 | nvidia,suspend-mode = <1>; |
Joseph Lo | a44a019 | 2013-04-03 19:31:52 +0800 | [diff] [blame] | 499 | nvidia,cpu-pwr-good-time = <2000>; |
| 500 | nvidia,cpu-pwr-off-time = <100>; |
| 501 | nvidia,core-pwr-good-time = <3845 3845>; |
| 502 | nvidia,core-pwr-off-time = <458>; |
| 503 | nvidia,sys-clock-req-active-high; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 504 | }; |
| 505 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 506 | usb@c5000000 { |
| 507 | status = "okay"; |
| 508 | }; |
| 509 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 510 | usb-phy@c5000000 { |
| 511 | status = "okay"; |
| 512 | }; |
| 513 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 514 | usb@c5004000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 515 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 516 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 517 | GPIO_ACTIVE_LOW>; |
Venu Byravarasu | 9dffe3b | 2013-05-16 19:42:56 +0530 | [diff] [blame] | 518 | }; |
| 519 | |
| 520 | usb-phy@c5004000 { |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 521 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 522 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 523 | GPIO_ACTIVE_LOW>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 524 | }; |
| 525 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 526 | usb@c5008000 { |
| 527 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 528 | }; |
| 529 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 530 | usb-phy@c5008000 { |
| 531 | status = "okay"; |
| 532 | }; |
| 533 | |
Wei Ni | c729429 | 2012-09-21 16:54:58 +0800 | [diff] [blame] | 534 | sdhci@c8000000 { |
| 535 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 536 | power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
Wei Ni | c729429 | 2012-09-21 16:54:58 +0800 | [diff] [blame] | 537 | bus-width = <4>; |
Joseph Lo | 7a2617a | 2013-04-03 14:34:39 -0600 | [diff] [blame] | 538 | keep-power-in-suspend; |
Wei Ni | c729429 | 2012-09-21 16:54:58 +0800 | [diff] [blame] | 539 | }; |
| 540 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 541 | sdhci@c8000400 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 542 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 543 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 544 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; |
| 545 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; |
Arnd Bergmann | deb88cc | 2012-05-14 22:35:04 +0200 | [diff] [blame] | 546 | bus-width = <4>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 547 | }; |
| 548 | |
| 549 | sdhci@c8000600 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 550 | status = "okay"; |
Arnd Bergmann | deb88cc | 2012-05-14 22:35:04 +0200 | [diff] [blame] | 551 | bus-width = <8>; |
Joseph Lo | 7a2617a | 2013-04-03 14:34:39 -0600 | [diff] [blame] | 552 | non-removable; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 553 | }; |
| 554 | |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 555 | clocks { |
| 556 | compatible = "simple-bus"; |
| 557 | #address-cells = <1>; |
| 558 | #size-cells = <0>; |
| 559 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 560 | clk32k_in: clock@0 { |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 561 | compatible = "fixed-clock"; |
| 562 | reg=<0>; |
| 563 | #clock-cells = <0>; |
| 564 | clock-frequency = <32768>; |
| 565 | }; |
| 566 | }; |
| 567 | |
Joseph Lo | 5741a25 | 2013-04-03 19:31:48 +0800 | [diff] [blame] | 568 | gpio-keys { |
| 569 | compatible = "gpio-keys"; |
| 570 | |
| 571 | power { |
| 572 | label = "Power"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 573 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
Laxman Dewangan | 6bccbd5 | 2013-12-02 18:39:57 +0530 | [diff] [blame] | 574 | linux,code = <KEY_POWER>; |
Joseph Lo | 5741a25 | 2013-04-03 19:31:48 +0800 | [diff] [blame] | 575 | gpio-key,wakeup; |
| 576 | }; |
| 577 | }; |
| 578 | |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 579 | regulators { |
| 580 | compatible = "simple-bus"; |
| 581 | #address-cells = <1>; |
| 582 | #size-cells = <0>; |
| 583 | |
| 584 | vdd_5v0_reg: regulator@0 { |
| 585 | compatible = "regulator-fixed"; |
| 586 | reg = <0>; |
| 587 | regulator-name = "vdd_5v0"; |
| 588 | regulator-min-microvolt = <5000000>; |
| 589 | regulator-max-microvolt = <5000000>; |
| 590 | regulator-always-on; |
| 591 | }; |
| 592 | |
| 593 | regulator@1 { |
| 594 | compatible = "regulator-fixed"; |
| 595 | reg = <1>; |
| 596 | regulator-name = "vdd_1v5"; |
| 597 | regulator-min-microvolt = <1500000>; |
| 598 | regulator-max-microvolt = <1500000>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 599 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 600 | }; |
| 601 | |
| 602 | regulator@2 { |
| 603 | compatible = "regulator-fixed"; |
| 604 | reg = <2>; |
| 605 | regulator-name = "vdd_1v2"; |
| 606 | regulator-min-microvolt = <1200000>; |
| 607 | regulator-max-microvolt = <1200000>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 608 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 609 | enable-active-high; |
| 610 | }; |
| 611 | |
| 612 | regulator@3 { |
| 613 | compatible = "regulator-fixed"; |
| 614 | reg = <3>; |
| 615 | regulator-name = "vdd_pnl"; |
| 616 | regulator-min-microvolt = <2800000>; |
| 617 | regulator-max-microvolt = <2800000>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 618 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 619 | enable-active-high; |
| 620 | }; |
| 621 | |
| 622 | regulator@4 { |
| 623 | compatible = "regulator-fixed"; |
| 624 | reg = <4>; |
| 625 | regulator-name = "vdd_bl"; |
| 626 | regulator-min-microvolt = <2800000>; |
| 627 | regulator-max-microvolt = <2800000>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 628 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
Stephen Warren | 017a010 | 2012-06-20 16:53:41 -0600 | [diff] [blame] | 629 | enable-active-high; |
| 630 | }; |
| 631 | }; |
| 632 | |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 633 | sound { |
| 634 | compatible = "nvidia,tegra-audio-wm8903-ventana", |
| 635 | "nvidia,tegra-audio-wm8903"; |
| 636 | nvidia,model = "NVIDIA Tegra Ventana"; |
| 637 | |
| 638 | nvidia,audio-routing = |
| 639 | "Headphone Jack", "HPOUTR", |
| 640 | "Headphone Jack", "HPOUTL", |
| 641 | "Int Spk", "ROP", |
| 642 | "Int Spk", "RON", |
| 643 | "Int Spk", "LOP", |
| 644 | "Int Spk", "LON", |
| 645 | "Mic Jack", "MICBIAS", |
| 646 | "IN1L", "Mic Jack"; |
| 647 | |
| 648 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 649 | nvidia,audio-codec = <&wm8903>; |
| 650 | |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 651 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 652 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; |
| 653 | nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) |
| 654 | GPIO_ACTIVE_HIGH>; |
| 655 | nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) |
| 656 | GPIO_ACTIVE_HIGH>; |
Stephen Warren | f9cd2b3 | 2013-03-26 16:45:52 -0600 | [diff] [blame] | 657 | |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 658 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 659 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, |
| 660 | <&tegra_car TEGRA20_CLK_CDEV1>; |
Stephen Warren | f9cd2b3 | 2013-03-26 16:45:52 -0600 | [diff] [blame] | 661 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
Stephen Warren | 797acf7 | 2012-01-11 16:09:57 -0700 | [diff] [blame] | 662 | }; |
Peter De Schrijver | add29e6 | 2011-10-12 14:53:05 +0300 | [diff] [blame] | 663 | }; |