blob: 363d125300eacfbef6287644f89af6abe007c920 [file] [log] [blame]
Sarah Sharp74c68742009-04-27 19:52:22 -07001/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include "xhci.h"
24
25#define XHCI_INIT_VALUE 0x0
26
27/* Add verbose debugging later, just print everything for now */
28
29void xhci_dbg_regs(struct xhci_hcd *xhci)
30{
31 u32 temp;
32
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -070033 xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
34 xhci->cap_regs);
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +020035 temp = readl(&xhci->cap_regs->hc_capbase);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -070036 xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
37 &xhci->cap_regs->hc_capbase, temp);
Sarah Sharp74c68742009-04-27 19:52:22 -070038 xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
39 (unsigned int) HC_LENGTH(temp));
Sarah Sharp74c68742009-04-27 19:52:22 -070040 xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
41 (unsigned int) HC_VERSION(temp));
Sarah Sharp74c68742009-04-27 19:52:22 -070042
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -070043 xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
Sarah Sharp74c68742009-04-27 19:52:22 -070044
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +020045 temp = readl(&xhci->cap_regs->run_regs_off);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -070046 xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
47 &xhci->cap_regs->run_regs_off,
Sarah Sharp74c68742009-04-27 19:52:22 -070048 (unsigned int) temp & RTSOFF_MASK);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -070049 xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
Sarah Sharp74c68742009-04-27 19:52:22 -070050
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +020051 temp = readl(&xhci->cap_regs->db_off);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -070052 xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
53 xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
Sarah Sharp74c68742009-04-27 19:52:22 -070054}
55
Sarah Sharp23e3be12009-04-29 19:05:20 -070056static void xhci_print_cap_regs(struct xhci_hcd *xhci)
Sarah Sharp74c68742009-04-27 19:52:22 -070057{
58 u32 temp;
Lu Baolu04abb6d2015-10-01 18:40:31 +030059 u32 hci_version;
Sarah Sharp74c68742009-04-27 19:52:22 -070060
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -070061 xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
Sarah Sharp74c68742009-04-27 19:52:22 -070062
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +020063 temp = readl(&xhci->cap_regs->hc_capbase);
Lu Baolu04abb6d2015-10-01 18:40:31 +030064 hci_version = HC_VERSION(temp);
Sarah Sharp74c68742009-04-27 19:52:22 -070065 xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
66 (unsigned int) temp);
67 xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
68 (unsigned int) HC_LENGTH(temp));
Lu Baolu04abb6d2015-10-01 18:40:31 +030069 xhci_dbg(xhci, "HCIVERSION: 0x%x\n", hci_version);
Sarah Sharp74c68742009-04-27 19:52:22 -070070
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +020071 temp = readl(&xhci->cap_regs->hcs_params1);
Sarah Sharp74c68742009-04-27 19:52:22 -070072 xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
73 (unsigned int) temp);
74 xhci_dbg(xhci, " Max device slots: %u\n",
75 (unsigned int) HCS_MAX_SLOTS(temp));
76 xhci_dbg(xhci, " Max interrupters: %u\n",
77 (unsigned int) HCS_MAX_INTRS(temp));
78 xhci_dbg(xhci, " Max ports: %u\n",
79 (unsigned int) HCS_MAX_PORTS(temp));
80
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +020081 temp = readl(&xhci->cap_regs->hcs_params2);
Sarah Sharp74c68742009-04-27 19:52:22 -070082 xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
83 (unsigned int) temp);
84 xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
85 (unsigned int) HCS_IST(temp));
86 xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
87 (unsigned int) HCS_ERST_MAX(temp));
88
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +020089 temp = readl(&xhci->cap_regs->hcs_params3);
Sarah Sharp74c68742009-04-27 19:52:22 -070090 xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
91 (unsigned int) temp);
92 xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
93 (unsigned int) HCS_U1_LATENCY(temp));
94 xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
95 (unsigned int) HCS_U2_LATENCY(temp));
96
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +020097 temp = readl(&xhci->cap_regs->hcc_params);
Sarah Sharp74c68742009-04-27 19:52:22 -070098 xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
99 xhci_dbg(xhci, " HC generates %s bit addresses\n",
100 HCC_64BIT_ADDR(temp) ? "64" : "32");
Lu Baolu79b80942015-08-06 19:24:00 +0300101 xhci_dbg(xhci, " HC %s Contiguous Frame ID Capability\n",
102 HCC_CFC(temp) ? "has" : "hasn't");
Lu Baolu40a3b772015-08-06 19:24:01 +0300103 xhci_dbg(xhci, " HC %s generate Stopped - Short Package event\n",
104 HCC_SPC(temp) ? "can" : "can't");
Sarah Sharp74c68742009-04-27 19:52:22 -0700105 /* FIXME */
106 xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
107
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200108 temp = readl(&xhci->cap_regs->run_regs_off);
Sarah Sharp74c68742009-04-27 19:52:22 -0700109 xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
Lu Baolu04abb6d2015-10-01 18:40:31 +0300110
111 /* xhci 1.1 controllers have the HCCPARAMS2 register */
112 if (hci_version > 100) {
113 temp = readl(&xhci->cap_regs->hcc_params2);
114 xhci_dbg(xhci, "HCC PARAMS2 0x%x:\n", (unsigned int) temp);
115 xhci_dbg(xhci, " HC %s Force save context capability",
116 HCC2_FSC(temp) ? "supports" : "doesn't support");
117 xhci_dbg(xhci, " HC %s Large ESIT Payload Capability",
118 HCC2_LEC(temp) ? "supports" : "doesn't support");
119 xhci_dbg(xhci, " HC %s Extended TBC capability",
120 HCC2_ETC(temp) ? "supports" : "doesn't support");
121 }
Sarah Sharp74c68742009-04-27 19:52:22 -0700122}
123
Sarah Sharp23e3be12009-04-29 19:05:20 -0700124static void xhci_print_command_reg(struct xhci_hcd *xhci)
Sarah Sharp74c68742009-04-27 19:52:22 -0700125{
126 u32 temp;
127
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200128 temp = readl(&xhci->op_regs->command);
Sarah Sharp74c68742009-04-27 19:52:22 -0700129 xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
130 xhci_dbg(xhci, " HC is %s\n",
131 (temp & CMD_RUN) ? "running" : "being stopped");
132 xhci_dbg(xhci, " HC has %sfinished hard reset\n",
133 (temp & CMD_RESET) ? "not " : "");
134 xhci_dbg(xhci, " Event Interrupts %s\n",
135 (temp & CMD_EIE) ? "enabled " : "disabled");
136 xhci_dbg(xhci, " Host System Error Interrupts %s\n",
Alex Hebb334e92012-03-22 15:06:59 +0800137 (temp & CMD_HSEIE) ? "enabled " : "disabled");
Sarah Sharp74c68742009-04-27 19:52:22 -0700138 xhci_dbg(xhci, " HC has %sfinished light reset\n",
139 (temp & CMD_LRESET) ? "not " : "");
140}
141
Sarah Sharp23e3be12009-04-29 19:05:20 -0700142static void xhci_print_status(struct xhci_hcd *xhci)
Sarah Sharp74c68742009-04-27 19:52:22 -0700143{
144 u32 temp;
145
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200146 temp = readl(&xhci->op_regs->status);
Sarah Sharp74c68742009-04-27 19:52:22 -0700147 xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
148 xhci_dbg(xhci, " Event ring is %sempty\n",
149 (temp & STS_EINT) ? "not " : "");
150 xhci_dbg(xhci, " %sHost System Error\n",
151 (temp & STS_FATAL) ? "WARNING: " : "No ");
152 xhci_dbg(xhci, " HC is %s\n",
153 (temp & STS_HALT) ? "halted" : "running");
154}
155
Sarah Sharp23e3be12009-04-29 19:05:20 -0700156static void xhci_print_op_regs(struct xhci_hcd *xhci)
Sarah Sharp74c68742009-04-27 19:52:22 -0700157{
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700158 xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
Sarah Sharp74c68742009-04-27 19:52:22 -0700159 xhci_print_command_reg(xhci);
160 xhci_print_status(xhci);
161}
162
Sarah Sharp23e3be12009-04-29 19:05:20 -0700163static void xhci_print_ports(struct xhci_hcd *xhci)
Sarah Sharp0f2a7932009-04-27 19:57:12 -0700164{
Matt Evans28ccd292011-03-29 13:40:46 +1100165 __le32 __iomem *addr;
Sarah Sharp0f2a7932009-04-27 19:57:12 -0700166 int i, j;
167 int ports;
168 char *names[NUM_PORT_REGS] = {
169 "status",
170 "power",
171 "link",
172 "reserved",
173 };
174
175 ports = HCS_MAX_PORTS(xhci->hcs_params1);
176 addr = &xhci->op_regs->port_status_base;
177 for (i = 0; i < ports; i++) {
Felipe Balbi98871e92017-01-23 14:20:04 +0200178 for (j = 0; j < NUM_PORT_REGS; j++) {
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700179 xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
180 addr, names[j],
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200181 (unsigned int) readl(addr));
Sarah Sharp0f2a7932009-04-27 19:57:12 -0700182 addr++;
183 }
184 }
185}
186
Dmitry Torokhov09ece302011-02-08 16:29:33 -0800187void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
Sarah Sharp74c68742009-04-27 19:52:22 -0700188{
Dmitry Torokhov09ece302011-02-08 16:29:33 -0800189 struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
190 void __iomem *addr;
Sarah Sharp74c68742009-04-27 19:52:22 -0700191 u32 temp;
Sarah Sharp8e595a52009-07-27 12:03:31 -0700192 u64 temp_64;
Sarah Sharp74c68742009-04-27 19:52:22 -0700193
194 addr = &ir_set->irq_pending;
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200195 temp = readl(addr);
Sarah Sharp74c68742009-04-27 19:52:22 -0700196 if (temp == XHCI_INIT_VALUE)
197 return;
198
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700199 xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num);
Sarah Sharp74c68742009-04-27 19:52:22 -0700200
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700201 xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr,
202 (unsigned int)temp);
Sarah Sharp74c68742009-04-27 19:52:22 -0700203
204 addr = &ir_set->irq_control;
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200205 temp = readl(addr);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700206 xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr,
207 (unsigned int)temp);
Sarah Sharp74c68742009-04-27 19:52:22 -0700208
209 addr = &ir_set->erst_size;
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200210 temp = readl(addr);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700211 xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr,
212 (unsigned int)temp);
Sarah Sharp74c68742009-04-27 19:52:22 -0700213
214 addr = &ir_set->rsvd;
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200215 temp = readl(addr);
Sarah Sharp74c68742009-04-27 19:52:22 -0700216 if (temp != XHCI_INIT_VALUE)
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700217 xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n",
218 addr, (unsigned int)temp);
Sarah Sharp74c68742009-04-27 19:52:22 -0700219
Sarah Sharp8e595a52009-07-27 12:03:31 -0700220 addr = &ir_set->erst_base;
Sarah Sharpf7b2e402014-01-30 13:27:49 -0800221 temp_64 = xhci_read_64(xhci, addr);
Sarah Sharp8e595a52009-07-27 12:03:31 -0700222 xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
223 addr, temp_64);
Sarah Sharp74c68742009-04-27 19:52:22 -0700224
Sarah Sharp8e595a52009-07-27 12:03:31 -0700225 addr = &ir_set->erst_dequeue;
Sarah Sharpf7b2e402014-01-30 13:27:49 -0800226 temp_64 = xhci_read_64(xhci, addr);
Sarah Sharp8e595a52009-07-27 12:03:31 -0700227 xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
228 addr, temp_64);
Sarah Sharp74c68742009-04-27 19:52:22 -0700229}
230
231void xhci_print_run_regs(struct xhci_hcd *xhci)
232{
233 u32 temp;
234 int i;
235
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700236 xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200237 temp = readl(&xhci->run_regs->microframe_index);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700238 xhci_dbg(xhci, " %p: Microframe index = 0x%x\n",
239 &xhci->run_regs->microframe_index,
Sarah Sharp74c68742009-04-27 19:52:22 -0700240 (unsigned int) temp);
Felipe Balbi98871e92017-01-23 14:20:04 +0200241 for (i = 0; i < 7; i++) {
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200242 temp = readl(&xhci->run_regs->rsvd[i]);
Sarah Sharp74c68742009-04-27 19:52:22 -0700243 if (temp != XHCI_INIT_VALUE)
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700244 xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n",
245 &xhci->run_regs->rsvd[i],
Sarah Sharp74c68742009-04-27 19:52:22 -0700246 i, (unsigned int) temp);
247 }
248}
249
250void xhci_print_registers(struct xhci_hcd *xhci)
251{
252 xhci_print_cap_regs(xhci);
253 xhci_print_op_regs(xhci);
Sarah Sharp0f2a7932009-04-27 19:57:12 -0700254 xhci_print_ports(xhci);
Sarah Sharp74c68742009-04-27 19:52:22 -0700255}
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700256
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700257void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
258{
259 int i;
Felipe Balbi98871e92017-01-23 14:20:04 +0200260 for (i = 0; i < 4; i++)
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700261 xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
262 i*4, trb->generic.field[i]);
263}
264
265/**
266 * Debug a transfer request block (TRB).
267 */
268void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
269{
270 u64 address;
Matt Evans28ccd292011-03-29 13:40:46 +1100271 u32 type = le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700272
273 switch (type) {
274 case TRB_TYPE(TRB_LINK):
275 xhci_dbg(xhci, "Link TRB:\n");
276 xhci_print_trb_offsets(xhci, trb);
277
Matt Evans28ccd292011-03-29 13:40:46 +1100278 address = le64_to_cpu(trb->link.segment_ptr);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700279 xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
280
281 xhci_dbg(xhci, "Interrupter target = 0x%x\n",
Matt Evans28ccd292011-03-29 13:40:46 +1100282 GET_INTR_TARGET(le32_to_cpu(trb->link.intr_target)));
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700283 xhci_dbg(xhci, "Cycle bit = %u\n",
Matt Evansf5960b62011-06-01 10:22:55 +1000284 le32_to_cpu(trb->link.control) & TRB_CYCLE);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700285 xhci_dbg(xhci, "Toggle cycle bit = %u\n",
Matt Evansf5960b62011-06-01 10:22:55 +1000286 le32_to_cpu(trb->link.control) & LINK_TOGGLE);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700287 xhci_dbg(xhci, "No Snoop bit = %u\n",
Matt Evansf5960b62011-06-01 10:22:55 +1000288 le32_to_cpu(trb->link.control) & TRB_NO_SNOOP);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700289 break;
290 case TRB_TYPE(TRB_TRANSFER):
Matt Evans28ccd292011-03-29 13:40:46 +1100291 address = le64_to_cpu(trb->trans_event.buffer);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700292 /*
293 * FIXME: look at flags to figure out if it's an address or if
294 * the data is directly in the buffer field.
295 */
296 xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
297 break;
298 case TRB_TYPE(TRB_COMPLETION):
Matt Evans28ccd292011-03-29 13:40:46 +1100299 address = le64_to_cpu(trb->event_cmd.cmd_trb);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700300 xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
301 xhci_dbg(xhci, "Completion status = %u\n",
Matt Evansf5960b62011-06-01 10:22:55 +1000302 GET_COMP_CODE(le32_to_cpu(trb->event_cmd.status)));
Matt Evans28ccd292011-03-29 13:40:46 +1100303 xhci_dbg(xhci, "Flags = 0x%x\n",
Matt Evansf5960b62011-06-01 10:22:55 +1000304 le32_to_cpu(trb->event_cmd.flags));
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700305 break;
306 default:
307 xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
308 (unsigned int) type>>10);
309 xhci_print_trb_offsets(xhci, trb);
310 break;
311 }
312}
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700313
314/**
315 * Debug a segment with an xHCI ring.
316 *
317 * @return The Link TRB of the segment, or NULL if there is no Link TRB
318 * (which is a bug, since all segments must have a Link TRB).
319 *
320 * Prints out all TRBs in the segment, even those after the Link TRB.
321 *
322 * XXX: should we print out TRBs that the HC owns? As long as we don't
323 * write, that should be fine... We shouldn't expect that the memory pointed to
324 * by the TRB is valid at all. Do we care about ones the HC owns? Probably,
325 * for HC debugging.
326 */
327void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
328{
329 int i;
Matt Evans28ccd292011-03-29 13:40:46 +1100330 u64 addr = seg->dma;
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700331 union xhci_trb *trb = seg->trbs;
332
Felipe Balbi98871e92017-01-23 14:20:04 +0200333 for (i = 0; i < TRBS_PER_SEGMENT; i++) {
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700334 trb = &seg->trbs[i];
Matt Evans28ccd292011-03-29 13:40:46 +1100335 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr,
Matt Evansf5960b62011-06-01 10:22:55 +1000336 lower_32_bits(le64_to_cpu(trb->link.segment_ptr)),
337 upper_32_bits(le64_to_cpu(trb->link.segment_ptr)),
338 le32_to_cpu(trb->link.intr_target),
339 le32_to_cpu(trb->link.control));
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700340 addr += sizeof(*trb);
341 }
342}
343
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700344void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
345{
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700346 xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
347 ring->dequeue,
Sarah Sharp23e3be12009-04-29 19:05:20 -0700348 (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700349 ring->dequeue));
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700350 xhci_dbg(xhci, "Ring deq updated %u times\n",
351 ring->deq_updates);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700352 xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
353 ring->enqueue,
Sarah Sharp23e3be12009-04-29 19:05:20 -0700354 (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700355 ring->enqueue));
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700356 xhci_dbg(xhci, "Ring enq updated %u times\n",
357 ring->enq_updates);
358}
359
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700360/**
361 * Debugging for an xHCI ring, which is a queue broken into multiple segments.
362 *
363 * Print out each segment in the ring. Check that the DMA address in
364 * each link segment actually matches the segment's stored DMA address.
365 * Check that the link end bit is only set at the end of the ring.
366 * Check that the dequeue and enqueue pointers point to real data in this ring
367 * (not some other ring).
368 */
369void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
370{
371 /* FIXME: Throw an error if any segment doesn't have a Link TRB */
372 struct xhci_segment *seg;
373 struct xhci_segment *first_seg = ring->first_seg;
374 xhci_debug_segment(xhci, first_seg);
375
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700376 if (!ring->enq_updates && !ring->deq_updates) {
377 xhci_dbg(xhci, " Ring has not been updated\n");
378 return;
379 }
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700380 for (seg = first_seg->next; seg != first_seg; seg = seg->next)
381 xhci_debug_segment(xhci, seg);
382}
383
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700384void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
385 unsigned int slot_id, unsigned int ep_index,
386 struct xhci_virt_ep *ep)
387{
388 int i;
389 struct xhci_ring *ring;
390
391 if (ep->ep_state & EP_HAS_STREAMS) {
392 for (i = 1; i < ep->stream_info->num_streams; i++) {
393 ring = ep->stream_info->stream_rings[i];
394 xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
395 slot_id, ep_index, i);
396 xhci_debug_segment(xhci, ring->deq_seg);
397 }
398 } else {
399 ring = ep->ring;
400 if (!ring)
401 return;
402 xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
403 slot_id, ep_index);
404 xhci_debug_segment(xhci, ring->deq_seg);
405 }
406}
407
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700408void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
409{
Matt Evans28ccd292011-03-29 13:40:46 +1100410 u64 addr = erst->erst_dma_addr;
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700411 int i;
412 struct xhci_erst_entry *entry;
413
Felipe Balbi98871e92017-01-23 14:20:04 +0200414 for (i = 0; i < erst->num_entries; i++) {
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700415 entry = &erst->entries[i];
Matt Evans28ccd292011-03-29 13:40:46 +1100416 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
417 addr,
418 lower_32_bits(le64_to_cpu(entry->seg_addr)),
419 upper_32_bits(le64_to_cpu(entry->seg_addr)),
Matt Evansf5960b62011-06-01 10:22:55 +1000420 le32_to_cpu(entry->seg_size),
421 le32_to_cpu(entry->rsvd));
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700422 addr += sizeof(*entry);
423 }
424}
425
426void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
427{
Sarah Sharp8e595a52009-07-27 12:03:31 -0700428 u64 val;
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700429
Sarah Sharpf7b2e402014-01-30 13:27:49 -0800430 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
Sarah Sharp8e595a52009-07-27 12:03:31 -0700431 xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
432 lower_32_bits(val));
433 xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
434 upper_32_bits(val));
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700435}
Sarah Sharp3ffbba92009-04-27 19:57:38 -0700436
John Yound115b042009-07-27 12:05:15 -0700437/* Print the last 32 bytes for 64-byte contexts */
438static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
439{
440 int i;
Felipe Balbi98871e92017-01-23 14:20:04 +0200441 for (i = 0; i < 4; i++) {
John Yound115b042009-07-27 12:05:15 -0700442 xhci_dbg(xhci, "@%p (virt) @%08llx "
443 "(dma) %#08llx - rsvd64[%d]\n",
444 &ctx[4 + i], (unsigned long long)dma,
445 ctx[4 + i], i);
446 dma += 8;
447 }
448}
449
Sarah Sharp9c9a7dbf2010-01-04 12:20:17 -0800450char *xhci_get_slot_state(struct xhci_hcd *xhci,
Sarah Sharp2a8f82c2009-12-09 15:59:13 -0800451 struct xhci_container_ctx *ctx)
452{
453 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
454
Matt Evans28ccd292011-03-29 13:40:46 +1100455 switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state))) {
Maarten Lankhorste2b02172011-06-01 23:27:49 +0200456 case SLOT_STATE_ENABLED:
Sarah Sharp2a8f82c2009-12-09 15:59:13 -0800457 return "enabled/disabled";
Maarten Lankhorste2b02172011-06-01 23:27:49 +0200458 case SLOT_STATE_DEFAULT:
Sarah Sharp2a8f82c2009-12-09 15:59:13 -0800459 return "default";
Maarten Lankhorste2b02172011-06-01 23:27:49 +0200460 case SLOT_STATE_ADDRESSED:
Sarah Sharp2a8f82c2009-12-09 15:59:13 -0800461 return "addressed";
Maarten Lankhorste2b02172011-06-01 23:27:49 +0200462 case SLOT_STATE_CONFIGURED:
Sarah Sharp2a8f82c2009-12-09 15:59:13 -0800463 return "configured";
464 default:
465 return "reserved";
466 }
467}
468
Dmitry Torokhov8212a492011-02-08 13:55:59 -0800469static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700470{
471 /* Fields are 32 bits wide, DMA addresses are in bytes */
472 int field_size = 32 / 8;
473 int i;
474
John Yound115b042009-07-27 12:05:15 -0700475 struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
Sarah Sharp018218d2009-08-07 14:04:40 -0700476 dma_addr_t dma = ctx->dma +
477 ((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
John Yound115b042009-07-27 12:05:15 -0700478 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
479
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700480 xhci_dbg(xhci, "Slot Context:\n");
481 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
John Yound115b042009-07-27 12:05:15 -0700482 &slot_ctx->dev_info,
483 (unsigned long long)dma, slot_ctx->dev_info);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700484 dma += field_size;
485 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
John Yound115b042009-07-27 12:05:15 -0700486 &slot_ctx->dev_info2,
487 (unsigned long long)dma, slot_ctx->dev_info2);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700488 dma += field_size;
489 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
John Yound115b042009-07-27 12:05:15 -0700490 &slot_ctx->tt_info,
491 (unsigned long long)dma, slot_ctx->tt_info);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700492 dma += field_size;
493 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
John Yound115b042009-07-27 12:05:15 -0700494 &slot_ctx->dev_state,
495 (unsigned long long)dma, slot_ctx->dev_state);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700496 dma += field_size;
Felipe Balbi98871e92017-01-23 14:20:04 +0200497 for (i = 0; i < 4; i++) {
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700498 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
John Yound115b042009-07-27 12:05:15 -0700499 &slot_ctx->reserved[i], (unsigned long long)dma,
500 slot_ctx->reserved[i], i);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700501 dma += field_size;
502 }
503
John Yound115b042009-07-27 12:05:15 -0700504 if (csz)
505 dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700506}
507
Dmitry Torokhov8212a492011-02-08 13:55:59 -0800508static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
John Yound115b042009-07-27 12:05:15 -0700509 struct xhci_container_ctx *ctx,
510 unsigned int last_ep)
Sarah Sharp3ffbba92009-04-27 19:57:38 -0700511{
512 int i, j;
513 int last_ep_ctx = 31;
514 /* Fields are 32 bits wide, DMA addresses are in bytes */
515 int field_size = 32 / 8;
John Yound115b042009-07-27 12:05:15 -0700516 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
Sarah Sharp3ffbba92009-04-27 19:57:38 -0700517
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700518 if (last_ep < 31)
519 last_ep_ctx = last_ep + 1;
Felipe Balbi98871e92017-01-23 14:20:04 +0200520 for (i = 0; i < last_ep_ctx; i++) {
Julius Werner01c5f442013-04-15 15:55:04 -0700521 unsigned int epaddr = xhci_get_endpoint_address(i);
John Yound115b042009-07-27 12:05:15 -0700522 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
523 dma_addr_t dma = ctx->dma +
Sarah Sharp018218d2009-08-07 14:04:40 -0700524 ((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
John Yound115b042009-07-27 12:05:15 -0700525
Julius Werner01c5f442013-04-15 15:55:04 -0700526 xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n",
527 usb_endpoint_out(epaddr) ? "OUT" : "IN",
528 epaddr & USB_ENDPOINT_NUMBER_MASK, i);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700529 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
John Yound115b042009-07-27 12:05:15 -0700530 &ep_ctx->ep_info,
531 (unsigned long long)dma, ep_ctx->ep_info);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700532 dma += field_size;
533 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
John Yound115b042009-07-27 12:05:15 -0700534 &ep_ctx->ep_info2,
535 (unsigned long long)dma, ep_ctx->ep_info2);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700536 dma += field_size;
537 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
John Yound115b042009-07-27 12:05:15 -0700538 &ep_ctx->deq,
539 (unsigned long long)dma, ep_ctx->deq);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700540 dma += 2*field_size;
541 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
John Yound115b042009-07-27 12:05:15 -0700542 &ep_ctx->tx_info,
543 (unsigned long long)dma, ep_ctx->tx_info);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700544 dma += field_size;
Felipe Balbi98871e92017-01-23 14:20:04 +0200545 for (j = 0; j < 3; j++) {
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700546 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
John Yound115b042009-07-27 12:05:15 -0700547 &ep_ctx->reserved[j],
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700548 (unsigned long long)dma,
John Yound115b042009-07-27 12:05:15 -0700549 ep_ctx->reserved[j], j);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700550 dma += field_size;
551 }
John Yound115b042009-07-27 12:05:15 -0700552
553 if (csz)
554 dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700555 }
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700556}
557
John Yound115b042009-07-27 12:05:15 -0700558void xhci_dbg_ctx(struct xhci_hcd *xhci,
559 struct xhci_container_ctx *ctx,
560 unsigned int last_ep)
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700561{
562 int i;
563 /* Fields are 32 bits wide, DMA addresses are in bytes */
564 int field_size = 32 / 8;
John Yound115b042009-07-27 12:05:15 -0700565 dma_addr_t dma = ctx->dma;
566 int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
Sarah Sharp28c2d2e2009-07-27 12:05:08 -0700567
John Yound115b042009-07-27 12:05:15 -0700568 if (ctx->type == XHCI_CTX_TYPE_INPUT) {
569 struct xhci_input_control_ctx *ctrl_ctx =
Lin Wang4daf9df2015-01-09 16:06:31 +0200570 xhci_get_input_control_ctx(ctx);
Sarah Sharp92f8e762013-04-23 17:11:14 -0700571 if (!ctrl_ctx) {
572 xhci_warn(xhci, "Could not get input context, bad type.\n");
573 return;
574 }
575
John Yound115b042009-07-27 12:05:15 -0700576 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
577 &ctrl_ctx->drop_flags, (unsigned long long)dma,
578 ctrl_ctx->drop_flags);
Sarah Sharp3ffbba92009-04-27 19:57:38 -0700579 dma += field_size;
John Yound115b042009-07-27 12:05:15 -0700580 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
581 &ctrl_ctx->add_flags, (unsigned long long)dma,
582 ctrl_ctx->add_flags);
583 dma += field_size;
Felipe Balbi98871e92017-01-23 14:20:04 +0200584 for (i = 0; i < 6; i++) {
John Yound115b042009-07-27 12:05:15 -0700585 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
586 &ctrl_ctx->rsvd2[i], (unsigned long long)dma,
587 ctrl_ctx->rsvd2[i], i);
588 dma += field_size;
589 }
Sarah Sharp3ffbba92009-04-27 19:57:38 -0700590
John Yound115b042009-07-27 12:05:15 -0700591 if (csz)
592 dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
593 }
594
John Yound115b042009-07-27 12:05:15 -0700595 xhci_dbg_slot_ctx(xhci, ctx);
596 xhci_dbg_ep_ctx(xhci, ctx, last_ep);
Sarah Sharp3ffbba92009-04-27 19:57:38 -0700597}
Xenia Ragiadakou84a99f62013-08-06 00:22:15 +0300598
599void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
600 const char *fmt, ...)
601{
602 struct va_format vaf;
603 va_list args;
604
605 va_start(args, fmt);
606 vaf.fmt = fmt;
607 vaf.va = &args;
608 xhci_dbg(xhci, "%pV\n", &vaf);
609 trace(&vaf);
610 va_end(args);
611}
Andrew Bresticker436e8c72014-10-03 11:35:28 +0300612EXPORT_SYMBOL_GPL(xhci_dbg_trace);