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Antti Palosaari831e0b72011-07-08 23:36:07 -03001/*
2 * Realtek RTL28xxU DVB USB driver
3 *
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#ifndef RTL28XXU_H
23#define RTL28XXU_H
24
Antti Palosaaric01a3592012-08-12 22:27:07 -030025#include "dvb_usb.h"
Antti Palosaari831e0b72011-07-08 23:36:07 -030026
Antti Palosaaric01a3592012-08-12 22:27:07 -030027#define deb_dump(r, t, v, i, b, l) { \
28 char *direction; \
Antti Palosaari831e0b72011-07-08 23:36:07 -030029 if (t == (USB_TYPE_VENDOR | USB_DIR_OUT)) \
Antti Palosaaric01a3592012-08-12 22:27:07 -030030 direction = ">>>"; \
Antti Palosaari831e0b72011-07-08 23:36:07 -030031 else \
Antti Palosaaric01a3592012-08-12 22:27:07 -030032 direction = "<<<"; \
33 dev_dbg(&d->udev->dev, "%s: %02x %02x %02x %02x %02x %02x %02x %02x " \
34 "%s [%d bytes]\n", __func__, t, r, v & 0xff, v >> 8, \
35 i & 0xff, i >> 8, l & 0xff, l >> 8, direction, l); \
Antti Palosaari831e0b72011-07-08 23:36:07 -030036}
37
38/*
39 * USB commands
40 * (usb_control_msg() index parameter)
41 */
Antti Palosaari34ec2932011-08-04 20:21:16 -030042
Antti Palosaari9935eea2012-01-21 22:26:52 -030043#define DEMOD 0x0000
44#define USB 0x0100
45#define SYS 0x0200
46#define I2C 0x0300
47#define I2C_DA 0x0600
48
49#define CMD_WR_FLAG 0x0010
50#define CMD_DEMOD_RD 0x0000
51#define CMD_DEMOD_WR 0x0010
52#define CMD_USB_RD 0x0100
53#define CMD_USB_WR 0x0110
54#define CMD_SYS_RD 0x0200
55#define CMD_IR_RD 0x0201
56#define CMD_IR_WR 0x0211
57#define CMD_SYS_WR 0x0210
58#define CMD_I2C_RD 0x0300
59#define CMD_I2C_WR 0x0310
60#define CMD_I2C_DA_RD 0x0600
61#define CMD_I2C_DA_WR 0x0610
62
Antti Palosaari831e0b72011-07-08 23:36:07 -030063
64struct rtl28xxu_priv {
65 u8 chip_id;
66 u8 tuner;
Antti Palosaari34ec2932011-08-04 20:21:16 -030067 u8 page; /* integrated demod active register page */
Antti Palosaarib5cbaa42011-08-04 13:26:10 -030068 bool rc_active;
Antti Palosaari831e0b72011-07-08 23:36:07 -030069};
70
71enum rtl28xxu_chip_id {
Antti Palosaari9935eea2012-01-21 22:26:52 -030072 CHIP_ID_NONE,
Antti Palosaari831e0b72011-07-08 23:36:07 -030073 CHIP_ID_RTL2831U,
74 CHIP_ID_RTL2832U,
75};
76
77enum rtl28xxu_tuner {
Antti Palosaari9935eea2012-01-21 22:26:52 -030078 TUNER_NONE,
Antti Palosaarib5cbaa42011-08-04 13:26:10 -030079
Antti Palosaari831e0b72011-07-08 23:36:07 -030080 TUNER_RTL2830_QT1010,
81 TUNER_RTL2830_MT2060,
82 TUNER_RTL2830_MXL5005S,
Antti Palosaarib5cbaa42011-08-04 13:26:10 -030083
84 TUNER_RTL2832_MT2266,
85 TUNER_RTL2832_FC2580,
86 TUNER_RTL2832_MT2063,
87 TUNER_RTL2832_MAX3543,
88 TUNER_RTL2832_TUA9001,
89 TUNER_RTL2832_MXL5007T,
90 TUNER_RTL2832_FC0012,
91 TUNER_RTL2832_E4000,
92 TUNER_RTL2832_TDA18272,
93 TUNER_RTL2832_FC0013,
Antti Palosaari831e0b72011-07-08 23:36:07 -030094};
95
96struct rtl28xxu_req {
97 u16 value;
98 u16 index;
99 u16 size;
100 u8 *data;
101};
102
103struct rtl28xxu_reg_val {
104 u16 reg;
105 u8 val;
106};
107
108/*
109 * memory map
110 *
111 * 0x0000 DEMOD : demodulator
112 * 0x2000 USB : SIE, USB endpoint, debug, DMA
113 * 0x3000 SYS : system
114 * 0xfc00 RC : remote controller (not RTL2831U)
115 */
116
117/*
118 * USB registers
119 */
120/* SIE Control Registers */
121#define USB_SYSCTL 0x2000 /* USB system control */
122#define USB_SYSCTL_0 0x2000 /* USB system control */
123#define USB_SYSCTL_1 0x2001 /* USB system control */
124#define USB_SYSCTL_2 0x2002 /* USB system control */
125#define USB_SYSCTL_3 0x2003 /* USB system control */
126#define USB_IRQSTAT 0x2008 /* SIE interrupt status */
127#define USB_IRQEN 0x200C /* SIE interrupt enable */
128#define USB_CTRL 0x2010 /* USB control */
129#define USB_STAT 0x2014 /* USB status */
130#define USB_DEVADDR 0x2018 /* USB device address */
131#define USB_TEST 0x201C /* USB test mode */
132#define USB_FRAME_NUMBER 0x2020 /* frame number */
133#define USB_FIFO_ADDR 0x2028 /* address of SIE FIFO RAM */
134#define USB_FIFO_CMD 0x202A /* SIE FIFO RAM access command */
135#define USB_FIFO_DATA 0x2030 /* SIE FIFO RAM data */
136/* Endpoint Registers */
137#define EP0_SETUPA 0x20F8 /* EP 0 setup packet lower byte */
138#define EP0_SETUPB 0x20FC /* EP 0 setup packet higher byte */
139#define USB_EP0_CFG 0x2104 /* EP 0 configure */
140#define USB_EP0_CTL 0x2108 /* EP 0 control */
141#define USB_EP0_STAT 0x210C /* EP 0 status */
142#define USB_EP0_IRQSTAT 0x2110 /* EP 0 interrupt status */
143#define USB_EP0_IRQEN 0x2114 /* EP 0 interrupt enable */
144#define USB_EP0_MAXPKT 0x2118 /* EP 0 max packet size */
145#define USB_EP0_BC 0x2120 /* EP 0 FIFO byte counter */
146#define USB_EPA_CFG 0x2144 /* EP A configure */
147#define USB_EPA_CFG_0 0x2144 /* EP A configure */
148#define USB_EPA_CFG_1 0x2145 /* EP A configure */
149#define USB_EPA_CFG_2 0x2146 /* EP A configure */
150#define USB_EPA_CFG_3 0x2147 /* EP A configure */
151#define USB_EPA_CTL 0x2148 /* EP A control */
152#define USB_EPA_CTL_0 0x2148 /* EP A control */
153#define USB_EPA_CTL_1 0x2149 /* EP A control */
154#define USB_EPA_CTL_2 0x214A /* EP A control */
155#define USB_EPA_CTL_3 0x214B /* EP A control */
156#define USB_EPA_STAT 0x214C /* EP A status */
157#define USB_EPA_IRQSTAT 0x2150 /* EP A interrupt status */
158#define USB_EPA_IRQEN 0x2154 /* EP A interrupt enable */
159#define USB_EPA_MAXPKT 0x2158 /* EP A max packet size */
160#define USB_EPA_MAXPKT_0 0x2158 /* EP A max packet size */
161#define USB_EPA_MAXPKT_1 0x2159 /* EP A max packet size */
162#define USB_EPA_MAXPKT_2 0x215A /* EP A max packet size */
163#define USB_EPA_MAXPKT_3 0x215B /* EP A max packet size */
164#define USB_EPA_FIFO_CFG 0x2160 /* EP A FIFO configure */
165#define USB_EPA_FIFO_CFG_0 0x2160 /* EP A FIFO configure */
166#define USB_EPA_FIFO_CFG_1 0x2161 /* EP A FIFO configure */
167#define USB_EPA_FIFO_CFG_2 0x2162 /* EP A FIFO configure */
168#define USB_EPA_FIFO_CFG_3 0x2163 /* EP A FIFO configure */
169/* Debug Registers */
170#define USB_PHYTSTDIS 0x2F04 /* PHY test disable */
171#define USB_TOUT_VAL 0x2F08 /* USB time-out time */
172#define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
173#define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */
174#define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */
175#define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
176#define USB_UTMI_TST 0x2F80 /* UTMI test */
177#define USB_UTMI_STATUS 0x2F84 /* UTMI status */
178#define USB_TSTCTL 0x2F88 /* test control */
179#define USB_TSTCTL2 0x2F8C /* test control 2 */
180#define USB_PID_FORCE 0x2F90 /* force PID */
181#define USB_PKTERR_CNT 0x2F94 /* packet error counter */
182#define USB_RXERR_CNT 0x2F98 /* RX error counter */
183#define USB_MEM_BIST 0x2F9C /* MEM BIST test */
184#define USB_SLBBIST 0x2FA0 /* self-loop-back BIST */
185#define USB_CNTTEST 0x2FA4 /* counter test */
186#define USB_PHYTST 0x2FC0 /* USB PHY test */
187#define USB_DBGIDX 0x2FF0 /* select individual block debug signal */
188#define USB_DBGMUX 0x2FF4 /* debug signal module mux */
189
190/*
191 * SYS registers
192 */
193/* demod control registers */
194#define SYS_SYS0 0x3000 /* include DEMOD_CTL, GPO, GPI, GPOE */
195#define SYS_DEMOD_CTL 0x3000 /* control register for DVB-T demodulator */
196/* GPIO registers */
197#define SYS_GPIO_OUT_VAL 0x3001 /* output value of GPIO */
198#define SYS_GPIO_IN_VAL 0x3002 /* input value of GPIO */
199#define SYS_GPIO_OUT_EN 0x3003 /* output enable of GPIO */
200#define SYS_SYS1 0x3004 /* include GPD, SYSINTE, SYSINTS, GP_CFG0 */
201#define SYS_GPIO_DIR 0x3004 /* direction control for GPIO */
202#define SYS_SYSINTE 0x3005 /* system interrupt enable */
203#define SYS_SYSINTS 0x3006 /* system interrupt status */
204#define SYS_GPIO_CFG0 0x3007 /* PAD configuration for GPIO0-GPIO3 */
205#define SYS_SYS2 0x3008 /* include GP_CFG1 and 3 reserved bytes */
206#define SYS_GPIO_CFG1 0x3008 /* PAD configuration for GPIO4 */
Antti Palosaarib5cbaa42011-08-04 13:26:10 -0300207#define SYS_DEMOD_CTL1 0x300B
208
Antti Palosaari831e0b72011-07-08 23:36:07 -0300209/* IrDA registers */
210#define SYS_IRRC_PSR 0x3020 /* IR protocol selection */
211#define SYS_IRRC_PER 0x3024 /* IR protocol extension */
212#define SYS_IRRC_SF 0x3028 /* IR sampling frequency */
213#define SYS_IRRC_DPIR 0x302C /* IR data package interval */
214#define SYS_IRRC_CR 0x3030 /* IR control */
215#define SYS_IRRC_RP 0x3034 /* IR read port */
216#define SYS_IRRC_SR 0x3038 /* IR status */
217/* I2C master registers */
218#define SYS_I2CCR 0x3040 /* I2C clock */
219#define SYS_I2CMCR 0x3044 /* I2C master control */
220#define SYS_I2CMSTR 0x3048 /* I2C master SCL timing */
221#define SYS_I2CMSR 0x304C /* I2C master status */
222#define SYS_I2CMFR 0x3050 /* I2C master FIFO */
223
Antti Palosaarib5cbaa42011-08-04 13:26:10 -0300224/*
225 * IR registers
226 */
227#define IR_RX_BUF 0xFC00
228#define IR_RX_IE 0xFD00
229#define IR_RX_IF 0xFD01
230#define IR_RX_CTRL 0xFD02
231#define IR_RX_CFG 0xFD03
232#define IR_MAX_DURATION0 0xFD04
233#define IR_MAX_DURATION1 0xFD05
234#define IR_IDLE_LEN0 0xFD06
235#define IR_IDLE_LEN1 0xFD07
236#define IR_GLITCH_LEN 0xFD08
237#define IR_RX_BUF_CTRL 0xFD09
238#define IR_RX_BUF_DATA 0xFD0A
239#define IR_RX_BC 0xFD0B
240#define IR_RX_CLK 0xFD0C
241#define IR_RX_C_COUNT_L 0xFD0D
242#define IR_RX_C_COUNT_H 0xFD0E
243#define IR_SUSPEND_CTRL 0xFD10
244#define IR_ERR_TOL_CTRL 0xFD11
245#define IR_UNIT_LEN 0xFD12
246#define IR_ERR_TOL_LEN 0xFD13
247#define IR_MAX_H_TOL_LEN 0xFD14
248#define IR_MAX_L_TOL_LEN 0xFD15
249#define IR_MASK_CTRL 0xFD16
250#define IR_MASK_DATA 0xFD17
251#define IR_RES_MASK_ADDR 0xFD18
252#define IR_RES_MASK_T_LEN 0xFD19
253
Antti Palosaari831e0b72011-07-08 23:36:07 -0300254#endif