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Andrew Victor62c16602006-11-30 12:27:38 +01001/*
Andrew Victor9d041262007-02-05 11:42:07 +01002 * arch/arm/mach-at91/at91sam9260.c
Andrew Victor62c16602006-11-30 12:27:38 +01003 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/arch/at91sam9260.h>
18#include <asm/arch/at91_pmc.h>
Andrew Victore9d10a12007-01-09 12:47:51 +010019#include <asm/arch/at91_rstc.h>
Andrew Victor62c16602006-11-30 12:27:38 +010020
21#include "generic.h"
22#include "clock.h"
23
24static struct map_desc at91sam9260_io_desc[] __initdata = {
25 {
26 .virtual = AT91_VA_BASE_SYS,
27 .pfn = __phys_to_pfn(AT91_BASE_SYS),
28 .length = SZ_16K,
29 .type = MT_DEVICE,
30 }, {
31 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
32 .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
33 .length = AT91SAM9260_SRAM0_SIZE,
34 .type = MT_DEVICE,
35 }, {
36 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
37 .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
38 .length = AT91SAM9260_SRAM1_SIZE,
39 .type = MT_DEVICE,
40 },
41};
42
43/* --------------------------------------------------------------------
44 * Clocks
45 * -------------------------------------------------------------------- */
46
47/*
48 * The peripheral clocks.
49 */
50static struct clk pioA_clk = {
51 .name = "pioA_clk",
52 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
53 .type = CLK_TYPE_PERIPHERAL,
54};
55static struct clk pioB_clk = {
56 .name = "pioB_clk",
57 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
58 .type = CLK_TYPE_PERIPHERAL,
59};
60static struct clk pioC_clk = {
61 .name = "pioC_clk",
62 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
63 .type = CLK_TYPE_PERIPHERAL,
64};
65static struct clk adc_clk = {
66 .name = "adc_clk",
67 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
68 .type = CLK_TYPE_PERIPHERAL,
69};
70static struct clk usart0_clk = {
71 .name = "usart0_clk",
72 .pmc_mask = 1 << AT91SAM9260_ID_US0,
73 .type = CLK_TYPE_PERIPHERAL,
74};
75static struct clk usart1_clk = {
76 .name = "usart1_clk",
77 .pmc_mask = 1 << AT91SAM9260_ID_US1,
78 .type = CLK_TYPE_PERIPHERAL,
79};
80static struct clk usart2_clk = {
81 .name = "usart2_clk",
82 .pmc_mask = 1 << AT91SAM9260_ID_US2,
83 .type = CLK_TYPE_PERIPHERAL,
84};
85static struct clk mmc_clk = {
86 .name = "mci_clk",
87 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
88 .type = CLK_TYPE_PERIPHERAL,
89};
90static struct clk udc_clk = {
91 .name = "udc_clk",
92 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
93 .type = CLK_TYPE_PERIPHERAL,
94};
95static struct clk twi_clk = {
96 .name = "twi_clk",
97 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
98 .type = CLK_TYPE_PERIPHERAL,
99};
100static struct clk spi0_clk = {
101 .name = "spi0_clk",
102 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
103 .type = CLK_TYPE_PERIPHERAL,
104};
105static struct clk spi1_clk = {
106 .name = "spi1_clk",
107 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
108 .type = CLK_TYPE_PERIPHERAL,
109};
Andrew Victorc177a1e2007-02-08 10:25:38 +0100110static struct clk tc0_clk = {
111 .name = "tc0_clk",
112 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
113 .type = CLK_TYPE_PERIPHERAL,
114};
115static struct clk tc1_clk = {
116 .name = "tc1_clk",
117 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
118 .type = CLK_TYPE_PERIPHERAL,
119};
120static struct clk tc2_clk = {
121 .name = "tc2_clk",
122 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
123 .type = CLK_TYPE_PERIPHERAL,
124};
Andrew Victor62c16602006-11-30 12:27:38 +0100125static struct clk ohci_clk = {
126 .name = "ohci_clk",
127 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
128 .type = CLK_TYPE_PERIPHERAL,
129};
130static struct clk ether_clk = {
131 .name = "ether_clk",
132 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
133 .type = CLK_TYPE_PERIPHERAL,
134};
135static struct clk isi_clk = {
136 .name = "isi_clk",
137 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
138 .type = CLK_TYPE_PERIPHERAL,
139};
140static struct clk usart3_clk = {
141 .name = "usart3_clk",
142 .pmc_mask = 1 << AT91SAM9260_ID_US3,
143 .type = CLK_TYPE_PERIPHERAL,
144};
145static struct clk usart4_clk = {
146 .name = "usart4_clk",
147 .pmc_mask = 1 << AT91SAM9260_ID_US4,
148 .type = CLK_TYPE_PERIPHERAL,
149};
150static struct clk usart5_clk = {
151 .name = "usart5_clk",
152 .pmc_mask = 1 << AT91SAM9260_ID_US5,
153 .type = CLK_TYPE_PERIPHERAL,
154};
Andrew Victorc177a1e2007-02-08 10:25:38 +0100155static struct clk tc3_clk = {
156 .name = "tc3_clk",
157 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
158 .type = CLK_TYPE_PERIPHERAL,
159};
160static struct clk tc4_clk = {
161 .name = "tc4_clk",
162 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
163 .type = CLK_TYPE_PERIPHERAL,
164};
165static struct clk tc5_clk = {
166 .name = "tc5_clk",
167 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
168 .type = CLK_TYPE_PERIPHERAL,
169};
Andrew Victor62c16602006-11-30 12:27:38 +0100170
171static struct clk *periph_clocks[] __initdata = {
172 &pioA_clk,
173 &pioB_clk,
174 &pioC_clk,
175 &adc_clk,
176 &usart0_clk,
177 &usart1_clk,
178 &usart2_clk,
179 &mmc_clk,
180 &udc_clk,
181 &twi_clk,
182 &spi0_clk,
183 &spi1_clk,
184 // ssc
Andrew Victorc177a1e2007-02-08 10:25:38 +0100185 &tc0_clk,
186 &tc1_clk,
187 &tc2_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100188 &ohci_clk,
189 &ether_clk,
190 &isi_clk,
191 &usart3_clk,
192 &usart4_clk,
193 &usart5_clk,
Andrew Victorc177a1e2007-02-08 10:25:38 +0100194 &tc3_clk,
195 &tc4_clk,
196 &tc5_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100197 // irq0 .. irq2
198};
199
200/*
201 * The two programmable clocks.
202 * You must configure pin multiplexing to bring these signals out.
203 */
204static struct clk pck0 = {
205 .name = "pck0",
206 .pmc_mask = AT91_PMC_PCK0,
207 .type = CLK_TYPE_PROGRAMMABLE,
208 .id = 0,
209};
210static struct clk pck1 = {
211 .name = "pck1",
212 .pmc_mask = AT91_PMC_PCK1,
213 .type = CLK_TYPE_PROGRAMMABLE,
214 .id = 1,
215};
216
217static void __init at91sam9260_register_clocks(void)
218{
219 int i;
220
221 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
222 clk_register(periph_clocks[i]);
223
224 clk_register(&pck0);
225 clk_register(&pck1);
226}
227
228/* --------------------------------------------------------------------
229 * GPIO
230 * -------------------------------------------------------------------- */
231
232static struct at91_gpio_bank at91sam9260_gpio[] = {
233 {
234 .id = AT91SAM9260_ID_PIOA,
235 .offset = AT91_PIOA,
236 .clock = &pioA_clk,
237 }, {
238 .id = AT91SAM9260_ID_PIOB,
239 .offset = AT91_PIOB,
240 .clock = &pioB_clk,
241 }, {
242 .id = AT91SAM9260_ID_PIOC,
243 .offset = AT91_PIOC,
244 .clock = &pioC_clk,
245 }
246};
247
248static void at91sam9260_reset(void)
249{
Andrew Victore9d10a12007-01-09 12:47:51 +0100250 at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
Andrew Victor62c16602006-11-30 12:27:38 +0100251}
252
253
254/* --------------------------------------------------------------------
255 * AT91SAM9260 processor initialization
256 * -------------------------------------------------------------------- */
257
258void __init at91sam9260_initialize(unsigned long main_clock)
259{
260 /* Map peripherals */
261 iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
262
263 at91_arch_reset = at91sam9260_reset;
264 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
265 | (1 << AT91SAM9260_ID_IRQ2);
266
267 /* Init clock subsystem */
268 at91_clock_init(main_clock);
269
270 /* Register the processor-specific clocks */
271 at91sam9260_register_clocks();
272
273 /* Register GPIO subsystem */
274 at91_gpio_init(at91sam9260_gpio, 3);
275}
276
277/* --------------------------------------------------------------------
278 * Interrupt initialization
279 * -------------------------------------------------------------------- */
280
281/*
282 * The default interrupt priority levels (0 = lowest, 7 = highest).
283 */
284static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
285 7, /* Advanced Interrupt Controller */
286 7, /* System Peripherals */
287 0, /* Parallel IO Controller A */
288 0, /* Parallel IO Controller B */
289 0, /* Parallel IO Controller C */
290 0, /* Analog-to-Digital Converter */
291 6, /* USART 0 */
292 6, /* USART 1 */
293 6, /* USART 2 */
294 0, /* Multimedia Card Interface */
295 4, /* USB Device Port */
296 0, /* Two-Wire Interface */
297 6, /* Serial Peripheral Interface 0 */
298 6, /* Serial Peripheral Interface 1 */
299 5, /* Serial Synchronous Controller */
300 0,
301 0,
302 0, /* Timer Counter 0 */
303 0, /* Timer Counter 1 */
304 0, /* Timer Counter 2 */
305 3, /* USB Host port */
306 3, /* Ethernet */
307 0, /* Image Sensor Interface */
308 6, /* USART 3 */
309 6, /* USART 4 */
310 6, /* USART 5 */
311 0, /* Timer Counter 3 */
312 0, /* Timer Counter 4 */
313 0, /* Timer Counter 5 */
314 0, /* Advanced Interrupt Controller */
315 0, /* Advanced Interrupt Controller */
316 0, /* Advanced Interrupt Controller */
317};
318
319void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
320{
321 if (!priority)
322 priority = at91sam9260_default_irq_priority;
323
324 /* Initialize the AIC interrupt controller */
325 at91_aic_init(priority);
326
327 /* Enable GPIO interrupts */
328 at91_gpio_irq_setup();
329}