Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 1 | /* |
| 2 | * SPI bus driver for CSR SiRFprimaII |
| 3 | * |
| 4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. |
| 5 | * |
| 6 | * Licensed under GPLv2 or later. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/module.h> |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/slab.h> |
| 12 | #include <linux/clk.h> |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 13 | #include <linux/completion.h> |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/of.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/of_gpio.h> |
| 21 | #include <linux/spi/spi.h> |
| 22 | #include <linux/spi/spi_bitbang.h> |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 23 | #include <linux/dmaengine.h> |
| 24 | #include <linux/dma-direction.h> |
| 25 | #include <linux/dma-mapping.h> |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 26 | |
| 27 | #define DRIVER_NAME "sirfsoc_spi" |
| 28 | |
| 29 | #define SIRFSOC_SPI_CTRL 0x0000 |
| 30 | #define SIRFSOC_SPI_CMD 0x0004 |
| 31 | #define SIRFSOC_SPI_TX_RX_EN 0x0008 |
| 32 | #define SIRFSOC_SPI_INT_EN 0x000C |
| 33 | #define SIRFSOC_SPI_INT_STATUS 0x0010 |
| 34 | #define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100 |
| 35 | #define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104 |
| 36 | #define SIRFSOC_SPI_TXFIFO_CTRL 0x0108 |
| 37 | #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C |
| 38 | #define SIRFSOC_SPI_TXFIFO_OP 0x0110 |
| 39 | #define SIRFSOC_SPI_TXFIFO_STATUS 0x0114 |
| 40 | #define SIRFSOC_SPI_TXFIFO_DATA 0x0118 |
| 41 | #define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120 |
| 42 | #define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124 |
| 43 | #define SIRFSOC_SPI_RXFIFO_CTRL 0x0128 |
| 44 | #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C |
| 45 | #define SIRFSOC_SPI_RXFIFO_OP 0x0130 |
| 46 | #define SIRFSOC_SPI_RXFIFO_STATUS 0x0134 |
| 47 | #define SIRFSOC_SPI_RXFIFO_DATA 0x0138 |
| 48 | #define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144 |
| 49 | |
| 50 | /* SPI CTRL register defines */ |
| 51 | #define SIRFSOC_SPI_SLV_MODE BIT(16) |
| 52 | #define SIRFSOC_SPI_CMD_MODE BIT(17) |
| 53 | #define SIRFSOC_SPI_CS_IO_OUT BIT(18) |
| 54 | #define SIRFSOC_SPI_CS_IO_MODE BIT(19) |
| 55 | #define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20) |
| 56 | #define SIRFSOC_SPI_CS_IDLE_STAT BIT(21) |
| 57 | #define SIRFSOC_SPI_TRAN_MSB BIT(22) |
| 58 | #define SIRFSOC_SPI_DRV_POS_EDGE BIT(23) |
| 59 | #define SIRFSOC_SPI_CS_HOLD_TIME BIT(24) |
| 60 | #define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25) |
| 61 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26) |
| 62 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26) |
| 63 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26) |
| 64 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26) |
| 65 | #define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28) |
| 66 | #define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30) |
| 67 | #define SIRFSOC_SPI_MUL_DAT_MODE BIT(31) |
| 68 | |
| 69 | /* Interrupt Enable */ |
| 70 | #define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0) |
| 71 | #define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1) |
| 72 | #define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2) |
| 73 | #define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3) |
| 74 | #define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4) |
| 75 | #define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5) |
| 76 | #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6) |
| 77 | #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7) |
| 78 | #define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8) |
| 79 | #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9) |
| 80 | #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10) |
| 81 | |
| 82 | #define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF |
| 83 | |
| 84 | /* Interrupt status */ |
| 85 | #define SIRFSOC_SPI_RX_DONE BIT(0) |
| 86 | #define SIRFSOC_SPI_TX_DONE BIT(1) |
| 87 | #define SIRFSOC_SPI_RX_OFLOW BIT(2) |
| 88 | #define SIRFSOC_SPI_TX_UFLOW BIT(3) |
| 89 | #define SIRFSOC_SPI_RX_FIFO_FULL BIT(6) |
| 90 | #define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7) |
| 91 | #define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8) |
| 92 | #define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9) |
| 93 | #define SIRFSOC_SPI_FRM_END BIT(10) |
| 94 | |
| 95 | /* TX RX enable */ |
| 96 | #define SIRFSOC_SPI_RX_EN BIT(0) |
| 97 | #define SIRFSOC_SPI_TX_EN BIT(1) |
| 98 | #define SIRFSOC_SPI_CMD_TX_EN BIT(2) |
| 99 | |
| 100 | #define SIRFSOC_SPI_IO_MODE_SEL BIT(0) |
| 101 | #define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2) |
| 102 | |
| 103 | /* FIFO OPs */ |
| 104 | #define SIRFSOC_SPI_FIFO_RESET BIT(0) |
| 105 | #define SIRFSOC_SPI_FIFO_START BIT(1) |
| 106 | |
| 107 | /* FIFO CTRL */ |
| 108 | #define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0) |
| 109 | #define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0) |
| 110 | #define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0) |
| 111 | |
| 112 | /* FIFO Status */ |
| 113 | #define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF |
| 114 | #define SIRFSOC_SPI_FIFO_FULL BIT(8) |
| 115 | #define SIRFSOC_SPI_FIFO_EMPTY BIT(9) |
| 116 | |
| 117 | /* 256 bytes rx/tx FIFO */ |
| 118 | #define SIRFSOC_SPI_FIFO_SIZE 256 |
| 119 | #define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024) |
| 120 | |
| 121 | #define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F) |
| 122 | #define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10) |
| 123 | #define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20) |
| 124 | #define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2) |
| 125 | |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 126 | /* |
| 127 | * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma |
| 128 | * due to the limitation of dma controller |
| 129 | */ |
| 130 | |
| 131 | #define ALIGNED(x) (!((u32)x & 0x3)) |
| 132 | #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \ |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 133 | ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE)) |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 134 | |
Qipan Li | eeb71395 | 2014-03-01 12:38:17 +0800 | [diff] [blame] | 135 | #define SIRFSOC_MAX_CMD_BYTES 4 |
| 136 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 137 | struct sirfsoc_spi { |
| 138 | struct spi_bitbang bitbang; |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 139 | struct completion rx_done; |
| 140 | struct completion tx_done; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 141 | |
| 142 | void __iomem *base; |
| 143 | u32 ctrl_freq; /* SPI controller clock speed */ |
| 144 | struct clk *clk; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 145 | |
| 146 | /* rx & tx bufs from the spi_transfer */ |
| 147 | const void *tx; |
| 148 | void *rx; |
| 149 | |
| 150 | /* place received word into rx buffer */ |
| 151 | void (*rx_word) (struct sirfsoc_spi *); |
| 152 | /* get word from tx buffer for sending */ |
| 153 | void (*tx_word) (struct sirfsoc_spi *); |
| 154 | |
| 155 | /* number of words left to be tranmitted/received */ |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 156 | unsigned int left_tx_word; |
| 157 | unsigned int left_rx_word; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 158 | |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 159 | /* rx & tx DMA channels */ |
| 160 | struct dma_chan *rx_chan; |
| 161 | struct dma_chan *tx_chan; |
| 162 | dma_addr_t src_start; |
| 163 | dma_addr_t dst_start; |
| 164 | void *dummypage; |
| 165 | int word_width; /* in bytes */ |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 166 | |
Qipan Li | eeb71395 | 2014-03-01 12:38:17 +0800 | [diff] [blame] | 167 | /* |
| 168 | * if tx size is not more than 4 and rx size is NULL, use |
| 169 | * command model |
| 170 | */ |
| 171 | bool tx_by_cmd; |
| 172 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 173 | int chipselect[0]; |
| 174 | }; |
| 175 | |
| 176 | static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi) |
| 177 | { |
| 178 | u32 data; |
| 179 | u8 *rx = sspi->rx; |
| 180 | |
| 181 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); |
| 182 | |
| 183 | if (rx) { |
| 184 | *rx++ = (u8) data; |
| 185 | sspi->rx = rx; |
| 186 | } |
| 187 | |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 188 | sspi->left_rx_word--; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi) |
| 192 | { |
| 193 | u32 data = 0; |
| 194 | const u8 *tx = sspi->tx; |
| 195 | |
| 196 | if (tx) { |
| 197 | data = *tx++; |
| 198 | sspi->tx = tx; |
| 199 | } |
| 200 | |
| 201 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 202 | sspi->left_tx_word--; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi) |
| 206 | { |
| 207 | u32 data; |
| 208 | u16 *rx = sspi->rx; |
| 209 | |
| 210 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); |
| 211 | |
| 212 | if (rx) { |
| 213 | *rx++ = (u16) data; |
| 214 | sspi->rx = rx; |
| 215 | } |
| 216 | |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 217 | sspi->left_rx_word--; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi) |
| 221 | { |
| 222 | u32 data = 0; |
| 223 | const u16 *tx = sspi->tx; |
| 224 | |
| 225 | if (tx) { |
| 226 | data = *tx++; |
| 227 | sspi->tx = tx; |
| 228 | } |
| 229 | |
| 230 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 231 | sspi->left_tx_word--; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi) |
| 235 | { |
| 236 | u32 data; |
| 237 | u32 *rx = sspi->rx; |
| 238 | |
| 239 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); |
| 240 | |
| 241 | if (rx) { |
| 242 | *rx++ = (u32) data; |
| 243 | sspi->rx = rx; |
| 244 | } |
| 245 | |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 246 | sspi->left_rx_word--; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 247 | |
| 248 | } |
| 249 | |
| 250 | static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi) |
| 251 | { |
| 252 | u32 data = 0; |
| 253 | const u32 *tx = sspi->tx; |
| 254 | |
| 255 | if (tx) { |
| 256 | data = *tx++; |
| 257 | sspi->tx = tx; |
| 258 | } |
| 259 | |
| 260 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 261 | sspi->left_tx_word--; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 262 | } |
| 263 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 264 | static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id) |
| 265 | { |
| 266 | struct sirfsoc_spi *sspi = dev_id; |
| 267 | u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS); |
| 268 | |
| 269 | writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS); |
| 270 | |
Qipan Li | eeb71395 | 2014-03-01 12:38:17 +0800 | [diff] [blame] | 271 | if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) { |
| 272 | complete(&sspi->tx_done); |
| 273 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); |
| 274 | return IRQ_HANDLED; |
| 275 | } |
| 276 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 277 | /* Error Conditions */ |
| 278 | if (spi_stat & SIRFSOC_SPI_RX_OFLOW || |
| 279 | spi_stat & SIRFSOC_SPI_TX_UFLOW) { |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 280 | complete(&sspi->rx_done); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 281 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); |
| 282 | } |
| 283 | |
Qipan Li | 237ce46 | 2013-05-18 19:46:06 +0800 | [diff] [blame] | 284 | if (spi_stat & (SIRFSOC_SPI_FRM_END |
| 285 | | SIRFSOC_SPI_RXFIFO_THD_REACH)) |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 286 | while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS) |
| 287 | & SIRFSOC_SPI_FIFO_EMPTY)) && |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 288 | sspi->left_rx_word) |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 289 | sspi->rx_word(sspi); |
| 290 | |
Qipan Li | 818e916 | 2014-04-14 14:29:57 +0800 | [diff] [blame] | 291 | if (spi_stat & (SIRFSOC_SPI_TXFIFO_EMPTY | |
| 292 | SIRFSOC_SPI_TXFIFO_THD_REACH)) |
Qipan Li | 237ce46 | 2013-05-18 19:46:06 +0800 | [diff] [blame] | 293 | while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) |
| 294 | & SIRFSOC_SPI_FIFO_FULL)) && |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 295 | sspi->left_tx_word) |
Qipan Li | 237ce46 | 2013-05-18 19:46:06 +0800 | [diff] [blame] | 296 | sspi->tx_word(sspi); |
| 297 | |
| 298 | /* Received all words */ |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 299 | if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) { |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 300 | complete(&sspi->rx_done); |
Qipan Li | 237ce46 | 2013-05-18 19:46:06 +0800 | [diff] [blame] | 301 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 302 | } |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 303 | return IRQ_HANDLED; |
| 304 | } |
| 305 | |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 306 | static void spi_sirfsoc_dma_fini_callback(void *data) |
| 307 | { |
| 308 | struct completion *dma_complete = data; |
| 309 | |
| 310 | complete(dma_complete); |
| 311 | } |
| 312 | |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 313 | static int spi_sirfsoc_cmd_transfer(struct spi_device *spi, |
| 314 | struct spi_transfer *t) |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 315 | { |
| 316 | struct sirfsoc_spi *sspi; |
| 317 | int timeout = t->len * 10; |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 318 | u32 cmd; |
| 319 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 320 | sspi = spi_master_get_devdata(spi->master); |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 321 | memcpy(&cmd, sspi->tx, t->len); |
| 322 | if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST)) |
| 323 | cmd = cpu_to_be32(cmd) >> |
| 324 | ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8); |
| 325 | if (sspi->word_width == 2 && t->len == 4 && |
| 326 | (!(spi->mode & SPI_LSB_FIRST))) |
| 327 | cmd = ((cmd & 0xffff) << 16) | (cmd >> 16); |
| 328 | writel(cmd, sspi->base + SIRFSOC_SPI_CMD); |
| 329 | writel(SIRFSOC_SPI_FRM_END_INT_EN, |
| 330 | sspi->base + SIRFSOC_SPI_INT_EN); |
| 331 | writel(SIRFSOC_SPI_CMD_TX_EN, |
| 332 | sspi->base + SIRFSOC_SPI_TX_RX_EN); |
| 333 | if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { |
| 334 | dev_err(&spi->dev, "cmd transfer timeout\n"); |
| 335 | return 0; |
Qipan Li | eeb71395 | 2014-03-01 12:38:17 +0800 | [diff] [blame] | 336 | } |
| 337 | |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 338 | return t->len; |
| 339 | } |
| 340 | |
| 341 | static void spi_sirfsoc_dma_transfer(struct spi_device *spi, |
| 342 | struct spi_transfer *t) |
| 343 | { |
| 344 | struct sirfsoc_spi *sspi; |
| 345 | struct dma_async_tx_descriptor *rx_desc, *tx_desc; |
| 346 | int timeout = t->len * 10; |
| 347 | |
| 348 | sspi = spi_master_get_devdata(spi->master); |
| 349 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 350 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
| 351 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 352 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
| 353 | writel(0, sspi->base + SIRFSOC_SPI_INT_EN); |
| 354 | writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); |
| 355 | if (sspi->left_tx_word < SIRFSOC_SPI_DAT_FRM_LEN_MAX) { |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 356 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 357 | SIRFSOC_SPI_ENA_AUTO_CLR | SIRFSOC_SPI_MUL_DAT_MODE, |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 358 | sspi->base + SIRFSOC_SPI_CTRL); |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 359 | writel(sspi->left_tx_word - 1, |
| 360 | sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); |
| 361 | writel(sspi->left_tx_word - 1, |
| 362 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 363 | } else { |
| 364 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL), |
| 365 | sspi->base + SIRFSOC_SPI_CTRL); |
| 366 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); |
| 367 | writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); |
| 368 | } |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 369 | sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, |
| 370 | (t->tx_buf != t->rx_buf) ? |
| 371 | DMA_FROM_DEVICE : DMA_BIDIRECTIONAL); |
| 372 | rx_desc = dmaengine_prep_slave_single(sspi->rx_chan, |
| 373 | sspi->dst_start, t->len, DMA_DEV_TO_MEM, |
| 374 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 375 | rx_desc->callback = spi_sirfsoc_dma_fini_callback; |
| 376 | rx_desc->callback_param = &sspi->rx_done; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 377 | |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 378 | sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, |
| 379 | (t->tx_buf != t->rx_buf) ? |
| 380 | DMA_TO_DEVICE : DMA_BIDIRECTIONAL); |
| 381 | tx_desc = dmaengine_prep_slave_single(sspi->tx_chan, |
| 382 | sspi->src_start, t->len, DMA_MEM_TO_DEV, |
| 383 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 384 | tx_desc->callback = spi_sirfsoc_dma_fini_callback; |
| 385 | tx_desc->callback_param = &sspi->tx_done; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 386 | |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 387 | dmaengine_submit(tx_desc); |
| 388 | dmaengine_submit(rx_desc); |
| 389 | dma_async_issue_pending(sspi->tx_chan); |
| 390 | dma_async_issue_pending(sspi->rx_chan); |
Qipan Li | d77ec5d | 2014-04-14 14:30:00 +0800 | [diff] [blame] | 391 | writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, |
| 392 | sspi->base + SIRFSOC_SPI_TX_RX_EN); |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 393 | if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) { |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 394 | dev_err(&spi->dev, "transfer timeout\n"); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 395 | dmaengine_terminate_all(sspi->rx_chan); |
| 396 | } else |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 397 | sspi->left_rx_word = 0; |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 398 | /* |
| 399 | * we only wait tx-done event if transferring by DMA. for PIO, |
| 400 | * we get rx data by writing tx data, so if rx is done, tx has |
| 401 | * done earlier |
| 402 | */ |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 403 | if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { |
| 404 | dev_err(&spi->dev, "transfer timeout\n"); |
| 405 | dmaengine_terminate_all(sspi->tx_chan); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 406 | } |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 407 | dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE); |
| 408 | dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 409 | /* TX, RX FIFO stop */ |
| 410 | writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 411 | writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 412 | if (sspi->left_tx_word >= SIRFSOC_SPI_DAT_FRM_LEN_MAX) |
| 413 | writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); |
| 414 | } |
| 415 | |
| 416 | static void spi_sirfsoc_pio_transfer(struct spi_device *spi, |
| 417 | struct spi_transfer *t) |
| 418 | { |
| 419 | struct sirfsoc_spi *sspi; |
| 420 | int timeout = t->len * 10; |
| 421 | |
| 422 | sspi = spi_master_get_devdata(spi->master); |
| 423 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 424 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
| 425 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 426 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
| 427 | writel(0, sspi->base + SIRFSOC_SPI_INT_EN); |
| 428 | writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); |
| 429 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | SIRFSOC_SPI_MUL_DAT_MODE | |
| 430 | SIRFSOC_SPI_ENA_AUTO_CLR, sspi->base + SIRFSOC_SPI_CTRL); |
| 431 | writel(sspi->left_tx_word - 1, |
| 432 | sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); |
| 433 | writel(sspi->left_rx_word - 1, |
| 434 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); |
| 435 | sspi->tx_word(sspi); |
| 436 | writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN | |
| 437 | SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_RXFIFO_THD_INT_EN | |
| 438 | SIRFSOC_SPI_TXFIFO_THD_INT_EN | SIRFSOC_SPI_FRM_END_INT_EN| |
| 439 | SIRFSOC_SPI_RXFIFO_FULL_INT_EN, |
| 440 | sspi->base + SIRFSOC_SPI_INT_EN); |
| 441 | writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, |
| 442 | sspi->base + SIRFSOC_SPI_TX_RX_EN); |
| 443 | if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) |
| 444 | dev_err(&spi->dev, "transfer timeout\n"); |
| 445 | writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 446 | writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 447 | writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); |
| 448 | writel(0, sspi->base + SIRFSOC_SPI_INT_EN); |
Qipan Li | c908ef3 | 2014-04-15 15:24:59 +0800 | [diff] [blame^] | 449 | } |
| 450 | |
| 451 | static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) |
| 452 | { |
| 453 | struct sirfsoc_spi *sspi; |
| 454 | sspi = spi_master_get_devdata(spi->master); |
| 455 | |
| 456 | sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage; |
| 457 | sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage; |
| 458 | sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width; |
| 459 | reinit_completion(&sspi->rx_done); |
| 460 | reinit_completion(&sspi->tx_done); |
| 461 | /* |
| 462 | * in the transfer, if transfer data using command register with rx_buf |
| 463 | * null, just fill command data into command register and wait for its |
| 464 | * completion. |
| 465 | */ |
| 466 | if (sspi->tx_by_cmd) |
| 467 | spi_sirfsoc_cmd_transfer(spi, t); |
| 468 | else if (IS_DMA_VALID(t)) |
| 469 | spi_sirfsoc_dma_transfer(spi, t); |
| 470 | else |
| 471 | spi_sirfsoc_pio_transfer(spi, t); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 472 | |
Qipan Li | 692fb0f | 2013-08-25 21:42:50 +0800 | [diff] [blame] | 473 | return t->len - sspi->left_rx_word * sspi->word_width; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 474 | } |
| 475 | |
| 476 | static void spi_sirfsoc_chipselect(struct spi_device *spi, int value) |
| 477 | { |
| 478 | struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master); |
| 479 | |
| 480 | if (sspi->chipselect[spi->chip_select] == 0) { |
| 481 | u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 482 | switch (value) { |
| 483 | case BITBANG_CS_ACTIVE: |
| 484 | if (spi->mode & SPI_CS_HIGH) |
| 485 | regval |= SIRFSOC_SPI_CS_IO_OUT; |
| 486 | else |
| 487 | regval &= ~SIRFSOC_SPI_CS_IO_OUT; |
| 488 | break; |
| 489 | case BITBANG_CS_INACTIVE: |
| 490 | if (spi->mode & SPI_CS_HIGH) |
| 491 | regval &= ~SIRFSOC_SPI_CS_IO_OUT; |
| 492 | else |
| 493 | regval |= SIRFSOC_SPI_CS_IO_OUT; |
| 494 | break; |
| 495 | } |
| 496 | writel(regval, sspi->base + SIRFSOC_SPI_CTRL); |
| 497 | } else { |
| 498 | int gpio = sspi->chipselect[spi->chip_select]; |
Qipan Li | 6ee8a2f | 2014-04-14 14:29:59 +0800 | [diff] [blame] | 499 | switch (value) { |
| 500 | case BITBANG_CS_ACTIVE: |
| 501 | gpio_direction_output(gpio, |
| 502 | spi->mode & SPI_CS_HIGH ? 1 : 0); |
| 503 | break; |
| 504 | case BITBANG_CS_INACTIVE: |
| 505 | gpio_direction_output(gpio, |
| 506 | spi->mode & SPI_CS_HIGH ? 0 : 1); |
| 507 | break; |
| 508 | } |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 509 | } |
| 510 | } |
| 511 | |
| 512 | static int |
| 513 | spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
| 514 | { |
| 515 | struct sirfsoc_spi *sspi; |
| 516 | u8 bits_per_word = 0; |
| 517 | int hz = 0; |
| 518 | u32 regval; |
| 519 | u32 txfifo_ctrl, rxfifo_ctrl; |
| 520 | u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4; |
| 521 | |
| 522 | sspi = spi_master_get_devdata(spi->master); |
| 523 | |
Laxman Dewangan | 766ed70 | 2012-12-18 14:25:43 +0530 | [diff] [blame] | 524 | bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 525 | hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; |
| 526 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 527 | regval = (sspi->ctrl_freq / (2 * hz)) - 1; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 528 | if (regval > 0xFFFF || regval < 0) { |
| 529 | dev_err(&spi->dev, "Speed %d not supported\n", hz); |
| 530 | return -EINVAL; |
| 531 | } |
| 532 | |
| 533 | switch (bits_per_word) { |
| 534 | case 8: |
| 535 | regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8; |
| 536 | sspi->rx_word = spi_sirfsoc_rx_word_u8; |
| 537 | sspi->tx_word = spi_sirfsoc_tx_word_u8; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 538 | break; |
| 539 | case 12: |
| 540 | case 16: |
Qipan Li | d77ec5d | 2014-04-14 14:30:00 +0800 | [diff] [blame] | 541 | regval |= (bits_per_word == 12) ? |
| 542 | SIRFSOC_SPI_TRAN_DAT_FORMAT_12 : |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 543 | SIRFSOC_SPI_TRAN_DAT_FORMAT_16; |
| 544 | sspi->rx_word = spi_sirfsoc_rx_word_u16; |
| 545 | sspi->tx_word = spi_sirfsoc_tx_word_u16; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 546 | break; |
| 547 | case 32: |
| 548 | regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32; |
| 549 | sspi->rx_word = spi_sirfsoc_rx_word_u32; |
| 550 | sspi->tx_word = spi_sirfsoc_tx_word_u32; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 551 | break; |
Arnd Bergmann | 804ae43 | 2013-06-03 15:24:53 +0200 | [diff] [blame] | 552 | default: |
| 553 | BUG(); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 554 | } |
| 555 | |
Axel Lin | 8c328a2 | 2014-01-15 17:07:43 +0800 | [diff] [blame] | 556 | sspi->word_width = DIV_ROUND_UP(bits_per_word, 8); |
| 557 | txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | |
| 558 | sspi->word_width; |
| 559 | rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | |
| 560 | sspi->word_width; |
| 561 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 562 | if (!(spi->mode & SPI_CS_HIGH)) |
| 563 | regval |= SIRFSOC_SPI_CS_IDLE_STAT; |
| 564 | if (!(spi->mode & SPI_LSB_FIRST)) |
| 565 | regval |= SIRFSOC_SPI_TRAN_MSB; |
| 566 | if (spi->mode & SPI_CPOL) |
| 567 | regval |= SIRFSOC_SPI_CLK_IDLE_STAT; |
| 568 | |
| 569 | /* |
Qipan Li | d77ec5d | 2014-04-14 14:30:00 +0800 | [diff] [blame] | 570 | * Data should be driven at least 1/2 cycle before the fetch edge |
| 571 | * to make sure that data gets stable at the fetch edge. |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 572 | */ |
| 573 | if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) || |
| 574 | (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) |
| 575 | regval &= ~SIRFSOC_SPI_DRV_POS_EDGE; |
| 576 | else |
| 577 | regval |= SIRFSOC_SPI_DRV_POS_EDGE; |
| 578 | |
| 579 | writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) | |
| 580 | SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | |
| 581 | SIRFSOC_SPI_FIFO_HC(2), |
| 582 | sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK); |
| 583 | writel(SIRFSOC_SPI_FIFO_SC(2) | |
| 584 | SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | |
| 585 | SIRFSOC_SPI_FIFO_HC(fifo_size - 2), |
| 586 | sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK); |
| 587 | writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL); |
| 588 | writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL); |
| 589 | |
Qipan Li | eeb71395 | 2014-03-01 12:38:17 +0800 | [diff] [blame] | 590 | if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) { |
| 591 | regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) | |
| 592 | SIRFSOC_SPI_CMD_MODE); |
| 593 | sspi->tx_by_cmd = true; |
| 594 | } else { |
| 595 | regval &= ~SIRFSOC_SPI_CMD_MODE; |
| 596 | sspi->tx_by_cmd = false; |
| 597 | } |
Qipan Li | 625227a4 | 2014-04-14 14:29:58 +0800 | [diff] [blame] | 598 | /* |
| 599 | * set spi controller in RISC chipselect mode, we are controlling CS by |
| 600 | * software BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE. |
| 601 | */ |
| 602 | regval |= SIRFSOC_SPI_CS_IO_MODE; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 603 | writel(regval, sspi->base + SIRFSOC_SPI_CTRL); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 604 | |
| 605 | if (IS_DMA_VALID(t)) { |
| 606 | /* Enable DMA mode for RX, TX */ |
| 607 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); |
Qipan Li | d77ec5d | 2014-04-14 14:30:00 +0800 | [diff] [blame] | 608 | writel(SIRFSOC_SPI_RX_DMA_FLUSH, |
| 609 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 610 | } else { |
| 611 | /* Enable IO mode for RX, TX */ |
Qipan Li | d77ec5d | 2014-04-14 14:30:00 +0800 | [diff] [blame] | 612 | writel(SIRFSOC_SPI_IO_MODE_SEL, |
| 613 | sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); |
| 614 | writel(SIRFSOC_SPI_IO_MODE_SEL, |
| 615 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 616 | } |
| 617 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 618 | return 0; |
| 619 | } |
| 620 | |
| 621 | static int spi_sirfsoc_setup(struct spi_device *spi) |
| 622 | { |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 623 | if (!spi->max_speed_hz) |
| 624 | return -EINVAL; |
| 625 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 626 | return spi_sirfsoc_setup_transfer(spi, NULL); |
| 627 | } |
| 628 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 629 | static int spi_sirfsoc_probe(struct platform_device *pdev) |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 630 | { |
| 631 | struct sirfsoc_spi *sspi; |
| 632 | struct spi_master *master; |
| 633 | struct resource *mem_res; |
| 634 | int num_cs, cs_gpio, irq; |
| 635 | int i; |
| 636 | int ret; |
| 637 | |
| 638 | ret = of_property_read_u32(pdev->dev.of_node, |
| 639 | "sirf,spi-num-chipselects", &num_cs); |
| 640 | if (ret < 0) { |
| 641 | dev_err(&pdev->dev, "Unable to get chip select number\n"); |
| 642 | goto err_cs; |
| 643 | } |
| 644 | |
Qipan Li | d77ec5d | 2014-04-14 14:30:00 +0800 | [diff] [blame] | 645 | master = spi_alloc_master(&pdev->dev, |
| 646 | sizeof(*sspi) + sizeof(int) * num_cs); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 647 | if (!master) { |
| 648 | dev_err(&pdev->dev, "Unable to allocate SPI master\n"); |
| 649 | return -ENOMEM; |
| 650 | } |
| 651 | platform_set_drvdata(pdev, master); |
| 652 | sspi = spi_master_get_devdata(master); |
| 653 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 654 | master->num_chipselect = num_cs; |
| 655 | |
| 656 | for (i = 0; i < master->num_chipselect; i++) { |
| 657 | cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i); |
| 658 | if (cs_gpio < 0) { |
| 659 | dev_err(&pdev->dev, "can't get cs gpio from DT\n"); |
| 660 | ret = -ENODEV; |
| 661 | goto free_master; |
| 662 | } |
| 663 | |
| 664 | sspi->chipselect[i] = cs_gpio; |
| 665 | if (cs_gpio == 0) |
| 666 | continue; /* use cs from spi controller */ |
| 667 | |
| 668 | ret = gpio_request(cs_gpio, DRIVER_NAME); |
| 669 | if (ret) { |
| 670 | while (i > 0) { |
| 671 | i--; |
| 672 | if (sspi->chipselect[i] > 0) |
| 673 | gpio_free(sspi->chipselect[i]); |
| 674 | } |
| 675 | dev_err(&pdev->dev, "fail to request cs gpios\n"); |
| 676 | goto free_master; |
| 677 | } |
| 678 | } |
| 679 | |
Julia Lawall | 2479790 | 2013-08-14 11:11:29 +0200 | [diff] [blame] | 680 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Thierry Reding | b0ee560 | 2013-01-21 11:09:18 +0100 | [diff] [blame] | 681 | sspi->base = devm_ioremap_resource(&pdev->dev, mem_res); |
| 682 | if (IS_ERR(sspi->base)) { |
| 683 | ret = PTR_ERR(sspi->base); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 684 | goto free_master; |
| 685 | } |
| 686 | |
| 687 | irq = platform_get_irq(pdev, 0); |
| 688 | if (irq < 0) { |
| 689 | ret = -ENXIO; |
| 690 | goto free_master; |
| 691 | } |
| 692 | ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0, |
| 693 | DRIVER_NAME, sspi); |
| 694 | if (ret) |
| 695 | goto free_master; |
| 696 | |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 697 | sspi->bitbang.master = master; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 698 | sspi->bitbang.chipselect = spi_sirfsoc_chipselect; |
| 699 | sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer; |
| 700 | sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer; |
| 701 | sspi->bitbang.master->setup = spi_sirfsoc_setup; |
| 702 | master->bus_num = pdev->id; |
Qipan Li | 94b1f0d | 2013-06-25 19:45:29 +0800 | [diff] [blame] | 703 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 704 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) | |
| 705 | SPI_BPW_MASK(16) | SPI_BPW_MASK(32); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 706 | sspi->bitbang.master->dev.of_node = pdev->dev.of_node; |
| 707 | |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 708 | /* request DMA channels */ |
Barry Song | dd7243d | 2014-02-13 00:30:19 +0800 | [diff] [blame] | 709 | sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx"); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 710 | if (!sspi->rx_chan) { |
| 711 | dev_err(&pdev->dev, "can not allocate rx dma channel\n"); |
Wei Yongjun | 6cca9e2 | 2013-08-23 08:33:39 +0800 | [diff] [blame] | 712 | ret = -ENODEV; |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 713 | goto free_master; |
| 714 | } |
Barry Song | dd7243d | 2014-02-13 00:30:19 +0800 | [diff] [blame] | 715 | sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx"); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 716 | if (!sspi->tx_chan) { |
| 717 | dev_err(&pdev->dev, "can not allocate tx dma channel\n"); |
Wei Yongjun | 6cca9e2 | 2013-08-23 08:33:39 +0800 | [diff] [blame] | 718 | ret = -ENODEV; |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 719 | goto free_rx_dma; |
| 720 | } |
| 721 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 722 | sspi->clk = clk_get(&pdev->dev, NULL); |
| 723 | if (IS_ERR(sspi->clk)) { |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 724 | ret = PTR_ERR(sspi->clk); |
| 725 | goto free_tx_dma; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 726 | } |
Barry Song | e5118cd | 2012-12-26 10:48:33 +0800 | [diff] [blame] | 727 | clk_prepare_enable(sspi->clk); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 728 | sspi->ctrl_freq = clk_get_rate(sspi->clk); |
| 729 | |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 730 | init_completion(&sspi->rx_done); |
| 731 | init_completion(&sspi->tx_done); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 732 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 733 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 734 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
| 735 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 736 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
| 737 | /* We are not using dummy delay between command and data */ |
| 738 | writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL); |
| 739 | |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 740 | sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL); |
Wei Yongjun | 6cca9e2 | 2013-08-23 08:33:39 +0800 | [diff] [blame] | 741 | if (!sspi->dummypage) { |
| 742 | ret = -ENOMEM; |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 743 | goto free_clk; |
Wei Yongjun | 6cca9e2 | 2013-08-23 08:33:39 +0800 | [diff] [blame] | 744 | } |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 745 | |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 746 | ret = spi_bitbang_start(&sspi->bitbang); |
| 747 | if (ret) |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 748 | goto free_dummypage; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 749 | |
| 750 | dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num); |
| 751 | |
| 752 | return 0; |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 753 | free_dummypage: |
| 754 | kfree(sspi->dummypage); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 755 | free_clk: |
Barry Song | e5118cd | 2012-12-26 10:48:33 +0800 | [diff] [blame] | 756 | clk_disable_unprepare(sspi->clk); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 757 | clk_put(sspi->clk); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 758 | free_tx_dma: |
| 759 | dma_release_channel(sspi->tx_chan); |
| 760 | free_rx_dma: |
| 761 | dma_release_channel(sspi->rx_chan); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 762 | free_master: |
| 763 | spi_master_put(master); |
| 764 | err_cs: |
| 765 | return ret; |
| 766 | } |
| 767 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 768 | static int spi_sirfsoc_remove(struct platform_device *pdev) |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 769 | { |
| 770 | struct spi_master *master; |
| 771 | struct sirfsoc_spi *sspi; |
| 772 | int i; |
| 773 | |
| 774 | master = platform_get_drvdata(pdev); |
| 775 | sspi = spi_master_get_devdata(master); |
| 776 | |
| 777 | spi_bitbang_stop(&sspi->bitbang); |
| 778 | for (i = 0; i < master->num_chipselect; i++) { |
| 779 | if (sspi->chipselect[i] > 0) |
| 780 | gpio_free(sspi->chipselect[i]); |
| 781 | } |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 782 | kfree(sspi->dummypage); |
Barry Song | e5118cd | 2012-12-26 10:48:33 +0800 | [diff] [blame] | 783 | clk_disable_unprepare(sspi->clk); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 784 | clk_put(sspi->clk); |
Barry Song | de39f5f | 2013-08-06 14:21:21 +0800 | [diff] [blame] | 785 | dma_release_channel(sspi->rx_chan); |
| 786 | dma_release_channel(sspi->tx_chan); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 787 | spi_master_put(master); |
| 788 | return 0; |
| 789 | } |
| 790 | |
Qipan Li | facffed | 2014-02-13 00:30:20 +0800 | [diff] [blame] | 791 | #ifdef CONFIG_PM_SLEEP |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 792 | static int spi_sirfsoc_suspend(struct device *dev) |
| 793 | { |
Axel Lin | a1216394 | 2013-08-09 15:35:16 +0800 | [diff] [blame] | 794 | struct spi_master *master = dev_get_drvdata(dev); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 795 | struct sirfsoc_spi *sspi = spi_master_get_devdata(master); |
Axel Lin | a82ba3a | 2014-03-05 15:19:09 +0800 | [diff] [blame] | 796 | int ret; |
| 797 | |
| 798 | ret = spi_master_suspend(master); |
| 799 | if (ret) |
| 800 | return ret; |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 801 | |
| 802 | clk_disable(sspi->clk); |
| 803 | return 0; |
| 804 | } |
| 805 | |
| 806 | static int spi_sirfsoc_resume(struct device *dev) |
| 807 | { |
Axel Lin | a1216394 | 2013-08-09 15:35:16 +0800 | [diff] [blame] | 808 | struct spi_master *master = dev_get_drvdata(dev); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 809 | struct sirfsoc_spi *sspi = spi_master_get_devdata(master); |
| 810 | |
| 811 | clk_enable(sspi->clk); |
| 812 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 813 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
| 814 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
| 815 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); |
| 816 | |
Axel Lin | a82ba3a | 2014-03-05 15:19:09 +0800 | [diff] [blame] | 817 | return spi_master_resume(master); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 818 | } |
Qipan Li | facffed | 2014-02-13 00:30:20 +0800 | [diff] [blame] | 819 | #endif |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 820 | |
Jingoo Han | 71aa2e3 | 2014-02-26 10:32:48 +0900 | [diff] [blame] | 821 | static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend, |
| 822 | spi_sirfsoc_resume); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 823 | |
| 824 | static const struct of_device_id spi_sirfsoc_of_match[] = { |
| 825 | { .compatible = "sirf,prima2-spi", }, |
Barry Song | f3b8a8e | 2012-12-26 10:48:34 +0800 | [diff] [blame] | 826 | { .compatible = "sirf,marco-spi", }, |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 827 | {} |
| 828 | }; |
Arnd Bergmann | 3af4ed7 | 2013-04-23 18:30:41 +0200 | [diff] [blame] | 829 | MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 830 | |
| 831 | static struct platform_driver spi_sirfsoc_driver = { |
| 832 | .driver = { |
| 833 | .name = DRIVER_NAME, |
| 834 | .owner = THIS_MODULE, |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 835 | .pm = &spi_sirfsoc_pm_ops, |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 836 | .of_match_table = spi_sirfsoc_of_match, |
| 837 | }, |
| 838 | .probe = spi_sirfsoc_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 839 | .remove = spi_sirfsoc_remove, |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 840 | }; |
| 841 | module_platform_driver(spi_sirfsoc_driver); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 842 | MODULE_DESCRIPTION("SiRF SoC SPI master driver"); |
Qipan Li | d77ec5d | 2014-04-14 14:30:00 +0800 | [diff] [blame] | 843 | MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>"); |
| 844 | MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>"); |
Zhiwu Song | 1cc2df9 | 2012-02-13 17:45:38 +0800 | [diff] [blame] | 845 | MODULE_LICENSE("GPL v2"); |