blob: 0d9372e75f69d56f2f698e6f2ed2e1b471b31c55 [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040030#include <linux/export.h>
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070035#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010036#include <drm/i915_drm.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070037#include "i915_drv.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070038
Keith Packarda4fc5ed2009-04-07 16:16:42 -070039#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080041struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080060static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070067/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020076 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070079}
80
Imre Deak68b4d822013-05-08 13:14:06 +030081static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070082{
Imre Deak68b4d822013-05-08 13:14:06 +030083 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070086}
87
Chris Wilsondf0e9242010-09-09 16:20:55 +010088static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
Paulo Zanonifa90ece2012-10-26 19:05:44 -020090 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
Chris Wilsondf0e9242010-09-09 16:20:55 +010091}
92
Chris Wilsonea5b2132010-08-04 13:50:23 +010093static void intel_dp_link_down(struct intel_dp *intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -070094
95static int
Chris Wilsonea5b2132010-08-04 13:50:23 +010096intel_dp_max_link_bw(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -070097{
Jesse Barnes7183dc22011-07-07 11:10:58 -070098 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -070099
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
Imre Deakd4eead52013-07-09 17:05:26 +0300104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700107 default:
Imre Deakd4eead52013-07-09 17:05:26 +0300108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700133static int
Keith Packardc8982612012-01-25 08:16:25 -0800134intel_dp_link_required(int pixel_clock, int bpp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700135{
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400136 return (pixel_clock * bpp + 9) / 10;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700137}
138
139static int
Dave Airliefe27d532010-06-30 11:46:17 +1000140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
145static int
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100149 struct intel_dp *intel_dp = intel_attached_dp(connector);
Jani Nikuladd06f902012-10-19 14:51:50 +0300150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
Daniel Vetter36008362013-03-27 00:44:59 +0100152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700154
Jani Nikuladd06f902012-10-19 14:51:50 +0300155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100157 return MODE_PANEL;
158
Jani Nikuladd06f902012-10-19 14:51:50 +0300159 if (mode->vdisplay > fixed_mode->vdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100160 return MODE_PANEL;
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200161
162 target_clock = fixed_mode->clock;
Zhao Yakui7de56f42010-07-19 09:43:14 +0100163 }
164
Daniel Vetter36008362013-03-27 00:44:59 +0100165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
Daniel Vetterc4867932012-04-10 10:42:36 +0200172 return MODE_CLOCK_HIGH;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
Daniel Vetter0af78a22012-05-23 11:30:55 +0200177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
Vijay Purushothaman9473c8f2012-09-27 19:13:01 +0530213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
Jani Nikulabf13e812013-09-06 07:40:05 +0300240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
Keith Packardebf33b12011-09-29 15:53:27 -0700297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
Paulo Zanoni30add222012-10-26 19:05:45 -0200299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700300 struct drm_i915_private *dev_priv = dev->dev_private;
301
Jani Nikulabf13e812013-09-06 07:40:05 +0300302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
Paulo Zanoni30add222012-10-26 19:05:45 -0200307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700308 struct drm_i915_private *dev_priv = dev->dev_private;
309
Jani Nikulabf13e812013-09-06 07:40:05 +0300310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700311}
312
Keith Packard9b984da2011-09-19 13:54:47 -0700313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
Paulo Zanoni30add222012-10-26 19:05:45 -0200316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard9b984da2011-09-19 13:54:47 -0700317 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardebf33b12011-09-29 15:53:27 -0700318
Keith Packard9b984da2011-09-19 13:54:47 -0700319 if (!is_edp(intel_dp))
320 return;
Jesse Barnes453c5422013-03-28 09:55:41 -0700321
Keith Packardebf33b12011-09-29 15:53:27 -0700322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
Keith Packard9b984da2011-09-19 13:54:47 -0700323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
Jani Nikulabf13e812013-09-06 07:40:05 +0300325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
Keith Packard9b984da2011-09-19 13:54:47 -0700327 }
328}
329
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100337 uint32_t status;
338 bool done;
339
Daniel Vetteref04f002012-12-01 21:03:59 +0100340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100341 if (has_aux_irq)
Paulo Zanonib18ac462013-02-18 19:00:24 -0300342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
Imre Deak35987062013-05-21 20:03:20 +0300343 msecs_to_jiffies_timeout(10));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
Chris Wilsonbc866252013-07-21 16:00:03 +0100354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300356{
357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
359 struct drm_i915_private *dev_priv = dev->dev_private;
360
361 /* The clock divider is based off the hrawclk,
362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
367 */
368 if (IS_VALLEYVIEW(dev)) {
Chris Wilsonbc866252013-07-21 16:00:03 +0100369 return index ? 0 : 100;
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300370 } else if (intel_dig_port->port == PORT_A) {
Chris Wilsonbc866252013-07-21 16:00:03 +0100371 if (index)
372 return 0;
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300373 if (HAS_DDI(dev))
Chris Wilsonbc866252013-07-21 16:00:03 +0100374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300375 else if (IS_GEN6(dev) || IS_GEN7(dev))
376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
377 else
378 return 225; /* eDP input clock at 450Mhz */
379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
Chris Wilsonbc866252013-07-21 16:00:03 +0100381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300386 } else if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonbc866252013-07-21 16:00:03 +0100387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300388 } else {
Chris Wilsonbc866252013-07-21 16:00:03 +0100389 return index ? 0 :intel_hrawclk(dev) / 2;
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300390 }
391}
392
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700393static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100394intel_dp_aux_ch(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
Paulo Zanoni174edf12012-10-26 19:05:50 -0200398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700400 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700402 uint32_t ch_data = ch_ctl + 4;
Chris Wilsonbc866252013-07-21 16:00:03 +0100403 uint32_t aux_clock_divider;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100404 int i, ret, recv_bytes;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700405 uint32_t status;
Chris Wilsonbc866252013-07-21 16:00:03 +0100406 int try, precharge, clock = 0;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
408
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
411 * deep sleep states.
412 */
413 pm_qos_update_request(&dev_priv->pm_qos, 0);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700414
Keith Packard9b984da2011-09-19 13:54:47 -0700415 intel_dp_check_edp(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800416
Daniel Vetter6b4e0a92012-06-14 22:15:00 +0200417 if (IS_GEN6(dev))
418 precharge = 3;
419 else
420 precharge = 5;
421
Paulo Zanonic67a4702013-08-19 13:18:09 -0300422 intel_aux_display_runtime_get(dev_priv);
423
Jesse Barnes11bee432011-08-01 15:02:20 -0700424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
Daniel Vetteref04f002012-12-01 21:03:59 +0100426 status = I915_READ_NOTRACE(ch_ctl);
Jesse Barnes11bee432011-08-01 15:02:20 -0700427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
428 break;
429 msleep(1);
430 }
431
432 if (try == 3) {
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
434 I915_READ(ch_ctl));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100435 ret = -EBUSY;
436 goto out;
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100437 }
438
Chris Wilsonbc866252013-07-21 16:00:03 +0100439 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
440 /* Must try at least 3 times according to DP spec */
441 for (try = 0; try < 5; try++) {
442 /* Load the send data into the aux channel data registers */
443 for (i = 0; i < send_bytes; i += 4)
444 I915_WRITE(ch_data + i,
445 pack_aux(send + i, send_bytes - i));
Akshay Joshi0206e352011-08-16 15:34:10 -0400446
Chris Wilsonbc866252013-07-21 16:00:03 +0100447 /* Send the command and wait for it to complete */
448 I915_WRITE(ch_ctl,
449 DP_AUX_CH_CTL_SEND_BUSY |
450 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
451 DP_AUX_CH_CTL_TIME_OUT_400us |
452 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
453 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
454 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
455 DP_AUX_CH_CTL_DONE |
456 DP_AUX_CH_CTL_TIME_OUT_ERROR |
457 DP_AUX_CH_CTL_RECEIVE_ERROR);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100458
Chris Wilsonbc866252013-07-21 16:00:03 +0100459 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
Akshay Joshi0206e352011-08-16 15:34:10 -0400460
Chris Wilsonbc866252013-07-21 16:00:03 +0100461 /* Clear done status and any errors */
462 I915_WRITE(ch_ctl,
463 status |
464 DP_AUX_CH_CTL_DONE |
465 DP_AUX_CH_CTL_TIME_OUT_ERROR |
466 DP_AUX_CH_CTL_RECEIVE_ERROR);
Adam Jacksond7e96fe2011-07-26 15:39:46 -0400467
Chris Wilsonbc866252013-07-21 16:00:03 +0100468 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR))
470 continue;
471 if (status & DP_AUX_CH_CTL_DONE)
472 break;
473 }
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100474 if (status & DP_AUX_CH_CTL_DONE)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700475 break;
476 }
477
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700478 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700479 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100480 ret = -EBUSY;
481 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700482 }
483
484 /* Check for timeout or receive error.
485 * Timeouts occur when the sink is not connected
486 */
Keith Packarda5b3da52009-06-11 22:30:32 -0700487 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700488 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100489 ret = -EIO;
490 goto out;
Keith Packarda5b3da52009-06-11 22:30:32 -0700491 }
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700492
493 /* Timeouts occur when the device isn't connected, so they're
494 * "normal" -- don't fill the kernel log with these */
Keith Packarda5b3da52009-06-11 22:30:32 -0700495 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
Zhao Yakui28c97732009-10-09 11:39:41 +0800496 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100497 ret = -ETIMEDOUT;
498 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700499 }
500
501 /* Unload any bytes sent back from the other side */
502 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
503 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700504 if (recv_bytes > recv_size)
505 recv_bytes = recv_size;
Akshay Joshi0206e352011-08-16 15:34:10 -0400506
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100507 for (i = 0; i < recv_bytes; i += 4)
508 unpack_aux(I915_READ(ch_data + i),
509 recv + i, recv_bytes - i);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700510
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100511 ret = recv_bytes;
512out:
513 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
Paulo Zanonic67a4702013-08-19 13:18:09 -0300514 intel_aux_display_runtime_put(dev_priv);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100515
516 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700517}
518
519/* Write data to the aux channel in native mode */
520static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100521intel_dp_aux_native_write(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700522 uint16_t address, uint8_t *send, int send_bytes)
523{
524 int ret;
525 uint8_t msg[20];
526 int msg_bytes;
527 uint8_t ack;
528
Keith Packard9b984da2011-09-19 13:54:47 -0700529 intel_dp_check_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700530 if (send_bytes > 16)
531 return -1;
532 msg[0] = AUX_NATIVE_WRITE << 4;
533 msg[1] = address >> 8;
Zhenyu Wangeebc8632009-07-24 01:00:30 +0800534 msg[2] = address & 0xff;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700535 msg[3] = send_bytes - 1;
536 memcpy(&msg[4], send, send_bytes);
537 msg_bytes = send_bytes + 4;
538 for (;;) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700540 if (ret < 0)
541 return ret;
542 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
543 break;
544 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
545 udelay(100);
546 else
Keith Packarda5b3da52009-06-11 22:30:32 -0700547 return -EIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700548 }
549 return send_bytes;
550}
551
552/* Write a single byte to the aux channel in native mode */
553static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100554intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700555 uint16_t address, uint8_t byte)
556{
Chris Wilsonea5b2132010-08-04 13:50:23 +0100557 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700558}
559
560/* read bytes from a native aux channel */
561static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100562intel_dp_aux_native_read(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700563 uint16_t address, uint8_t *recv, int recv_bytes)
564{
565 uint8_t msg[4];
566 int msg_bytes;
567 uint8_t reply[20];
568 int reply_bytes;
569 uint8_t ack;
570 int ret;
571
Keith Packard9b984da2011-09-19 13:54:47 -0700572 intel_dp_check_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700573 msg[0] = AUX_NATIVE_READ << 4;
574 msg[1] = address >> 8;
575 msg[2] = address & 0xff;
576 msg[3] = recv_bytes - 1;
577
578 msg_bytes = 4;
579 reply_bytes = recv_bytes + 1;
580
581 for (;;) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100582 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700583 reply, reply_bytes);
Keith Packarda5b3da52009-06-11 22:30:32 -0700584 if (ret == 0)
585 return -EPROTO;
586 if (ret < 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700587 return ret;
588 ack = reply[0];
589 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
590 memcpy(recv, reply + 1, ret - 1);
591 return ret - 1;
592 }
593 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
594 udelay(100);
595 else
Keith Packarda5b3da52009-06-11 22:30:32 -0700596 return -EIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700597 }
598}
599
600static int
Dave Airlieab2c0672009-12-04 10:55:24 +1000601intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
602 uint8_t write_byte, uint8_t *read_byte)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700603{
Dave Airlieab2c0672009-12-04 10:55:24 +1000604 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100605 struct intel_dp *intel_dp = container_of(adapter,
606 struct intel_dp,
607 adapter);
Dave Airlieab2c0672009-12-04 10:55:24 +1000608 uint16_t address = algo_data->address;
609 uint8_t msg[5];
610 uint8_t reply[2];
David Flynn8316f332010-12-08 16:10:21 +0000611 unsigned retry;
Dave Airlieab2c0672009-12-04 10:55:24 +1000612 int msg_bytes;
613 int reply_bytes;
614 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700615
Keith Packard9b984da2011-09-19 13:54:47 -0700616 intel_dp_check_edp(intel_dp);
Dave Airlieab2c0672009-12-04 10:55:24 +1000617 /* Set up the command byte */
618 if (mode & MODE_I2C_READ)
619 msg[0] = AUX_I2C_READ << 4;
620 else
621 msg[0] = AUX_I2C_WRITE << 4;
622
623 if (!(mode & MODE_I2C_STOP))
624 msg[0] |= AUX_I2C_MOT << 4;
625
626 msg[1] = address >> 8;
627 msg[2] = address;
628
629 switch (mode) {
630 case MODE_I2C_WRITE:
631 msg[3] = 0;
632 msg[4] = write_byte;
633 msg_bytes = 5;
634 reply_bytes = 1;
635 break;
636 case MODE_I2C_READ:
637 msg[3] = 0;
638 msg_bytes = 4;
639 reply_bytes = 2;
640 break;
641 default:
642 msg_bytes = 3;
643 reply_bytes = 1;
644 break;
645 }
646
David Flynn8316f332010-12-08 16:10:21 +0000647 for (retry = 0; retry < 5; retry++) {
648 ret = intel_dp_aux_ch(intel_dp,
649 msg, msg_bytes,
650 reply, reply_bytes);
Dave Airlieab2c0672009-12-04 10:55:24 +1000651 if (ret < 0) {
Dave Airlie3ff99162009-12-08 14:03:47 +1000652 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
Dave Airlieab2c0672009-12-04 10:55:24 +1000653 return ret;
654 }
David Flynn8316f332010-12-08 16:10:21 +0000655
656 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
657 case AUX_NATIVE_REPLY_ACK:
658 /* I2C-over-AUX Reply field is only valid
659 * when paired with AUX ACK.
660 */
661 break;
662 case AUX_NATIVE_REPLY_NACK:
663 DRM_DEBUG_KMS("aux_ch native nack\n");
664 return -EREMOTEIO;
665 case AUX_NATIVE_REPLY_DEFER:
666 udelay(100);
667 continue;
668 default:
669 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
670 reply[0]);
671 return -EREMOTEIO;
672 }
673
Dave Airlieab2c0672009-12-04 10:55:24 +1000674 switch (reply[0] & AUX_I2C_REPLY_MASK) {
675 case AUX_I2C_REPLY_ACK:
676 if (mode == MODE_I2C_READ) {
677 *read_byte = reply[1];
678 }
679 return reply_bytes - 1;
680 case AUX_I2C_REPLY_NACK:
David Flynn8316f332010-12-08 16:10:21 +0000681 DRM_DEBUG_KMS("aux_i2c nack\n");
Dave Airlieab2c0672009-12-04 10:55:24 +1000682 return -EREMOTEIO;
683 case AUX_I2C_REPLY_DEFER:
David Flynn8316f332010-12-08 16:10:21 +0000684 DRM_DEBUG_KMS("aux_i2c defer\n");
Dave Airlieab2c0672009-12-04 10:55:24 +1000685 udelay(100);
686 break;
687 default:
David Flynn8316f332010-12-08 16:10:21 +0000688 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
Dave Airlieab2c0672009-12-04 10:55:24 +1000689 return -EREMOTEIO;
690 }
691 }
David Flynn8316f332010-12-08 16:10:21 +0000692
693 DRM_ERROR("too many retries, giving up\n");
694 return -EREMOTEIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700695}
696
697static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100698intel_dp_i2c_init(struct intel_dp *intel_dp,
Zhenyu Wang55f78c42010-03-29 16:13:57 +0800699 struct intel_connector *intel_connector, const char *name)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700700{
Keith Packard0b5c5412011-09-28 16:41:05 -0700701 int ret;
702
Zhenyu Wangd54e9d22009-10-19 15:43:51 +0800703 DRM_DEBUG_KMS("i2c_init %s\n", name);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100704 intel_dp->algo.running = false;
705 intel_dp->algo.address = 0;
706 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700707
Akshay Joshi0206e352011-08-16 15:34:10 -0400708 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
Chris Wilsonea5b2132010-08-04 13:50:23 +0100709 intel_dp->adapter.owner = THIS_MODULE;
710 intel_dp->adapter.class = I2C_CLASS_DDC;
Akshay Joshi0206e352011-08-16 15:34:10 -0400711 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100712 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
713 intel_dp->adapter.algo_data = &intel_dp->algo;
714 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
715
Keith Packard0b5c5412011-09-28 16:41:05 -0700716 ironlake_edp_panel_vdd_on(intel_dp);
717 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
Keith Packardbd943152011-09-18 23:09:52 -0700718 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard0b5c5412011-09-28 16:41:05 -0700719 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700720}
721
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200722static void
723intel_dp_set_clock(struct intel_encoder *encoder,
724 struct intel_crtc_config *pipe_config, int link_bw)
725{
726 struct drm_device *dev = encoder->base.dev;
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800727 const struct dp_link_dpll *divisor = NULL;
728 int i, count = 0;
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200729
730 if (IS_G4X(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800731 divisor = gen4_dpll;
732 count = ARRAY_SIZE(gen4_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200733 } else if (IS_HASWELL(dev)) {
734 /* Haswell has special-purpose DP DDI clocks. */
735 } else if (HAS_PCH_SPLIT(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800736 divisor = pch_dpll;
737 count = ARRAY_SIZE(pch_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200738 } else if (IS_VALLEYVIEW(dev)) {
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +0800739 divisor = vlv_dpll;
740 count = ARRAY_SIZE(vlv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200741 }
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800742
743 if (divisor && count) {
744 for (i = 0; i < count; i++) {
745 if (link_bw == divisor[i].link_bw) {
746 pipe_config->dpll = divisor[i].dpll;
747 pipe_config->clock_set = true;
748 break;
749 }
750 }
751 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200752}
753
Paulo Zanoni00c09d72012-10-26 19:05:52 -0200754bool
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100755intel_dp_compute_config(struct intel_encoder *encoder,
756 struct intel_crtc_config *pipe_config)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700757{
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100758 struct drm_device *dev = encoder->base.dev;
Daniel Vetter36008362013-03-27 00:44:59 +0100759 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100760 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100761 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +0300762 enum port port = dp_to_dig_port(intel_dp)->port;
Jesse Barnes2dd24552013-04-25 12:55:01 -0700763 struct intel_crtc *intel_crtc = encoder->new_crtc;
Jani Nikuladd06f902012-10-19 14:51:50 +0300764 struct intel_connector *intel_connector = intel_dp->attached_connector;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700765 int lane_count, clock;
Daniel Vetter397fe152012-10-22 22:56:43 +0200766 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100767 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
Daniel Vetter083f9562012-04-20 20:23:49 +0200768 int bpp, mode_rate;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700769 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
Daniel Vetterff9a6752013-06-01 17:16:21 +0200770 int link_avail, link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700771
Imre Deakbc7d38a2013-05-16 14:40:36 +0300772 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100773 pipe_config->has_pch_encoder = true;
774
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200775 pipe_config->has_dp_encoder = true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700776
Jani Nikuladd06f902012-10-19 14:51:50 +0300777 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
778 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
779 adjusted_mode);
Jesse Barnes2dd24552013-04-25 12:55:01 -0700780 if (!HAS_PCH_SPLIT(dev))
781 intel_gmch_panel_fitting(intel_crtc, pipe_config,
782 intel_connector->panel.fitting_mode);
783 else
Jesse Barnesb074cec2013-04-25 12:55:02 -0700784 intel_pch_panel_fitting(intel_crtc, pipe_config,
785 intel_connector->panel.fitting_mode);
Zhao Yakui0d3a1be2010-07-19 09:43:13 +0100786 }
787
Daniel Vettercb1793c2012-06-04 18:39:21 +0200788 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
Daniel Vetter0af78a22012-05-23 11:30:55 +0200789 return false;
790
Daniel Vetter083f9562012-04-20 20:23:49 +0200791 DRM_DEBUG_KMS("DP link computation with max lane count %i "
792 "max bw %02x pixel clock %iKHz\n",
Daniel Vetter71244652012-06-04 18:39:20 +0200793 max_lane_count, bws[max_clock], adjusted_mode->clock);
Daniel Vetter083f9562012-04-20 20:23:49 +0200794
Daniel Vetter36008362013-03-27 00:44:59 +0100795 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
796 * bpc in between. */
Daniel Vetter3e7ca982013-06-01 19:45:56 +0200797 bpp = pipe_config->pipe_bpp;
Imre Deak79842112013-07-18 17:44:13 +0300798 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
799 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
800 dev_priv->vbt.edp_bpp);
Daniel Vettere1b73cb2013-05-21 09:52:16 +0200801 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
Imre Deak79842112013-07-18 17:44:13 +0300802 }
Daniel Vetter657445f2013-05-04 10:09:18 +0200803
Daniel Vetter36008362013-03-27 00:44:59 +0100804 for (; bpp >= 6*3; bpp -= 2*3) {
Daniel Vetterff9a6752013-06-01 17:16:21 +0200805 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
Daniel Vetterc4867932012-04-10 10:42:36 +0200806
Daniel Vetter36008362013-03-27 00:44:59 +0100807 for (clock = 0; clock <= max_clock; clock++) {
808 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
809 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
810 link_avail = intel_dp_max_data_rate(link_clock,
811 lane_count);
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200812
Daniel Vetter36008362013-03-27 00:44:59 +0100813 if (mode_rate <= link_avail) {
814 goto found;
815 }
816 }
817 }
818 }
819
820 return false;
821
822found:
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200823 if (intel_dp->color_range_auto) {
824 /*
825 * See:
826 * CEA-861-E - 5.1 Default Encoding Parameters
827 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
828 */
Thierry Reding18316c82012-12-20 15:41:44 +0100829 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200830 intel_dp->color_range = DP_COLOR_RANGE_16_235;
831 else
832 intel_dp->color_range = 0;
833 }
834
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200835 if (intel_dp->color_range)
Daniel Vetter50f3b012013-03-27 00:44:56 +0100836 pipe_config->limited_color_range = true;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200837
Daniel Vetter36008362013-03-27 00:44:59 +0100838 intel_dp->link_bw = bws[clock];
839 intel_dp->lane_count = lane_count;
Daniel Vetter657445f2013-05-04 10:09:18 +0200840 pipe_config->pipe_bpp = bpp;
Daniel Vetterff9a6752013-06-01 17:16:21 +0200841 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
Daniel Vetterc4867932012-04-10 10:42:36 +0200842
Daniel Vetter36008362013-03-27 00:44:59 +0100843 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
844 intel_dp->link_bw, intel_dp->lane_count,
Daniel Vetterff9a6752013-06-01 17:16:21 +0200845 pipe_config->port_clock, bpp);
Daniel Vetter36008362013-03-27 00:44:59 +0100846 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
847 mode_rate, link_avail);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700848
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200849 intel_link_compute_m_n(bpp, lane_count,
Daniel Vetterff9a6752013-06-01 17:16:21 +0200850 adjusted_mode->clock, pipe_config->port_clock,
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200851 &pipe_config->dp_m_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700852
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200853 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
854
Daniel Vetter36008362013-03-27 00:44:59 +0100855 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700856}
857
Paulo Zanoni247d89f2012-10-15 15:51:33 -0300858void intel_dp_init_link_config(struct intel_dp *intel_dp)
859{
860 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
861 intel_dp->link_configuration[0] = intel_dp->link_bw;
862 intel_dp->link_configuration[1] = intel_dp->lane_count;
863 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
864 /*
865 * Check for DPCD version > 1.1 and enhanced framing support
866 */
867 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
868 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
869 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
870 }
871}
872
Daniel Vetter7c62a162013-06-01 17:16:20 +0200873static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
Daniel Vetterea9b6002012-11-29 15:59:31 +0100874{
Daniel Vetter7c62a162013-06-01 17:16:20 +0200875 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
876 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
877 struct drm_device *dev = crtc->base.dev;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100878 struct drm_i915_private *dev_priv = dev->dev_private;
879 u32 dpa_ctl;
880
Daniel Vetterff9a6752013-06-01 17:16:21 +0200881 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
Daniel Vetterea9b6002012-11-29 15:59:31 +0100882 dpa_ctl = I915_READ(DP_A);
883 dpa_ctl &= ~DP_PLL_FREQ_MASK;
884
Daniel Vetterff9a6752013-06-01 17:16:21 +0200885 if (crtc->config.port_clock == 162000) {
Daniel Vetter1ce17032012-11-29 15:59:32 +0100886 /* For a long time we've carried around a ILK-DevA w/a for the
887 * 160MHz clock. If we're really unlucky, it's still required.
888 */
889 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
Daniel Vetterea9b6002012-11-29 15:59:31 +0100890 dpa_ctl |= DP_PLL_FREQ_160MHZ;
Daniel Vetter7c62a162013-06-01 17:16:20 +0200891 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100892 } else {
893 dpa_ctl |= DP_PLL_FREQ_270MHZ;
Daniel Vetter7c62a162013-06-01 17:16:20 +0200894 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100895 }
Daniel Vetter1ce17032012-11-29 15:59:32 +0100896
Daniel Vetterea9b6002012-11-29 15:59:31 +0100897 I915_WRITE(DP_A, dpa_ctl);
898
899 POSTING_READ(DP_A);
900 udelay(500);
901}
902
Daniel Vetterb934223d2013-07-21 21:37:05 +0200903static void intel_dp_mode_set(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700904{
Daniel Vetterb934223d2013-07-21 21:37:05 +0200905 struct drm_device *dev = encoder->base.dev;
Keith Packard417e8222011-11-01 19:54:11 -0700906 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200907 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +0300908 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200909 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
910 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700911
Keith Packard417e8222011-11-01 19:54:11 -0700912 /*
Keith Packard1a2eb462011-11-16 16:26:07 -0800913 * There are four kinds of DP registers:
Keith Packard417e8222011-11-01 19:54:11 -0700914 *
915 * IBX PCH
Keith Packard1a2eb462011-11-16 16:26:07 -0800916 * SNB CPU
917 * IVB CPU
Keith Packard417e8222011-11-01 19:54:11 -0700918 * CPT PCH
919 *
920 * IBX PCH and CPU are the same for almost everything,
921 * except that the CPU DP PLL is configured in this
922 * register
923 *
924 * CPT PCH is quite different, having many bits moved
925 * to the TRANS_DP_CTL register instead. That
926 * configuration happens (oddly) in ironlake_pch_enable
927 */
Adam Jackson9c9e7922010-04-05 17:57:59 -0400928
Keith Packard417e8222011-11-01 19:54:11 -0700929 /* Preserve the BIOS-computed detected bit. This is
930 * supposed to be read-only.
931 */
932 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700933
Keith Packard417e8222011-11-01 19:54:11 -0700934 /* Handle DP bits in common between all three register formats */
Keith Packard417e8222011-11-01 19:54:11 -0700935 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Daniel Vetter17aa6be2013-04-30 14:01:40 +0200936 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700937
Wu Fengguange0dac652011-09-05 14:25:34 +0800938 if (intel_dp->has_audio) {
939 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
Daniel Vetter7c62a162013-06-01 17:16:20 +0200940 pipe_name(crtc->pipe));
Chris Wilsonea5b2132010-08-04 13:50:23 +0100941 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200942 intel_write_eld(&encoder->base, adjusted_mode);
Wu Fengguange0dac652011-09-05 14:25:34 +0800943 }
Paulo Zanoni247d89f2012-10-15 15:51:33 -0300944
945 intel_dp_init_link_config(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700946
Keith Packard417e8222011-11-01 19:54:11 -0700947 /* Split out the IBX/CPU vs CPT settings */
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800948
Imre Deakbc7d38a2013-05-16 14:40:36 +0300949 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
Keith Packard1a2eb462011-11-16 16:26:07 -0800950 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
951 intel_dp->DP |= DP_SYNC_HS_HIGH;
952 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
953 intel_dp->DP |= DP_SYNC_VS_HIGH;
954 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
955
956 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
957 intel_dp->DP |= DP_ENHANCED_FRAMING;
958
Daniel Vetter7c62a162013-06-01 17:16:20 +0200959 intel_dp->DP |= crtc->pipe << 29;
Imre Deakbc7d38a2013-05-16 14:40:36 +0300960 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
Jesse Barnesb2634012013-03-28 09:55:40 -0700961 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200962 intel_dp->DP |= intel_dp->color_range;
Keith Packard417e8222011-11-01 19:54:11 -0700963
964 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
965 intel_dp->DP |= DP_SYNC_HS_HIGH;
966 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
967 intel_dp->DP |= DP_SYNC_VS_HIGH;
968 intel_dp->DP |= DP_LINK_TRAIN_OFF;
969
970 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
971 intel_dp->DP |= DP_ENHANCED_FRAMING;
972
Daniel Vetter7c62a162013-06-01 17:16:20 +0200973 if (crtc->pipe == 1)
Keith Packard417e8222011-11-01 19:54:11 -0700974 intel_dp->DP |= DP_PIPEB_SELECT;
Keith Packard417e8222011-11-01 19:54:11 -0700975 } else {
976 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800977 }
Daniel Vetterea9b6002012-11-29 15:59:31 +0100978
Imre Deakbc7d38a2013-05-16 14:40:36 +0300979 if (port == PORT_A && !IS_VALLEYVIEW(dev))
Daniel Vetter7c62a162013-06-01 17:16:20 +0200980 ironlake_set_pll_cpu_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700981}
982
Keith Packard99ea7122011-11-01 19:57:50 -0700983#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
984#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
985
986#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
987#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
988
989#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
990#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
991
992static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
993 u32 mask,
994 u32 value)
995{
Paulo Zanoni30add222012-10-26 19:05:45 -0200996 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -0700997 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -0700998 u32 pp_stat_reg, pp_ctrl_reg;
999
Jani Nikulabf13e812013-09-06 07:40:05 +03001000 pp_stat_reg = _pp_stat_reg(intel_dp);
1001 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001002
1003 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001004 mask, value,
1005 I915_READ(pp_stat_reg),
1006 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001007
Jesse Barnes453c5422013-03-28 09:55:41 -07001008 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
Keith Packard99ea7122011-11-01 19:57:50 -07001009 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001010 I915_READ(pp_stat_reg),
1011 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001012 }
1013}
1014
1015static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1016{
1017 DRM_DEBUG_KMS("Wait for panel power on\n");
1018 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1019}
1020
Keith Packardbd943152011-09-18 23:09:52 -07001021static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1022{
Keith Packardbd943152011-09-18 23:09:52 -07001023 DRM_DEBUG_KMS("Wait for panel power off time\n");
Keith Packard99ea7122011-11-01 19:57:50 -07001024 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
Keith Packardbd943152011-09-18 23:09:52 -07001025}
Keith Packardbd943152011-09-18 23:09:52 -07001026
Keith Packard99ea7122011-11-01 19:57:50 -07001027static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1028{
1029 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1030 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1031}
Keith Packardbd943152011-09-18 23:09:52 -07001032
Keith Packard99ea7122011-11-01 19:57:50 -07001033
Keith Packard832dd3c2011-11-01 19:34:06 -07001034/* Read the current pp_control value, unlocking the register if it
1035 * is locked
1036 */
1037
Jesse Barnes453c5422013-03-28 09:55:41 -07001038static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
Keith Packard832dd3c2011-11-01 19:34:06 -07001039{
Jesse Barnes453c5422013-03-28 09:55:41 -07001040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 u32 control;
Jesse Barnes453c5422013-03-28 09:55:41 -07001043
Jani Nikulabf13e812013-09-06 07:40:05 +03001044 control = I915_READ(_pp_ctrl_reg(intel_dp));
Keith Packard832dd3c2011-11-01 19:34:06 -07001045 control &= ~PANEL_UNLOCK_MASK;
1046 control |= PANEL_UNLOCK_REGS;
1047 return control;
Keith Packardbd943152011-09-18 23:09:52 -07001048}
1049
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001050void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001051{
Paulo Zanoni30add222012-10-26 19:05:45 -02001052 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001055 u32 pp_stat_reg, pp_ctrl_reg;
Jesse Barnes5d613502011-01-24 17:10:54 -08001056
Keith Packard97af61f572011-09-28 16:23:51 -07001057 if (!is_edp(intel_dp))
1058 return;
Keith Packardf01eca22011-09-28 16:48:10 -07001059 DRM_DEBUG_KMS("Turn eDP VDD on\n");
Jesse Barnes5d613502011-01-24 17:10:54 -08001060
Keith Packardbd943152011-09-18 23:09:52 -07001061 WARN(intel_dp->want_panel_vdd,
1062 "eDP VDD already requested on\n");
1063
1064 intel_dp->want_panel_vdd = true;
Keith Packard99ea7122011-11-01 19:57:50 -07001065
Keith Packardbd943152011-09-18 23:09:52 -07001066 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1067 DRM_DEBUG_KMS("eDP VDD already on\n");
1068 return;
1069 }
1070
Keith Packard99ea7122011-11-01 19:57:50 -07001071 if (!ironlake_edp_have_panel_power(intel_dp))
1072 ironlake_wait_panel_power_cycle(intel_dp);
1073
Jesse Barnes453c5422013-03-28 09:55:41 -07001074 pp = ironlake_get_pp_control(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001075 pp |= EDP_FORCE_VDD;
Keith Packardebf33b12011-09-29 15:53:27 -07001076
Jani Nikulabf13e812013-09-06 07:40:05 +03001077 pp_stat_reg = _pp_stat_reg(intel_dp);
1078 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001079
1080 I915_WRITE(pp_ctrl_reg, pp);
1081 POSTING_READ(pp_ctrl_reg);
1082 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1083 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Keith Packardebf33b12011-09-29 15:53:27 -07001084 /*
1085 * If the panel wasn't on, delay before accessing aux channel
1086 */
1087 if (!ironlake_edp_have_panel_power(intel_dp)) {
Keith Packardbd943152011-09-18 23:09:52 -07001088 DRM_DEBUG_KMS("eDP was not running\n");
Keith Packardf01eca22011-09-28 16:48:10 -07001089 msleep(intel_dp->panel_power_up_delay);
Keith Packardf01eca22011-09-28 16:48:10 -07001090 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001091}
1092
Keith Packardbd943152011-09-18 23:09:52 -07001093static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001094{
Paulo Zanoni30add222012-10-26 19:05:45 -02001095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001098 u32 pp_stat_reg, pp_ctrl_reg;
Jesse Barnes5d613502011-01-24 17:10:54 -08001099
Daniel Vettera0e99e62012-12-02 01:05:46 +01001100 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1101
Keith Packardbd943152011-09-18 23:09:52 -07001102 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
Jesse Barnes453c5422013-03-28 09:55:41 -07001103 pp = ironlake_get_pp_control(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001104 pp &= ~EDP_FORCE_VDD;
Jesse Barnes453c5422013-03-28 09:55:41 -07001105
Jani Nikulabf13e812013-09-06 07:40:05 +03001106 pp_stat_reg = _pp_ctrl_reg(intel_dp);
1107 pp_ctrl_reg = _pp_stat_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001108
1109 I915_WRITE(pp_ctrl_reg, pp);
1110 POSTING_READ(pp_ctrl_reg);
Jesse Barnes5d613502011-01-24 17:10:54 -08001111
Keith Packardbd943152011-09-18 23:09:52 -07001112 /* Make sure sequencer is idle before allowing subsequent activity */
Jesse Barnes453c5422013-03-28 09:55:41 -07001113 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1114 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001115 msleep(intel_dp->panel_power_down_delay);
Keith Packardbd943152011-09-18 23:09:52 -07001116 }
1117}
1118
1119static void ironlake_panel_vdd_work(struct work_struct *__work)
1120{
1121 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1122 struct intel_dp, panel_vdd_work);
Paulo Zanoni30add222012-10-26 19:05:45 -02001123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001124
Keith Packard627f7672011-10-31 11:30:10 -07001125 mutex_lock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001126 ironlake_panel_vdd_off_sync(intel_dp);
Keith Packard627f7672011-10-31 11:30:10 -07001127 mutex_unlock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001128}
1129
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001130void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
Keith Packardbd943152011-09-18 23:09:52 -07001131{
Keith Packard97af61f572011-09-28 16:23:51 -07001132 if (!is_edp(intel_dp))
1133 return;
Jesse Barnes5d613502011-01-24 17:10:54 -08001134
Keith Packardbd943152011-09-18 23:09:52 -07001135 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1136 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
Keith Packardf2e8b182011-11-01 20:01:35 -07001137
Keith Packardbd943152011-09-18 23:09:52 -07001138 intel_dp->want_panel_vdd = false;
1139
1140 if (sync) {
1141 ironlake_panel_vdd_off_sync(intel_dp);
1142 } else {
1143 /*
1144 * Queue the timer to fire a long
1145 * time from now (relative to the power down delay)
1146 * to keep the panel power up across a sequence of operations
1147 */
1148 schedule_delayed_work(&intel_dp->panel_vdd_work,
1149 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1150 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001151}
1152
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001153void ironlake_edp_panel_on(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001154{
Paulo Zanoni30add222012-10-26 19:05:45 -02001155 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001156 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packard99ea7122011-11-01 19:57:50 -07001157 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001158 u32 pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07001159
Keith Packard97af61f572011-09-28 16:23:51 -07001160 if (!is_edp(intel_dp))
Keith Packardbd943152011-09-18 23:09:52 -07001161 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001162
1163 DRM_DEBUG_KMS("Turn eDP power on\n");
1164
1165 if (ironlake_edp_have_panel_power(intel_dp)) {
1166 DRM_DEBUG_KMS("eDP power already on\n");
Keith Packard7d639f32011-09-29 16:05:34 -07001167 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001168 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001169
Keith Packard99ea7122011-11-01 19:57:50 -07001170 ironlake_wait_panel_power_cycle(intel_dp);
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001171
Jani Nikulabf13e812013-09-06 07:40:05 +03001172 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001173 pp = ironlake_get_pp_control(intel_dp);
Keith Packard05ce1a42011-09-29 16:33:01 -07001174 if (IS_GEN5(dev)) {
1175 /* ILK workaround: disable reset around power sequence */
1176 pp &= ~PANEL_POWER_RESET;
Jani Nikulabf13e812013-09-06 07:40:05 +03001177 I915_WRITE(pp_ctrl_reg, pp);
1178 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07001179 }
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001180
Keith Packard1c0ae802011-09-19 13:59:29 -07001181 pp |= POWER_TARGET_ON;
Keith Packard99ea7122011-11-01 19:57:50 -07001182 if (!IS_GEN5(dev))
1183 pp |= PANEL_POWER_RESET;
1184
Jesse Barnes453c5422013-03-28 09:55:41 -07001185 I915_WRITE(pp_ctrl_reg, pp);
1186 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07001187
Keith Packard99ea7122011-11-01 19:57:50 -07001188 ironlake_wait_panel_on(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001189
Keith Packard05ce1a42011-09-29 16:33:01 -07001190 if (IS_GEN5(dev)) {
1191 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
Jani Nikulabf13e812013-09-06 07:40:05 +03001192 I915_WRITE(pp_ctrl_reg, pp);
1193 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07001194 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001195}
1196
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001197void ironlake_edp_panel_off(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001198{
Paulo Zanoni30add222012-10-26 19:05:45 -02001199 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001200 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packard99ea7122011-11-01 19:57:50 -07001201 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001202 u32 pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07001203
Keith Packard97af61f572011-09-28 16:23:51 -07001204 if (!is_edp(intel_dp))
1205 return;
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001206
Keith Packard99ea7122011-11-01 19:57:50 -07001207 DRM_DEBUG_KMS("Turn eDP power off\n");
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001208
Daniel Vetter6cb49832012-05-20 17:14:50 +02001209 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
Jesse Barnes9934c132010-07-22 13:18:19 -07001210
Jesse Barnes453c5422013-03-28 09:55:41 -07001211 pp = ironlake_get_pp_control(intel_dp);
Daniel Vetter35a38552012-08-12 22:17:14 +02001212 /* We need to switch off panel power _and_ force vdd, for otherwise some
1213 * panels get very unhappy and cease to work. */
1214 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
Jesse Barnes453c5422013-03-28 09:55:41 -07001215
Jani Nikulabf13e812013-09-06 07:40:05 +03001216 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001217
1218 I915_WRITE(pp_ctrl_reg, pp);
1219 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07001220
Daniel Vetter35a38552012-08-12 22:17:14 +02001221 intel_dp->want_panel_vdd = false;
1222
Keith Packard99ea7122011-11-01 19:57:50 -07001223 ironlake_wait_panel_off(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001224}
1225
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001226void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001227{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001228 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1229 struct drm_device *dev = intel_dig_port->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001230 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001231 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001232 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001233 u32 pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001234
Keith Packardf01eca22011-09-28 16:48:10 -07001235 if (!is_edp(intel_dp))
1236 return;
1237
Zhao Yakui28c97732009-10-09 11:39:41 +08001238 DRM_DEBUG_KMS("\n");
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001239 /*
1240 * If we enable the backlight right away following a panel power
1241 * on, we may see slight flicker as the panel syncs with the eDP
1242 * link. So delay a bit to make sure the image is solid before
1243 * allowing it to appear.
1244 */
Keith Packardf01eca22011-09-28 16:48:10 -07001245 msleep(intel_dp->backlight_on_delay);
Jesse Barnes453c5422013-03-28 09:55:41 -07001246 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001247 pp |= EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07001248
Jani Nikulabf13e812013-09-06 07:40:05 +03001249 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001250
1251 I915_WRITE(pp_ctrl_reg, pp);
1252 POSTING_READ(pp_ctrl_reg);
Daniel Vetter035aa3d2012-10-20 20:57:42 +02001253
1254 intel_panel_enable_backlight(dev, pipe);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001255}
1256
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001257void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001258{
Paulo Zanoni30add222012-10-26 19:05:45 -02001259 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001262 u32 pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001263
Keith Packardf01eca22011-09-28 16:48:10 -07001264 if (!is_edp(intel_dp))
1265 return;
1266
Daniel Vetter035aa3d2012-10-20 20:57:42 +02001267 intel_panel_disable_backlight(dev);
1268
Zhao Yakui28c97732009-10-09 11:39:41 +08001269 DRM_DEBUG_KMS("\n");
Jesse Barnes453c5422013-03-28 09:55:41 -07001270 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001271 pp &= ~EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07001272
Jani Nikulabf13e812013-09-06 07:40:05 +03001273 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001274
1275 I915_WRITE(pp_ctrl_reg, pp);
1276 POSTING_READ(pp_ctrl_reg);
Keith Packardf01eca22011-09-28 16:48:10 -07001277 msleep(intel_dp->backlight_off_delay);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001278}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001279
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001280static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07001281{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1283 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1284 struct drm_device *dev = crtc->dev;
Jesse Barnesd240f202010-08-13 15:43:26 -07001285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 u32 dpa_ctl;
1287
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001288 assert_pipe_disabled(dev_priv,
1289 to_intel_crtc(crtc)->pipe);
1290
Jesse Barnesd240f202010-08-13 15:43:26 -07001291 DRM_DEBUG_KMS("\n");
1292 dpa_ctl = I915_READ(DP_A);
Daniel Vetter07679352012-09-06 22:15:42 +02001293 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1294 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1295
1296 /* We don't adjust intel_dp->DP while tearing down the link, to
1297 * facilitate link retraining (e.g. after hotplug). Hence clear all
1298 * enable bits here to ensure that we don't enable too much. */
1299 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1300 intel_dp->DP |= DP_PLL_ENABLE;
1301 I915_WRITE(DP_A, intel_dp->DP);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001302 POSTING_READ(DP_A);
1303 udelay(200);
Jesse Barnesd240f202010-08-13 15:43:26 -07001304}
1305
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001306static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07001307{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1310 struct drm_device *dev = crtc->dev;
Jesse Barnesd240f202010-08-13 15:43:26 -07001311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 u32 dpa_ctl;
1313
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001314 assert_pipe_disabled(dev_priv,
1315 to_intel_crtc(crtc)->pipe);
1316
Jesse Barnesd240f202010-08-13 15:43:26 -07001317 dpa_ctl = I915_READ(DP_A);
Daniel Vetter07679352012-09-06 22:15:42 +02001318 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1319 "dp pll off, should be on\n");
1320 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1321
1322 /* We can't rely on the value tracked for the DP register in
1323 * intel_dp->DP because link_down must not change that (otherwise link
1324 * re-training will fail. */
Jesse Barnes298b0b32010-10-07 16:01:24 -07001325 dpa_ctl &= ~DP_PLL_ENABLE;
Jesse Barnesd240f202010-08-13 15:43:26 -07001326 I915_WRITE(DP_A, dpa_ctl);
Chris Wilson1af5fa12010-09-08 21:07:28 +01001327 POSTING_READ(DP_A);
Jesse Barnesd240f202010-08-13 15:43:26 -07001328 udelay(200);
1329}
1330
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001331/* If the sink supports it, try to set the power state appropriately */
Paulo Zanonic19b0662012-10-15 15:51:41 -03001332void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001333{
1334 int ret, i;
1335
1336 /* Should have a valid DPCD by this point */
1337 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1338 return;
1339
1340 if (mode != DRM_MODE_DPMS_ON) {
1341 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1342 DP_SET_POWER_D3);
1343 if (ret != 1)
1344 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1345 } else {
1346 /*
1347 * When turning on, we need to retry for 1ms to give the sink
1348 * time to wake up.
1349 */
1350 for (i = 0; i < 3; i++) {
1351 ret = intel_dp_aux_native_write_1(intel_dp,
1352 DP_SET_POWER,
1353 DP_SET_POWER_D0);
1354 if (ret == 1)
1355 break;
1356 msleep(1);
1357 }
1358 }
1359}
1360
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001361static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1362 enum pipe *pipe)
Jesse Barnesd240f202010-08-13 15:43:26 -07001363{
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001364 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001365 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001366 struct drm_device *dev = encoder->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 u32 tmp = I915_READ(intel_dp->output_reg);
Jesse Barnesd240f202010-08-13 15:43:26 -07001369
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001370 if (!(tmp & DP_PORT_EN))
1371 return false;
1372
Imre Deakbc7d38a2013-05-16 14:40:36 +03001373 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001374 *pipe = PORT_TO_PIPE_CPT(tmp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001375 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001376 *pipe = PORT_TO_PIPE(tmp);
1377 } else {
1378 u32 trans_sel;
1379 u32 trans_dp;
1380 int i;
1381
1382 switch (intel_dp->output_reg) {
1383 case PCH_DP_B:
1384 trans_sel = TRANS_DP_PORT_SEL_B;
1385 break;
1386 case PCH_DP_C:
1387 trans_sel = TRANS_DP_PORT_SEL_C;
1388 break;
1389 case PCH_DP_D:
1390 trans_sel = TRANS_DP_PORT_SEL_D;
1391 break;
1392 default:
1393 return true;
1394 }
1395
1396 for_each_pipe(i) {
1397 trans_dp = I915_READ(TRANS_DP_CTL(i));
1398 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1399 *pipe = i;
1400 return true;
1401 }
1402 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001403
Daniel Vetter4a0833e2012-10-26 10:58:11 +02001404 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1405 intel_dp->output_reg);
1406 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001407
1408 return true;
1409}
1410
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001411static void intel_dp_get_config(struct intel_encoder *encoder,
1412 struct intel_crtc_config *pipe_config)
1413{
1414 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001415 u32 tmp, flags = 0;
Xiong Zhang63000ef2013-06-28 12:59:06 +08001416 struct drm_device *dev = encoder->base.dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 enum port port = dp_to_dig_port(intel_dp)->port;
1419 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Ville Syrjälä18442d02013-09-13 16:00:08 +03001420 int dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001421
Xiong Zhang63000ef2013-06-28 12:59:06 +08001422 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1423 tmp = I915_READ(intel_dp->output_reg);
1424 if (tmp & DP_SYNC_HS_HIGH)
1425 flags |= DRM_MODE_FLAG_PHSYNC;
1426 else
1427 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001428
Xiong Zhang63000ef2013-06-28 12:59:06 +08001429 if (tmp & DP_SYNC_VS_HIGH)
1430 flags |= DRM_MODE_FLAG_PVSYNC;
1431 else
1432 flags |= DRM_MODE_FLAG_NVSYNC;
1433 } else {
1434 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1435 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1436 flags |= DRM_MODE_FLAG_PHSYNC;
1437 else
1438 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001439
Xiong Zhang63000ef2013-06-28 12:59:06 +08001440 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1441 flags |= DRM_MODE_FLAG_PVSYNC;
1442 else
1443 flags |= DRM_MODE_FLAG_NVSYNC;
1444 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001445
1446 pipe_config->adjusted_mode.flags |= flags;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03001447
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03001448 pipe_config->has_dp_encoder = true;
1449
1450 intel_dp_get_m_n(crtc, pipe_config);
1451
Ville Syrjälä18442d02013-09-13 16:00:08 +03001452 if (port == PORT_A) {
Jesse Barnesf1f644d2013-06-27 00:39:25 +03001453 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1454 pipe_config->port_clock = 162000;
1455 else
1456 pipe_config->port_clock = 270000;
1457 }
Ville Syrjälä18442d02013-09-13 16:00:08 +03001458
1459 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1460 &pipe_config->dp_m_n);
1461
1462 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1463 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1464
1465 pipe_config->adjusted_mode.clock = dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001466}
1467
Shobhit Kumar2293bb52013-07-11 18:44:56 -03001468static bool is_edp_psr(struct intel_dp *intel_dp)
1469{
1470 return is_edp(intel_dp) &&
1471 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1472}
1473
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001474static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1475{
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1477
1478 if (!IS_HASWELL(dev))
1479 return false;
1480
1481 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1482}
1483
1484static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1485 struct edp_vsc_psr *vsc_psr)
1486{
1487 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1488 struct drm_device *dev = dig_port->base.base.dev;
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1491 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1492 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1493 uint32_t *data = (uint32_t *) vsc_psr;
1494 unsigned int i;
1495
1496 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1497 the video DIP being updated before program video DIP data buffer
1498 registers for DIP being updated. */
1499 I915_WRITE(ctl_reg, 0);
1500 POSTING_READ(ctl_reg);
1501
1502 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1503 if (i < sizeof(struct edp_vsc_psr))
1504 I915_WRITE(data_reg + i, *data++);
1505 else
1506 I915_WRITE(data_reg + i, 0);
1507 }
1508
1509 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1510 POSTING_READ(ctl_reg);
1511}
1512
1513static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1514{
1515 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517 struct edp_vsc_psr psr_vsc;
1518
1519 if (intel_dp->psr_setup_done)
1520 return;
1521
1522 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1523 memset(&psr_vsc, 0, sizeof(psr_vsc));
1524 psr_vsc.sdp_header.HB0 = 0;
1525 psr_vsc.sdp_header.HB1 = 0x7;
1526 psr_vsc.sdp_header.HB2 = 0x2;
1527 psr_vsc.sdp_header.HB3 = 0x8;
1528 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1529
1530 /* Avoid continuous PSR exit by masking memup and hpd */
1531 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1532 EDP_PSR_DEBUG_MASK_HPD);
1533
1534 intel_dp->psr_setup_done = true;
1535}
1536
1537static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1538{
1539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1540 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbc866252013-07-21 16:00:03 +01001541 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001542 int precharge = 0x3;
1543 int msg_size = 5; /* Header(4) + Message(1) */
1544
1545 /* Enable PSR in sink */
1546 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1547 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1548 DP_PSR_ENABLE &
1549 ~DP_PSR_MAIN_LINK_ACTIVE);
1550 else
1551 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1552 DP_PSR_ENABLE |
1553 DP_PSR_MAIN_LINK_ACTIVE);
1554
1555 /* Setup AUX registers */
1556 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1557 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1558 I915_WRITE(EDP_PSR_AUX_CTL,
1559 DP_AUX_CH_CTL_TIME_OUT_400us |
1560 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1561 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1562 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1563}
1564
1565static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1566{
1567 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569 uint32_t max_sleep_time = 0x1f;
1570 uint32_t idle_frames = 1;
1571 uint32_t val = 0x0;
1572
1573 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1574 val |= EDP_PSR_LINK_STANDBY;
1575 val |= EDP_PSR_TP2_TP3_TIME_0us;
1576 val |= EDP_PSR_TP1_TIME_0us;
1577 val |= EDP_PSR_SKIP_AUX_EXIT;
1578 } else
1579 val |= EDP_PSR_LINK_DISABLE;
1580
1581 I915_WRITE(EDP_PSR_CTL, val |
1582 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1583 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1584 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1585 EDP_PSR_ENABLE);
1586}
1587
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001588static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1589{
1590 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1591 struct drm_device *dev = dig_port->base.base.dev;
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 struct drm_crtc *crtc = dig_port->base.base.crtc;
1594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1595 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1596 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1597
1598 if (!IS_HASWELL(dev)) {
1599 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1600 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1601 return false;
1602 }
1603
1604 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1605 (dig_port->port != PORT_A)) {
1606 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1607 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1608 return false;
1609 }
1610
1611 if (!is_edp_psr(intel_dp)) {
1612 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1613 dev_priv->no_psr_reason = PSR_NO_SINK;
1614 return false;
1615 }
1616
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001617 if (!i915_enable_psr) {
1618 DRM_DEBUG_KMS("PSR disable by flag\n");
1619 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1620 return false;
1621 }
1622
Chris Wilsoncd234b02013-08-02 20:39:49 +01001623 crtc = dig_port->base.base.crtc;
1624 if (crtc == NULL) {
1625 DRM_DEBUG_KMS("crtc not active for PSR\n");
1626 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1627 return false;
1628 }
1629
1630 intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläca73b4f2013-09-04 18:25:24 +03001631 if (!intel_crtc->active || !crtc->fb ||
1632 !intel_crtc->config.adjusted_mode.clock) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001633 DRM_DEBUG_KMS("crtc not active for PSR\n");
1634 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1635 return false;
1636 }
1637
Chris Wilsoncd234b02013-08-02 20:39:49 +01001638 obj = to_intel_framebuffer(crtc->fb)->obj;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001639 if (obj->tiling_mode != I915_TILING_X ||
1640 obj->fence_reg == I915_FENCE_REG_NONE) {
1641 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1642 dev_priv->no_psr_reason = PSR_NOT_TILED;
1643 return false;
1644 }
1645
1646 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1647 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1648 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1649 return false;
1650 }
1651
1652 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1653 S3D_ENABLE) {
1654 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1655 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1656 return false;
1657 }
1658
Ville Syrjäläca73b4f2013-09-04 18:25:24 +03001659 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001660 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1661 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1662 return false;
1663 }
1664
1665 return true;
1666}
1667
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001668static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001669{
1670 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1671
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001672 if (!intel_edp_psr_match_conditions(intel_dp) ||
1673 intel_edp_is_psr_enabled(dev))
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001674 return;
1675
1676 /* Setup PSR once */
1677 intel_edp_psr_setup(intel_dp);
1678
1679 /* Enable PSR on the panel */
1680 intel_edp_psr_enable_sink(intel_dp);
1681
1682 /* Enable PSR on the host */
1683 intel_edp_psr_enable_source(intel_dp);
1684}
1685
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001686void intel_edp_psr_enable(struct intel_dp *intel_dp)
1687{
1688 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1689
1690 if (intel_edp_psr_match_conditions(intel_dp) &&
1691 !intel_edp_is_psr_enabled(dev))
1692 intel_edp_psr_do_enable(intel_dp);
1693}
1694
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001695void intel_edp_psr_disable(struct intel_dp *intel_dp)
1696{
1697 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699
1700 if (!intel_edp_is_psr_enabled(dev))
1701 return;
1702
1703 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1704
1705 /* Wait till PSR is idle */
1706 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1707 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1708 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1709}
1710
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001711void intel_edp_psr_update(struct drm_device *dev)
1712{
1713 struct intel_encoder *encoder;
1714 struct intel_dp *intel_dp = NULL;
1715
1716 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1717 if (encoder->type == INTEL_OUTPUT_EDP) {
1718 intel_dp = enc_to_intel_dp(&encoder->base);
1719
1720 if (!is_edp_psr(intel_dp))
1721 return;
1722
1723 if (!intel_edp_psr_match_conditions(intel_dp))
1724 intel_edp_psr_disable(intel_dp);
1725 else
1726 if (!intel_edp_is_psr_enabled(dev))
1727 intel_edp_psr_do_enable(intel_dp);
1728 }
1729}
1730
Daniel Vettere8cb4552012-07-01 13:05:48 +02001731static void intel_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001732{
Daniel Vettere8cb4552012-07-01 13:05:48 +02001733 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03001734 enum port port = dp_to_dig_port(intel_dp)->port;
1735 struct drm_device *dev = encoder->base.dev;
Daniel Vetter6cb49832012-05-20 17:14:50 +02001736
1737 /* Make sure the panel is off before trying to change the mode. But also
1738 * ensure that we have vdd while we switch off the panel. */
1739 ironlake_edp_panel_vdd_on(intel_dp);
Keith Packard21264c62011-11-01 20:25:21 -07001740 ironlake_edp_backlight_off(intel_dp);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001741 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
Daniel Vetter35a38552012-08-12 22:17:14 +02001742 ironlake_edp_panel_off(intel_dp);
Daniel Vetter37398502012-09-06 22:15:44 +02001743
1744 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
Imre Deak982a3862013-05-23 19:39:40 +03001745 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
Daniel Vetter37398502012-09-06 22:15:44 +02001746 intel_dp_link_down(intel_dp);
Jesse Barnesd240f202010-08-13 15:43:26 -07001747}
1748
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001749static void intel_post_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001750{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001751 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03001752 enum port port = dp_to_dig_port(intel_dp)->port;
Jesse Barnesb2634012013-03-28 09:55:40 -07001753 struct drm_device *dev = encoder->base.dev;
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001754
Imre Deak982a3862013-05-23 19:39:40 +03001755 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
Daniel Vetter37398502012-09-06 22:15:44 +02001756 intel_dp_link_down(intel_dp);
Jesse Barnesb2634012013-03-28 09:55:40 -07001757 if (!IS_VALLEYVIEW(dev))
1758 ironlake_edp_pll_off(intel_dp);
Daniel Vetter37398502012-09-06 22:15:44 +02001759 }
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001760}
1761
Daniel Vettere8cb4552012-07-01 13:05:48 +02001762static void intel_enable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001763{
Daniel Vettere8cb4552012-07-01 13:05:48 +02001764 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1765 struct drm_device *dev = encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001766 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001767 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001768
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02001769 if (WARN_ON(dp_reg & DP_PORT_EN))
1770 return;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001771
1772 ironlake_edp_panel_vdd_on(intel_dp);
1773 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1774 intel_dp_start_link_train(intel_dp);
1775 ironlake_edp_panel_on(intel_dp);
1776 ironlake_edp_panel_vdd_off(intel_dp, true);
1777 intel_dp_complete_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03001778 intel_dp_stop_link_train(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001779}
Jesse Barnes89b667f2013-04-18 14:51:36 -07001780
Jani Nikulaecff4f32013-09-06 07:38:29 +03001781static void g4x_enable_dp(struct intel_encoder *encoder)
1782{
Jani Nikula828f5c62013-09-05 16:44:45 +03001783 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1784
Jani Nikulaecff4f32013-09-06 07:38:29 +03001785 intel_enable_dp(encoder);
Jani Nikula828f5c62013-09-05 16:44:45 +03001786 ironlake_edp_backlight_on(intel_dp);
Jani Nikulaecff4f32013-09-06 07:38:29 +03001787}
1788
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001789static void vlv_enable_dp(struct intel_encoder *encoder)
1790{
Jani Nikula828f5c62013-09-05 16:44:45 +03001791 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1792
1793 ironlake_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001794}
1795
Jani Nikulaecff4f32013-09-06 07:38:29 +03001796static void g4x_pre_enable_dp(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001797{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001798 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001799 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001800
1801 if (dport->port == PORT_A)
1802 ironlake_edp_pll_on(intel_dp);
1803}
1804
1805static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1806{
1807 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1808 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jesse Barnesb2634012013-03-28 09:55:40 -07001809 struct drm_device *dev = encoder->base.dev;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001810 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1812 int port = vlv_dport_to_channel(dport);
1813 int pipe = intel_crtc->pipe;
Jani Nikulabf13e812013-09-06 07:40:05 +03001814 struct edp_power_seq power_seq;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001815 u32 val;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001816
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001817 mutex_lock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001818
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001819 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001820 val = 0;
1821 if (pipe)
1822 val |= (1<<21);
1823 else
1824 val &= ~(1<<21);
1825 val |= 0x001000c4;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001826 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1827 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1828 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001829
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001830 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001831
Jani Nikulabf13e812013-09-06 07:40:05 +03001832 /* init power sequencer on this pipe and port */
1833 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1834 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1835 &power_seq);
1836
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001837 intel_enable_dp(encoder);
1838
1839 vlv_wait_port_ready(dev_priv, port);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001840}
1841
Jani Nikulaecff4f32013-09-06 07:38:29 +03001842static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001843{
1844 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1845 struct drm_device *dev = encoder->base.dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001847 struct intel_crtc *intel_crtc =
1848 to_intel_crtc(encoder->base.crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001849 int port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001850 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001851
Jesse Barnes89b667f2013-04-18 14:51:36 -07001852 /* Program Tx lane resets to default */
Chris Wilson0980a602013-07-26 19:57:35 +01001853 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001854 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001855 DPIO_PCS_TX_LANE2_RESET |
1856 DPIO_PCS_TX_LANE1_RESET);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001857 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001858 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1859 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1860 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1861 DPIO_PCS_CLK_SOFT_RESET);
1862
1863 /* Fix up inter-pair skew failure */
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001864 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1865 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1866 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
Chris Wilson0980a602013-07-26 19:57:35 +01001867 mutex_unlock(&dev_priv->dpio_lock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001868}
1869
1870/*
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001871 * Native read with retry for link status and receiver capability reads for
1872 * cases where the sink may still be asleep.
1873 */
1874static bool
1875intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1876 uint8_t *recv, int recv_bytes)
1877{
1878 int ret, i;
1879
1880 /*
1881 * Sinks are *supposed* to come up within 1ms from an off state,
1882 * but we're also supposed to retry 3 times per the spec.
1883 */
1884 for (i = 0; i < 3; i++) {
1885 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1886 recv_bytes);
1887 if (ret == recv_bytes)
1888 return true;
1889 msleep(1);
1890 }
1891
1892 return false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001893}
1894
1895/*
1896 * Fetch AUX CH registers 0x202 - 0x207 which contain
1897 * link status information
1898 */
1899static bool
Keith Packard93f62da2011-11-01 19:45:03 -07001900intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001901{
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001902 return intel_dp_aux_native_read_retry(intel_dp,
1903 DP_LANE0_1_STATUS,
Keith Packard93f62da2011-11-01 19:45:03 -07001904 link_status,
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001905 DP_LINK_STATUS_SIZE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001906}
1907
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001908#if 0
1909static char *voltage_names[] = {
1910 "0.4V", "0.6V", "0.8V", "1.2V"
1911};
1912static char *pre_emph_names[] = {
1913 "0dB", "3.5dB", "6dB", "9.5dB"
1914};
1915static char *link_train_names[] = {
1916 "pattern 1", "pattern 2", "idle", "off"
1917};
1918#endif
1919
1920/*
1921 * These are source-specific values; current Intel hardware supports
1922 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1923 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001924
1925static uint8_t
Keith Packard1a2eb462011-11-16 16:26:07 -08001926intel_dp_voltage_max(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001927{
Paulo Zanoni30add222012-10-26 19:05:45 -02001928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001929 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08001930
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07001931 if (IS_VALLEYVIEW(dev))
1932 return DP_TRAIN_VOLTAGE_SWING_1200;
Imre Deakbc7d38a2013-05-16 14:40:36 +03001933 else if (IS_GEN7(dev) && port == PORT_A)
Keith Packard1a2eb462011-11-16 16:26:07 -08001934 return DP_TRAIN_VOLTAGE_SWING_800;
Imre Deakbc7d38a2013-05-16 14:40:36 +03001935 else if (HAS_PCH_CPT(dev) && port != PORT_A)
Keith Packard1a2eb462011-11-16 16:26:07 -08001936 return DP_TRAIN_VOLTAGE_SWING_1200;
1937 else
1938 return DP_TRAIN_VOLTAGE_SWING_800;
1939}
1940
1941static uint8_t
1942intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1943{
Paulo Zanoni30add222012-10-26 19:05:45 -02001944 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001945 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08001946
Paulo Zanoni22b8bf12013-02-18 19:00:23 -03001947 if (HAS_DDI(dev)) {
Paulo Zanonid6c0d722012-10-15 15:51:34 -03001948 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1949 case DP_TRAIN_VOLTAGE_SWING_400:
1950 return DP_TRAIN_PRE_EMPHASIS_9_5;
1951 case DP_TRAIN_VOLTAGE_SWING_600:
1952 return DP_TRAIN_PRE_EMPHASIS_6;
1953 case DP_TRAIN_VOLTAGE_SWING_800:
1954 return DP_TRAIN_PRE_EMPHASIS_3_5;
1955 case DP_TRAIN_VOLTAGE_SWING_1200:
1956 default:
1957 return DP_TRAIN_PRE_EMPHASIS_0;
1958 }
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07001959 } else if (IS_VALLEYVIEW(dev)) {
1960 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1961 case DP_TRAIN_VOLTAGE_SWING_400:
1962 return DP_TRAIN_PRE_EMPHASIS_9_5;
1963 case DP_TRAIN_VOLTAGE_SWING_600:
1964 return DP_TRAIN_PRE_EMPHASIS_6;
1965 case DP_TRAIN_VOLTAGE_SWING_800:
1966 return DP_TRAIN_PRE_EMPHASIS_3_5;
1967 case DP_TRAIN_VOLTAGE_SWING_1200:
1968 default:
1969 return DP_TRAIN_PRE_EMPHASIS_0;
1970 }
Imre Deakbc7d38a2013-05-16 14:40:36 +03001971 } else if (IS_GEN7(dev) && port == PORT_A) {
Keith Packard1a2eb462011-11-16 16:26:07 -08001972 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1973 case DP_TRAIN_VOLTAGE_SWING_400:
1974 return DP_TRAIN_PRE_EMPHASIS_6;
1975 case DP_TRAIN_VOLTAGE_SWING_600:
1976 case DP_TRAIN_VOLTAGE_SWING_800:
1977 return DP_TRAIN_PRE_EMPHASIS_3_5;
1978 default:
1979 return DP_TRAIN_PRE_EMPHASIS_0;
1980 }
1981 } else {
1982 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1983 case DP_TRAIN_VOLTAGE_SWING_400:
1984 return DP_TRAIN_PRE_EMPHASIS_6;
1985 case DP_TRAIN_VOLTAGE_SWING_600:
1986 return DP_TRAIN_PRE_EMPHASIS_6;
1987 case DP_TRAIN_VOLTAGE_SWING_800:
1988 return DP_TRAIN_PRE_EMPHASIS_3_5;
1989 case DP_TRAIN_VOLTAGE_SWING_1200:
1990 default:
1991 return DP_TRAIN_PRE_EMPHASIS_0;
1992 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001993 }
1994}
1995
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07001996static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1997{
1998 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002001 struct intel_crtc *intel_crtc =
2002 to_intel_crtc(dport->base.base.crtc);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002003 unsigned long demph_reg_value, preemph_reg_value,
2004 uniqtranscale_reg_value;
2005 uint8_t train_set = intel_dp->train_set[0];
Jesse Barnescece5d52013-04-19 08:46:35 -07002006 int port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002007 int pipe = intel_crtc->pipe;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002008
2009 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2010 case DP_TRAIN_PRE_EMPHASIS_0:
2011 preemph_reg_value = 0x0004000;
2012 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2013 case DP_TRAIN_VOLTAGE_SWING_400:
2014 demph_reg_value = 0x2B405555;
2015 uniqtranscale_reg_value = 0x552AB83A;
2016 break;
2017 case DP_TRAIN_VOLTAGE_SWING_600:
2018 demph_reg_value = 0x2B404040;
2019 uniqtranscale_reg_value = 0x5548B83A;
2020 break;
2021 case DP_TRAIN_VOLTAGE_SWING_800:
2022 demph_reg_value = 0x2B245555;
2023 uniqtranscale_reg_value = 0x5560B83A;
2024 break;
2025 case DP_TRAIN_VOLTAGE_SWING_1200:
2026 demph_reg_value = 0x2B405555;
2027 uniqtranscale_reg_value = 0x5598DA3A;
2028 break;
2029 default:
2030 return 0;
2031 }
2032 break;
2033 case DP_TRAIN_PRE_EMPHASIS_3_5:
2034 preemph_reg_value = 0x0002000;
2035 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2036 case DP_TRAIN_VOLTAGE_SWING_400:
2037 demph_reg_value = 0x2B404040;
2038 uniqtranscale_reg_value = 0x5552B83A;
2039 break;
2040 case DP_TRAIN_VOLTAGE_SWING_600:
2041 demph_reg_value = 0x2B404848;
2042 uniqtranscale_reg_value = 0x5580B83A;
2043 break;
2044 case DP_TRAIN_VOLTAGE_SWING_800:
2045 demph_reg_value = 0x2B404040;
2046 uniqtranscale_reg_value = 0x55ADDA3A;
2047 break;
2048 default:
2049 return 0;
2050 }
2051 break;
2052 case DP_TRAIN_PRE_EMPHASIS_6:
2053 preemph_reg_value = 0x0000000;
2054 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2055 case DP_TRAIN_VOLTAGE_SWING_400:
2056 demph_reg_value = 0x2B305555;
2057 uniqtranscale_reg_value = 0x5570B83A;
2058 break;
2059 case DP_TRAIN_VOLTAGE_SWING_600:
2060 demph_reg_value = 0x2B2B4040;
2061 uniqtranscale_reg_value = 0x55ADDA3A;
2062 break;
2063 default:
2064 return 0;
2065 }
2066 break;
2067 case DP_TRAIN_PRE_EMPHASIS_9_5:
2068 preemph_reg_value = 0x0006000;
2069 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2070 case DP_TRAIN_VOLTAGE_SWING_400:
2071 demph_reg_value = 0x1B405555;
2072 uniqtranscale_reg_value = 0x55ADDA3A;
2073 break;
2074 default:
2075 return 0;
2076 }
2077 break;
2078 default:
2079 return 0;
2080 }
2081
Chris Wilson0980a602013-07-26 19:57:35 +01002082 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002083 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2084 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2085 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002086 uniqtranscale_reg_value);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002087 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2088 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2089 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2090 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
Chris Wilson0980a602013-07-26 19:57:35 +01002091 mutex_unlock(&dev_priv->dpio_lock);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002092
2093 return 0;
2094}
2095
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002096static void
Keith Packard93f62da2011-11-01 19:45:03 -07002097intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002098{
2099 uint8_t v = 0;
2100 uint8_t p = 0;
2101 int lane;
Keith Packard1a2eb462011-11-16 16:26:07 -08002102 uint8_t voltage_max;
2103 uint8_t preemph_max;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002104
Jesse Barnes33a34e42010-09-08 12:42:02 -07002105 for (lane = 0; lane < intel_dp->lane_count; lane++) {
Daniel Vetter0f037bd2012-10-18 10:15:27 +02002106 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2107 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002108
2109 if (this_v > v)
2110 v = this_v;
2111 if (this_p > p)
2112 p = this_p;
2113 }
2114
Keith Packard1a2eb462011-11-16 16:26:07 -08002115 voltage_max = intel_dp_voltage_max(intel_dp);
Keith Packard417e8222011-11-01 19:54:11 -07002116 if (v >= voltage_max)
2117 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002118
Keith Packard1a2eb462011-11-16 16:26:07 -08002119 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2120 if (p >= preemph_max)
2121 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002122
2123 for (lane = 0; lane < 4; lane++)
Jesse Barnes33a34e42010-09-08 12:42:02 -07002124 intel_dp->train_set[lane] = v | p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002125}
2126
2127static uint32_t
Paulo Zanonif0a34242012-12-06 16:51:50 -02002128intel_gen4_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002129{
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002130 uint32_t signal_levels = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002131
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002132 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002133 case DP_TRAIN_VOLTAGE_SWING_400:
2134 default:
2135 signal_levels |= DP_VOLTAGE_0_4;
2136 break;
2137 case DP_TRAIN_VOLTAGE_SWING_600:
2138 signal_levels |= DP_VOLTAGE_0_6;
2139 break;
2140 case DP_TRAIN_VOLTAGE_SWING_800:
2141 signal_levels |= DP_VOLTAGE_0_8;
2142 break;
2143 case DP_TRAIN_VOLTAGE_SWING_1200:
2144 signal_levels |= DP_VOLTAGE_1_2;
2145 break;
2146 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002147 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002148 case DP_TRAIN_PRE_EMPHASIS_0:
2149 default:
2150 signal_levels |= DP_PRE_EMPHASIS_0;
2151 break;
2152 case DP_TRAIN_PRE_EMPHASIS_3_5:
2153 signal_levels |= DP_PRE_EMPHASIS_3_5;
2154 break;
2155 case DP_TRAIN_PRE_EMPHASIS_6:
2156 signal_levels |= DP_PRE_EMPHASIS_6;
2157 break;
2158 case DP_TRAIN_PRE_EMPHASIS_9_5:
2159 signal_levels |= DP_PRE_EMPHASIS_9_5;
2160 break;
2161 }
2162 return signal_levels;
2163}
2164
Zhenyu Wange3421a12010-04-08 09:43:27 +08002165/* Gen6's DP voltage swing and pre-emphasis control */
2166static uint32_t
2167intel_gen6_edp_signal_levels(uint8_t train_set)
2168{
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002169 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2170 DP_TRAIN_PRE_EMPHASIS_MASK);
2171 switch (signal_levels) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08002172 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002173 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2174 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2175 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2176 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002177 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002178 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2179 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002180 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002181 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2182 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002183 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002184 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2185 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002186 default:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002187 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2188 "0x%x\n", signal_levels);
2189 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002190 }
2191}
2192
Keith Packard1a2eb462011-11-16 16:26:07 -08002193/* Gen7's DP voltage swing and pre-emphasis control */
2194static uint32_t
2195intel_gen7_edp_signal_levels(uint8_t train_set)
2196{
2197 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2198 DP_TRAIN_PRE_EMPHASIS_MASK);
2199 switch (signal_levels) {
2200 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2201 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2202 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2203 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2204 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2205 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2206
2207 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2208 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2209 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2210 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2211
2212 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2213 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2214 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2215 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2216
2217 default:
2218 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2219 "0x%x\n", signal_levels);
2220 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2221 }
2222}
2223
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002224/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2225static uint32_t
Paulo Zanonif0a34242012-12-06 16:51:50 -02002226intel_hsw_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002227{
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002228 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2229 DP_TRAIN_PRE_EMPHASIS_MASK);
2230 switch (signal_levels) {
2231 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2232 return DDI_BUF_EMP_400MV_0DB_HSW;
2233 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2234 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2235 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2236 return DDI_BUF_EMP_400MV_6DB_HSW;
2237 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2238 return DDI_BUF_EMP_400MV_9_5DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002239
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002240 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2241 return DDI_BUF_EMP_600MV_0DB_HSW;
2242 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2243 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2244 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2245 return DDI_BUF_EMP_600MV_6DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002246
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002247 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2248 return DDI_BUF_EMP_800MV_0DB_HSW;
2249 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2250 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2251 default:
2252 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2253 "0x%x\n", signal_levels);
2254 return DDI_BUF_EMP_400MV_0DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002255 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002256}
2257
Paulo Zanonif0a34242012-12-06 16:51:50 -02002258/* Properly updates "DP" with the correct signal levels. */
2259static void
2260intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2261{
2262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002263 enum port port = intel_dig_port->port;
Paulo Zanonif0a34242012-12-06 16:51:50 -02002264 struct drm_device *dev = intel_dig_port->base.base.dev;
2265 uint32_t signal_levels, mask;
2266 uint8_t train_set = intel_dp->train_set[0];
2267
Paulo Zanoni22b8bf12013-02-18 19:00:23 -03002268 if (HAS_DDI(dev)) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002269 signal_levels = intel_hsw_signal_levels(train_set);
2270 mask = DDI_BUF_EMP_MASK;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002271 } else if (IS_VALLEYVIEW(dev)) {
2272 signal_levels = intel_vlv_signal_levels(intel_dp);
2273 mask = 0;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002274 } else if (IS_GEN7(dev) && port == PORT_A) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002275 signal_levels = intel_gen7_edp_signal_levels(train_set);
2276 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002277 } else if (IS_GEN6(dev) && port == PORT_A) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002278 signal_levels = intel_gen6_edp_signal_levels(train_set);
2279 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2280 } else {
2281 signal_levels = intel_gen4_signal_levels(train_set);
2282 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2283 }
2284
2285 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2286
2287 *DP = (*DP & ~mask) | signal_levels;
2288}
2289
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002290static bool
Chris Wilsonea5b2132010-08-04 13:50:23 +01002291intel_dp_set_link_train(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002292 uint32_t dp_reg_value,
Chris Wilson58e10eb2010-10-03 10:56:11 +01002293 uint8_t dp_train_pat)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002294{
Paulo Zanoni174edf12012-10-26 19:05:50 -02002295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2296 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002297 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02002298 enum port port = intel_dig_port->port;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002299 int ret;
2300
Paulo Zanoni22b8bf12013-02-18 19:00:23 -03002301 if (HAS_DDI(dev)) {
Imre Deak3ab9c632013-05-03 12:57:41 +03002302 uint32_t temp = I915_READ(DP_TP_CTL(port));
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002303
2304 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2305 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2306 else
2307 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2308
2309 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2310 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2311 case DP_TRAINING_PATTERN_DISABLE:
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002312 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2313
2314 break;
2315 case DP_TRAINING_PATTERN_1:
2316 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2317 break;
2318 case DP_TRAINING_PATTERN_2:
2319 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2320 break;
2321 case DP_TRAINING_PATTERN_3:
2322 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2323 break;
2324 }
Paulo Zanoni174edf12012-10-26 19:05:50 -02002325 I915_WRITE(DP_TP_CTL(port), temp);
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002326
Imre Deakbc7d38a2013-05-16 14:40:36 +03002327 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002328 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2329
2330 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2331 case DP_TRAINING_PATTERN_DISABLE:
2332 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2333 break;
2334 case DP_TRAINING_PATTERN_1:
2335 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2336 break;
2337 case DP_TRAINING_PATTERN_2:
2338 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2339 break;
2340 case DP_TRAINING_PATTERN_3:
2341 DRM_ERROR("DP training pattern 3 not supported\n");
2342 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2343 break;
2344 }
2345
2346 } else {
2347 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2348
2349 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2350 case DP_TRAINING_PATTERN_DISABLE:
2351 dp_reg_value |= DP_LINK_TRAIN_OFF;
2352 break;
2353 case DP_TRAINING_PATTERN_1:
2354 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2355 break;
2356 case DP_TRAINING_PATTERN_2:
2357 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2358 break;
2359 case DP_TRAINING_PATTERN_3:
2360 DRM_ERROR("DP training pattern 3 not supported\n");
2361 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2362 break;
2363 }
2364 }
2365
Chris Wilsonea5b2132010-08-04 13:50:23 +01002366 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2367 POSTING_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002368
Chris Wilsonea5b2132010-08-04 13:50:23 +01002369 intel_dp_aux_native_write_1(intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002370 DP_TRAINING_PATTERN_SET,
2371 dp_train_pat);
2372
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002373 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2374 DP_TRAINING_PATTERN_DISABLE) {
2375 ret = intel_dp_aux_native_write(intel_dp,
2376 DP_TRAINING_LANE0_SET,
2377 intel_dp->train_set,
2378 intel_dp->lane_count);
2379 if (ret != intel_dp->lane_count)
2380 return false;
2381 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002382
2383 return true;
2384}
2385
Imre Deak3ab9c632013-05-03 12:57:41 +03002386static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2387{
2388 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2389 struct drm_device *dev = intel_dig_port->base.base.dev;
2390 struct drm_i915_private *dev_priv = dev->dev_private;
2391 enum port port = intel_dig_port->port;
2392 uint32_t val;
2393
2394 if (!HAS_DDI(dev))
2395 return;
2396
2397 val = I915_READ(DP_TP_CTL(port));
2398 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2399 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2400 I915_WRITE(DP_TP_CTL(port), val);
2401
2402 /*
2403 * On PORT_A we can have only eDP in SST mode. There the only reason
2404 * we need to set idle transmission mode is to work around a HW issue
2405 * where we enable the pipe while not in idle link-training mode.
2406 * In this case there is requirement to wait for a minimum number of
2407 * idle patterns to be sent.
2408 */
2409 if (port == PORT_A)
2410 return;
2411
2412 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2413 1))
2414 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2415}
2416
Jesse Barnes33a34e42010-09-08 12:42:02 -07002417/* Enable corresponding port and start training pattern 1 */
Paulo Zanonic19b0662012-10-15 15:51:41 -03002418void
Jesse Barnes33a34e42010-09-08 12:42:02 -07002419intel_dp_start_link_train(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002420{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002421 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
Paulo Zanonic19b0662012-10-15 15:51:41 -03002422 struct drm_device *dev = encoder->dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002423 int i;
2424 uint8_t voltage;
Keith Packardcdb0e952011-11-01 20:00:06 -07002425 int voltage_tries, loop_tries;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002426 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002427
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002428 if (HAS_DDI(dev))
Paulo Zanonic19b0662012-10-15 15:51:41 -03002429 intel_ddi_prepare_link_retrain(encoder);
2430
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002431 /* Write the link configuration data */
2432 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2433 intel_dp->link_configuration,
2434 DP_LINK_CONFIGURATION_SIZE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002435
2436 DP |= DP_PORT_EN;
Keith Packard1a2eb462011-11-16 16:26:07 -08002437
Jesse Barnes33a34e42010-09-08 12:42:02 -07002438 memset(intel_dp->train_set, 0, 4);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002439 voltage = 0xff;
Keith Packardcdb0e952011-11-01 20:00:06 -07002440 voltage_tries = 0;
2441 loop_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002442 for (;;) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07002443 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
Keith Packard93f62da2011-11-01 19:45:03 -07002444 uint8_t link_status[DP_LINK_STATUS_SIZE];
Keith Packard417e8222011-11-01 19:54:11 -07002445
Paulo Zanonif0a34242012-12-06 16:51:50 -02002446 intel_dp_set_signal_levels(intel_dp, &DP);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002447
Daniel Vettera7c96552012-10-18 10:15:30 +02002448 /* Set training pattern 1 */
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002449 if (!intel_dp_set_link_train(intel_dp, DP,
Adam Jackson81055852011-07-21 17:48:37 -04002450 DP_TRAINING_PATTERN_1 |
2451 DP_LINK_SCRAMBLING_DISABLE))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002452 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002453
Daniel Vettera7c96552012-10-18 10:15:30 +02002454 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
Keith Packard93f62da2011-11-01 19:45:03 -07002455 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2456 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002457 break;
Keith Packard93f62da2011-11-01 19:45:03 -07002458 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002459
Daniel Vetter01916272012-10-18 10:15:25 +02002460 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Keith Packard93f62da2011-11-01 19:45:03 -07002461 DRM_DEBUG_KMS("clock recovery OK\n");
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002462 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002463 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002464
2465 /* Check to see if we've tried the max voltage */
2466 for (i = 0; i < intel_dp->lane_count; i++)
2467 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2468 break;
Takashi Iwai3b4f8192013-03-11 18:40:16 +01002469 if (i == intel_dp->lane_count) {
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002470 ++loop_tries;
2471 if (loop_tries == 5) {
Keith Packardcdb0e952011-11-01 20:00:06 -07002472 DRM_DEBUG_KMS("too many full retries, give up\n");
2473 break;
2474 }
2475 memset(intel_dp->train_set, 0, 4);
2476 voltage_tries = 0;
2477 continue;
2478 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002479
2480 /* Check to see if we've tried the same voltage 5 times */
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002481 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
Chris Wilson24773672012-09-26 16:48:30 +01002482 ++voltage_tries;
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002483 if (voltage_tries == 5) {
2484 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2485 break;
2486 }
2487 } else
2488 voltage_tries = 0;
2489 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002490
2491 /* Compute new intel_dp->train_set as requested by target */
Keith Packard93f62da2011-11-01 19:45:03 -07002492 intel_get_adjust_train(intel_dp, link_status);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002493 }
2494
Jesse Barnes33a34e42010-09-08 12:42:02 -07002495 intel_dp->DP = DP;
2496}
2497
Paulo Zanonic19b0662012-10-15 15:51:41 -03002498void
Jesse Barnes33a34e42010-09-08 12:42:02 -07002499intel_dp_complete_link_train(struct intel_dp *intel_dp)
2500{
Jesse Barnes33a34e42010-09-08 12:42:02 -07002501 bool channel_eq = false;
Jesse Barnes37f80972011-01-05 14:45:24 -08002502 int tries, cr_tries;
Jesse Barnes33a34e42010-09-08 12:42:02 -07002503 uint32_t DP = intel_dp->DP;
2504
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002505 /* channel equalization */
2506 tries = 0;
Jesse Barnes37f80972011-01-05 14:45:24 -08002507 cr_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002508 channel_eq = false;
2509 for (;;) {
Keith Packard93f62da2011-11-01 19:45:03 -07002510 uint8_t link_status[DP_LINK_STATUS_SIZE];
Zhenyu Wange3421a12010-04-08 09:43:27 +08002511
Jesse Barnes37f80972011-01-05 14:45:24 -08002512 if (cr_tries > 5) {
2513 DRM_ERROR("failed to train DP, aborting\n");
2514 intel_dp_link_down(intel_dp);
2515 break;
2516 }
2517
Paulo Zanonif0a34242012-12-06 16:51:50 -02002518 intel_dp_set_signal_levels(intel_dp, &DP);
Zhenyu Wange3421a12010-04-08 09:43:27 +08002519
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002520 /* channel eq pattern */
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002521 if (!intel_dp_set_link_train(intel_dp, DP,
Adam Jackson81055852011-07-21 17:48:37 -04002522 DP_TRAINING_PATTERN_2 |
2523 DP_LINK_SCRAMBLING_DISABLE))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002524 break;
2525
Daniel Vettera7c96552012-10-18 10:15:30 +02002526 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
Keith Packard93f62da2011-11-01 19:45:03 -07002527 if (!intel_dp_get_link_status(intel_dp, link_status))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002528 break;
Jesse Barnes869184a2010-10-07 16:01:22 -07002529
Jesse Barnes37f80972011-01-05 14:45:24 -08002530 /* Make sure clock is still ok */
Daniel Vetter01916272012-10-18 10:15:25 +02002531 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Jesse Barnes37f80972011-01-05 14:45:24 -08002532 intel_dp_start_link_train(intel_dp);
2533 cr_tries++;
2534 continue;
2535 }
2536
Daniel Vetter1ffdff12012-10-18 10:15:24 +02002537 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002538 channel_eq = true;
2539 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002540 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002541
Jesse Barnes37f80972011-01-05 14:45:24 -08002542 /* Try 5 times, then try clock recovery if that fails */
2543 if (tries > 5) {
2544 intel_dp_link_down(intel_dp);
2545 intel_dp_start_link_train(intel_dp);
2546 tries = 0;
2547 cr_tries++;
2548 continue;
2549 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002550
2551 /* Compute new intel_dp->train_set as requested by target */
Keith Packard93f62da2011-11-01 19:45:03 -07002552 intel_get_adjust_train(intel_dp, link_status);
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002553 ++tries;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002554 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002555
Imre Deak3ab9c632013-05-03 12:57:41 +03002556 intel_dp_set_idle_link_train(intel_dp);
2557
2558 intel_dp->DP = DP;
2559
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002560 if (channel_eq)
Masanari Iida07f42252013-03-20 11:00:34 +09002561 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002562
Imre Deak3ab9c632013-05-03 12:57:41 +03002563}
2564
2565void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2566{
2567 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2568 DP_TRAINING_PATTERN_DISABLE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002569}
2570
2571static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01002572intel_dp_link_down(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002573{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002574 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002575 enum port port = intel_dig_port->port;
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002576 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002577 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterab527ef2012-11-29 15:59:33 +01002578 struct intel_crtc *intel_crtc =
2579 to_intel_crtc(intel_dig_port->base.base.crtc);
Chris Wilsonea5b2132010-08-04 13:50:23 +01002580 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002581
Paulo Zanonic19b0662012-10-15 15:51:41 -03002582 /*
2583 * DDI code has a strict mode set sequence and we should try to respect
2584 * it, otherwise we might hang the machine in many different ways. So we
2585 * really should be disabling the port only on a complete crtc_disable
2586 * sequence. This function is just called under two conditions on DDI
2587 * code:
2588 * - Link train failed while doing crtc_enable, and on this case we
2589 * really should respect the mode set sequence and wait for a
2590 * crtc_disable.
2591 * - Someone turned the monitor off and intel_dp_check_link_status
2592 * called us. We don't need to disable the whole port on this case, so
2593 * when someone turns the monitor on again,
2594 * intel_ddi_prepare_link_retrain will take care of redoing the link
2595 * train.
2596 */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002597 if (HAS_DDI(dev))
Paulo Zanonic19b0662012-10-15 15:51:41 -03002598 return;
2599
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02002600 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
Chris Wilson1b39d6f2010-12-06 11:20:45 +00002601 return;
2602
Zhao Yakui28c97732009-10-09 11:39:41 +08002603 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002604
Imre Deakbc7d38a2013-05-16 14:40:36 +03002605 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08002606 DP &= ~DP_LINK_TRAIN_MASK_CPT;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002607 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
Zhenyu Wange3421a12010-04-08 09:43:27 +08002608 } else {
2609 DP &= ~DP_LINK_TRAIN_MASK;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002610 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
Zhenyu Wange3421a12010-04-08 09:43:27 +08002611 }
Chris Wilsonfe255d02010-09-11 21:37:48 +01002612 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002613
Daniel Vetterab527ef2012-11-29 15:59:33 +01002614 /* We don't really know why we're doing this */
2615 intel_wait_for_vblank(dev, intel_crtc->pipe);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002616
Daniel Vetter493a7082012-05-30 12:31:56 +02002617 if (HAS_PCH_IBX(dev) &&
Chris Wilson1b39d6f2010-12-06 11:20:45 +00002618 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002619 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
Chris Wilson31acbcc2011-04-17 06:38:35 +01002620
Eric Anholt5bddd172010-11-18 09:32:59 +08002621 /* Hardware workaround: leaving our transcoder select
2622 * set to transcoder B while it's off will prevent the
2623 * corresponding HDMI output on transcoder A.
2624 *
2625 * Combine this with another hardware workaround:
2626 * transcoder select bit can only be cleared while the
2627 * port is enabled.
2628 */
2629 DP &= ~DP_PIPEB_SELECT;
2630 I915_WRITE(intel_dp->output_reg, DP);
2631
2632 /* Changes to enable or select take place the vblank
2633 * after being written.
2634 */
Daniel Vetterff50afe2012-11-29 15:59:34 +01002635 if (WARN_ON(crtc == NULL)) {
2636 /* We should never try to disable a port without a crtc
2637 * attached. For paranoia keep the code around for a
2638 * bit. */
Chris Wilson31acbcc2011-04-17 06:38:35 +01002639 POSTING_READ(intel_dp->output_reg);
2640 msleep(50);
2641 } else
Daniel Vetterab527ef2012-11-29 15:59:33 +01002642 intel_wait_for_vblank(dev, intel_crtc->pipe);
Eric Anholt5bddd172010-11-18 09:32:59 +08002643 }
2644
Wu Fengguang832afda2011-12-09 20:42:21 +08002645 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002646 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2647 POSTING_READ(intel_dp->output_reg);
Keith Packardf01eca22011-09-28 16:48:10 -07002648 msleep(intel_dp->panel_power_down_delay);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002649}
2650
Keith Packard26d61aa2011-07-25 20:01:09 -07002651static bool
2652intel_dp_get_dpcd(struct intel_dp *intel_dp)
Keith Packard92fd8fd2011-07-25 19:50:10 -07002653{
Damien Lespiau577c7a52012-12-13 16:09:02 +00002654 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2655
Keith Packard92fd8fd2011-07-25 19:50:10 -07002656 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
Adam Jacksonedb39242012-09-18 10:58:49 -04002657 sizeof(intel_dp->dpcd)) == 0)
2658 return false; /* aux transfer failed */
Keith Packard92fd8fd2011-07-25 19:50:10 -07002659
Damien Lespiau577c7a52012-12-13 16:09:02 +00002660 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2661 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2662 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2663
Adam Jacksonedb39242012-09-18 10:58:49 -04002664 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2665 return false; /* DPCD not present */
2666
Shobhit Kumar2293bb52013-07-11 18:44:56 -03002667 /* Check if the panel supports PSR */
2668 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2669 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2670 intel_dp->psr_dpcd,
2671 sizeof(intel_dp->psr_dpcd));
2672 if (is_edp_psr(intel_dp))
2673 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
Adam Jacksonedb39242012-09-18 10:58:49 -04002674 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2675 DP_DWN_STRM_PORT_PRESENT))
2676 return true; /* native DP sink */
2677
2678 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2679 return true; /* no per-port downstream info */
2680
2681 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2682 intel_dp->downstream_ports,
2683 DP_MAX_DOWNSTREAM_PORTS) == 0)
2684 return false; /* downstream port status fetch failed */
2685
2686 return true;
Keith Packard92fd8fd2011-07-25 19:50:10 -07002687}
2688
Adam Jackson0d198322012-05-14 16:05:47 -04002689static void
2690intel_dp_probe_oui(struct intel_dp *intel_dp)
2691{
2692 u8 buf[3];
2693
2694 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2695 return;
2696
Daniel Vetter351cfc32012-06-12 13:20:47 +02002697 ironlake_edp_panel_vdd_on(intel_dp);
2698
Adam Jackson0d198322012-05-14 16:05:47 -04002699 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2700 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2701 buf[0], buf[1], buf[2]);
2702
2703 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2704 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2705 buf[0], buf[1], buf[2]);
Daniel Vetter351cfc32012-06-12 13:20:47 +02002706
2707 ironlake_edp_panel_vdd_off(intel_dp, false);
Adam Jackson0d198322012-05-14 16:05:47 -04002708}
2709
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002710static bool
2711intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2712{
2713 int ret;
2714
2715 ret = intel_dp_aux_native_read_retry(intel_dp,
2716 DP_DEVICE_SERVICE_IRQ_VECTOR,
2717 sink_irq_vector, 1);
2718 if (!ret)
2719 return false;
2720
2721 return true;
2722}
2723
2724static void
2725intel_dp_handle_test_request(struct intel_dp *intel_dp)
2726{
2727 /* NAK by default */
Daniel Vetter9324cf72012-10-20 21:13:05 +02002728 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002729}
2730
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002731/*
2732 * According to DP spec
2733 * 5.1.2:
2734 * 1. Read DPCD
2735 * 2. Configure link according to Receiver Capabilities
2736 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2737 * 4. Check link status on receipt of hot-plug interrupt
2738 */
2739
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002740void
Chris Wilsonea5b2132010-08-04 13:50:23 +01002741intel_dp_check_link_status(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002742{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002743 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002744 u8 sink_irq_vector;
Keith Packard93f62da2011-11-01 19:45:03 -07002745 u8 link_status[DP_LINK_STATUS_SIZE];
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002746
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002747 if (!intel_encoder->connectors_active)
Keith Packardd2b996a2011-07-25 22:37:51 -07002748 return;
Jesse Barnes59cd09e2011-07-07 11:10:59 -07002749
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002750 if (WARN_ON(!intel_encoder->base.crtc))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002751 return;
2752
Keith Packard92fd8fd2011-07-25 19:50:10 -07002753 /* Try to read receiver status if the link appears to be up */
Keith Packard93f62da2011-11-01 19:45:03 -07002754 if (!intel_dp_get_link_status(intel_dp, link_status)) {
Chris Wilsonea5b2132010-08-04 13:50:23 +01002755 intel_dp_link_down(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002756 return;
2757 }
2758
Keith Packard92fd8fd2011-07-25 19:50:10 -07002759 /* Now read the DPCD to see if it's actually running */
Keith Packard26d61aa2011-07-25 20:01:09 -07002760 if (!intel_dp_get_dpcd(intel_dp)) {
Jesse Barnes59cd09e2011-07-07 11:10:59 -07002761 intel_dp_link_down(intel_dp);
2762 return;
2763 }
2764
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002765 /* Try to read the source of the interrupt */
2766 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2767 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2768 /* Clear interrupt source */
2769 intel_dp_aux_native_write_1(intel_dp,
2770 DP_DEVICE_SERVICE_IRQ_VECTOR,
2771 sink_irq_vector);
2772
2773 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2774 intel_dp_handle_test_request(intel_dp);
2775 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2776 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2777 }
2778
Daniel Vetter1ffdff12012-10-18 10:15:24 +02002779 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
Keith Packard92fd8fd2011-07-25 19:50:10 -07002780 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002781 drm_get_encoder_name(&intel_encoder->base));
Jesse Barnes33a34e42010-09-08 12:42:02 -07002782 intel_dp_start_link_train(intel_dp);
2783 intel_dp_complete_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03002784 intel_dp_stop_link_train(intel_dp);
Jesse Barnes33a34e42010-09-08 12:42:02 -07002785 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002786}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002787
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04002788/* XXX this is probably wrong for multiple downstream ports */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002789static enum drm_connector_status
Keith Packard26d61aa2011-07-25 20:01:09 -07002790intel_dp_detect_dpcd(struct intel_dp *intel_dp)
Adam Jackson71ba90002011-07-12 17:38:04 -04002791{
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04002792 uint8_t *dpcd = intel_dp->dpcd;
2793 bool hpd;
2794 uint8_t type;
2795
2796 if (!intel_dp_get_dpcd(intel_dp))
2797 return connector_status_disconnected;
2798
2799 /* if there's no downstream port, we're done */
2800 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
Keith Packard26d61aa2011-07-25 20:01:09 -07002801 return connector_status_connected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04002802
2803 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2804 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2805 if (hpd) {
Adam Jackson23235172012-09-20 16:42:45 -04002806 uint8_t reg;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04002807 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
Adam Jackson23235172012-09-20 16:42:45 -04002808 &reg, 1))
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04002809 return connector_status_unknown;
Adam Jackson23235172012-09-20 16:42:45 -04002810 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2811 : connector_status_disconnected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04002812 }
2813
2814 /* If no HPD, poke DDC gently */
2815 if (drm_probe_ddc(&intel_dp->adapter))
2816 return connector_status_connected;
2817
2818 /* Well we tried, say unknown for unreliable port types */
2819 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2820 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2821 return connector_status_unknown;
2822
2823 /* Anything else is out of spec, warn and ignore */
2824 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
Keith Packard26d61aa2011-07-25 20:01:09 -07002825 return connector_status_disconnected;
Adam Jackson71ba90002011-07-12 17:38:04 -04002826}
2827
2828static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002829ironlake_dp_detect(struct intel_dp *intel_dp)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002830{
Paulo Zanoni30add222012-10-26 19:05:45 -02002831 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Damien Lespiau1b469632012-12-13 16:09:01 +00002832 struct drm_i915_private *dev_priv = dev->dev_private;
2833 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002834 enum drm_connector_status status;
2835
Chris Wilsonfe16d942011-02-12 10:29:38 +00002836 /* Can't disconnect eDP, but you can close the lid... */
2837 if (is_edp(intel_dp)) {
Paulo Zanoni30add222012-10-26 19:05:45 -02002838 status = intel_panel_detect(dev);
Chris Wilsonfe16d942011-02-12 10:29:38 +00002839 if (status == connector_status_unknown)
2840 status = connector_status_connected;
2841 return status;
2842 }
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002843
Damien Lespiau1b469632012-12-13 16:09:01 +00002844 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2845 return connector_status_disconnected;
2846
Keith Packard26d61aa2011-07-25 20:01:09 -07002847 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002848}
2849
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002850static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002851g4x_dp_detect(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002852{
Paulo Zanoni30add222012-10-26 19:05:45 -02002853 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002854 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä34f2be42013-01-24 15:29:27 +02002855 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Chris Wilson10f76a32012-05-11 18:01:32 +01002856 uint32_t bit;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002857
Jesse Barnes35aad752013-03-01 13:14:31 -08002858 /* Can't disconnect eDP, but you can close the lid... */
2859 if (is_edp(intel_dp)) {
2860 enum drm_connector_status status;
2861
2862 status = intel_panel_detect(dev);
2863 if (status == connector_status_unknown)
2864 status = connector_status_connected;
2865 return status;
2866 }
2867
Ville Syrjälä34f2be42013-01-24 15:29:27 +02002868 switch (intel_dig_port->port) {
2869 case PORT_B:
Daniel Vetter26739f12013-02-07 12:42:32 +01002870 bit = PORTB_HOTPLUG_LIVE_STATUS;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002871 break;
Ville Syrjälä34f2be42013-01-24 15:29:27 +02002872 case PORT_C:
Daniel Vetter26739f12013-02-07 12:42:32 +01002873 bit = PORTC_HOTPLUG_LIVE_STATUS;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002874 break;
Ville Syrjälä34f2be42013-01-24 15:29:27 +02002875 case PORT_D:
Daniel Vetter26739f12013-02-07 12:42:32 +01002876 bit = PORTD_HOTPLUG_LIVE_STATUS;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002877 break;
2878 default:
2879 return connector_status_unknown;
2880 }
2881
Chris Wilson10f76a32012-05-11 18:01:32 +01002882 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002883 return connector_status_disconnected;
2884
Keith Packard26d61aa2011-07-25 20:01:09 -07002885 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002886}
2887
Keith Packard8c241fe2011-09-28 16:38:44 -07002888static struct edid *
2889intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2890{
Jani Nikula9cd300e2012-10-19 14:51:52 +03002891 struct intel_connector *intel_connector = to_intel_connector(connector);
Keith Packard8c241fe2011-09-28 16:38:44 -07002892
Jani Nikula9cd300e2012-10-19 14:51:52 +03002893 /* use cached edid if we have one */
2894 if (intel_connector->edid) {
2895 struct edid *edid;
2896 int size;
2897
2898 /* invalid edid */
2899 if (IS_ERR(intel_connector->edid))
Jesse Barnesd6f24d02012-06-14 15:28:33 -04002900 return NULL;
2901
Jani Nikula9cd300e2012-10-19 14:51:52 +03002902 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
Thomas Meyeredbe1582013-05-22 23:07:09 +02002903 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
Jesse Barnesd6f24d02012-06-14 15:28:33 -04002904 if (!edid)
2905 return NULL;
2906
Jesse Barnesd6f24d02012-06-14 15:28:33 -04002907 return edid;
2908 }
2909
Jani Nikula9cd300e2012-10-19 14:51:52 +03002910 return drm_get_edid(connector, adapter);
Keith Packard8c241fe2011-09-28 16:38:44 -07002911}
2912
2913static int
2914intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2915{
Jani Nikula9cd300e2012-10-19 14:51:52 +03002916 struct intel_connector *intel_connector = to_intel_connector(connector);
Keith Packard8c241fe2011-09-28 16:38:44 -07002917
Jani Nikula9cd300e2012-10-19 14:51:52 +03002918 /* use cached edid if we have one */
2919 if (intel_connector->edid) {
2920 /* invalid edid */
2921 if (IS_ERR(intel_connector->edid))
2922 return 0;
2923
2924 return intel_connector_update_modes(connector,
2925 intel_connector->edid);
Jesse Barnesd6f24d02012-06-14 15:28:33 -04002926 }
2927
Jani Nikula9cd300e2012-10-19 14:51:52 +03002928 return intel_ddc_get_modes(connector, adapter);
Keith Packard8c241fe2011-09-28 16:38:44 -07002929}
2930
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002931static enum drm_connector_status
2932intel_dp_detect(struct drm_connector *connector, bool force)
2933{
2934 struct intel_dp *intel_dp = intel_attached_dp(connector);
Paulo Zanonid63885d2012-10-26 19:05:49 -02002935 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2936 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02002937 struct drm_device *dev = connector->dev;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002938 enum drm_connector_status status;
2939 struct edid *edid = NULL;
2940
Chris Wilson164c8592013-07-20 20:27:08 +01002941 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2942 connector->base.id, drm_get_connector_name(connector));
2943
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002944 intel_dp->has_audio = false;
2945
2946 if (HAS_PCH_SPLIT(dev))
2947 status = ironlake_dp_detect(intel_dp);
2948 else
2949 status = g4x_dp_detect(intel_dp);
Adam Jackson1b9be9d2011-07-12 17:38:01 -04002950
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002951 if (status != connector_status_connected)
2952 return status;
2953
Adam Jackson0d198322012-05-14 16:05:47 -04002954 intel_dp_probe_oui(intel_dp);
2955
Daniel Vetterc3e5f672012-02-23 17:14:47 +01002956 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2957 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
Chris Wilsonf6849602010-09-19 09:29:33 +01002958 } else {
Keith Packard8c241fe2011-09-28 16:38:44 -07002959 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
Chris Wilsonf6849602010-09-19 09:29:33 +01002960 if (edid) {
2961 intel_dp->has_audio = drm_detect_monitor_audio(edid);
Chris Wilsonf6849602010-09-19 09:29:33 +01002962 kfree(edid);
2963 }
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002964 }
2965
Paulo Zanonid63885d2012-10-26 19:05:49 -02002966 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2967 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002968 return connector_status_connected;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002969}
2970
2971static int intel_dp_get_modes(struct drm_connector *connector)
2972{
Chris Wilsondf0e9242010-09-09 16:20:55 +01002973 struct intel_dp *intel_dp = intel_attached_dp(connector);
Jani Nikuladd06f902012-10-19 14:51:50 +03002974 struct intel_connector *intel_connector = to_intel_connector(connector);
Paulo Zanonifa90ece2012-10-26 19:05:44 -02002975 struct drm_device *dev = connector->dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002976 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002977
2978 /* We should parse the EDID data and find out if it has an audio sink
2979 */
2980
Keith Packard8c241fe2011-09-28 16:38:44 -07002981 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
Jani Nikulaf8779fd2012-10-19 14:51:48 +03002982 if (ret)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002983 return ret;
2984
Jani Nikulaf8779fd2012-10-19 14:51:48 +03002985 /* if eDP has no EDID, fall back to fixed mode */
Jani Nikuladd06f902012-10-19 14:51:50 +03002986 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
Jani Nikulaf8779fd2012-10-19 14:51:48 +03002987 struct drm_display_mode *mode;
Jani Nikuladd06f902012-10-19 14:51:50 +03002988 mode = drm_mode_duplicate(dev,
2989 intel_connector->panel.fixed_mode);
Jani Nikulaf8779fd2012-10-19 14:51:48 +03002990 if (mode) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002991 drm_mode_probed_add(connector, mode);
2992 return 1;
2993 }
2994 }
2995 return 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002996}
2997
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002998static bool
2999intel_dp_detect_audio(struct drm_connector *connector)
3000{
3001 struct intel_dp *intel_dp = intel_attached_dp(connector);
3002 struct edid *edid;
3003 bool has_audio = false;
3004
Keith Packard8c241fe2011-09-28 16:38:44 -07003005 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003006 if (edid) {
3007 has_audio = drm_detect_monitor_audio(edid);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003008 kfree(edid);
3009 }
3010
3011 return has_audio;
3012}
3013
Chris Wilsonf6849602010-09-19 09:29:33 +01003014static int
3015intel_dp_set_property(struct drm_connector *connector,
3016 struct drm_property *property,
3017 uint64_t val)
3018{
Chris Wilsone953fd72011-02-21 22:23:52 +00003019 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Yuly Novikov53b41832012-10-26 12:04:00 +03003020 struct intel_connector *intel_connector = to_intel_connector(connector);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003021 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3022 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonf6849602010-09-19 09:29:33 +01003023 int ret;
3024
Rob Clark662595d2012-10-11 20:36:04 -05003025 ret = drm_object_property_set_value(&connector->base, property, val);
Chris Wilsonf6849602010-09-19 09:29:33 +01003026 if (ret)
3027 return ret;
3028
Chris Wilson3f43c482011-05-12 22:17:24 +01003029 if (property == dev_priv->force_audio_property) {
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003030 int i = val;
3031 bool has_audio;
3032
3033 if (i == intel_dp->force_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01003034 return 0;
3035
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003036 intel_dp->force_audio = i;
Chris Wilsonf6849602010-09-19 09:29:33 +01003037
Daniel Vetterc3e5f672012-02-23 17:14:47 +01003038 if (i == HDMI_AUDIO_AUTO)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003039 has_audio = intel_dp_detect_audio(connector);
3040 else
Daniel Vetterc3e5f672012-02-23 17:14:47 +01003041 has_audio = (i == HDMI_AUDIO_ON);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003042
3043 if (has_audio == intel_dp->has_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01003044 return 0;
3045
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003046 intel_dp->has_audio = has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +01003047 goto done;
3048 }
3049
Chris Wilsone953fd72011-02-21 22:23:52 +00003050 if (property == dev_priv->broadcast_rgb_property) {
Daniel Vetterae4edb82013-04-22 17:07:23 +02003051 bool old_auto = intel_dp->color_range_auto;
3052 uint32_t old_range = intel_dp->color_range;
3053
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003054 switch (val) {
3055 case INTEL_BROADCAST_RGB_AUTO:
3056 intel_dp->color_range_auto = true;
3057 break;
3058 case INTEL_BROADCAST_RGB_FULL:
3059 intel_dp->color_range_auto = false;
3060 intel_dp->color_range = 0;
3061 break;
3062 case INTEL_BROADCAST_RGB_LIMITED:
3063 intel_dp->color_range_auto = false;
3064 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3065 break;
3066 default:
3067 return -EINVAL;
3068 }
Daniel Vetterae4edb82013-04-22 17:07:23 +02003069
3070 if (old_auto == intel_dp->color_range_auto &&
3071 old_range == intel_dp->color_range)
3072 return 0;
3073
Chris Wilsone953fd72011-02-21 22:23:52 +00003074 goto done;
3075 }
3076
Yuly Novikov53b41832012-10-26 12:04:00 +03003077 if (is_edp(intel_dp) &&
3078 property == connector->dev->mode_config.scaling_mode_property) {
3079 if (val == DRM_MODE_SCALE_NONE) {
3080 DRM_DEBUG_KMS("no scaling not supported\n");
3081 return -EINVAL;
3082 }
3083
3084 if (intel_connector->panel.fitting_mode == val) {
3085 /* the eDP scaling property is not changed */
3086 return 0;
3087 }
3088 intel_connector->panel.fitting_mode = val;
3089
3090 goto done;
3091 }
3092
Chris Wilsonf6849602010-09-19 09:29:33 +01003093 return -EINVAL;
3094
3095done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00003096 if (intel_encoder->base.crtc)
3097 intel_crtc_restore_mode(intel_encoder->base.crtc);
Chris Wilsonf6849602010-09-19 09:29:33 +01003098
3099 return 0;
3100}
3101
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003102static void
Paulo Zanoni73845ad2013-06-12 17:27:30 -03003103intel_dp_connector_destroy(struct drm_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003104{
Jani Nikula1d508702012-10-19 14:51:49 +03003105 struct intel_connector *intel_connector = to_intel_connector(connector);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02003106
Jani Nikula9cd300e2012-10-19 14:51:52 +03003107 if (!IS_ERR_OR_NULL(intel_connector->edid))
3108 kfree(intel_connector->edid);
3109
Paulo Zanoniacd8db102013-06-12 17:27:23 -03003110 /* Can't call is_edp() since the encoder may have been destroyed
3111 * already. */
3112 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
Jani Nikula1d508702012-10-19 14:51:49 +03003113 intel_panel_fini(&intel_connector->panel);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02003114
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003115 drm_sysfs_connector_remove(connector);
3116 drm_connector_cleanup(connector);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08003117 kfree(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003118}
3119
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003120void intel_dp_encoder_destroy(struct drm_encoder *encoder)
Daniel Vetter24d05922010-08-20 18:08:28 +02003121{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003122 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3123 struct intel_dp *intel_dp = &intel_dig_port->dp;
Daniel Vetterbd173812013-03-25 11:24:10 +01003124 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Daniel Vetter24d05922010-08-20 18:08:28 +02003125
3126 i2c_del_adapter(&intel_dp->adapter);
3127 drm_encoder_cleanup(encoder);
Keith Packardbd943152011-09-18 23:09:52 -07003128 if (is_edp(intel_dp)) {
3129 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
Daniel Vetterbd173812013-03-25 11:24:10 +01003130 mutex_lock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07003131 ironlake_panel_vdd_off_sync(intel_dp);
Daniel Vetterbd173812013-03-25 11:24:10 +01003132 mutex_unlock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07003133 }
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003134 kfree(intel_dig_port);
Daniel Vetter24d05922010-08-20 18:08:28 +02003135}
3136
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003137static const struct drm_connector_funcs intel_dp_connector_funcs = {
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02003138 .dpms = intel_connector_dpms,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003139 .detect = intel_dp_detect,
3140 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilsonf6849602010-09-19 09:29:33 +01003141 .set_property = intel_dp_set_property,
Paulo Zanoni73845ad2013-06-12 17:27:30 -03003142 .destroy = intel_dp_connector_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003143};
3144
3145static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3146 .get_modes = intel_dp_get_modes,
3147 .mode_valid = intel_dp_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01003148 .best_encoder = intel_best_encoder,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003149};
3150
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003151static const struct drm_encoder_funcs intel_dp_enc_funcs = {
Daniel Vetter24d05922010-08-20 18:08:28 +02003152 .destroy = intel_dp_encoder_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003153};
3154
Chris Wilson995b67622010-08-20 13:23:26 +01003155static void
Eric Anholt21d40d32010-03-25 11:11:14 -07003156intel_dp_hot_plug(struct intel_encoder *intel_encoder)
Keith Packardc8110e52009-05-06 11:51:10 -07003157{
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003158 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Keith Packardc8110e52009-05-06 11:51:10 -07003159
Jesse Barnes885a5012011-07-07 11:11:01 -07003160 intel_dp_check_link_status(intel_dp);
Keith Packardc8110e52009-05-06 11:51:10 -07003161}
3162
Zhenyu Wange3421a12010-04-08 09:43:27 +08003163/* Return which DP Port should be selected for Transcoder DP control */
3164int
Akshay Joshi0206e352011-08-16 15:34:10 -04003165intel_trans_dp_port_sel(struct drm_crtc *crtc)
Zhenyu Wange3421a12010-04-08 09:43:27 +08003166{
3167 struct drm_device *dev = crtc->dev;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003168 struct intel_encoder *intel_encoder;
3169 struct intel_dp *intel_dp;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003170
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003171 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3172 intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003173
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003174 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3175 intel_encoder->type == INTEL_OUTPUT_EDP)
Chris Wilsonea5b2132010-08-04 13:50:23 +01003176 return intel_dp->output_reg;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003177 }
Chris Wilsonea5b2132010-08-04 13:50:23 +01003178
Zhenyu Wange3421a12010-04-08 09:43:27 +08003179 return -1;
3180}
3181
Zhao Yakui36e83a12010-06-12 14:32:21 +08003182/* check the VBT to see whether the eDP is on DP-D port */
Adam Jacksoncb0953d2010-07-16 14:46:29 -04003183bool intel_dpd_is_edp(struct drm_device *dev)
Zhao Yakui36e83a12010-06-12 14:32:21 +08003184{
3185 struct drm_i915_private *dev_priv = dev->dev_private;
3186 struct child_device_config *p_child;
3187 int i;
3188
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003189 if (!dev_priv->vbt.child_dev_num)
Zhao Yakui36e83a12010-06-12 14:32:21 +08003190 return false;
3191
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003192 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3193 p_child = dev_priv->vbt.child_dev + i;
Zhao Yakui36e83a12010-06-12 14:32:21 +08003194
3195 if (p_child->dvo_port == PORT_IDPD &&
3196 p_child->device_type == DEVICE_TYPE_eDP)
3197 return true;
3198 }
3199 return false;
3200}
3201
Chris Wilsonf6849602010-09-19 09:29:33 +01003202static void
3203intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3204{
Yuly Novikov53b41832012-10-26 12:04:00 +03003205 struct intel_connector *intel_connector = to_intel_connector(connector);
3206
Chris Wilson3f43c482011-05-12 22:17:24 +01003207 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00003208 intel_attach_broadcast_rgb_property(connector);
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003209 intel_dp->color_range_auto = true;
Yuly Novikov53b41832012-10-26 12:04:00 +03003210
3211 if (is_edp(intel_dp)) {
3212 drm_mode_create_scaling_mode_property(connector->dev);
Rob Clark6de6d842012-10-11 20:36:04 -05003213 drm_object_attach_property(
3214 &connector->base,
Yuly Novikov53b41832012-10-26 12:04:00 +03003215 connector->dev->mode_config.scaling_mode_property,
Yuly Novikov8e740cd2012-10-26 12:04:01 +03003216 DRM_MODE_SCALE_ASPECT);
3217 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
Yuly Novikov53b41832012-10-26 12:04:00 +03003218 }
Chris Wilsonf6849602010-09-19 09:29:33 +01003219}
3220
Daniel Vetter67a54562012-10-20 20:57:45 +02003221static void
3222intel_dp_init_panel_power_sequencer(struct drm_device *dev,
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003223 struct intel_dp *intel_dp,
3224 struct edp_power_seq *out)
Daniel Vetter67a54562012-10-20 20:57:45 +02003225{
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227 struct edp_power_seq cur, vbt, spec, final;
3228 u32 pp_on, pp_off, pp_div, pp;
Jani Nikulabf13e812013-09-06 07:40:05 +03003229 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
Jesse Barnes453c5422013-03-28 09:55:41 -07003230
3231 if (HAS_PCH_SPLIT(dev)) {
Jani Nikulabf13e812013-09-06 07:40:05 +03003232 pp_ctrl_reg = PCH_PP_CONTROL;
Jesse Barnes453c5422013-03-28 09:55:41 -07003233 pp_on_reg = PCH_PP_ON_DELAYS;
3234 pp_off_reg = PCH_PP_OFF_DELAYS;
3235 pp_div_reg = PCH_PP_DIVISOR;
3236 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03003237 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3238
3239 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3240 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3241 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3242 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07003243 }
Daniel Vetter67a54562012-10-20 20:57:45 +02003244
3245 /* Workaround: Need to write PP_CONTROL with the unlock key as
3246 * the very first thing. */
Jesse Barnes453c5422013-03-28 09:55:41 -07003247 pp = ironlake_get_pp_control(intel_dp);
Jani Nikulabf13e812013-09-06 07:40:05 +03003248 I915_WRITE(pp_ctrl_reg, pp);
Daniel Vetter67a54562012-10-20 20:57:45 +02003249
Jesse Barnes453c5422013-03-28 09:55:41 -07003250 pp_on = I915_READ(pp_on_reg);
3251 pp_off = I915_READ(pp_off_reg);
3252 pp_div = I915_READ(pp_div_reg);
Daniel Vetter67a54562012-10-20 20:57:45 +02003253
3254 /* Pull timing values out of registers */
3255 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3256 PANEL_POWER_UP_DELAY_SHIFT;
3257
3258 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3259 PANEL_LIGHT_ON_DELAY_SHIFT;
3260
3261 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3262 PANEL_LIGHT_OFF_DELAY_SHIFT;
3263
3264 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3265 PANEL_POWER_DOWN_DELAY_SHIFT;
3266
3267 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3268 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3269
3270 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3271 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3272
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003273 vbt = dev_priv->vbt.edp_pps;
Daniel Vetter67a54562012-10-20 20:57:45 +02003274
3275 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3276 * our hw here, which are all in 100usec. */
3277 spec.t1_t3 = 210 * 10;
3278 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3279 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3280 spec.t10 = 500 * 10;
3281 /* This one is special and actually in units of 100ms, but zero
3282 * based in the hw (so we need to add 100 ms). But the sw vbt
3283 * table multiplies it with 1000 to make it in units of 100usec,
3284 * too. */
3285 spec.t11_t12 = (510 + 100) * 10;
3286
3287 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3288 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3289
3290 /* Use the max of the register settings and vbt. If both are
3291 * unset, fall back to the spec limits. */
3292#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3293 spec.field : \
3294 max(cur.field, vbt.field))
3295 assign_final(t1_t3);
3296 assign_final(t8);
3297 assign_final(t9);
3298 assign_final(t10);
3299 assign_final(t11_t12);
3300#undef assign_final
3301
3302#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3303 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3304 intel_dp->backlight_on_delay = get_delay(t8);
3305 intel_dp->backlight_off_delay = get_delay(t9);
3306 intel_dp->panel_power_down_delay = get_delay(t10);
3307 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3308#undef get_delay
3309
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003310 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3311 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3312 intel_dp->panel_power_cycle_delay);
3313
3314 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3315 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3316
3317 if (out)
3318 *out = final;
3319}
3320
3321static void
3322intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3323 struct intel_dp *intel_dp,
3324 struct edp_power_seq *seq)
3325{
3326 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -07003327 u32 pp_on, pp_off, pp_div, port_sel = 0;
3328 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3329 int pp_on_reg, pp_off_reg, pp_div_reg;
3330
3331 if (HAS_PCH_SPLIT(dev)) {
3332 pp_on_reg = PCH_PP_ON_DELAYS;
3333 pp_off_reg = PCH_PP_OFF_DELAYS;
3334 pp_div_reg = PCH_PP_DIVISOR;
3335 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03003336 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3337
3338 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3339 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3340 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07003341 }
3342
Daniel Vetter67a54562012-10-20 20:57:45 +02003343 /* And finally store the new values in the power sequencer. */
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003344 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3345 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3346 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3347 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
Daniel Vetter67a54562012-10-20 20:57:45 +02003348 /* Compute the divisor for the pp clock, simply match the Bspec
3349 * formula. */
Jesse Barnes453c5422013-03-28 09:55:41 -07003350 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003351 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
Daniel Vetter67a54562012-10-20 20:57:45 +02003352 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3353
3354 /* Haswell doesn't have any port selection bits for the panel
3355 * power sequencer any more. */
Imre Deakbc7d38a2013-05-16 14:40:36 +03003356 if (IS_VALLEYVIEW(dev)) {
Jani Nikulabf13e812013-09-06 07:40:05 +03003357 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3358 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3359 else
3360 port_sel = PANEL_PORT_SELECT_DPC_VLV;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003361 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3362 if (dp_to_dig_port(intel_dp)->port == PORT_A)
Jani Nikulaa24c1442013-09-05 16:44:46 +03003363 port_sel = PANEL_PORT_SELECT_DPA;
Daniel Vetter67a54562012-10-20 20:57:45 +02003364 else
Jani Nikulaa24c1442013-09-05 16:44:46 +03003365 port_sel = PANEL_PORT_SELECT_DPD;
Daniel Vetter67a54562012-10-20 20:57:45 +02003366 }
3367
Jesse Barnes453c5422013-03-28 09:55:41 -07003368 pp_on |= port_sel;
3369
3370 I915_WRITE(pp_on_reg, pp_on);
3371 I915_WRITE(pp_off_reg, pp_off);
3372 I915_WRITE(pp_div_reg, pp_div);
Daniel Vetter67a54562012-10-20 20:57:45 +02003373
Daniel Vetter67a54562012-10-20 20:57:45 +02003374 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07003375 I915_READ(pp_on_reg),
3376 I915_READ(pp_off_reg),
3377 I915_READ(pp_div_reg));
Keith Packardc8110e52009-05-06 11:51:10 -07003378}
3379
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003380static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3381 struct intel_connector *intel_connector)
3382{
3383 struct drm_connector *connector = &intel_connector->base;
3384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3385 struct drm_device *dev = intel_dig_port->base.base.dev;
3386 struct drm_i915_private *dev_priv = dev->dev_private;
3387 struct drm_display_mode *fixed_mode = NULL;
3388 struct edp_power_seq power_seq = { 0 };
3389 bool has_dpcd;
3390 struct drm_display_mode *scan;
3391 struct edid *edid;
3392
3393 if (!is_edp(intel_dp))
3394 return true;
3395
3396 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3397
3398 /* Cache DPCD and EDID for edp. */
3399 ironlake_edp_panel_vdd_on(intel_dp);
3400 has_dpcd = intel_dp_get_dpcd(intel_dp);
3401 ironlake_edp_panel_vdd_off(intel_dp, false);
3402
3403 if (has_dpcd) {
3404 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3405 dev_priv->no_aux_handshake =
3406 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3407 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3408 } else {
3409 /* if this fails, presume the device is a ghost */
3410 DRM_INFO("failed to retrieve link info, disabling eDP\n");
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003411 return false;
3412 }
3413
3414 /* We now know it's not a ghost, init power sequence regs. */
3415 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3416 &power_seq);
3417
3418 ironlake_edp_panel_vdd_on(intel_dp);
3419 edid = drm_get_edid(connector, &intel_dp->adapter);
3420 if (edid) {
3421 if (drm_add_edid_modes(connector, edid)) {
3422 drm_mode_connector_update_edid_property(connector,
3423 edid);
3424 drm_edid_to_eld(connector, edid);
3425 } else {
3426 kfree(edid);
3427 edid = ERR_PTR(-EINVAL);
3428 }
3429 } else {
3430 edid = ERR_PTR(-ENOENT);
3431 }
3432 intel_connector->edid = edid;
3433
3434 /* prefer fixed mode from EDID if available */
3435 list_for_each_entry(scan, &connector->probed_modes, head) {
3436 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3437 fixed_mode = drm_mode_duplicate(dev, scan);
3438 break;
3439 }
3440 }
3441
3442 /* fallback to VBT if available for eDP */
3443 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3444 fixed_mode = drm_mode_duplicate(dev,
3445 dev_priv->vbt.lfp_lvds_vbt_mode);
3446 if (fixed_mode)
3447 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3448 }
3449
3450 ironlake_edp_panel_vdd_off(intel_dp, false);
3451
3452 intel_panel_init(&intel_connector->panel, fixed_mode);
3453 intel_panel_setup_backlight(connector);
3454
3455 return true;
3456}
3457
Paulo Zanoni16c25532013-06-12 17:27:25 -03003458bool
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003459intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3460 struct intel_connector *intel_connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003461{
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003462 struct drm_connector *connector = &intel_connector->base;
3463 struct intel_dp *intel_dp = &intel_dig_port->dp;
3464 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3465 struct drm_device *dev = intel_encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003466 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02003467 enum port port = intel_dig_port->port;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003468 const char *name = NULL;
Paulo Zanonib2a14752013-06-12 17:27:28 -03003469 int type, error;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003470
Daniel Vetter07679352012-09-06 22:15:42 +02003471 /* Preserve the current hw state. */
3472 intel_dp->DP = I915_READ(intel_dp->output_reg);
Jani Nikuladd06f902012-10-19 14:51:50 +03003473 intel_dp->attached_connector = intel_connector;
Chris Wilson3d3dc142011-02-12 10:33:12 +00003474
Imre Deakf7d24902013-05-08 13:14:05 +03003475 type = DRM_MODE_CONNECTOR_DisplayPort;
Gajanan Bhat19c03922012-09-27 19:13:07 +05303476 /*
3477 * FIXME : We need to initialize built-in panels before external panels.
3478 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3479 */
Imre Deakf7d24902013-05-08 13:14:05 +03003480 switch (port) {
3481 case PORT_A:
Gajanan Bhat19c03922012-09-27 19:13:07 +05303482 type = DRM_MODE_CONNECTOR_eDP;
Imre Deakf7d24902013-05-08 13:14:05 +03003483 break;
3484 case PORT_C:
3485 if (IS_VALLEYVIEW(dev))
3486 type = DRM_MODE_CONNECTOR_eDP;
3487 break;
3488 case PORT_D:
3489 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3490 type = DRM_MODE_CONNECTOR_eDP;
3491 break;
3492 default: /* silence GCC warning */
3493 break;
Adam Jacksonb3295302010-07-16 14:46:28 -04003494 }
3495
Imre Deakf7d24902013-05-08 13:14:05 +03003496 /*
3497 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3498 * for DP the encoder type can be set by the caller to
3499 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3500 */
3501 if (type == DRM_MODE_CONNECTOR_eDP)
3502 intel_encoder->type = INTEL_OUTPUT_EDP;
3503
Imre Deake7281ea2013-05-08 13:14:08 +03003504 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3505 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3506 port_name(port));
3507
Adam Jacksonb3295302010-07-16 14:46:28 -04003508 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003509 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3510
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003511 connector->interlace_allowed = true;
3512 connector->doublescan_allowed = 0;
Ma Lingf8aed702009-08-24 13:50:24 +08003513
Daniel Vetter66a92782012-07-12 20:08:18 +02003514 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3515 ironlake_panel_vdd_work);
Zhenyu Wang6251ec02010-01-12 05:38:32 +08003516
Chris Wilsondf0e9242010-09-09 16:20:55 +01003517 intel_connector_attach_encoder(intel_connector, intel_encoder);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003518 drm_sysfs_connector_add(connector);
3519
Paulo Zanoniaffa9352012-11-23 15:30:39 -02003520 if (HAS_DDI(dev))
Paulo Zanonibcbc8892012-10-26 19:05:51 -02003521 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3522 else
3523 intel_connector->get_hw_state = intel_connector_get_hw_state;
3524
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -03003525 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3526 if (HAS_DDI(dev)) {
3527 switch (intel_dig_port->port) {
3528 case PORT_A:
3529 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3530 break;
3531 case PORT_B:
3532 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3533 break;
3534 case PORT_C:
3535 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3536 break;
3537 case PORT_D:
3538 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3539 break;
3540 default:
3541 BUG();
3542 }
3543 }
Daniel Vettere8cb4552012-07-01 13:05:48 +02003544
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003545 /* Set up the DDC bus. */
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003546 switch (port) {
3547 case PORT_A:
Egbert Eich1d843f92013-02-25 12:06:49 -05003548 intel_encoder->hpd_pin = HPD_PORT_A;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003549 name = "DPDDC-A";
3550 break;
3551 case PORT_B:
Egbert Eich1d843f92013-02-25 12:06:49 -05003552 intel_encoder->hpd_pin = HPD_PORT_B;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003553 name = "DPDDC-B";
3554 break;
3555 case PORT_C:
Egbert Eich1d843f92013-02-25 12:06:49 -05003556 intel_encoder->hpd_pin = HPD_PORT_C;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003557 name = "DPDDC-C";
3558 break;
3559 case PORT_D:
Egbert Eich1d843f92013-02-25 12:06:49 -05003560 intel_encoder->hpd_pin = HPD_PORT_D;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003561 name = "DPDDC-D";
3562 break;
3563 default:
Damien Lespiauad1c0b12013-03-07 15:30:28 +00003564 BUG();
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003565 }
3566
Paulo Zanonib2a14752013-06-12 17:27:28 -03003567 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3568 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3569 error, port_name(port));
Dave Airliec1f05262012-08-30 11:06:18 +10003570
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003571 intel_dp->psr_setup_done = false;
3572
Paulo Zanonib2f246a2013-06-12 17:27:26 -03003573 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
Paulo Zanoni15b1d172013-06-12 17:27:27 -03003574 i2c_del_adapter(&intel_dp->adapter);
3575 if (is_edp(intel_dp)) {
3576 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3577 mutex_lock(&dev->mode_config.mutex);
3578 ironlake_panel_vdd_off_sync(intel_dp);
3579 mutex_unlock(&dev->mode_config.mutex);
3580 }
Paulo Zanonib2f246a2013-06-12 17:27:26 -03003581 drm_sysfs_connector_remove(connector);
3582 drm_connector_cleanup(connector);
Paulo Zanoni16c25532013-06-12 17:27:25 -03003583 return false;
Paulo Zanonib2f246a2013-06-12 17:27:26 -03003584 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003585
Chris Wilsonf6849602010-09-19 09:29:33 +01003586 intel_dp_add_properties(intel_dp, connector);
3587
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003588 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3589 * 0xd. Failure to do so will result in spurious interrupts being
3590 * generated on the port when a cable is not attached.
3591 */
3592 if (IS_G4X(dev) && !IS_GM45(dev)) {
3593 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3594 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3595 }
Paulo Zanoni16c25532013-06-12 17:27:25 -03003596
3597 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003598}
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003599
3600void
3601intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3602{
3603 struct intel_digital_port *intel_dig_port;
3604 struct intel_encoder *intel_encoder;
3605 struct drm_encoder *encoder;
3606 struct intel_connector *intel_connector;
3607
3608 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3609 if (!intel_dig_port)
3610 return;
3611
3612 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3613 if (!intel_connector) {
3614 kfree(intel_dig_port);
3615 return;
3616 }
3617
3618 intel_encoder = &intel_dig_port->base;
3619 encoder = &intel_encoder->base;
3620
3621 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3622 DRM_MODE_ENCODER_TMDS);
3623
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003624 intel_encoder->compute_config = intel_dp_compute_config;
Daniel Vetterb934223d2013-07-21 21:37:05 +02003625 intel_encoder->mode_set = intel_dp_mode_set;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003626 intel_encoder->disable = intel_disable_dp;
3627 intel_encoder->post_disable = intel_post_disable_dp;
3628 intel_encoder->get_hw_state = intel_dp_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07003629 intel_encoder->get_config = intel_dp_get_config;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03003630 if (IS_VALLEYVIEW(dev)) {
Jani Nikulaecff4f32013-09-06 07:38:29 +03003631 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03003632 intel_encoder->pre_enable = vlv_pre_enable_dp;
3633 intel_encoder->enable = vlv_enable_dp;
3634 } else {
Jani Nikulaecff4f32013-09-06 07:38:29 +03003635 intel_encoder->pre_enable = g4x_pre_enable_dp;
3636 intel_encoder->enable = g4x_enable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03003637 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003638
Paulo Zanoni174edf12012-10-26 19:05:50 -02003639 intel_dig_port->port = port;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003640 intel_dig_port->dp.output_reg = output_reg;
3641
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003642 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003643 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3644 intel_encoder->cloneable = false;
3645 intel_encoder->hot_plug = intel_dp_hot_plug;
3646
Paulo Zanoni15b1d172013-06-12 17:27:27 -03003647 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3648 drm_encoder_cleanup(encoder);
3649 kfree(intel_dig_port);
Paulo Zanonib2f246a2013-06-12 17:27:26 -03003650 kfree(intel_connector);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03003651 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003652}