blob: dfb029ab34483988ace5ee1427a254e9abfba767 [file] [log] [blame]
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33
34#include <linux/vga_switcheroo.h>
35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
Oded Gabbay130e0372015-06-12 21:35:14 +030037#include "amdgpu_amdkfd.h"
Alex Deucherd38ceaf2015-04-20 16:55:21 -040038
39#if defined(CONFIG_VGA_SWITCHEROO)
40bool amdgpu_has_atpx(void);
41#else
42static inline bool amdgpu_has_atpx(void) { return false; }
43#endif
44
45/**
46 * amdgpu_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * Returns 0 on success.
52 */
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -020053void amdgpu_driver_unload_kms(struct drm_device *dev)
Alex Deucherd38ceaf2015-04-20 16:55:21 -040054{
55 struct amdgpu_device *adev = dev->dev_private;
56
57 if (adev == NULL)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -020058 return;
Alex Deucherd38ceaf2015-04-20 16:55:21 -040059
60 if (adev->rmmio == NULL)
61 goto done_free;
62
Xiangliang Yu3149d9d2017-01-12 15:14:36 +080063 if (amdgpu_sriov_vf(adev))
64 amdgpu_virt_request_full_gpu(adev, false);
65
Lukas Wunner4a788542016-06-08 18:47:27 +020066 if (amdgpu_device_is_px(dev)) {
67 pm_runtime_get_sync(dev->dev);
Lukas Wunner6ce62d82016-06-08 18:47:27 +020068 pm_runtime_forbid(dev->dev);
Lukas Wunner4a788542016-06-08 18:47:27 +020069 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -040070
Oded Gabbay130e0372015-06-12 21:35:14 +030071 amdgpu_amdkfd_device_fini(adev);
72
Alex Deucherd38ceaf2015-04-20 16:55:21 -040073 amdgpu_acpi_fini(adev);
74
75 amdgpu_device_fini(adev);
76
77done_free:
78 kfree(adev);
79 dev->dev_private = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -040080}
81
82/**
83 * amdgpu_driver_load_kms - Main load function for KMS.
84 *
85 * @dev: drm dev pointer
86 * @flags: device flags
87 *
88 * This is the main load function for KMS (all asics).
89 * Returns 0 on success, error on failure.
90 */
91int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
92{
93 struct amdgpu_device *adev;
94 int r, acpi_status;
95
96 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
97 if (adev == NULL) {
98 return -ENOMEM;
99 }
100 dev->dev_private = (void *)adev;
101
102 if ((amdgpu_runtime_pm != 0) &&
103 amdgpu_has_atpx() &&
Alex Deucher84b15282016-10-31 11:02:31 -0400104 (amdgpu_is_atpx_hybrid() ||
105 amdgpu_has_atpx_dgpu_power_cntl()) &&
Lukas Wunner84c8b222017-03-10 21:23:45 +0100106 ((flags & AMD_IS_APU) == 0) &&
107 !pci_is_thunderbolt_attached(dev->pdev))
Jammy Zhou2f7d10b2015-07-22 11:29:01 +0800108 flags |= AMD_IS_PX;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400109
110 /* amdgpu_device_init should report only fatal error
111 * like memory allocation failure or iomapping failure,
112 * or memory manager initialization failure, it must
113 * properly initialize the GPU MC controller and permit
114 * VRAM allocation
115 */
116 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
117 if (r) {
118 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
119 goto out;
120 }
121
122 /* Call ACPI methods: require modeset init
123 * but failure is not fatal
124 */
125 if (!r) {
126 acpi_status = amdgpu_acpi_init(adev);
127 if (acpi_status)
128 dev_dbg(&dev->pdev->dev,
129 "Error during ACPI methods call\n");
130 }
131
Oded Gabbay130e0372015-06-12 21:35:14 +0300132 amdgpu_amdkfd_load_interface(adev);
133 amdgpu_amdkfd_device_probe(adev);
134 amdgpu_amdkfd_device_init(adev);
135
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400136 if (amdgpu_device_is_px(dev)) {
137 pm_runtime_use_autosuspend(dev->dev);
138 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
139 pm_runtime_set_active(dev->dev);
140 pm_runtime_allow(dev->dev);
141 pm_runtime_mark_last_busy(dev->dev);
142 pm_runtime_put_autosuspend(dev->dev);
143 }
144
Xiangliang Yu3149d9d2017-01-12 15:14:36 +0800145 if (amdgpu_sriov_vf(adev))
146 amdgpu_virt_release_full_gpu(adev, true);
147
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400148out:
Lukas Wunnerc9c9bbd2016-06-08 18:47:27 +0200149 if (r) {
150 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
151 if (adev->rmmio && amdgpu_device_is_px(dev))
152 pm_runtime_put_noidle(dev->dev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400153 amdgpu_driver_unload_kms(dev);
Lukas Wunnerc9c9bbd2016-06-08 18:47:27 +0200154 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400155
156 return r;
157}
158
Huang Rui000cab92016-06-12 15:44:44 +0800159static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
160 struct drm_amdgpu_query_fw *query_fw,
161 struct amdgpu_device *adev)
162{
163 switch (query_fw->fw_type) {
164 case AMDGPU_INFO_FW_VCE:
165 fw_info->ver = adev->vce.fw_version;
166 fw_info->feature = adev->vce.fb_version;
167 break;
168 case AMDGPU_INFO_FW_UVD:
169 fw_info->ver = adev->uvd.fw_version;
170 fw_info->feature = 0;
171 break;
172 case AMDGPU_INFO_FW_GMC:
173 fw_info->ver = adev->mc.fw_version;
174 fw_info->feature = 0;
175 break;
176 case AMDGPU_INFO_FW_GFX_ME:
177 fw_info->ver = adev->gfx.me_fw_version;
178 fw_info->feature = adev->gfx.me_feature_version;
179 break;
180 case AMDGPU_INFO_FW_GFX_PFP:
181 fw_info->ver = adev->gfx.pfp_fw_version;
182 fw_info->feature = adev->gfx.pfp_feature_version;
183 break;
184 case AMDGPU_INFO_FW_GFX_CE:
185 fw_info->ver = adev->gfx.ce_fw_version;
186 fw_info->feature = adev->gfx.ce_feature_version;
187 break;
188 case AMDGPU_INFO_FW_GFX_RLC:
189 fw_info->ver = adev->gfx.rlc_fw_version;
190 fw_info->feature = adev->gfx.rlc_feature_version;
191 break;
192 case AMDGPU_INFO_FW_GFX_MEC:
193 if (query_fw->index == 0) {
194 fw_info->ver = adev->gfx.mec_fw_version;
195 fw_info->feature = adev->gfx.mec_feature_version;
196 } else if (query_fw->index == 1) {
197 fw_info->ver = adev->gfx.mec2_fw_version;
198 fw_info->feature = adev->gfx.mec2_feature_version;
199 } else
200 return -EINVAL;
201 break;
202 case AMDGPU_INFO_FW_SMC:
203 fw_info->ver = adev->pm.fw_version;
204 fw_info->feature = 0;
205 break;
206 case AMDGPU_INFO_FW_SDMA:
207 if (query_fw->index >= adev->sdma.num_instances)
208 return -EINVAL;
209 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
210 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
211 break;
Huang Rui6a7ed072017-03-03 19:15:26 -0500212 case AMDGPU_INFO_FW_SOS:
213 fw_info->ver = adev->psp.sos_fw_version;
214 fw_info->feature = adev->psp.sos_feature_version;
215 break;
216 case AMDGPU_INFO_FW_ASD:
217 fw_info->ver = adev->psp.asd_fw_version;
218 fw_info->feature = adev->psp.asd_feature_version;
219 break;
Huang Rui000cab92016-06-12 15:44:44 +0800220 default:
221 return -EINVAL;
222 }
223 return 0;
224}
225
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400226/*
227 * Userspace get information ioctl
228 */
229/**
230 * amdgpu_info_ioctl - answer a device specific request.
231 *
232 * @adev: amdgpu device pointer
233 * @data: request object
234 * @filp: drm filp
235 *
236 * This function is used to pass device specific parameters to the userspace
237 * drivers. Examples include: pci device id, pipeline parms, tiling params,
238 * etc. (all asics).
239 * Returns 0 on success, -EINVAL on failure.
240 */
241static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
242{
243 struct amdgpu_device *adev = dev->dev_private;
244 struct drm_amdgpu_info *info = data;
245 struct amdgpu_mode_info *minfo = &adev->mode_info;
246 void __user *out = (void __user *)(long)info->return_pointer;
247 uint32_t size = info->return_size;
248 struct drm_crtc *crtc;
249 uint32_t ui32 = 0;
250 uint64_t ui64 = 0;
251 int i, found;
Alex Deucher5ebbac42017-03-08 18:25:15 -0500252 int ui32_size = sizeof(ui32);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400253
254 if (!info->return_size || !info->return_pointer)
255 return -EINVAL;
256
257 switch (info->query) {
258 case AMDGPU_INFO_ACCEL_WORKING:
259 ui32 = adev->accel_working;
260 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
261 case AMDGPU_INFO_CRTC_FROM_ID:
262 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
263 crtc = (struct drm_crtc *)minfo->crtcs[i];
264 if (crtc && crtc->base.id == info->mode_crtc.id) {
265 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
266 ui32 = amdgpu_crtc->crtc_id;
267 found = 1;
268 break;
269 }
270 }
271 if (!found) {
272 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
273 return -EINVAL;
274 }
275 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
276 case AMDGPU_INFO_HW_IP_INFO: {
277 struct drm_amdgpu_info_hw_ip ip = {};
yanyang15fc3aee2015-05-22 14:39:35 -0400278 enum amd_ip_block_type type;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400279 uint32_t ring_mask = 0;
Ken Wang71062f42015-06-04 21:26:57 +0800280 uint32_t ib_start_alignment = 0;
281 uint32_t ib_size_alignment = 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400282
283 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
284 return -EINVAL;
285
286 switch (info->query_hw_ip.type) {
287 case AMDGPU_HW_IP_GFX:
yanyang15fc3aee2015-05-22 14:39:35 -0400288 type = AMD_IP_BLOCK_TYPE_GFX;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400289 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
290 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
Ken Wang71062f42015-06-04 21:26:57 +0800291 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
292 ib_size_alignment = 8;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400293 break;
294 case AMDGPU_HW_IP_COMPUTE:
yanyang15fc3aee2015-05-22 14:39:35 -0400295 type = AMD_IP_BLOCK_TYPE_GFX;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400296 for (i = 0; i < adev->gfx.num_compute_rings; i++)
297 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
Ken Wang71062f42015-06-04 21:26:57 +0800298 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
299 ib_size_alignment = 8;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400300 break;
301 case AMDGPU_HW_IP_DMA:
yanyang15fc3aee2015-05-22 14:39:35 -0400302 type = AMD_IP_BLOCK_TYPE_SDMA;
Alex Deucherc113ea12015-10-08 16:30:37 -0400303 for (i = 0; i < adev->sdma.num_instances; i++)
304 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
Ken Wang71062f42015-06-04 21:26:57 +0800305 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
306 ib_size_alignment = 1;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400307 break;
308 case AMDGPU_HW_IP_UVD:
yanyang15fc3aee2015-05-22 14:39:35 -0400309 type = AMD_IP_BLOCK_TYPE_UVD;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400310 ring_mask = adev->uvd.ring.ready ? 1 : 0;
Ken Wang71062f42015-06-04 21:26:57 +0800311 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
Alex Deucherc4795ca2016-08-22 16:31:36 -0400312 ib_size_alignment = 16;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400313 break;
314 case AMDGPU_HW_IP_VCE:
yanyang15fc3aee2015-05-22 14:39:35 -0400315 type = AMD_IP_BLOCK_TYPE_VCE;
Alex Deucher75c65482016-08-24 16:56:21 -0400316 for (i = 0; i < adev->vce.num_rings; i++)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400317 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
Ken Wang71062f42015-06-04 21:26:57 +0800318 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
Alex Deuchera22f8032016-08-23 10:44:16 -0400319 ib_size_alignment = 1;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400320 break;
Leo Liu63defd32017-01-10 11:50:08 -0500321 case AMDGPU_HW_IP_UVD_ENC:
322 type = AMD_IP_BLOCK_TYPE_UVD;
323 for (i = 0; i < adev->uvd.num_enc_rings; i++)
324 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
325 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
326 ib_size_alignment = 1;
327 break;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400328 default:
329 return -EINVAL;
330 }
331
332 for (i = 0; i < adev->num_ip_blocks; i++) {
Alex Deuchera1255102016-10-13 17:41:13 -0400333 if (adev->ip_blocks[i].version->type == type &&
334 adev->ip_blocks[i].status.valid) {
335 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
336 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400337 ip.capabilities_flags = 0;
338 ip.available_rings = ring_mask;
Ken Wang71062f42015-06-04 21:26:57 +0800339 ip.ib_start_alignment = ib_start_alignment;
340 ip.ib_size_alignment = ib_size_alignment;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400341 break;
342 }
343 }
344 return copy_to_user(out, &ip,
345 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
346 }
347 case AMDGPU_INFO_HW_IP_COUNT: {
yanyang15fc3aee2015-05-22 14:39:35 -0400348 enum amd_ip_block_type type;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400349 uint32_t count = 0;
350
351 switch (info->query_hw_ip.type) {
352 case AMDGPU_HW_IP_GFX:
yanyang15fc3aee2015-05-22 14:39:35 -0400353 type = AMD_IP_BLOCK_TYPE_GFX;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400354 break;
355 case AMDGPU_HW_IP_COMPUTE:
yanyang15fc3aee2015-05-22 14:39:35 -0400356 type = AMD_IP_BLOCK_TYPE_GFX;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400357 break;
358 case AMDGPU_HW_IP_DMA:
yanyang15fc3aee2015-05-22 14:39:35 -0400359 type = AMD_IP_BLOCK_TYPE_SDMA;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400360 break;
361 case AMDGPU_HW_IP_UVD:
yanyang15fc3aee2015-05-22 14:39:35 -0400362 type = AMD_IP_BLOCK_TYPE_UVD;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400363 break;
364 case AMDGPU_HW_IP_VCE:
yanyang15fc3aee2015-05-22 14:39:35 -0400365 type = AMD_IP_BLOCK_TYPE_VCE;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400366 break;
Leo Liu63defd32017-01-10 11:50:08 -0500367 case AMDGPU_HW_IP_UVD_ENC:
368 type = AMD_IP_BLOCK_TYPE_UVD;
369 break;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400370 default:
371 return -EINVAL;
372 }
373
374 for (i = 0; i < adev->num_ip_blocks; i++)
Alex Deuchera1255102016-10-13 17:41:13 -0400375 if (adev->ip_blocks[i].version->type == type &&
376 adev->ip_blocks[i].status.valid &&
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400377 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
378 count++;
379
380 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
381 }
382 case AMDGPU_INFO_TIMESTAMP:
Alex Deucherb95e31f2016-07-07 15:01:42 -0400383 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400384 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
385 case AMDGPU_INFO_FW_VERSION: {
386 struct drm_amdgpu_info_firmware fw_info;
Huang Rui000cab92016-06-12 15:44:44 +0800387 int ret;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400388
389 /* We only support one instance of each IP block right now. */
390 if (info->query_fw.ip_instance != 0)
391 return -EINVAL;
392
Huang Rui000cab92016-06-12 15:44:44 +0800393 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
394 if (ret)
395 return ret;
396
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400397 return copy_to_user(out, &fw_info,
398 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
399 }
400 case AMDGPU_INFO_NUM_BYTES_MOVED:
401 ui64 = atomic64_read(&adev->num_bytes_moved);
402 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
Marek Olšák83a59b62016-08-17 23:58:58 +0200403 case AMDGPU_INFO_NUM_EVICTIONS:
404 ui64 = atomic64_read(&adev->num_evictions);
405 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400406 case AMDGPU_INFO_VRAM_USAGE:
407 ui64 = atomic64_read(&adev->vram_usage);
408 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
409 case AMDGPU_INFO_VIS_VRAM_USAGE:
410 ui64 = atomic64_read(&adev->vram_vis_usage);
411 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
412 case AMDGPU_INFO_GTT_USAGE:
413 ui64 = atomic64_read(&adev->gtt_usage);
414 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
415 case AMDGPU_INFO_GDS_CONFIG: {
416 struct drm_amdgpu_info_gds gds_info;
417
Alex Deucherc92b90c2015-04-30 11:47:03 -0400418 memset(&gds_info, 0, sizeof(gds_info));
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400419 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
420 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
421 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
422 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
423 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
424 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
425 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
426 return copy_to_user(out, &gds_info,
427 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
428 }
429 case AMDGPU_INFO_VRAM_GTT: {
430 struct drm_amdgpu_info_vram_gtt vram_gtt;
431
432 vram_gtt.vram_size = adev->mc.real_vram_size;
Chunming Zhou7c0ecda2016-04-01 17:05:30 +0800433 vram_gtt.vram_size -= adev->vram_pin_size;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400434 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
Chunming Zhoue131b912016-04-05 10:48:48 +0800435 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400436 vram_gtt.gtt_size = adev->mc.gtt_size;
437 vram_gtt.gtt_size -= adev->gart_pin_size;
438 return copy_to_user(out, &vram_gtt,
439 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
440 }
Junwei Zhange0adf6c2016-09-29 09:39:10 +0800441 case AMDGPU_INFO_MEMORY: {
442 struct drm_amdgpu_memory_info mem;
Junwei Zhang9f6163e2016-09-21 10:17:22 +0800443
Junwei Zhange0adf6c2016-09-29 09:39:10 +0800444 memset(&mem, 0, sizeof(mem));
445 mem.vram.total_heap_size = adev->mc.real_vram_size;
446 mem.vram.usable_heap_size =
447 adev->mc.real_vram_size - adev->vram_pin_size;
448 mem.vram.heap_usage = atomic64_read(&adev->vram_usage);
449 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
Junwei Zhangcfa32552016-09-21 10:33:26 +0800450
Junwei Zhange0adf6c2016-09-29 09:39:10 +0800451 mem.cpu_accessible_vram.total_heap_size =
452 adev->mc.visible_vram_size;
453 mem.cpu_accessible_vram.usable_heap_size =
454 adev->mc.visible_vram_size -
455 (adev->vram_pin_size - adev->invisible_pin_size);
456 mem.cpu_accessible_vram.heap_usage =
457 atomic64_read(&adev->vram_vis_usage);
458 mem.cpu_accessible_vram.max_allocation =
459 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
Junwei Zhangcfa32552016-09-21 10:33:26 +0800460
Junwei Zhange0adf6c2016-09-29 09:39:10 +0800461 mem.gtt.total_heap_size = adev->mc.gtt_size;
462 mem.gtt.usable_heap_size =
463 adev->mc.gtt_size - adev->gart_pin_size;
464 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage);
465 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
Junwei Zhangcfa32552016-09-21 10:33:26 +0800466
Junwei Zhange0adf6c2016-09-29 09:39:10 +0800467 return copy_to_user(out, &mem,
468 min((size_t)size, sizeof(mem)))
Junwei Zhangcfa32552016-09-21 10:33:26 +0800469 ? -EFAULT : 0;
470 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400471 case AMDGPU_INFO_READ_MMR_REG: {
Dan Carpenter0d2edd32015-09-23 14:00:12 +0300472 unsigned n, alloc_size;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400473 uint32_t *regs;
474 unsigned se_num = (info->read_mmr_reg.instance >>
475 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
476 AMDGPU_INFO_MMR_SE_INDEX_MASK;
477 unsigned sh_num = (info->read_mmr_reg.instance >>
478 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
479 AMDGPU_INFO_MMR_SH_INDEX_MASK;
480
481 /* set full masks if the userspace set all bits
482 * in the bitfields */
483 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
484 se_num = 0xffffffff;
485 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
486 sh_num = 0xffffffff;
487
Dan Carpenter0d2edd32015-09-23 14:00:12 +0300488 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400489 if (!regs)
490 return -ENOMEM;
Dan Carpenter0d2edd32015-09-23 14:00:12 +0300491 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400492
493 for (i = 0; i < info->read_mmr_reg.count; i++)
494 if (amdgpu_asic_read_register(adev, se_num, sh_num,
495 info->read_mmr_reg.dword_offset + i,
496 &regs[i])) {
497 DRM_DEBUG_KMS("unallowed offset %#x\n",
498 info->read_mmr_reg.dword_offset + i);
499 kfree(regs);
500 return -EFAULT;
501 }
502 n = copy_to_user(out, regs, min(size, alloc_size));
503 kfree(regs);
504 return n ? -EFAULT : 0;
505 }
506 case AMDGPU_INFO_DEV_INFO: {
Dan Carpenterc193fa912015-07-28 18:51:29 +0300507 struct drm_amdgpu_info_device dev_info = {};
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400508
509 dev_info.device_id = dev->pdev->device;
510 dev_info.chip_rev = adev->rev_id;
511 dev_info.external_rev = adev->external_rev_id;
512 dev_info.pci_rev = dev->pdev->revision;
513 dev_info.family = adev->family;
514 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
515 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
516 /* return all clocks in KHz */
517 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
Ken Wang32bf7102015-06-03 17:36:54 +0800518 if (adev->pm.dpm_enabled) {
Evan Quan1304f0c2016-10-17 09:49:29 +0800519 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
520 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
Ken Wang32bf7102015-06-03 17:36:54 +0800521 } else {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400522 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
Ken Wang32bf7102015-06-03 17:36:54 +0800523 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
524 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400525 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
Alex Deucher0b100292016-06-17 10:17:17 -0400526 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
527 adev->gfx.config.max_shader_engines;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400528 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
529 dev_info._pad = 0;
530 dev_info.ids_flags = 0;
Jammy Zhou2f7d10b2015-07-22 11:29:01 +0800531 if (adev->flags & AMD_IS_APU)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400532 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
Monk Liuaafcafa2016-10-24 11:36:17 +0800533 if (amdgpu_sriov_vf(adev))
534 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400535 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
Jammy Zhou02b70c82015-05-12 22:46:45 +0800536 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
Christian Königc548b342015-08-07 20:22:40 +0200537 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400538 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
539 AMDGPU_GPU_PAGE_SIZE;
540 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
541
Alex Deucher7dae69a2016-05-03 16:25:53 -0400542 dev_info.cu_active_number = adev->gfx.cu_info.number;
543 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
Ken Wanga101a892015-06-03 17:47:54 +0800544 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
Alex Deucher7dae69a2016-05-03 16:25:53 -0400545 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
546 sizeof(adev->gfx.cu_info.bitmap));
Ken Wang81c59f52015-06-03 21:02:01 +0800547 dev_info.vram_type = adev->mc.vram_type;
548 dev_info.vram_bit_width = adev->mc.vram_width;
Leo Liufa927542015-07-13 12:46:23 -0400549 dev_info.vce_harvest_config = adev->vce.harvest_config;
Junwei Zhangdf6e2c42017-02-17 11:05:49 +0800550 dev_info.gc_double_offchip_lds_buf =
551 adev->gfx.config.double_offchip_lds_buf;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400552
Alex Deucherbce23e02017-03-28 12:52:08 -0400553 if (amdgpu_ngg) {
554 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[PRIM].gpu_addr;
555 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[POS].gpu_addr;
556 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[CNTL].gpu_addr;
557 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[PARAM].gpu_addr;
558 }
559
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400560 return copy_to_user(out, &dev_info,
561 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
562 }
Alex Deucher07fecde2016-10-07 12:22:02 -0400563 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
564 unsigned i;
565 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
566 struct amd_vce_state *vce_state;
567
568 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
569 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
570 if (vce_state) {
571 vce_clk_table.entries[i].sclk = vce_state->sclk;
572 vce_clk_table.entries[i].mclk = vce_state->mclk;
573 vce_clk_table.entries[i].eclk = vce_state->evclk;
574 vce_clk_table.num_valid_entries++;
575 }
576 }
577
578 return copy_to_user(out, &vce_clk_table,
579 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
580 }
Evan Quan40ee5882016-12-07 10:05:09 +0800581 case AMDGPU_INFO_VBIOS: {
582 uint32_t bios_size = adev->bios_size;
583
584 switch (info->vbios_info.type) {
585 case AMDGPU_INFO_VBIOS_SIZE:
586 return copy_to_user(out, &bios_size,
587 min((size_t)size, sizeof(bios_size)))
588 ? -EFAULT : 0;
589 case AMDGPU_INFO_VBIOS_IMAGE: {
590 uint8_t *bios;
591 uint32_t bios_offset = info->vbios_info.offset;
592
593 if (bios_offset >= bios_size)
594 return -EINVAL;
595
596 bios = adev->bios + bios_offset;
597 return copy_to_user(out, bios,
598 min((size_t)size, (size_t)(bios_size - bios_offset)))
599 ? -EFAULT : 0;
600 }
601 default:
602 DRM_DEBUG_KMS("Invalid request %d\n",
603 info->vbios_info.type);
604 return -EINVAL;
605 }
606 }
Arindam Nath44879b62016-12-12 15:29:33 +0530607 case AMDGPU_INFO_NUM_HANDLES: {
608 struct drm_amdgpu_info_num_handles handle;
609
610 switch (info->query_hw_ip.type) {
611 case AMDGPU_HW_IP_UVD:
612 /* Starting Polaris, we support unlimited UVD handles */
613 if (adev->asic_type < CHIP_POLARIS10) {
614 handle.uvd_max_handles = adev->uvd.max_handles;
615 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
616
617 return copy_to_user(out, &handle,
618 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
619 } else {
620 return -ENODATA;
621 }
622
623 break;
624 default:
625 return -EINVAL;
626 }
627 }
Alex Deucher5ebbac42017-03-08 18:25:15 -0500628 case AMDGPU_INFO_SENSOR: {
629 struct pp_gpu_power query = {0};
630 int query_size = sizeof(query);
631
632 if (amdgpu_dpm == 0)
633 return -ENOENT;
634
635 switch (info->sensor_info.type) {
636 case AMDGPU_INFO_SENSOR_GFX_SCLK:
637 /* get sclk in Mhz */
638 if (amdgpu_dpm_read_sensor(adev,
639 AMDGPU_PP_SENSOR_GFX_SCLK,
640 (void *)&ui32, &ui32_size)) {
641 return -EINVAL;
642 }
643 ui32 /= 100;
644 break;
645 case AMDGPU_INFO_SENSOR_GFX_MCLK:
646 /* get mclk in Mhz */
647 if (amdgpu_dpm_read_sensor(adev,
648 AMDGPU_PP_SENSOR_GFX_MCLK,
649 (void *)&ui32, &ui32_size)) {
650 return -EINVAL;
651 }
652 ui32 /= 100;
653 break;
654 case AMDGPU_INFO_SENSOR_GPU_TEMP:
655 /* get temperature in millidegrees C */
656 if (amdgpu_dpm_read_sensor(adev,
657 AMDGPU_PP_SENSOR_GPU_TEMP,
658 (void *)&ui32, &ui32_size)) {
659 return -EINVAL;
660 }
661 break;
662 case AMDGPU_INFO_SENSOR_GPU_LOAD:
663 /* get GPU load */
664 if (amdgpu_dpm_read_sensor(adev,
665 AMDGPU_PP_SENSOR_GPU_LOAD,
666 (void *)&ui32, &ui32_size)) {
667 return -EINVAL;
668 }
669 break;
670 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
671 /* get average GPU power */
672 if (amdgpu_dpm_read_sensor(adev,
673 AMDGPU_PP_SENSOR_GPU_POWER,
674 (void *)&query, &query_size)) {
675 return -EINVAL;
676 }
677 ui32 = query.average_gpu_power >> 8;
678 break;
679 case AMDGPU_INFO_SENSOR_VDDNB:
680 /* get VDDNB in millivolts */
681 if (amdgpu_dpm_read_sensor(adev,
682 AMDGPU_PP_SENSOR_VDDNB,
683 (void *)&ui32, &ui32_size)) {
684 return -EINVAL;
685 }
686 break;
687 case AMDGPU_INFO_SENSOR_VDDGFX:
688 /* get VDDGFX in millivolts */
689 if (amdgpu_dpm_read_sensor(adev,
690 AMDGPU_PP_SENSOR_VDDGFX,
691 (void *)&ui32, &ui32_size)) {
692 return -EINVAL;
693 }
694 break;
695 default:
696 DRM_DEBUG_KMS("Invalid request %d\n",
697 info->sensor_info.type);
698 return -EINVAL;
699 }
700 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
701 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400702 default:
703 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
704 return -EINVAL;
705 }
706 return 0;
707}
708
709
710/*
711 * Outdated mess for old drm with Xorg being in charge (void function now).
712 */
713/**
Alex Deucher8b7530b2015-10-02 16:59:34 -0400714 * amdgpu_driver_lastclose_kms - drm callback for last close
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400715 *
716 * @dev: drm dev pointer
717 *
Lukas Wunner16944672015-09-05 11:17:35 +0200718 * Switch vga_switcheroo state after last close (all asics).
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400719 */
720void amdgpu_driver_lastclose_kms(struct drm_device *dev)
721{
Alex Deucher8b7530b2015-10-02 16:59:34 -0400722 struct amdgpu_device *adev = dev->dev_private;
723
724 amdgpu_fbdev_restore_mode(adev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400725 vga_switcheroo_process_delayed_switch();
726}
727
728/**
729 * amdgpu_driver_open_kms - drm callback for open
730 *
731 * @dev: drm dev pointer
732 * @file_priv: drm file
733 *
734 * On device open, init vm on cayman+ (all asics).
735 * Returns 0 on success, error on failure.
736 */
737int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
738{
739 struct amdgpu_device *adev = dev->dev_private;
740 struct amdgpu_fpriv *fpriv;
741 int r;
742
743 file_priv->driver_priv = NULL;
744
745 r = pm_runtime_get_sync(dev->dev);
746 if (r < 0)
747 return r;
748
749 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
Alex Deucherdc082672016-08-27 12:30:25 -0400750 if (unlikely(!fpriv)) {
751 r = -ENOMEM;
752 goto out_suspend;
753 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400754
755 r = amdgpu_vm_init(adev, &fpriv->vm);
Alex Deucherdc082672016-08-27 12:30:25 -0400756 if (r) {
757 kfree(fpriv);
758 goto out_suspend;
759 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400760
Junwei Zhangb85891b2017-01-16 13:59:01 +0800761 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
762 if (!fpriv->prt_va) {
763 r = -ENOMEM;
764 amdgpu_vm_fini(adev, &fpriv->vm);
765 kfree(fpriv);
766 goto out_suspend;
767 }
768
Monk Liu24936642017-01-09 15:54:32 +0800769 if (amdgpu_sriov_vf(adev)) {
770 r = amdgpu_map_static_csa(adev, &fpriv->vm);
771 if (r)
772 goto out_suspend;
773 }
774
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400775 mutex_init(&fpriv->bo_list_lock);
776 idr_init(&fpriv->bo_list_handles);
777
Christian Königefd4ccb2015-08-04 16:20:31 +0200778 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400779
780 file_priv->driver_priv = fpriv;
781
Alex Deucherdc082672016-08-27 12:30:25 -0400782out_suspend:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400783 pm_runtime_mark_last_busy(dev->dev);
784 pm_runtime_put_autosuspend(dev->dev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400785
786 return r;
787}
788
789/**
790 * amdgpu_driver_postclose_kms - drm callback for post close
791 *
792 * @dev: drm dev pointer
793 * @file_priv: drm file
794 *
795 * On device post close, tear down vm on cayman+ (all asics).
796 */
797void amdgpu_driver_postclose_kms(struct drm_device *dev,
798 struct drm_file *file_priv)
799{
800 struct amdgpu_device *adev = dev->dev_private;
801 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
802 struct amdgpu_bo_list *list;
803 int handle;
804
805 if (!fpriv)
806 return;
807
Daniel Vetter04e30c92017-03-08 15:12:52 +0100808 pm_runtime_get_sync(dev->dev);
809
Christian König02537d62015-08-25 15:05:20 +0200810 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
811
Leo Liucd437e32016-07-22 14:13:11 -0400812 amdgpu_uvd_free_handles(adev, file_priv);
813 amdgpu_vce_free_handles(adev, file_priv);
814
Junwei Zhangb85891b2017-01-16 13:59:01 +0800815 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
816
Monk Liu24936642017-01-09 15:54:32 +0800817 if (amdgpu_sriov_vf(adev)) {
818 /* TODO: how to handle reserve failure */
819 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
820 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
821 fpriv->vm.csa_bo_va = NULL;
822 amdgpu_bo_unreserve(adev->virt.csa_obj);
823 }
824
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400825 amdgpu_vm_fini(adev, &fpriv->vm);
826
827 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
828 amdgpu_bo_list_free(list);
829
830 idr_destroy(&fpriv->bo_list_handles);
831 mutex_destroy(&fpriv->bo_list_lock);
832
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400833 kfree(fpriv);
834 file_priv->driver_priv = NULL;
Alex Deucherd6bda7b2016-08-27 12:27:24 -0400835
836 pm_runtime_mark_last_busy(dev->dev);
837 pm_runtime_put_autosuspend(dev->dev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400838}
839
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400840/*
841 * VBlank related functions.
842 */
843/**
844 * amdgpu_get_vblank_counter_kms - get frame count
845 *
846 * @dev: drm dev pointer
Thierry Reding88e72712015-09-24 18:35:31 +0200847 * @pipe: crtc to get the frame count from
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400848 *
849 * Gets the frame count on the requested crtc (all asics).
850 * Returns frame count on success, -EINVAL on failure.
851 */
Thierry Reding88e72712015-09-24 18:35:31 +0200852u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400853{
854 struct amdgpu_device *adev = dev->dev_private;
Alex Deucher8e36f9d2015-12-03 12:31:56 -0500855 int vpos, hpos, stat;
856 u32 count;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400857
Thierry Reding88e72712015-09-24 18:35:31 +0200858 if (pipe >= adev->mode_info.num_crtc) {
859 DRM_ERROR("Invalid crtc %u\n", pipe);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400860 return -EINVAL;
861 }
862
Alex Deucher8e36f9d2015-12-03 12:31:56 -0500863 /* The hw increments its frame counter at start of vsync, not at start
864 * of vblank, as is required by DRM core vblank counter handling.
865 * Cook the hw count here to make it appear to the caller as if it
866 * incremented at start of vblank. We measure distance to start of
867 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
868 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
869 * result by 1 to give the proper appearance to caller.
870 */
871 if (adev->mode_info.crtcs[pipe]) {
872 /* Repeat readout if needed to provide stable result if
873 * we cross start of vsync during the queries.
874 */
875 do {
876 count = amdgpu_display_vblank_get_counter(adev, pipe);
877 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
878 * distance to start of vblank, instead of regular
879 * vertical scanout pos.
880 */
881 stat = amdgpu_get_crtc_scanoutpos(
882 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
883 &vpos, &hpos, NULL, NULL,
884 &adev->mode_info.crtcs[pipe]->base.hwmode);
885 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
886
887 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
888 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
889 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
890 } else {
891 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
892 pipe, vpos);
893
894 /* Bump counter if we are at >= leading edge of vblank,
895 * but before vsync where vpos would turn negative and
896 * the hw counter really increments.
897 */
898 if (vpos >= 0)
899 count++;
900 }
901 } else {
902 /* Fallback to use value as is. */
903 count = amdgpu_display_vblank_get_counter(adev, pipe);
904 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
905 }
906
907 return count;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400908}
909
910/**
911 * amdgpu_enable_vblank_kms - enable vblank interrupt
912 *
913 * @dev: drm dev pointer
Thierry Reding88e72712015-09-24 18:35:31 +0200914 * @pipe: crtc to enable vblank interrupt for
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400915 *
916 * Enable the interrupt on the requested crtc (all asics).
917 * Returns 0 on success, -EINVAL on failure.
918 */
Thierry Reding88e72712015-09-24 18:35:31 +0200919int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400920{
921 struct amdgpu_device *adev = dev->dev_private;
Thierry Reding88e72712015-09-24 18:35:31 +0200922 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400923
924 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
925}
926
927/**
928 * amdgpu_disable_vblank_kms - disable vblank interrupt
929 *
930 * @dev: drm dev pointer
Thierry Reding88e72712015-09-24 18:35:31 +0200931 * @pipe: crtc to disable vblank interrupt for
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400932 *
933 * Disable the interrupt on the requested crtc (all asics).
934 */
Thierry Reding88e72712015-09-24 18:35:31 +0200935void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400936{
937 struct amdgpu_device *adev = dev->dev_private;
Thierry Reding88e72712015-09-24 18:35:31 +0200938 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400939
940 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
941}
942
943/**
944 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
945 *
946 * @dev: drm dev pointer
947 * @crtc: crtc to get the timestamp for
948 * @max_error: max error
949 * @vblank_time: time value
950 * @flags: flags passed to the driver
951 *
952 * Gets the timestamp on the requested crtc based on the
953 * scanout position. (all asics).
954 * Returns postive status flags on success, negative error on failure.
955 */
Thierry Reding88e72712015-09-24 18:35:31 +0200956int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400957 int *max_error,
958 struct timeval *vblank_time,
959 unsigned flags)
960{
Thierry Reding88e72712015-09-24 18:35:31 +0200961 struct drm_crtc *crtc;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400962 struct amdgpu_device *adev = dev->dev_private;
963
Thierry Reding88e72712015-09-24 18:35:31 +0200964 if (pipe >= dev->num_crtcs) {
965 DRM_ERROR("Invalid crtc %u\n", pipe);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400966 return -EINVAL;
967 }
968
969 /* Get associated drm_crtc: */
Thierry Reding88e72712015-09-24 18:35:31 +0200970 crtc = &adev->mode_info.crtcs[pipe]->base;
Harry Wentland9ddf9402015-11-25 15:42:09 -0500971 if (!crtc) {
972 /* This can occur on driver load if some component fails to
973 * initialize completely and driver is unloaded */
974 DRM_ERROR("Uninitialized crtc %d\n", pipe);
975 return -EINVAL;
976 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400977
978 /* Helper routine in DRM core does all the work: */
Thierry Reding88e72712015-09-24 18:35:31 +0200979 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400980 vblank_time, flags,
Thierry Reding88e72712015-09-24 18:35:31 +0200981 &crtc->hwmode);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400982}
983
984const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
Daniel Vetterf8c47142015-09-08 13:56:30 +0200985 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
986 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
987 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400988 /* KMS */
Daniel Vetterf8c47142015-09-08 13:56:30 +0200989 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
990 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
991 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
992 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
993 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
Junwei Zhangeef18a82016-11-04 16:16:10 -0400994 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
Daniel Vetterf8c47142015-09-08 13:56:30 +0200995 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
997 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
998 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400999};
Nils Wallméniusf498d9e2016-04-10 16:29:59 +02001000const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
Huang Rui50ab2532016-06-12 15:51:09 +08001001
1002/*
1003 * Debugfs info
1004 */
1005#if defined(CONFIG_DEBUG_FS)
1006
1007static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1008{
1009 struct drm_info_node *node = (struct drm_info_node *) m->private;
1010 struct drm_device *dev = node->minor->dev;
1011 struct amdgpu_device *adev = dev->dev_private;
1012 struct drm_amdgpu_info_firmware fw_info;
1013 struct drm_amdgpu_query_fw query_fw;
1014 int ret, i;
1015
1016 /* VCE */
1017 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1018 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1019 if (ret)
1020 return ret;
1021 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1022 fw_info.feature, fw_info.ver);
1023
1024 /* UVD */
1025 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1026 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1027 if (ret)
1028 return ret;
1029 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1030 fw_info.feature, fw_info.ver);
1031
1032 /* GMC */
1033 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1034 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1035 if (ret)
1036 return ret;
1037 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1038 fw_info.feature, fw_info.ver);
1039
1040 /* ME */
1041 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1042 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1043 if (ret)
1044 return ret;
1045 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1046 fw_info.feature, fw_info.ver);
1047
1048 /* PFP */
1049 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1050 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1051 if (ret)
1052 return ret;
1053 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1054 fw_info.feature, fw_info.ver);
1055
1056 /* CE */
1057 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1058 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1059 if (ret)
1060 return ret;
1061 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1062 fw_info.feature, fw_info.ver);
1063
1064 /* RLC */
1065 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1066 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1067 if (ret)
1068 return ret;
1069 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1070 fw_info.feature, fw_info.ver);
1071
1072 /* MEC */
1073 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1074 query_fw.index = 0;
1075 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1076 if (ret)
1077 return ret;
1078 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1079 fw_info.feature, fw_info.ver);
1080
1081 /* MEC2 */
1082 if (adev->asic_type == CHIP_KAVERI ||
1083 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1084 query_fw.index = 1;
1085 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1086 if (ret)
1087 return ret;
1088 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1089 fw_info.feature, fw_info.ver);
1090 }
1091
Huang Rui6a7ed072017-03-03 19:15:26 -05001092 /* PSP SOS */
1093 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1094 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1095 if (ret)
1096 return ret;
1097 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1098 fw_info.feature, fw_info.ver);
1099
1100
1101 /* PSP ASD */
1102 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1103 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1104 if (ret)
1105 return ret;
1106 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1107 fw_info.feature, fw_info.ver);
1108
Huang Rui50ab2532016-06-12 15:51:09 +08001109 /* SMC */
1110 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1111 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1112 if (ret)
1113 return ret;
1114 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1115 fw_info.feature, fw_info.ver);
1116
1117 /* SDMA */
1118 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1119 for (i = 0; i < adev->sdma.num_instances; i++) {
1120 query_fw.index = i;
1121 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1122 if (ret)
1123 return ret;
1124 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1125 i, fw_info.feature, fw_info.ver);
1126 }
1127
1128 return 0;
1129}
1130
1131static const struct drm_info_list amdgpu_firmware_info_list[] = {
1132 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1133};
1134#endif
1135
1136int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1137{
1138#if defined(CONFIG_DEBUG_FS)
1139 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1140 ARRAY_SIZE(amdgpu_firmware_info_list));
1141#else
1142 return 0;
1143#endif
1144}