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Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
29#include <drm/radeon_drm.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020030#include "radeon.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031
32/*
Alex Deucher03eec932012-07-17 14:02:39 -040033 * GART
34 * The GART (Graphics Aperture Remapping Table) is an aperture
35 * in the GPU's address space. System pages can be mapped into
36 * the aperture and look like contiguous pages from the GPU's
37 * perspective. A page table maps the pages in the aperture
38 * to the actual backing pages in system memory.
39 *
40 * Radeon GPUs support both an internal GART, as described above,
41 * and AGP. AGP works similarly, but the GART table is configured
42 * and maintained by the northbridge rather than the driver.
43 * Radeon hw has a separate AGP aperture that is programmed to
44 * point to the AGP aperture provided by the northbridge and the
45 * requests are passed through to the northbridge aperture.
46 * Both AGP and internal GART can be used at the same time, however
47 * that is not currently supported by the driver.
48 *
49 * This file handles the common internal GART management.
50 */
51
52/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +020053 * Common GART table functions.
54 */
Alex Deucher03eec932012-07-17 14:02:39 -040055/**
56 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
57 *
58 * @rdev: radeon_device pointer
59 *
60 * Allocate system memory for GART page table
61 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
62 * gart table to be in system memory.
63 * Returns 0 for success, -ENOMEM for failure.
64 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020065int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
66{
67 void *ptr;
68
69 ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
70 &rdev->gart.table_addr);
71 if (ptr == NULL) {
72 return -ENOMEM;
73 }
74#ifdef CONFIG_X86
75 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
76 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
77 set_memory_uc((unsigned long)ptr,
78 rdev->gart.table_size >> PAGE_SHIFT);
79 }
80#endif
Jerome Glissec9a1be92011-11-03 11:16:49 -040081 rdev->gart.ptr = ptr;
82 memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020083 return 0;
84}
85
Alex Deucher03eec932012-07-17 14:02:39 -040086/**
87 * radeon_gart_table_ram_free - free system ram for gart page table
88 *
89 * @rdev: radeon_device pointer
90 *
91 * Free system memory for GART page table
92 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
93 * gart table to be in system memory.
94 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020095void radeon_gart_table_ram_free(struct radeon_device *rdev)
96{
Jerome Glissec9a1be92011-11-03 11:16:49 -040097 if (rdev->gart.ptr == NULL) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +020098 return;
99 }
100#ifdef CONFIG_X86
101 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
102 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
Jerome Glissec9a1be92011-11-03 11:16:49 -0400103 set_memory_wb((unsigned long)rdev->gart.ptr,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200104 rdev->gart.table_size >> PAGE_SHIFT);
105 }
106#endif
107 pci_free_consistent(rdev->pdev, rdev->gart.table_size,
Jerome Glissec9a1be92011-11-03 11:16:49 -0400108 (void *)rdev->gart.ptr,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200109 rdev->gart.table_addr);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400110 rdev->gart.ptr = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200111 rdev->gart.table_addr = 0;
112}
113
Alex Deucher03eec932012-07-17 14:02:39 -0400114/**
115 * radeon_gart_table_vram_alloc - allocate vram for gart page table
116 *
117 * @rdev: radeon_device pointer
118 *
119 * Allocate video memory for GART page table
120 * (pcie r4xx, r5xx+). These asics require the
121 * gart table to be in video memory.
122 * Returns 0 for success, error for failure.
123 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200124int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
125{
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200126 int r;
127
Jerome Glissec9a1be92011-11-03 11:16:49 -0400128 if (rdev->gart.robj == NULL) {
Daniel Vetter441921d2011-02-18 17:59:16 +0100129 r = radeon_bo_create(rdev, rdev->gart.table_size,
Alex Deucher268b2512010-11-17 19:00:26 -0500130 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
Maarten Lankhorst831b6962014-09-18 14:11:56 +0200131 0, NULL, NULL, &rdev->gart.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200132 if (r) {
133 return r;
134 }
135 }
Jerome Glisse4aac0472009-09-14 18:29:49 +0200136 return 0;
137}
138
Alex Deucher03eec932012-07-17 14:02:39 -0400139/**
140 * radeon_gart_table_vram_pin - pin gart page table in vram
141 *
142 * @rdev: radeon_device pointer
143 *
144 * Pin the GART page table in vram so it will not be moved
145 * by the memory manager (pcie r4xx, r5xx+). These asics require the
146 * gart table to be in video memory.
147 * Returns 0 for success, error for failure.
148 */
Jerome Glisse4aac0472009-09-14 18:29:49 +0200149int radeon_gart_table_vram_pin(struct radeon_device *rdev)
150{
151 uint64_t gpu_addr;
152 int r;
153
Jerome Glissec9a1be92011-11-03 11:16:49 -0400154 r = radeon_bo_reserve(rdev->gart.robj, false);
Jerome Glisse4c788672009-11-20 14:29:23 +0100155 if (unlikely(r != 0))
156 return r;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400157 r = radeon_bo_pin(rdev->gart.robj,
Jerome Glisse4c788672009-11-20 14:29:23 +0100158 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159 if (r) {
Jerome Glissec9a1be92011-11-03 11:16:49 -0400160 radeon_bo_unreserve(rdev->gart.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200161 return r;
162 }
Jerome Glissec9a1be92011-11-03 11:16:49 -0400163 r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
Jerome Glisse4c788672009-11-20 14:29:23 +0100164 if (r)
Jerome Glissec9a1be92011-11-03 11:16:49 -0400165 radeon_bo_unpin(rdev->gart.robj);
166 radeon_bo_unreserve(rdev->gart.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200167 rdev->gart.table_addr = gpu_addr;
Jerome Glisse4c788672009-11-20 14:29:23 +0100168 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200169}
170
Alex Deucher03eec932012-07-17 14:02:39 -0400171/**
172 * radeon_gart_table_vram_unpin - unpin gart page table in vram
173 *
174 * @rdev: radeon_device pointer
175 *
176 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
177 * These asics require the gart table to be in video memory.
178 */
Jerome Glissec9a1be92011-11-03 11:16:49 -0400179void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200180{
Jerome Glisse4c788672009-11-20 14:29:23 +0100181 int r;
182
Jerome Glissec9a1be92011-11-03 11:16:49 -0400183 if (rdev->gart.robj == NULL) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200184 return;
185 }
Jerome Glissec9a1be92011-11-03 11:16:49 -0400186 r = radeon_bo_reserve(rdev->gart.robj, false);
Jerome Glisse4c788672009-11-20 14:29:23 +0100187 if (likely(r == 0)) {
Jerome Glissec9a1be92011-11-03 11:16:49 -0400188 radeon_bo_kunmap(rdev->gart.robj);
189 radeon_bo_unpin(rdev->gart.robj);
190 radeon_bo_unreserve(rdev->gart.robj);
191 rdev->gart.ptr = NULL;
Jerome Glisse4c788672009-11-20 14:29:23 +0100192 }
Jerome Glissec9a1be92011-11-03 11:16:49 -0400193}
194
Alex Deucher03eec932012-07-17 14:02:39 -0400195/**
196 * radeon_gart_table_vram_free - free gart page table vram
197 *
198 * @rdev: radeon_device pointer
199 *
200 * Free the video memory used for the GART page table
201 * (pcie r4xx, r5xx+). These asics require the gart table to
202 * be in video memory.
203 */
Jerome Glissec9a1be92011-11-03 11:16:49 -0400204void radeon_gart_table_vram_free(struct radeon_device *rdev)
205{
206 if (rdev->gart.robj == NULL) {
207 return;
208 }
Jerome Glissec9a1be92011-11-03 11:16:49 -0400209 radeon_bo_unref(&rdev->gart.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200210}
211
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200212/*
213 * Common gart functions.
214 */
Alex Deucher03eec932012-07-17 14:02:39 -0400215/**
216 * radeon_gart_unbind - unbind pages from the gart page table
217 *
218 * @rdev: radeon_device pointer
219 * @offset: offset into the GPU's gart aperture
220 * @pages: number of pages to unbind
221 *
222 * Unbinds the requested pages from the gart page table and
223 * replaces them with the dummy page (all asics).
224 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200225void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
226 int pages)
227{
228 unsigned t;
229 unsigned p;
230 int i, j;
231
232 if (!rdev->gart.ready) {
Tormod Voldenfcf4de52011-08-31 21:54:07 +0000233 WARN(1, "trying to unbind memory from uninitialized GART !\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200234 return;
235 }
Matt Turnera77f1712009-10-14 00:34:41 -0400236 t = offset / RADEON_GPU_PAGE_SIZE;
237 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200238 for (i = 0; i < pages; i++, p++) {
239 if (rdev->gart.pages[p]) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200240 rdev->gart.pages[p] = NULL;
Dave Airlie82568562010-02-05 16:00:07 +1000241 rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
Matt Turnera77f1712009-10-14 00:34:41 -0400242 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
Michel Dänzercb658902015-01-21 17:36:35 +0900243 rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400244 if (rdev->gart.ptr) {
Michel Dänzercb658902015-01-21 17:36:35 +0900245 radeon_gart_set_page(rdev, t,
246 rdev->dummy_page.entry);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400247 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200248 }
249 }
250 }
251 mb();
252 radeon_gart_tlb_flush(rdev);
253}
254
Alex Deucher03eec932012-07-17 14:02:39 -0400255/**
256 * radeon_gart_bind - bind pages into the gart page table
257 *
258 * @rdev: radeon_device pointer
259 * @offset: offset into the GPU's gart aperture
260 * @pages: number of pages to bind
261 * @pagelist: pages to bind
262 * @dma_addr: DMA addresses of pages
Michel Dänzer77497f22014-07-17 19:01:07 +0900263 * @flags: RADEON_GART_PAGE_* flags
Alex Deucher03eec932012-07-17 14:02:39 -0400264 *
265 * Binds the requested pages to the gart page table
266 * (all asics).
267 * Returns 0 for success, -EINVAL for failure.
268 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200269int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
Michel Dänzer77497f22014-07-17 19:01:07 +0900270 int pages, struct page **pagelist, dma_addr_t *dma_addr,
271 uint32_t flags)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200272{
273 unsigned t;
274 unsigned p;
Michel Dänzercb658902015-01-21 17:36:35 +0900275 uint64_t page_base, page_entry;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200276 int i, j;
277
278 if (!rdev->gart.ready) {
Tormod Voldenfcf4de52011-08-31 21:54:07 +0000279 WARN(1, "trying to bind memory to uninitialized GART !\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200280 return -EINVAL;
281 }
Matt Turnera77f1712009-10-14 00:34:41 -0400282 t = offset / RADEON_GPU_PAGE_SIZE;
283 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200284
285 for (i = 0; i < pages; i++, p++) {
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -0400286 rdev->gart.pages_addr[p] = dma_addr[i];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200287 rdev->gart.pages[p] = pagelist[i];
Michel Dänzercb658902015-01-21 17:36:35 +0900288 page_base = dma_addr[i];
289 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
290 page_entry = radeon_gart_get_page_entry(page_base, flags);
291 rdev->gart.pages_entry[t] = page_entry;
292 if (rdev->gart.ptr) {
293 radeon_gart_set_page(rdev, t, page_entry);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400294 }
Michel Dänzercb658902015-01-21 17:36:35 +0900295 page_base += RADEON_GPU_PAGE_SIZE;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200296 }
297 }
298 mb();
299 radeon_gart_tlb_flush(rdev);
300 return 0;
301}
302
Alex Deucher03eec932012-07-17 14:02:39 -0400303/**
Alex Deucher03eec932012-07-17 14:02:39 -0400304 * radeon_gart_init - init the driver info for managing the gart
305 *
306 * @rdev: radeon_device pointer
307 *
308 * Allocate the dummy page and init the gart driver info (all asics).
309 * Returns 0 for success, error for failure.
310 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200311int radeon_gart_init(struct radeon_device *rdev)
312{
Dave Airlie82568562010-02-05 16:00:07 +1000313 int r, i;
314
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200315 if (rdev->gart.pages) {
316 return 0;
317 }
Matt Turnera77f1712009-10-14 00:34:41 -0400318 /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
319 if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200320 DRM_ERROR("Page size is smaller than GPU page size!\n");
321 return -EINVAL;
322 }
Dave Airlie82568562010-02-05 16:00:07 +1000323 r = radeon_dummy_page_init(rdev);
324 if (r)
325 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200326 /* Compute table size */
327 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
Matt Turnera77f1712009-10-14 00:34:41 -0400328 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200329 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
330 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
331 /* Allocate pages table */
Christian König59240ee2012-10-23 15:53:17 +0200332 rdev->gart.pages = vzalloc(sizeof(void *) * rdev->gart.num_cpu_pages);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200333 if (rdev->gart.pages == NULL) {
334 radeon_gart_fini(rdev);
335 return -ENOMEM;
336 }
Christian König59240ee2012-10-23 15:53:17 +0200337 rdev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) *
338 rdev->gart.num_cpu_pages);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200339 if (rdev->gart.pages_addr == NULL) {
340 radeon_gart_fini(rdev);
341 return -ENOMEM;
342 }
Michel Dänzercb658902015-01-21 17:36:35 +0900343 rdev->gart.pages_entry = vmalloc(sizeof(uint64_t) *
344 rdev->gart.num_gpu_pages);
345 if (rdev->gart.pages_entry == NULL) {
346 radeon_gart_fini(rdev);
347 return -ENOMEM;
Dave Airlie82568562010-02-05 16:00:07 +1000348 }
Michel Dänzercb658902015-01-21 17:36:35 +0900349 /* set GART entry to point to the dummy page by default */
350 for (i = 0; i < rdev->gart.num_cpu_pages; i++)
351 rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
352 for (i = 0; i < rdev->gart.num_gpu_pages; i++)
353 rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200354 return 0;
355}
356
Alex Deucher03eec932012-07-17 14:02:39 -0400357/**
358 * radeon_gart_fini - tear down the driver info for managing the gart
359 *
360 * @rdev: radeon_device pointer
361 *
362 * Tear down the gart driver info and free the dummy page (all asics).
363 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200364void radeon_gart_fini(struct radeon_device *rdev)
365{
Michel Dänzercb658902015-01-21 17:36:35 +0900366 if (rdev->gart.ready) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200367 /* unbind pages */
368 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
369 }
370 rdev->gart.ready = false;
Christian König59240ee2012-10-23 15:53:17 +0200371 vfree(rdev->gart.pages);
372 vfree(rdev->gart.pages_addr);
Michel Dänzercb658902015-01-21 17:36:35 +0900373 vfree(rdev->gart.pages_entry);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200374 rdev->gart.pages = NULL;
375 rdev->gart.pages_addr = NULL;
Michel Dänzercb658902015-01-21 17:36:35 +0900376 rdev->gart.pages_entry = NULL;
Alex Deucher92656d72011-04-12 13:32:13 -0400377
378 radeon_dummy_page_fini(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200379}