blob: 550921f2ef7d5073f73d26481a44ebb1b4bbfb4d [file] [log] [blame]
Alex Dai33a732f2015-08-12 15:43:36 +01001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
28 */
29#include <linux/firmware.h>
30#include "i915_drv.h"
31#include "intel_guc.h"
32
33/**
Alex Daifeda33e2015-10-19 16:10:54 -070034 * DOC: GuC-specific firmware loader
Alex Dai33a732f2015-08-12 15:43:36 +010035 *
36 * intel_guc:
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
40 *
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
46 * of firmware.
47 *
48 * GuC address space:
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
53 *
54 * Firmware log:
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
58 * registers value.
59 *
60 */
61
Alex Daiaa557ab2015-08-18 14:32:35 -070062#define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
Alex Dai33a732f2015-08-12 15:43:36 +010063MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
64
65/* User-friendly representation of an enum */
66const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
67{
68 switch (status) {
69 case GUC_FIRMWARE_FAIL:
70 return "FAIL";
71 case GUC_FIRMWARE_NONE:
72 return "NONE";
73 case GUC_FIRMWARE_PENDING:
74 return "PENDING";
75 case GUC_FIRMWARE_SUCCESS:
76 return "SUCCESS";
77 default:
78 return "UNKNOWN!";
79 }
80};
81
Dave Gordon4df001d2015-08-12 15:43:42 +010082static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
83{
84 struct intel_engine_cs *ring;
85 int i, irqs;
86
87 /* tell all command streamers NOT to forward interrupts and vblank to GuC */
88 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
89 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
90 for_each_ring(ring, dev_priv, i)
91 I915_WRITE(RING_MODE_GEN7(ring), irqs);
92
Dave Gordon4df001d2015-08-12 15:43:42 +010093 /* route all GT interrupts to the host */
94 I915_WRITE(GUC_BCS_RCS_IER, 0);
95 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
96 I915_WRITE(GUC_WD_VECS_IER, 0);
97}
98
99static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
100{
101 struct intel_engine_cs *ring;
102 int i, irqs;
103
104 /* tell all command streamers to forward interrupts and vblank to GuC */
105 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
106 irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
107 for_each_ring(ring, dev_priv, i)
108 I915_WRITE(RING_MODE_GEN7(ring), irqs);
109
Dave Gordon4df001d2015-08-12 15:43:42 +0100110 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
111 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
112 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
113 /* These three registers have the same bit definitions */
114 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
115 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
116 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
117}
118
Alex Dai33a732f2015-08-12 15:43:36 +0100119static u32 get_gttype(struct drm_i915_private *dev_priv)
120{
121 /* XXX: GT type based on PCI device ID? field seems unused by fw */
122 return 0;
123}
124
125static u32 get_core_family(struct drm_i915_private *dev_priv)
126{
127 switch (INTEL_INFO(dev_priv)->gen) {
128 case 9:
129 return GFXCORE_FAMILY_GEN9;
130
131 default:
132 DRM_ERROR("GUC: unsupported core family\n");
133 return GFXCORE_FAMILY_UNKNOWN;
134 }
135}
136
137static void set_guc_init_params(struct drm_i915_private *dev_priv)
138{
139 struct intel_guc *guc = &dev_priv->guc;
140 u32 params[GUC_CTL_MAX_DWORDS];
141 int i;
142
143 memset(&params, 0, sizeof(params));
144
145 params[GUC_CTL_DEVICE_INFO] |=
146 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
147 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
148
149 /*
150 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
151 * second. This ARAR is calculated by:
152 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
153 */
154 params[GUC_CTL_ARAT_HIGH] = 0;
155 params[GUC_CTL_ARAT_LOW] = 100000000;
156
157 params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
158
159 params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
160 GUC_CTL_VCS2_ENABLED;
161
162 if (i915.guc_log_level >= 0) {
163 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
164 params[GUC_CTL_DEBUG] =
165 i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
166 }
167
Alex Daibac427f2015-08-12 15:43:39 +0100168 /* If GuC submission is enabled, set up additional parameters here */
169 if (i915.enable_guc_submission) {
170 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
171 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
172
173 pgs >>= PAGE_SHIFT;
174 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
175 (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
176
177 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
178
179 /* Unmask this bit to enable the GuC's internal scheduler */
180 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
181 }
182
Alex Dai33a732f2015-08-12 15:43:36 +0100183 I915_WRITE(SOFT_SCRATCH(0), 0);
184
185 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
186 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
187}
188
189/*
190 * Read the GuC status register (GUC_STATUS) and store it in the
191 * specified location; then return a boolean indicating whether
192 * the value matches either of two values representing completion
193 * of the GuC boot process.
194 *
195 * This is used for polling the GuC status in a wait_for_atomic()
196 * loop below.
197 */
198static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
199 u32 *status)
200{
201 u32 val = I915_READ(GUC_STATUS);
Alex Dai0d44d3f2015-09-22 13:48:40 -0700202 u32 uk_val = val & GS_UKERNEL_MASK;
Alex Dai33a732f2015-08-12 15:43:36 +0100203 *status = val;
Alex Dai0d44d3f2015-09-22 13:48:40 -0700204 return (uk_val == GS_UKERNEL_READY ||
205 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
Alex Dai33a732f2015-08-12 15:43:36 +0100206}
207
208/*
209 * Transfer the firmware image to RAM for execution by the microcontroller.
210 *
Alex Dai33a732f2015-08-12 15:43:36 +0100211 * Architecturally, the DMA engine is bidirectional, and can potentially even
212 * transfer between GTT locations. This functionality is left out of the API
213 * for now as there is no need for it.
214 *
215 * Note that GuC needs the CSS header plus uKernel code to be copied by the
216 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
217 */
Alex Dai33a732f2015-08-12 15:43:36 +0100218static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
219{
220 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
221 struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
222 unsigned long offset;
223 struct sg_table *sg = fw_obj->pages;
Alex Daifeda33e2015-10-19 16:10:54 -0700224 u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
Alex Dai33a732f2015-08-12 15:43:36 +0100225 int i, ret = 0;
226
Alex Daifeda33e2015-10-19 16:10:54 -0700227 /* where RSA signature starts */
228 offset = guc_fw->rsa_offset;
Alex Dai33a732f2015-08-12 15:43:36 +0100229
230 /* Copy RSA signature from the fw image to HW for verification */
Alex Daifeda33e2015-10-19 16:10:54 -0700231 sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
232 for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
Ville Syrjäläab9cc552015-09-18 20:03:24 +0300233 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
Alex Dai33a732f2015-08-12 15:43:36 +0100234
Alex Daifeda33e2015-10-19 16:10:54 -0700235 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
236 * other components */
237 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
238
Alex Dai33a732f2015-08-12 15:43:36 +0100239 /* Set the source address for the new blob */
Alex Daifeda33e2015-10-19 16:10:54 -0700240 offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset;
Alex Dai33a732f2015-08-12 15:43:36 +0100241 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
242 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
243
244 /*
245 * Set the DMA destination. Current uCode expects the code to be
246 * loaded at 8k; locations below this are used for the stack.
247 */
248 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
249 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
250
251 /* Finally start the DMA */
252 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
253
254 /*
255 * Spin-wait for the DMA to complete & the GuC to start up.
256 * NB: Docs recommend not using the interrupt for completion.
257 * Measurements indicate this should take no more than 20ms, so a
258 * timeout here indicates that the GuC has failed and is unusable.
259 * (Higher levels of the driver will attempt to fall back to
260 * execlist mode if this happens.)
261 */
262 ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
263
264 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
265 I915_READ(DMA_CTRL), status);
266
267 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
268 DRM_ERROR("GuC firmware signature verification failed\n");
269 ret = -ENOEXEC;
270 }
271
272 DRM_DEBUG_DRIVER("returning %d\n", ret);
273
274 return ret;
275}
276
277/*
278 * Load the GuC firmware blob into the MinuteIA.
279 */
280static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
281{
282 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
283 struct drm_device *dev = dev_priv->dev;
284 int ret;
285
286 ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
287 if (ret) {
288 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
289 return ret;
290 }
291
292 ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
293 if (ret) {
294 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
295 return ret;
296 }
297
298 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
299 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
300
301 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
302
303 /* init WOPCM */
304 I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
305 I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
306
307 /* Enable MIA caching. GuC clock gating is disabled. */
308 I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
309
Nick Hoathb970b482015-09-08 10:31:53 +0100310 /* WaDisableMinuteIaClockGating:skl,bxt */
Jani Nikulae87a0052015-10-20 15:22:02 +0300311 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
Tim Gorecbdc12a2015-10-26 10:48:58 +0000312 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
Nick Hoathb970b482015-09-08 10:31:53 +0100313 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
314 ~GUC_ENABLE_MIA_CLOCK_GATING));
315 }
316
Alex Dai33a732f2015-08-12 15:43:36 +0100317 /* WaC6DisallowByGfxPause*/
318 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
319
320 if (IS_BROXTON(dev))
321 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
322 else
323 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
324
325 if (IS_GEN9(dev)) {
326 /* DOP Clock Gating Enable for GuC clocks */
327 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
328 I915_READ(GEN7_MISCCPCTL)));
329
330 /* allows for 5us before GT can go to RC6 */
331 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
332 }
333
334 set_guc_init_params(dev_priv);
335
336 ret = guc_ucode_xfer_dma(dev_priv);
337
338 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
339
340 /*
341 * We keep the object pages for reuse during resume. But we can unpin it
342 * now that DMA has completed, so it doesn't continue to take up space.
343 */
344 i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
345
346 return ret;
347}
348
349/**
350 * intel_guc_ucode_load() - load GuC uCode into the device
351 * @dev: drm device
352 *
353 * Called from gem_init_hw() during driver loading and also after a GPU reset.
354 *
355 * The firmware image should have already been fetched into memory by the
356 * earlier call to intel_guc_ucode_init(), so here we need only check that
357 * is succeeded, and then transfer the image to the h/w.
358 *
359 * Return: non-zero code on error
360 */
361int intel_guc_ucode_load(struct drm_device *dev)
362{
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
365 int err = 0;
366
Daniel Vetter9f9e5392015-10-23 11:10:59 +0200367 if (!i915.enable_guc_submission)
368 return 0;
369
Alex Dai33a732f2015-08-12 15:43:36 +0100370 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
371 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
372 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
373
Dave Gordon4df001d2015-08-12 15:43:42 +0100374 direct_interrupts_to_host(dev_priv);
Dave Gordon44a28b12015-08-12 15:43:41 +0100375
Alex Dai33a732f2015-08-12 15:43:36 +0100376 if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
377 return 0;
378
379 if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
380 guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
381 return -ENOEXEC;
382
383 guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
384
385 DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
386 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
387
388 switch (guc_fw->guc_fw_fetch_status) {
389 case GUC_FIRMWARE_FAIL:
390 /* something went wrong :( */
391 err = -EIO;
392 goto fail;
393
394 case GUC_FIRMWARE_NONE:
395 case GUC_FIRMWARE_PENDING:
396 default:
397 /* "can't happen" */
398 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
399 guc_fw->guc_fw_path,
400 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
401 guc_fw->guc_fw_fetch_status);
402 err = -ENXIO;
403 goto fail;
404
405 case GUC_FIRMWARE_SUCCESS:
406 break;
407 }
408
Alex Daibac427f2015-08-12 15:43:39 +0100409 err = i915_guc_submission_init(dev);
410 if (err)
411 goto fail;
412
Alex Dai33a732f2015-08-12 15:43:36 +0100413 err = guc_ucode_xfer(dev_priv);
414 if (err)
415 goto fail;
416
417 guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
418
419 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
420 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
421 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
422
Dave Gordon44a28b12015-08-12 15:43:41 +0100423 if (i915.enable_guc_submission) {
Alex Daia1c41992015-09-30 09:46:37 -0700424 /* The execbuf_client will be recreated. Release it first. */
425 i915_guc_submission_disable(dev);
426
Dave Gordon44a28b12015-08-12 15:43:41 +0100427 err = i915_guc_submission_enable(dev);
428 if (err)
429 goto fail;
Dave Gordon4df001d2015-08-12 15:43:42 +0100430 direct_interrupts_to_guc(dev_priv);
Dave Gordon44a28b12015-08-12 15:43:41 +0100431 }
432
Alex Dai33a732f2015-08-12 15:43:36 +0100433 return 0;
434
435fail:
436 if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
437 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
438
Dave Gordon4df001d2015-08-12 15:43:42 +0100439 direct_interrupts_to_host(dev_priv);
Dave Gordon44a28b12015-08-12 15:43:41 +0100440 i915_guc_submission_disable(dev);
441
Alex Dai33a732f2015-08-12 15:43:36 +0100442 return err;
443}
444
445static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
446{
447 struct drm_i915_gem_object *obj;
448 const struct firmware *fw;
Alex Daifeda33e2015-10-19 16:10:54 -0700449 struct guc_css_header *css;
450 size_t size;
Alex Dai33a732f2015-08-12 15:43:36 +0100451 int err;
452
453 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
454 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
455
456 err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
457 if (err)
458 goto fail;
459 if (!fw)
460 goto fail;
461
462 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
463 guc_fw->guc_fw_path, fw);
Alex Dai33a732f2015-08-12 15:43:36 +0100464
Alex Daifeda33e2015-10-19 16:10:54 -0700465 /* Check the size of the blob before examining buffer contents */
466 if (fw->size < sizeof(struct guc_css_header)) {
467 DRM_ERROR("Firmware header is missing\n");
Alex Dai33a732f2015-08-12 15:43:36 +0100468 goto fail;
Alex Daifeda33e2015-10-19 16:10:54 -0700469 }
470
471 css = (struct guc_css_header *)fw->data;
472
473 /* Firmware bits always start from header */
474 guc_fw->header_offset = 0;
475 guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
476 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
477
478 if (guc_fw->header_size != sizeof(struct guc_css_header)) {
479 DRM_ERROR("CSS header definition mismatch\n");
480 goto fail;
481 }
482
483 /* then, uCode */
484 guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
485 guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
486
487 /* now RSA */
488 if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
489 DRM_ERROR("RSA key size is bad\n");
490 goto fail;
491 }
492 guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
493 guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
494
495 /* At least, it should have header, uCode and RSA. Size of all three. */
496 size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
497 if (fw->size < size) {
498 DRM_ERROR("Missing firmware components\n");
499 goto fail;
500 }
501
502 /* Header and uCode will be loaded to WOPCM. Size of the two. */
503 size = guc_fw->header_size + guc_fw->ucode_size;
504
505 /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
506 if (size > GUC_WOPCM_SIZE_VALUE - 0x8000) {
507 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
508 goto fail;
509 }
Alex Dai33a732f2015-08-12 15:43:36 +0100510
511 /*
512 * The GuC firmware image has the version number embedded at a well-known
513 * offset within the firmware blob; note that major / minor version are
514 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
515 * in terms of bytes (u8).
516 */
Alex Daifeda33e2015-10-19 16:10:54 -0700517 guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
518 guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
Alex Dai33a732f2015-08-12 15:43:36 +0100519
520 if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
521 guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
522 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
523 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
524 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
525 err = -ENOEXEC;
526 goto fail;
527 }
528
529 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
530 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
531 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
532
Daniel Stonebf248ca2015-11-03 21:42:31 +0000533 mutex_lock(&dev->struct_mutex);
Alex Dai33a732f2015-08-12 15:43:36 +0100534 obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
Daniel Stonebf248ca2015-11-03 21:42:31 +0000535 mutex_unlock(&dev->struct_mutex);
Alex Dai33a732f2015-08-12 15:43:36 +0100536 if (IS_ERR_OR_NULL(obj)) {
537 err = obj ? PTR_ERR(obj) : -ENOMEM;
538 goto fail;
539 }
540
541 guc_fw->guc_fw_obj = obj;
542 guc_fw->guc_fw_size = fw->size;
543
544 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
545 guc_fw->guc_fw_obj);
546
547 release_firmware(fw);
548 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
549 return;
550
551fail:
552 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
553 err, fw, guc_fw->guc_fw_obj);
554 DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
555 guc_fw->guc_fw_path, err);
556
557 obj = guc_fw->guc_fw_obj;
558 if (obj)
559 drm_gem_object_unreference(&obj->base);
560 guc_fw->guc_fw_obj = NULL;
561
562 release_firmware(fw); /* OK even if fw is NULL */
563 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
564}
565
566/**
567 * intel_guc_ucode_init() - define parameters and fetch firmware
568 * @dev: drm device
569 *
570 * Called early during driver load, but after GEM is initialised.
Alex Dai33a732f2015-08-12 15:43:36 +0100571 *
572 * The firmware will be transferred to the GuC's memory later,
573 * when intel_guc_ucode_load() is called.
574 */
575void intel_guc_ucode_init(struct drm_device *dev)
576{
577 struct drm_i915_private *dev_priv = dev->dev_private;
578 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
579 const char *fw_path;
580
581 if (!HAS_GUC_SCHED(dev))
582 i915.enable_guc_submission = false;
583
584 if (!HAS_GUC_UCODE(dev)) {
585 fw_path = NULL;
586 } else if (IS_SKYLAKE(dev)) {
587 fw_path = I915_SKL_GUC_UCODE;
Alex Daiaa557ab2015-08-18 14:32:35 -0700588 guc_fw->guc_fw_major_wanted = 4;
589 guc_fw->guc_fw_minor_wanted = 3;
Alex Dai33a732f2015-08-12 15:43:36 +0100590 } else {
591 i915.enable_guc_submission = false;
592 fw_path = ""; /* unknown device */
593 }
594
Daniel Vetter9f9e5392015-10-23 11:10:59 +0200595 if (!i915.enable_guc_submission)
596 return;
597
Alex Dai33a732f2015-08-12 15:43:36 +0100598 guc_fw->guc_dev = dev;
599 guc_fw->guc_fw_path = fw_path;
600 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
601 guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
602
603 if (fw_path == NULL)
604 return;
605
606 if (*fw_path == '\0') {
607 DRM_ERROR("No GuC firmware known for this platform\n");
608 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
609 return;
610 }
611
612 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
613 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
614 guc_fw_fetch(dev, guc_fw);
615 /* status must now be FAIL or SUCCESS */
616}
617
618/**
619 * intel_guc_ucode_fini() - clean up all allocated resources
620 * @dev: drm device
621 */
622void intel_guc_ucode_fini(struct drm_device *dev)
623{
624 struct drm_i915_private *dev_priv = dev->dev_private;
625 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
626
Dave Gordon4df001d2015-08-12 15:43:42 +0100627 direct_interrupts_to_host(dev_priv);
Alex Daibac427f2015-08-12 15:43:39 +0100628 i915_guc_submission_fini(dev);
629
Daniel Stonebf248ca2015-11-03 21:42:31 +0000630 mutex_lock(&dev->struct_mutex);
Alex Dai33a732f2015-08-12 15:43:36 +0100631 if (guc_fw->guc_fw_obj)
632 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
633 guc_fw->guc_fw_obj = NULL;
Daniel Stonebf248ca2015-11-03 21:42:31 +0000634 mutex_unlock(&dev->struct_mutex);
Alex Dai33a732f2015-08-12 15:43:36 +0100635
636 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
637}