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Benoit Cousson189892f2011-08-16 21:02:01 +05301/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard6d624ea2013-05-31 14:32:56 +020011#include <dt-bindings/gpio/gpio.h>
Florian Vaussard71fdc6e2013-06-11 16:49:46 +020012#include <dt-bindings/interrupt-controller/irq.h>
Florian Vaussardbcd3cca2013-05-31 14:32:59 +020013#include <dt-bindings/pinctrl/omap.h>
Florian Vaussard6d624ea2013-05-31 14:32:56 +020014
Florian Vaussard98ef79572013-05-31 14:32:55 +020015#include "skeleton.dtsi"
Benoit Cousson189892f2011-08-16 21:02:01 +053016
17/ {
18 compatible = "ti,omap3430", "ti,omap3";
Benoit Cousson4c94ac22012-10-24 10:47:52 +020019 interrupt-parent = <&intc>;
Benoit Cousson189892f2011-08-16 21:02:01 +053020
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +053021 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -050022 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +053025 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +053028 };
29
Benoit Cousson476b6792011-08-16 11:49:08 +020030 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +010031 #address-cells = <1>;
32 #size-cells = <0>;
33
Benoit Cousson476b6792011-08-16 11:49:08 +020034 cpu@0 {
35 compatible = "arm,cortex-a8";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +010036 device_type = "cpu";
37 reg = <0x0>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -060038
39 clocks = <&dpll1_ck>;
40 clock-names = "cpu";
41
42 clock-latency = <300000>; /* From omap-cpufreq driver */
Benoit Cousson476b6792011-08-16 11:49:08 +020043 };
44 };
45
Jon Hunter9b07b472012-10-18 09:28:52 -050046 pmu {
47 compatible = "arm,cortex-a8-pmu";
Tony Lindgrend7c8f252013-10-17 15:15:22 -070048 reg = <0x54000000 0x800000>;
Jon Hunter9b07b472012-10-18 09:28:52 -050049 interrupts = <3>;
50 ti,hwmods = "debugss";
51 };
52
Benoit Cousson189892f2011-08-16 21:02:01 +053053 /*
Christoph Fritz161e89a2013-03-29 17:32:05 +010054 * The soc node represents the soc top level view. It is used for IPs
Benoit Cousson189892f2011-08-16 21:02:01 +053055 * that are not memory mapped in the MPU view or for the MPU itself.
56 */
57 soc {
58 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +020059 mpu {
60 compatible = "ti,omap3-mpu";
61 ti,hwmods = "mpu";
62 };
63
Suman Anna4c051602014-04-22 17:23:37 -050064 iva: iva {
Benoit Cousson476b6792011-08-16 11:49:08 +020065 compatible = "ti,iva2.2";
66 ti,hwmods = "iva";
67
68 dsp {
69 compatible = "ti,omap3-c64";
70 };
71 };
Benoit Cousson189892f2011-08-16 21:02:01 +053072 };
73
74 /*
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +010077 * Since it will not bring real advantage to represent that in DT for
Benoit Cousson189892f2011-08-16 21:02:01 +053078 * the moment, just use a fake OCP bus entry to represent the whole bus
79 * hierarchy.
80 */
81 ocp {
Tony Lindgrenaa25729c2014-11-05 09:21:23 -080082 compatible = "ti,omap3-l3-smx", "simple-bus";
Tony Lindgrend7c8f252013-10-17 15:15:22 -070083 reg = <0x68000000 0x10000>;
84 interrupts = <9 10>;
Benoit Cousson189892f2011-08-16 21:02:01 +053085 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88 ti,hwmods = "l3_main";
89
Tony Lindgren7ce93f32013-11-25 14:23:45 -080090 aes: aes@480c5000 {
91 compatible = "ti,omap3-aes";
92 ti,hwmods = "aes";
93 reg = <0x480c5000 0x50>;
94 interrupts = <0>;
95 };
96
Tero Kristo657fc112013-07-22 12:29:29 +030097 prm: prm@48306000 {
98 compatible = "ti,omap3-prm";
99 reg = <0x48306000 0x4000>;
Nishanth Menon5081ce62014-08-22 09:03:50 -0500100 interrupts = <11>;
Tero Kristo657fc112013-07-22 12:29:29 +0300101
102 prm_clocks: clocks {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 };
106
107 prm_clockdomains: clockdomains {
108 };
109 };
110
111 cm: cm@48004000 {
112 compatible = "ti,omap3-cm";
113 reg = <0x48004000 0x4000>;
114
115 cm_clocks: clocks {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
119
120 cm_clockdomains: clockdomains {
121 };
122 };
123
124 scrm: scrm@48002000 {
125 compatible = "ti,omap3-scrm";
126 reg = <0x48002000 0x2000>;
127
128 scrm_clocks: clocks {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 };
132
133 scrm_clockdomains: clockdomains {
134 };
135 };
136
Jon Hunter510c0ff2012-10-25 14:24:14 -0500137 counter32k: counter@48320000 {
138 compatible = "ti,omap-counter32k";
139 reg = <0x48320000 0x20>;
140 ti,hwmods = "counter_32k";
141 };
142
Benoit Coussond65c5422011-11-30 19:26:42 +0100143 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700144 compatible = "ti,omap3-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530145 interrupt-controller;
146 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100147 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530148 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530149
Jon Hunter2c2dc542012-04-26 13:47:59 -0500150 sdma: dma-controller@48056000 {
151 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
152 reg = <0x48056000 0x1000>;
153 interrupts = <12>,
154 <13>,
155 <14>,
156 <15>;
157 #dma-cells = <1>;
Peter Ujfalusi7e8d25d2015-02-20 15:42:03 +0200158 dma-channels = <32>;
159 dma-requests = <96>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500160 };
161
Tony Lindgren679e3312012-09-10 10:34:51 -0700162 omap3_pmx_core: pinmux@48002030 {
163 compatible = "ti,omap3-padconf", "pinctrl-single";
Laurent Pinchart3d495382014-01-07 14:01:39 -0800164 reg = <0x48002030 0x0238>;
Tony Lindgren679e3312012-09-10 10:34:51 -0700165 #address-cells = <1>;
166 #size-cells = <0>;
Tony Lindgren30a69ef2013-10-10 15:45:13 -0700167 #interrupt-cells = <1>;
168 interrupt-controller;
Tony Lindgren679e3312012-09-10 10:34:51 -0700169 pinctrl-single,register-width = <16>;
Tony Lindgrend623a0e2013-10-07 10:22:01 -0700170 pinctrl-single,function-mask = <0xff1f>;
Tony Lindgren679e3312012-09-10 10:34:51 -0700171 };
172
Lee Jonesb7317772013-07-22 11:52:34 +0100173 omap3_pmx_wkup: pinmux@48002a00 {
Tony Lindgren679e3312012-09-10 10:34:51 -0700174 compatible = "ti,omap3-padconf", "pinctrl-single";
Christoph Fritz161e89a2013-03-29 17:32:05 +0100175 reg = <0x48002a00 0x5c>;
Tony Lindgren679e3312012-09-10 10:34:51 -0700176 #address-cells = <1>;
177 #size-cells = <0>;
Tony Lindgren30a69ef2013-10-10 15:45:13 -0700178 #interrupt-cells = <1>;
179 interrupt-controller;
Tony Lindgren679e3312012-09-10 10:34:51 -0700180 pinctrl-single,register-width = <16>;
Tony Lindgrend623a0e2013-10-07 10:22:01 -0700181 pinctrl-single,function-mask = <0xff1f>;
Tony Lindgren679e3312012-09-10 10:34:51 -0700182 };
183
Balaji T Kcd042fe2014-02-19 20:26:40 +0530184 omap3_scm_general: tisyscon@48002270 {
185 compatible = "syscon";
186 reg = <0x48002270 0x2f0>;
187 };
188
189 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap";
191 reg = <0x2b0 0x4>;
192 syscon = <&omap3_scm_general>;
193 pbias_mmc_reg: pbias_mmc_omap2430 {
194 regulator-name = "pbias_mmc_omap2430";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3000000>;
197 };
198 };
199
Benoit Cousson385a64b2011-08-16 11:51:54 +0200200 gpio1: gpio@48310000 {
201 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600202 reg = <0x48310000 0x200>;
203 interrupts = <29>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200204 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500205 ti,gpio-always-on;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600209 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200210 };
211
212 gpio2: gpio@49050000 {
213 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600214 reg = <0x49050000 0x200>;
215 interrupts = <30>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200216 ti,hwmods = "gpio2";
217 gpio-controller;
218 #gpio-cells = <2>;
219 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600220 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200221 };
222
223 gpio3: gpio@49052000 {
224 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600225 reg = <0x49052000 0x200>;
226 interrupts = <31>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200227 ti,hwmods = "gpio3";
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600231 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200232 };
233
234 gpio4: gpio@49054000 {
235 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600236 reg = <0x49054000 0x200>;
237 interrupts = <32>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200238 ti,hwmods = "gpio4";
239 gpio-controller;
240 #gpio-cells = <2>;
241 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600242 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200243 };
244
245 gpio5: gpio@49056000 {
246 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600247 reg = <0x49056000 0x200>;
248 interrupts = <33>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200249 ti,hwmods = "gpio5";
250 gpio-controller;
251 #gpio-cells = <2>;
252 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600253 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200254 };
255
256 gpio6: gpio@49058000 {
257 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600258 reg = <0x49058000 0x200>;
259 interrupts = <34>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200260 ti,hwmods = "gpio6";
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600264 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200265 };
266
Benoit Cousson19bfb762012-02-16 11:55:27 +0100267 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530268 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700269 reg = <0x4806a000 0x2000>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700270 interrupts-extended = <&intc 72>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700271 dmas = <&sdma 49 &sdma 50>;
272 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530273 ti,hwmods = "uart1";
274 clock-frequency = <48000000>;
275 };
276
Benoit Cousson19bfb762012-02-16 11:55:27 +0100277 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530278 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700279 reg = <0x4806c000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700280 interrupts-extended = <&intc 73>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700281 dmas = <&sdma 51 &sdma 52>;
282 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530283 ti,hwmods = "uart2";
284 clock-frequency = <48000000>;
285 };
286
Benoit Cousson19bfb762012-02-16 11:55:27 +0100287 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530288 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700289 reg = <0x49020000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700290 interrupts-extended = <&intc 74>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700291 dmas = <&sdma 53 &sdma 54>;
292 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530293 ti,hwmods = "uart3";
294 clock-frequency = <48000000>;
295 };
296
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200297 i2c1: i2c@48070000 {
298 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700299 reg = <0x48070000 0x80>;
300 interrupts = <56>;
301 dmas = <&sdma 27 &sdma 28>;
302 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200303 #address-cells = <1>;
304 #size-cells = <0>;
305 ti,hwmods = "i2c1";
306 };
307
308 i2c2: i2c@48072000 {
309 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700310 reg = <0x48072000 0x80>;
311 interrupts = <57>;
312 dmas = <&sdma 29 &sdma 30>;
313 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200314 #address-cells = <1>;
315 #size-cells = <0>;
316 ti,hwmods = "i2c2";
317 };
318
319 i2c3: i2c@48060000 {
320 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700321 reg = <0x48060000 0x80>;
322 interrupts = <61>;
323 dmas = <&sdma 25 &sdma 26>;
324 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200325 #address-cells = <1>;
326 #size-cells = <0>;
327 ti,hwmods = "i2c3";
328 };
Benoit Coussonfc72d242012-01-20 14:15:58 +0100329
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800330 mailbox: mailbox@48094000 {
331 compatible = "ti,omap3-mailbox";
332 ti,hwmods = "mailbox";
333 reg = <0x48094000 0x200>;
334 interrupts = <26>;
Suman Anna24df0452014-11-03 17:07:35 -0600335 #mbox-cells = <1>;
Suman Anna41ffada2014-07-11 16:44:34 -0500336 ti,mbox-num-users = <2>;
337 ti,mbox-num-fifos = <2>;
Suman Annad27704d2014-09-10 14:27:23 -0500338 mbox_dsp: dsp {
339 ti,mbox-tx = <0 0 0>;
340 ti,mbox-rx = <1 0 0>;
341 };
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800342 };
343
Benoit Coussonfc72d242012-01-20 14:15:58 +0100344 mcspi1: spi@48098000 {
345 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700346 reg = <0x48098000 0x100>;
347 interrupts = <65>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100348 #address-cells = <1>;
349 #size-cells = <0>;
350 ti,hwmods = "mcspi1";
351 ti,spi-num-cs = <4>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500352 dmas = <&sdma 35>,
353 <&sdma 36>,
354 <&sdma 37>,
355 <&sdma 38>,
356 <&sdma 39>,
357 <&sdma 40>,
358 <&sdma 41>,
359 <&sdma 42>;
360 dma-names = "tx0", "rx0", "tx1", "rx1",
361 "tx2", "rx2", "tx3", "rx3";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100362 };
363
364 mcspi2: spi@4809a000 {
365 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700366 reg = <0x4809a000 0x100>;
367 interrupts = <66>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100368 #address-cells = <1>;
369 #size-cells = <0>;
370 ti,hwmods = "mcspi2";
371 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500372 dmas = <&sdma 43>,
373 <&sdma 44>,
374 <&sdma 45>,
375 <&sdma 46>;
376 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100377 };
378
379 mcspi3: spi@480b8000 {
380 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700381 reg = <0x480b8000 0x100>;
382 interrupts = <91>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100383 #address-cells = <1>;
384 #size-cells = <0>;
385 ti,hwmods = "mcspi3";
386 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500387 dmas = <&sdma 15>,
388 <&sdma 16>,
389 <&sdma 23>,
390 <&sdma 24>;
391 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100392 };
393
394 mcspi4: spi@480ba000 {
395 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700396 reg = <0x480ba000 0x100>;
397 interrupts = <48>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100398 #address-cells = <1>;
399 #size-cells = <0>;
400 ti,hwmods = "mcspi4";
401 ti,spi-num-cs = <1>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500402 dmas = <&sdma 70>, <&sdma 71>;
403 dma-names = "tx0", "rx0";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100404 };
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530405
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700406 hdqw1w: 1w@480b2000 {
407 compatible = "ti,omap3-1w";
408 reg = <0x480b2000 0x1000>;
409 interrupts = <58>;
410 ti,hwmods = "hdq1w";
411 };
412
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530413 mmc1: mmc@4809c000 {
414 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700415 reg = <0x4809c000 0x200>;
416 interrupts = <83>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530417 ti,hwmods = "mmc1";
418 ti,dual-volt;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500419 dmas = <&sdma 61>, <&sdma 62>;
420 dma-names = "tx", "rx";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530421 pbias-supply = <&pbias_mmc_reg>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530422 };
423
424 mmc2: mmc@480b4000 {
425 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700426 reg = <0x480b4000 0x200>;
427 interrupts = <86>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530428 ti,hwmods = "mmc2";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500429 dmas = <&sdma 47>, <&sdma 48>;
430 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530431 };
432
433 mmc3: mmc@480ad000 {
434 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700435 reg = <0x480ad000 0x200>;
436 interrupts = <94>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530437 ti,hwmods = "mmc3";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500438 dmas = <&sdma 77>, <&sdma 78>;
439 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530440 };
Xiao Jiang94c30732012-06-01 12:44:14 +0800441
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800442 mmu_isp: mmu@480bd400 {
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600443 compatible = "ti,omap2-iommu";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800444 reg = <0x480bd400 0x80>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600445 interrupts = <24>;
446 ti,hwmods = "mmu_isp";
447 ti,#tlb-entries = <8>;
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800448 };
449
Florian Vaussard40ac0512014-03-05 18:24:17 -0600450 mmu_iva: mmu@5d000000 {
451 compatible = "ti,omap2-iommu";
452 reg = <0x5d000000 0x80>;
453 interrupts = <28>;
454 ti,hwmods = "mmu_iva";
455 status = "disabled";
456 };
457
Xiao Jiang94c30732012-06-01 12:44:14 +0800458 wdt2: wdt@48314000 {
459 compatible = "ti,omap3-wdt";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700460 reg = <0x48314000 0x80>;
Xiao Jiang94c30732012-06-01 12:44:14 +0800461 ti,hwmods = "wd_timer2";
462 };
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300463
464 mcbsp1: mcbsp@48074000 {
465 compatible = "ti,omap3-mcbsp";
466 reg = <0x48074000 0xff>;
467 reg-names = "mpu";
468 interrupts = <16>, /* OCP compliant interrupt */
469 <59>, /* TX interrupt */
470 <60>; /* RX interrupt */
471 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300472 ti,buffer-size = <128>;
473 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100474 dmas = <&sdma 31>,
475 <&sdma 32>;
476 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200477 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300478 };
479
480 mcbsp2: mcbsp@49022000 {
481 compatible = "ti,omap3-mcbsp";
482 reg = <0x49022000 0xff>,
483 <0x49028000 0xff>;
484 reg-names = "mpu", "sidetone";
485 interrupts = <17>, /* OCP compliant interrupt */
486 <62>, /* TX interrupt */
487 <63>, /* RX interrupt */
488 <4>; /* Sidetone */
489 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300490 ti,buffer-size = <1280>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200491 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100492 dmas = <&sdma 33>,
493 <&sdma 34>;
494 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200495 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300496 };
497
498 mcbsp3: mcbsp@49024000 {
499 compatible = "ti,omap3-mcbsp";
500 reg = <0x49024000 0xff>,
501 <0x4902a000 0xff>;
502 reg-names = "mpu", "sidetone";
503 interrupts = <22>, /* OCP compliant interrupt */
504 <89>, /* TX interrupt */
505 <90>, /* RX interrupt */
506 <5>; /* Sidetone */
507 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300508 ti,buffer-size = <128>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200509 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100510 dmas = <&sdma 17>,
511 <&sdma 18>;
512 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200513 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300514 };
515
516 mcbsp4: mcbsp@49026000 {
517 compatible = "ti,omap3-mcbsp";
518 reg = <0x49026000 0xff>;
519 reg-names = "mpu";
520 interrupts = <23>, /* OCP compliant interrupt */
521 <54>, /* TX interrupt */
522 <55>; /* RX interrupt */
523 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300524 ti,buffer-size = <128>;
525 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100526 dmas = <&sdma 19>,
527 <&sdma 20>;
528 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200529 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300530 };
531
532 mcbsp5: mcbsp@48096000 {
533 compatible = "ti,omap3-mcbsp";
534 reg = <0x48096000 0xff>;
535 reg-names = "mpu";
536 interrupts = <27>, /* OCP compliant interrupt */
537 <81>, /* TX interrupt */
538 <82>; /* RX interrupt */
539 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300540 ti,buffer-size = <128>;
541 ti,hwmods = "mcbsp5";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100542 dmas = <&sdma 21>,
543 <&sdma 22>;
544 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200545 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300546 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500547
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800548 sham: sham@480c3000 {
549 compatible = "ti,omap3-sham";
550 ti,hwmods = "sham";
551 reg = <0x480c3000 0x64>;
552 interrupts = <49>;
553 };
554
555 smartreflex_core: smartreflex@480cb000 {
556 compatible = "ti,omap3-smartreflex-core";
557 ti,hwmods = "smartreflex_core";
558 reg = <0x480cb000 0x400>;
559 interrupts = <19>;
560 };
561
562 smartreflex_mpu_iva: smartreflex@480c9000 {
563 compatible = "ti,omap3-smartreflex-iva";
564 ti,hwmods = "smartreflex_mpu_iva";
565 reg = <0x480c9000 0x400>;
566 interrupts = <18>;
567 };
568
Jon Hunterfab8ad02012-10-19 09:59:00 -0500569 timer1: timer@48318000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500570 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500571 reg = <0x48318000 0x400>;
572 interrupts = <37>;
573 ti,hwmods = "timer1";
574 ti,timer-alwon;
575 };
576
577 timer2: timer@49032000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500578 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500579 reg = <0x49032000 0x400>;
580 interrupts = <38>;
581 ti,hwmods = "timer2";
582 };
583
584 timer3: timer@49034000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500585 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500586 reg = <0x49034000 0x400>;
587 interrupts = <39>;
588 ti,hwmods = "timer3";
589 };
590
591 timer4: timer@49036000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500592 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500593 reg = <0x49036000 0x400>;
594 interrupts = <40>;
595 ti,hwmods = "timer4";
596 };
597
598 timer5: timer@49038000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500599 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500600 reg = <0x49038000 0x400>;
601 interrupts = <41>;
602 ti,hwmods = "timer5";
603 ti,timer-dsp;
604 };
605
606 timer6: timer@4903a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500607 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500608 reg = <0x4903a000 0x400>;
609 interrupts = <42>;
610 ti,hwmods = "timer6";
611 ti,timer-dsp;
612 };
613
614 timer7: timer@4903c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500615 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500616 reg = <0x4903c000 0x400>;
617 interrupts = <43>;
618 ti,hwmods = "timer7";
619 ti,timer-dsp;
620 };
621
622 timer8: timer@4903e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500623 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500624 reg = <0x4903e000 0x400>;
625 interrupts = <44>;
626 ti,hwmods = "timer8";
627 ti,timer-pwm;
628 ti,timer-dsp;
629 };
630
631 timer9: timer@49040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500632 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500633 reg = <0x49040000 0x400>;
634 interrupts = <45>;
635 ti,hwmods = "timer9";
636 ti,timer-pwm;
637 };
638
639 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500640 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500641 reg = <0x48086000 0x400>;
642 interrupts = <46>;
643 ti,hwmods = "timer10";
644 ti,timer-pwm;
645 };
646
647 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500648 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500649 reg = <0x48088000 0x400>;
650 interrupts = <47>;
651 ti,hwmods = "timer11";
652 ti,timer-pwm;
653 };
654
655 timer12: timer@48304000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500656 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500657 reg = <0x48304000 0x400>;
658 interrupts = <95>;
659 ti,hwmods = "timer12";
660 ti,timer-alwon;
661 ti,timer-secure;
662 };
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200663
664 usbhstll: usbhstll@48062000 {
665 compatible = "ti,usbhs-tll";
666 reg = <0x48062000 0x1000>;
667 interrupts = <78>;
668 ti,hwmods = "usb_tll_hs";
669 };
670
671 usbhshost: usbhshost@48064000 {
672 compatible = "ti,usbhs-host";
673 reg = <0x48064000 0x400>;
674 ti,hwmods = "usb_host_hs";
675 #address-cells = <1>;
676 #size-cells = <1>;
677 ranges;
678
679 usbhsohci: ohci@48064400 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200680 compatible = "ti,ohci-omap3";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200681 reg = <0x48064400 0x400>;
682 interrupt-parent = <&intc>;
683 interrupts = <76>;
684 };
685
686 usbhsehci: ehci@48064800 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200687 compatible = "ti,ehci-omap";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200688 reg = <0x48064800 0x400>;
689 interrupt-parent = <&intc>;
690 interrupts = <77>;
691 };
692 };
693
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100694 gpmc: gpmc@6e000000 {
695 compatible = "ti,omap3430-gpmc";
696 ti,hwmods = "gpmc";
Javier Martinez Canillas41644e72013-02-27 02:30:51 +0100697 reg = <0x6e000000 0x02d0>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100698 interrupts = <20>;
699 gpmc,num-cs = <8>;
700 gpmc,num-waitpins = <4>;
701 #address-cells = <2>;
702 #size-cells = <1>;
703 };
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530704
705 usb_otg_hs: usb_otg_hs@480ab000 {
706 compatible = "ti,omap3-musb";
707 reg = <0x480ab000 0x1000>;
Tony Lindgren304e71e2013-05-14 20:28:15 -0700708 interrupts = <92>, <93>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530709 interrupt-names = "mc", "dma";
710 ti,hwmods = "usb_otg_hs";
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530711 multipoint = <1>;
712 num-eps = <16>;
713 ram-bits = <12>;
714 };
Tomi Valkeinenb8a7e422013-03-19 11:38:13 +0200715
716 dss: dss@48050000 {
717 compatible = "ti,omap3-dss";
718 reg = <0x48050000 0x200>;
719 status = "disabled";
720 ti,hwmods = "dss_core";
721 clocks = <&dss1_alwon_fck>;
722 clock-names = "fck";
723 #address-cells = <1>;
724 #size-cells = <1>;
725 ranges;
726
727 dispc@48050400 {
728 compatible = "ti,omap3-dispc";
729 reg = <0x48050400 0x400>;
730 interrupts = <25>;
731 ti,hwmods = "dss_dispc";
732 clocks = <&dss1_alwon_fck>;
733 clock-names = "fck";
734 };
735
736 dsi: encoder@4804fc00 {
737 compatible = "ti,omap3-dsi";
738 reg = <0x4804fc00 0x200>,
739 <0x4804fe00 0x40>,
740 <0x4804ff00 0x20>;
741 reg-names = "proto", "phy", "pll";
742 interrupts = <25>;
743 status = "disabled";
744 ti,hwmods = "dss_dsi1";
745 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
746 clock-names = "fck", "sys_clk";
747 };
748
749 rfbi: encoder@48050800 {
750 compatible = "ti,omap3-rfbi";
751 reg = <0x48050800 0x100>;
752 status = "disabled";
753 ti,hwmods = "dss_rfbi";
754 clocks = <&dss1_alwon_fck>, <&dss_ick>;
755 clock-names = "fck", "ick";
756 };
757
758 venc: encoder@48050c00 {
759 compatible = "ti,omap3-venc";
760 reg = <0x48050c00 0x100>;
761 status = "disabled";
762 ti,hwmods = "dss_venc";
763 clocks = <&dss_tv_fck>;
764 clock-names = "fck";
765 };
766 };
Sebastian Reichel782e25a2014-05-10 18:37:49 +0200767
768 ssi: ssi-controller@48058000 {
769 compatible = "ti,omap3-ssi";
770 ti,hwmods = "ssi";
771
772 status = "disabled";
773
774 reg = <0x48058000 0x1000>,
775 <0x48059000 0x1000>;
776 reg-names = "sys",
777 "gdd";
778
779 interrupts = <71>;
780 interrupt-names = "gdd_mpu";
781
782 #address-cells = <1>;
783 #size-cells = <1>;
784 ranges;
785
786 ssi_port1: ssi-port@4805a000 {
787 compatible = "ti,omap3-ssi-port";
788
789 reg = <0x4805a000 0x800>,
790 <0x4805a800 0x800>;
791 reg-names = "tx",
792 "rx";
793
794 interrupt-parent = <&intc>;
795 interrupts = <67>,
796 <68>;
797 };
798
799 ssi_port2: ssi-port@4805b000 {
800 compatible = "ti,omap3-ssi-port";
801
802 reg = <0x4805b000 0x800>,
803 <0x4805b800 0x800>;
804 reg-names = "tx",
805 "rx";
806
807 interrupt-parent = <&intc>;
808 interrupts = <69>,
809 <70>;
810 };
811 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530812 };
813};
Tero Kristo657fc112013-07-22 12:29:29 +0300814
815/include/ "omap3xxx-clocks.dtsi"