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gerrit-public.fairphone.software / kernel / msm-4.19 / d7f9a3887b91df6404bb4aae101efecc4a4909f7 / . / arch / arm / boot / dts / rk3288.dtsi
blob: 37a8ac8b2a91408f164eca0a6447dbe875da9dfb [file] [log] [blame]
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
18#include "skeleton.dtsi"
19
20/ {
21 compatible = "rockchip,rk3288";
22
23 interrupt-parent = <&gic>;
24
25 aliases {
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
Doug Andersond7f9a382014-09-03 16:05:23 -0700[diff] [blame^]32 mshc0 = &emmc;
33 mshc1 = &sdmmc;
34 mshc2 = &sdio0;
35 mshc3 = &sdio1;
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]36 serial0 = &uart0;
37 serial1 = &uart1;
38 serial2 = &uart2;
39 serial3 = &uart3;
40 serial4 = &uart4;
huang lin1f531702014-09-05 09:53:11 -0700[diff] [blame]41 spi0 = &spi0;
42 spi1 = &spi1;
43 spi2 = &spi2;
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu@500 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a12";
53 reg = <0x500>;
54 };
55 cpu@501 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a12";
58 reg = <0x501>;
59 };
60 cpu@502 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a12";
63 reg = <0x502>;
64 };
65 cpu@503 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a12";
68 reg = <0x503>;
69 };
70 };
71
72 xin24m: oscillator {
73 compatible = "fixed-clock";
74 clock-frequency = <24000000>;
75 clock-output-names = "xin24m";
76 #clock-cells = <0>;
77 };
78
79 timer {
80 compatible = "arm,armv7-timer";
81 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
82 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
83 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
84 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
85 clock-frequency = <24000000>;
86 };
87
Doug Anderson85095bf2014-08-12 16:21:13 -0700[diff] [blame]88 sdmmc: dwmmc@ff0c0000 {
89 compatible = "rockchip,rk3288-dw-mshc";
90 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
91 clock-names = "biu", "ciu";
92 fifo-depth = <0x100>;
93 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
94 reg = <0xff0c0000 0x4000>;
95 status = "disabled";
96 };
97
Addy Kef1a07232014-08-19 18:21:08 +0800[diff] [blame]98 sdio0: dwmmc@ff0d0000 {
99 compatible = "rockchip,rk3288-dw-mshc";
100 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
101 clock-names = "biu", "ciu";
102 fifo-depth = <0x100>;
103 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
104 reg = <0xff0d0000 0x4000>;
105 status = "disabled";
106 };
107
108 sdio1: dwmmc@ff0e0000 {
109 compatible = "rockchip,rk3288-dw-mshc";
110 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
111 clock-names = "biu", "ciu";
112 fifo-depth = <0x100>;
113 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
114 reg = <0xff0e0000 0x4000>;
115 status = "disabled";
116 };
117
Doug Anderson85095bf2014-08-12 16:21:13 -0700[diff] [blame]118 emmc: dwmmc@ff0f0000 {
119 compatible = "rockchip,rk3288-dw-mshc";
120 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
121 clock-names = "biu", "ciu";
122 fifo-depth = <0x100>;
123 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
124 reg = <0xff0f0000 0x4000>;
125 status = "disabled";
126 };
127
Heiko Stübnerf23a6172014-08-20 21:09:24 +0200[diff] [blame]128 saradc: saradc@ff100000 {
129 compatible = "rockchip,saradc";
130 reg = <0xff100000 0x100>;
131 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
132 #io-channel-cells = <1>;
133 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
134 clock-names = "saradc", "apb_pclk";
135 status = "disabled";
136 };
137
huang lin1f531702014-09-05 09:53:11 -0700[diff] [blame]138 spi0: spi@ff110000 {
139 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
140 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
141 clock-names = "spiclk", "apb_pclk";
142 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
145 reg = <0xff110000 0x1000>;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 status = "disabled";
149 };
150
151 spi1: spi@ff120000 {
152 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
153 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
154 clock-names = "spiclk", "apb_pclk";
155 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
158 reg = <0xff120000 0x1000>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 status = "disabled";
162 };
163
164 spi2: spi@ff130000 {
165 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
166 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
167 clock-names = "spiclk", "apb_pclk";
168 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
171 reg = <0xff130000 0x1000>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 status = "disabled";
175 };
176
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]177 i2c1: i2c@ff140000 {
178 compatible = "rockchip,rk3288-i2c";
179 reg = <0xff140000 0x1000>;
180 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 clock-names = "i2c";
184 clocks = <&cru PCLK_I2C1>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&i2c1_xfer>;
187 status = "disabled";
188 };
189
190 i2c3: i2c@ff150000 {
191 compatible = "rockchip,rk3288-i2c";
192 reg = <0xff150000 0x1000>;
193 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 clock-names = "i2c";
197 clocks = <&cru PCLK_I2C3>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&i2c3_xfer>;
200 status = "disabled";
201 };
202
203 i2c4: i2c@ff160000 {
204 compatible = "rockchip,rk3288-i2c";
205 reg = <0xff160000 0x1000>;
206 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 clock-names = "i2c";
210 clocks = <&cru PCLK_I2C4>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&i2c4_xfer>;
213 status = "disabled";
214 };
215
216 i2c5: i2c@ff170000 {
217 compatible = "rockchip,rk3288-i2c";
218 reg = <0xff170000 0x1000>;
219 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
220 #address-cells = <1>;
221 #size-cells = <0>;
222 clock-names = "i2c";
223 clocks = <&cru PCLK_I2C5>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&i2c5_xfer>;
226 status = "disabled";
227 };
228
229 uart0: serial@ff180000 {
230 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
231 reg = <0xff180000 0x100>;
232 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
233 reg-shift = <2>;
234 reg-io-width = <4>;
235 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
236 clock-names = "baudclk", "apb_pclk";
237 pinctrl-names = "default";
238 pinctrl-0 = <&uart0_xfer>;
239 status = "disabled";
240 };
241
242 uart1: serial@ff190000 {
243 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
244 reg = <0xff190000 0x100>;
245 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
246 reg-shift = <2>;
247 reg-io-width = <4>;
248 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
249 clock-names = "baudclk", "apb_pclk";
250 pinctrl-names = "default";
251 pinctrl-0 = <&uart1_xfer>;
252 status = "disabled";
253 };
254
255 uart2: serial@ff690000 {
256 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
257 reg = <0xff690000 0x100>;
258 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
259 reg-shift = <2>;
260 reg-io-width = <4>;
261 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
262 clock-names = "baudclk", "apb_pclk";
263 pinctrl-names = "default";
264 pinctrl-0 = <&uart2_xfer>;
265 status = "disabled";
266 };
267
268 uart3: serial@ff1b0000 {
269 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
270 reg = <0xff1b0000 0x100>;
271 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
272 reg-shift = <2>;
273 reg-io-width = <4>;
274 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
275 clock-names = "baudclk", "apb_pclk";
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart3_xfer>;
278 status = "disabled";
279 };
280
281 uart4: serial@ff1c0000 {
282 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
283 reg = <0xff1c0000 0x100>;
284 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
285 reg-shift = <2>;
286 reg-io-width = <4>;
287 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
288 clock-names = "baudclk", "apb_pclk";
289 pinctrl-names = "default";
290 pinctrl-0 = <&uart4_xfer>;
291 status = "disabled";
292 };
293
Doug Andersonc9c32c52014-08-07 17:44:19 +0200[diff] [blame]294 usb_host0_ehci: usb@ff500000 {
295 compatible = "generic-ehci";
296 reg = <0xff500000 0x100>;
297 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&cru HCLK_USBHOST0>;
299 clock-names = "usbhost";
300 status = "disabled";
301 };
302
303 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
304
Kever Yang12dd3652014-08-08 11:55:58 +0800[diff] [blame]305 usb_host1: usb@ff540000 {
306 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
307 "snps,dwc2";
308 reg = <0xff540000 0x40000>;
309 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cru HCLK_USBHOST1>;
311 clock-names = "otg";
312 status = "disabled";
313 };
314
315 usb_otg: usb@ff580000 {
316 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
317 "snps,dwc2";
318 reg = <0xff580000 0x40000>;
319 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&cru HCLK_OTG0>;
321 clock-names = "otg";
322 status = "disabled";
323 };
324
Doug Andersonc9c32c52014-08-07 17:44:19 +0200[diff] [blame]325 usb_hsic: usb@ff5c0000 {
326 compatible = "generic-ehci";
327 reg = <0xff5c0000 0x100>;
328 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&cru HCLK_HSIC>;
330 clock-names = "usbhost";
331 status = "disabled";
332 };
333
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]334 i2c0: i2c@ff650000 {
335 compatible = "rockchip,rk3288-i2c";
336 reg = <0xff650000 0x1000>;
337 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 clock-names = "i2c";
341 clocks = <&cru PCLK_I2C0>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c0_xfer>;
344 status = "disabled";
345 };
346
347 i2c2: i2c@ff660000 {
348 compatible = "rockchip,rk3288-i2c";
349 reg = <0xff660000 0x1000>;
350 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 clock-names = "i2c";
354 clocks = <&cru PCLK_I2C2>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c2_xfer>;
357 status = "disabled";
358 };
359
Doug Andersondf542df2014-08-25 15:59:26 -0700[diff] [blame]360 pwm0: pwm@ff680000 {
361 compatible = "rockchip,rk3288-pwm";
362 reg = <0xff680000 0x10>;
363 #pwm-cells = <3>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pwm0_pin>;
366 clocks = <&cru PCLK_PWM>;
367 clock-names = "pwm";
368 status = "disabled";
369 };
370
371 pwm1: pwm@ff680010 {
372 compatible = "rockchip,rk3288-pwm";
373 reg = <0xff680010 0x10>;
374 #pwm-cells = <3>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pwm1_pin>;
377 clocks = <&cru PCLK_PWM>;
378 clock-names = "pwm";
379 status = "disabled";
380 };
381
382 pwm2: pwm@ff680020 {
383 compatible = "rockchip,rk3288-pwm";
384 reg = <0xff680020 0x10>;
385 #pwm-cells = <3>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pwm2_pin>;
388 clocks = <&cru PCLK_PWM>;
389 clock-names = "pwm";
390 status = "disabled";
391 };
392
393 pwm3: pwm@ff680030 {
394 compatible = "rockchip,rk3288-pwm";
395 reg = <0xff680030 0x10>;
396 #pwm-cells = <2>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pwm3_pin>;
399 clocks = <&cru PCLK_PWM>;
400 clock-names = "pwm";
401 status = "disabled";
402 };
403
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]404 pmu: power-management@ff730000 {
405 compatible = "rockchip,rk3288-pmu", "syscon";
406 reg = <0xff730000 0x100>;
407 };
408
409 sgrf: syscon@ff740000 {
410 compatible = "rockchip,rk3288-sgrf", "syscon";
411 reg = <0xff740000 0x1000>;
412 };
413
414 cru: clock-controller@ff760000 {
415 compatible = "rockchip,rk3288-cru";
416 reg = <0xff760000 0x1000>;
417 rockchip,grf = <&grf>;
418 #clock-cells = <1>;
419 #reset-cells = <1>;
420 };
421
422 grf: syscon@ff770000 {
423 compatible = "rockchip,rk3288-grf", "syscon";
424 reg = <0xff770000 0x1000>;
425 };
426
427 wdt: watchdog@ff800000 {
428 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
429 reg = <0xff800000 0x100>;
430 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
431 status = "disabled";
432 };
433
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]434 gic: interrupt-controller@ffc01000 {
435 compatible = "arm,gic-400";
436 interrupt-controller;
437 #interrupt-cells = <3>;
438 #address-cells = <0>;
439
440 reg = <0xffc01000 0x1000>,
441 <0xffc02000 0x1000>,
442 <0xffc04000 0x2000>,
443 <0xffc06000 0x2000>;
444 interrupts = <GIC_PPI 9 0xf04>;
445 };
446
447 pinctrl: pinctrl {
448 compatible = "rockchip,rk3288-pinctrl";
449 rockchip,grf = <&grf>;
450 rockchip,pmu = <&pmu>;
451 #address-cells = <1>;
452 #size-cells = <1>;
453 ranges;
454
455 gpio0: gpio0@ff750000 {
456 compatible = "rockchip,gpio-bank";
457 reg = <0xff750000 0x100>;
458 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&cru PCLK_GPIO0>;
460
461 gpio-controller;
462 #gpio-cells = <2>;
463
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 };
467
468 gpio1: gpio1@ff780000 {
469 compatible = "rockchip,gpio-bank";
470 reg = <0xff780000 0x100>;
471 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&cru PCLK_GPIO1>;
473
474 gpio-controller;
475 #gpio-cells = <2>;
476
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 };
480
481 gpio2: gpio2@ff790000 {
482 compatible = "rockchip,gpio-bank";
483 reg = <0xff790000 0x100>;
484 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&cru PCLK_GPIO2>;
486
487 gpio-controller;
488 #gpio-cells = <2>;
489
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 };
493
494 gpio3: gpio3@ff7a0000 {
495 compatible = "rockchip,gpio-bank";
496 reg = <0xff7a0000 0x100>;
497 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cru PCLK_GPIO3>;
499
500 gpio-controller;
501 #gpio-cells = <2>;
502
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 };
506
507 gpio4: gpio4@ff7b0000 {
508 compatible = "rockchip,gpio-bank";
509 reg = <0xff7b0000 0x100>;
510 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru PCLK_GPIO4>;
512
513 gpio-controller;
514 #gpio-cells = <2>;
515
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 };
519
520 gpio5: gpio5@ff7c0000 {
521 compatible = "rockchip,gpio-bank";
522 reg = <0xff7c0000 0x100>;
523 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cru PCLK_GPIO5>;
525
526 gpio-controller;
527 #gpio-cells = <2>;
528
529 interrupt-controller;
530 #interrupt-cells = <2>;
531 };
532
533 gpio6: gpio6@ff7d0000 {
534 compatible = "rockchip,gpio-bank";
535 reg = <0xff7d0000 0x100>;
536 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cru PCLK_GPIO6>;
538
539 gpio-controller;
540 #gpio-cells = <2>;
541
542 interrupt-controller;
543 #interrupt-cells = <2>;
544 };
545
546 gpio7: gpio7@ff7e0000 {
547 compatible = "rockchip,gpio-bank";
548 reg = <0xff7e0000 0x100>;
549 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&cru PCLK_GPIO7>;
551
552 gpio-controller;
553 #gpio-cells = <2>;
554
555 interrupt-controller;
556 #interrupt-cells = <2>;
557 };
558
559 gpio8: gpio8@ff7f0000 {
560 compatible = "rockchip,gpio-bank";
561 reg = <0xff7f0000 0x100>;
562 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru PCLK_GPIO8>;
564
565 gpio-controller;
566 #gpio-cells = <2>;
567
568 interrupt-controller;
569 #interrupt-cells = <2>;
570 };
571
572 pcfg_pull_up: pcfg-pull-up {
573 bias-pull-up;
574 };
575
576 pcfg_pull_down: pcfg-pull-down {
577 bias-pull-down;
578 };
579
580 pcfg_pull_none: pcfg-pull-none {
581 bias-disable;
582 };
583
584 i2c0 {
585 i2c0_xfer: i2c0-xfer {
586 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
587 <0 16 RK_FUNC_1 &pcfg_pull_none>;
588 };
589 };
590
591 i2c1 {
592 i2c1_xfer: i2c1-xfer {
593 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
594 <8 5 RK_FUNC_1 &pcfg_pull_none>;
595 };
596 };
597
598 i2c2 {
599 i2c2_xfer: i2c2-xfer {
600 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
601 <6 10 RK_FUNC_1 &pcfg_pull_none>;
602 };
603 };
604
605 i2c3 {
606 i2c3_xfer: i2c3-xfer {
607 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
608 <2 17 RK_FUNC_1 &pcfg_pull_none>;
609 };
610 };
611
612 i2c4 {
613 i2c4_xfer: i2c4-xfer {
614 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
615 <7 18 RK_FUNC_1 &pcfg_pull_none>;
616 };
617 };
618
619 i2c5 {
620 i2c5_xfer: i2c5-xfer {
621 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
622 <7 20 RK_FUNC_1 &pcfg_pull_none>;
623 };
624 };
625
626 sdmmc {
627 sdmmc_clk: sdmmc-clk {
628 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
629 };
630
631 sdmmc_cmd: sdmmc-cmd {
632 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
633 };
634
635 sdmmc_cd: sdmcc-cd {
636 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
637 };
638
639 sdmmc_bus1: sdmmc-bus1 {
640 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
641 };
642
643 sdmmc_bus4: sdmmc-bus4 {
644 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
645 <6 17 RK_FUNC_1 &pcfg_pull_up>,
646 <6 18 RK_FUNC_1 &pcfg_pull_up>,
647 <6 19 RK_FUNC_1 &pcfg_pull_up>;
648 };
649 };
650
Addy Kef1a07232014-08-19 18:21:08 +0800[diff] [blame]651 sdio0 {
652 sdio0_bus1: sdio0-bus1 {
653 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
654 };
655
656 sdio0_bus4: sdio0-bus4 {
657 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
658 <4 21 RK_FUNC_1 &pcfg_pull_up>,
659 <4 22 RK_FUNC_1 &pcfg_pull_up>,
660 <4 23 RK_FUNC_1 &pcfg_pull_up>;
661 };
662
663 sdio0_cmd: sdio0-cmd {
664 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
665 };
666
667 sdio0_clk: sdio0-clk {
668 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
669 };
670
671 sdio0_cd: sdio0-cd {
672 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
673 };
674
675 sdio0_wp: sdio0-wp {
676 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
677 };
678
679 sdio0_pwr: sdio0-pwr {
680 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
681 };
682
683 sdio0_bkpwr: sdio0-bkpwr {
684 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
685 };
686
687 sdio0_int: sdio0-int {
688 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
689 };
690 };
691
692 sdio1 {
693 sdio1_bus1: sdio1-bus1 {
694 rockchip,pins = <3 24 4 &pcfg_pull_up>;
695 };
696
697 sdio1_bus4: sdio1-bus4 {
698 rockchip,pins = <3 24 4 &pcfg_pull_up>,
699 <3 25 4 &pcfg_pull_up>,
700 <3 26 4 &pcfg_pull_up>,
701 <3 27 4 &pcfg_pull_up>;
702 };
703
704 sdio1_cd: sdio1-cd {
705 rockchip,pins = <3 28 4 &pcfg_pull_up>;
706 };
707
708 sdio1_wp: sdio1-wp {
709 rockchip,pins = <3 29 4 &pcfg_pull_up>;
710 };
711
712 sdio1_bkpwr: sdio1-bkpwr {
713 rockchip,pins = <3 30 4 &pcfg_pull_up>;
714 };
715
716 sdio1_int: sdio1-int {
717 rockchip,pins = <3 31 4 &pcfg_pull_up>;
718 };
719
720 sdio1_cmd: sdio1-cmd {
721 rockchip,pins = <4 6 4 &pcfg_pull_up>;
722 };
723
724 sdio1_clk: sdio1-clk {
725 rockchip,pins = <4 7 4 &pcfg_pull_none>;
726 };
727
728 sdio1_pwr: sdio1-pwr {
729 rockchip,pins = <4 9 4 &pcfg_pull_up>;
730 };
731 };
732
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]733 emmc {
734 emmc_clk: emmc-clk {
735 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
736 };
737
738 emmc_cmd: emmc-cmd {
739 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
740 };
741
742 emmc_pwr: emmc-pwr {
743 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
744 };
745
746 emmc_bus1: emmc-bus1 {
747 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
748 };
749
750 emmc_bus4: emmc-bus4 {
751 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
752 <3 1 RK_FUNC_2 &pcfg_pull_up>,
753 <3 2 RK_FUNC_2 &pcfg_pull_up>,
754 <3 3 RK_FUNC_2 &pcfg_pull_up>;
755 };
756
757 emmc_bus8: emmc-bus8 {
758 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
759 <3 1 RK_FUNC_2 &pcfg_pull_up>,
760 <3 2 RK_FUNC_2 &pcfg_pull_up>,
761 <3 3 RK_FUNC_2 &pcfg_pull_up>,
762 <3 4 RK_FUNC_2 &pcfg_pull_up>,
763 <3 5 RK_FUNC_2 &pcfg_pull_up>,
764 <3 6 RK_FUNC_2 &pcfg_pull_up>,
765 <3 7 RK_FUNC_2 &pcfg_pull_up>;
766 };
767 };
768
huang lin1f531702014-09-05 09:53:11 -0700[diff] [blame]769 spi0 {
770 spi0_clk: spi0-clk {
771 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
772 };
773 spi0_cs0: spi0-cs0 {
774 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
775 };
776 spi0_tx: spi0-tx {
777 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
778 };
779 spi0_rx: spi0-rx {
780 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
781 };
782 spi0_cs1: spi0-cs1 {
783 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
784 };
785 };
786 spi1 {
787 spi1_clk: spi1-clk {
788 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
789 };
790 spi1_cs0: spi1-cs0 {
791 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
792 };
793 spi1_rx: spi1-rx {
794 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
795 };
796 spi1_tx: spi1-tx {
797 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
798 };
799 };
800
801 spi2 {
802 spi2_cs1: spi2-cs1 {
803 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
804 };
805 spi2_clk: spi2-clk {
806 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
807 };
808 spi2_cs0: spi2-cs0 {
809 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
810 };
811 spi2_rx: spi2-rx {
812 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
813 };
814 spi2_tx: spi2-tx {
815 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
816 };
817 };
818
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]819 uart0 {
820 uart0_xfer: uart0-xfer {
821 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
822 <4 17 RK_FUNC_1 &pcfg_pull_none>;
823 };
824
825 uart0_cts: uart0-cts {
826 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
827 };
828
829 uart0_rts: uart0-rts {
830 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
831 };
832 };
833
834 uart1 {
835 uart1_xfer: uart1-xfer {
836 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
837 <5 9 RK_FUNC_1 &pcfg_pull_none>;
838 };
839
840 uart1_cts: uart1-cts {
841 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
842 };
843
844 uart1_rts: uart1-rts {
845 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
846 };
847 };
848
849 uart2 {
850 uart2_xfer: uart2-xfer {
851 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
852 <7 23 RK_FUNC_1 &pcfg_pull_none>;
853 };
854 /* no rts / cts for uart2 */
855 };
856
857 uart3 {
858 uart3_xfer: uart3-xfer {
859 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
860 <7 8 RK_FUNC_1 &pcfg_pull_none>;
861 };
862
863 uart3_cts: uart3-cts {
864 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
865 };
866
867 uart3_rts: uart3-rts {
868 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
869 };
870 };
871
872 uart4 {
873 uart4_xfer: uart4-xfer {
874 rockchip,pins = <5 12 3 &pcfg_pull_up>,
875 <5 13 3 &pcfg_pull_none>;
876 };
877
878 uart4_cts: uart4-cts {
879 rockchip,pins = <5 14 3 &pcfg_pull_none>;
880 };
881
882 uart4_rts: uart4-rts {
883 rockchip,pins = <5 15 3 &pcfg_pull_none>;
884 };
885 };
Doug Andersondf542df2014-08-25 15:59:26 -0700[diff] [blame]886
887 pwm0 {
888 pwm0_pin: pwm0-pin {
889 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
890 };
891 };
892
893 pwm1 {
894 pwm1_pin: pwm1-pin {
895 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
896 };
897 };
898
899 pwm2 {
900 pwm2_pin: pwm2-pin {
901 rockchip,pins = <7 22 3 &pcfg_pull_none>;
902 };
903 };
904
905 pwm3 {
906 pwm3_pin: pwm3-pin {
907 rockchip,pins = <7 23 3 &pcfg_pull_none>;
908 };
909 };
Heiko Stuebner2ab557b2014-07-15 20:16:19 +0200[diff] [blame]910 };
911};