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gerrit-public.fairphone.software / kernel / msm-4.19 / d8018361b58bb7b9a2a657104e54c33c2ef1439d / . / sound / soc / intel / skylake / skl.h
blob: a0709e344d4419f4a37d28636cc3c79f368acd36 [file] [log] [blame]
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]1/*
2 * skl.h - HD Audio skylake defintions.
3 *
4 * Copyright (C) 2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 *
19 */
20
21#ifndef __SOUND_SOC_SKL_H
22#define __SOUND_SOC_SKL_H
23
24#include <sound/hda_register.h>
25#include <sound/hdaudio_ext.h>
Jeeja KP473eb872015-07-21 23:53:55 +0530[diff] [blame]26#include "skl-nhlt.h"
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]27
28#define SKL_SUSPEND_DELAY 2000
29
30/* Vendor Specific Registers */
31#define AZX_REG_VS_EM1 0x1000
32#define AZX_REG_VS_INRC 0x1004
33#define AZX_REG_VS_OUTRC 0x1008
34#define AZX_REG_VS_FIFOTRK 0x100C
35#define AZX_REG_VS_FIFOTRK2 0x1010
36#define AZX_REG_VS_EM2 0x1030
37#define AZX_REG_VS_EM3L 0x1038
38#define AZX_REG_VS_EM3U 0x103C
39#define AZX_REG_VS_EM4L 0x1040
40#define AZX_REG_VS_EM4U 0x1044
41#define AZX_REG_VS_LTRC 0x1048
42#define AZX_REG_VS_D0I3C 0x104A
43#define AZX_REG_VS_PCE 0x104B
44#define AZX_REG_VS_L2MAGC 0x1050
45#define AZX_REG_VS_L2LAHPT 0x1054
46#define AZX_REG_VS_SDXDPIB_XBASE 0x1084
47#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
48#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
49#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
50
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100[diff] [blame]51struct skl_dsp_resource {
52 u32 max_mcps;
53 u32 max_mem;
54 u32 mcps;
55 u32 mem;
56};
57
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]58struct skl {
59 struct hdac_ext_bus ebus;
60 struct pci_dev *pci;
61
62 unsigned int init_failed:1; /* delayed init failed */
63 struct platform_device *dmic_dev;
Jeeja KP473eb872015-07-21 23:53:55 +0530[diff] [blame]64
Dan Williamsba40a852015-10-09 18:16:36 -0400[diff] [blame]65 void *nhlt; /* nhlt ptr */
Jeeja KPd255b092015-07-21 23:53:56 +0530[diff] [blame]66 struct skl_sst *skl_sst; /* sst skl ctx */
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100[diff] [blame]67
68 struct skl_dsp_resource resource;
69 struct list_head ppl_list;
70 struct list_head dapm_path_list;
Vinod Kould8018362016-01-05 17:16:04 +0530[diff] [blame^]71
72 const struct firmware *tplg;
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]73};
74
75#define skl_to_ebus(s) (&(s)->ebus)
76#define ebus_to_skl(sbus) \
77 container_of(sbus, struct skl, sbus)
78
79/* to pass dai dma data */
80struct skl_dma_params {
81 u32 format;
82 u8 stream_tag;
83};
84
85int skl_platform_unregister(struct device *dev);
86int skl_platform_register(struct device *dev);
87
Dan Williamsba40a852015-10-09 18:16:36 -0400[diff] [blame]88void *skl_nhlt_init(struct device *dev);
89void skl_nhlt_free(void *addr);
Jeeja KP473eb872015-07-21 23:53:55 +0530[diff] [blame]90struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
91 u8 link_type, u8 s_fmt, u8 no_ch, u32 s_rate, u8 dirn);
Jeeja KPd255b092015-07-21 23:53:56 +0530[diff] [blame]92
93int skl_init_dsp(struct skl *skl);
94void skl_free_dsp(struct skl *skl);
95int skl_suspend_dsp(struct skl *skl);
96int skl_resume_dsp(struct skl *skl);
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]97#endif /* __SOUND_SOC_SKL_H */