blob: 16c1e46e86036b23907d6a83334cb512f3fbaf00 [file] [log] [blame]
Adrian Bunkb00dc832008-05-19 16:52:27 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
Paul Gortmakercdd4f4c2016-09-19 17:36:29 -04008#include <linux/extable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/initrd.h>
17#include <linux/swap.h>
18#include <linux/pagemap.h>
Randy Dunlapc9cf5522006-06-27 02:53:52 -070019#include <linux/poison.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/fs.h>
21#include <linux/seq_file.h>
Prasanna S Panchamukhi05e14cb2005-09-06 15:19:30 -070022#include <linux/kprobes.h>
David S. Miller1ac4f5e2005-09-21 21:49:32 -070023#include <linux/cache.h>
David S. Miller13edad72005-09-29 17:58:26 -070024#include <linux/sort.h>
bob piccof6d4fb52014-03-03 11:54:42 -050025#include <linux/ioport.h>
David S. Miller5cbc3072007-05-25 15:49:59 -070026#include <linux/percpu.h>
Yinghai Lu95f72d12010-07-12 14:36:09 +100027#include <linux/memblock.h>
David S. Miller919ee672008-04-23 05:40:25 -070028#include <linux/mmzone.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
31#include <asm/head.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032#include <asm/page.h>
33#include <asm/pgalloc.h>
34#include <asm/pgtable.h>
35#include <asm/oplib.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
Linus Torvalds7c0f6ba2016-12-24 11:46:01 -080038#include <linux/uaccess.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <asm/mmu_context.h>
40#include <asm/tlbflush.h>
41#include <asm/dma.h>
42#include <asm/starfire.h>
43#include <asm/tlb.h>
44#include <asm/spitfire.h>
45#include <asm/sections.h>
David S. Miller517af332006-02-01 15:55:21 -080046#include <asm/tsb.h>
David S. Miller481295f2006-02-07 21:51:08 -080047#include <asm/hypervisor.h>
David S. Miller372b07b2006-06-21 15:35:28 -070048#include <asm/prom.h>
David S. Miller5cbc3072007-05-25 15:49:59 -070049#include <asm/mdesc.h>
David S. Miller3d5ae6b2008-03-25 21:51:40 -070050#include <asm/cpudata.h>
Sam Ravnborg59dec132014-05-16 23:26:07 +020051#include <asm/setup.h>
David S. Miller4f70f7a2008-08-12 18:33:56 -070052#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Sam Ravnborg27137e52008-11-16 20:08:45 -080054#include "init_64.h"
David S. Miller9cc3a1a2006-02-21 20:51:13 -080055
David S. Miller4f93d212012-09-06 18:13:58 -070056unsigned long kern_linear_pte_xor[4] __read_mostly;
Khalid Aziz494e5b62015-05-27 10:00:46 -060057static unsigned long page_cache4v_flag;
David S. Miller9cc3a1a2006-02-21 20:51:13 -080058
David S. Miller4f93d212012-09-06 18:13:58 -070059/* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
64 *
65 * 0 ==> 4MB
66 * 1 ==> 256MB
67 * 2 ==> 2GB
68 * 3 ==> 16GB
69 *
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
74 *
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
David S. Miller9cc3a1a2006-02-21 20:51:13 -080078 */
David S. Miller9cc3a1a2006-02-21 20:51:13 -080079
David S. Millerd1acb422007-03-16 17:20:28 -070080#ifndef CONFIG_DEBUG_PAGEALLOC
David S. Miller4f93d212012-09-06 18:13:58 -070081/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
David S. Miller2d9e2762007-05-29 01:58:31 -070084 */
85extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
David S. Millerd1acb422007-03-16 17:20:28 -070086#endif
David S. Miller0dd5b7b2014-09-24 20:56:11 -070087extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
David S. Millerd7744a02006-02-21 22:31:11 -080088
David S. Millerce33fdc2012-09-06 19:01:25 -070089static unsigned long cpu_pgsz_mask;
90
David S. Millerd195b712014-09-27 21:30:57 -070091#define MAX_BANKS 1024
David S. Miller10147572005-09-28 21:46:43 -070092
Greg Kroah-Hartman7c9503b2012-12-21 14:03:26 -080093static struct linux_prom64_registers pavail[MAX_BANKS];
94static int pavail_ents;
David S. Miller10147572005-09-28 21:46:43 -070095
Nitin Gupta52708d62015-11-02 16:30:24 -050096u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
97
David S. Miller13edad72005-09-29 17:58:26 -070098static int cmp_p64(const void *a, const void *b)
99{
100 const struct linux_prom64_registers *x = a, *y = b;
101
102 if (x->phys_addr > y->phys_addr)
103 return 1;
104 if (x->phys_addr < y->phys_addr)
105 return -1;
106 return 0;
107}
108
109static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
111 int *num_ents)
112{
Andres Salomon8d125562010-10-08 14:18:11 -0700113 phandle node = prom_finddevice("/memory");
David S. Miller13edad72005-09-29 17:58:26 -0700114 int prop_size = prom_getproplen(node, property);
115 int ents, ret, i;
116
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
122 prom_halt();
123 }
124
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
126 if (ret == -1) {
Akinobu Mita5da444a2012-09-29 03:14:49 +0000127 prom_printf("Couldn't get %s property from /memory.\n",
128 property);
David S. Miller13edad72005-09-29 17:58:26 -0700129 prom_halt();
130 }
131
David S. Miller13edad72005-09-29 17:58:26 -0700132 /* Sanitize what we got from the firmware, by page aligning
133 * everything.
134 */
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
137
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
140
141 size &= PAGE_MASK;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
144
145 size -= new_base - base;
146 if ((long) size < 0L)
147 size = 0UL;
148 base = new_base;
149 }
David S. Miller0015d3d2007-03-15 00:06:34 -0700150 if (size == 0UL) {
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
154 */
155 memmove(&regs[i], &regs[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
157 i--;
158 ents--;
159 continue;
160 }
David S. Miller13edad72005-09-29 17:58:26 -0700161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
163 }
David S. Miller486ad102006-06-22 00:00:00 -0700164
David S. Miller486ad102006-06-22 00:00:00 -0700165 *num_ents = ents;
166
David S. Millerc9c10832005-10-12 12:22:46 -0700167 sort(regs, ents, sizeof(struct linux_prom64_registers),
David S. Miller13edad72005-09-29 17:58:26 -0700168 cmp_p64, NULL);
169}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170
David S. Millerd1112012006-03-08 02:16:07 -0800171/* Kernel physical address base and size in bytes. */
David S. Miller1ac4f5e2005-09-21 21:49:32 -0700172unsigned long kern_base __read_mostly;
173unsigned long kern_size __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175/* Initial ramdisk setup */
176extern unsigned long sparc_ramdisk_image64;
177extern unsigned int sparc_ramdisk_image;
178extern unsigned int sparc_ramdisk_size;
179
David S. Miller1ac4f5e2005-09-21 21:49:32 -0700180struct page *mem_map_zero __read_mostly;
Aneesh Kumar K.V35802c02008-04-29 08:11:12 -0400181EXPORT_SYMBOL(mem_map_zero);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182
David S. Miller0835ae02005-10-04 15:23:20 -0700183unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184
185unsigned long sparc64_kern_pri_context __read_mostly;
186unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187unsigned long sparc64_kern_sec_context __read_mostly;
188
David S. Miller64658742008-03-21 17:01:38 -0700189int num_kernel_image_mappings;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191#ifdef CONFIG_DEBUG_DCFLUSH
192atomic_t dcpage_flushes = ATOMIC_INIT(0);
193#ifdef CONFIG_SMP
194atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
195#endif
196#endif
197
David S. Miller7a591cf2006-02-26 19:44:50 -0800198inline void flush_dcache_page_impl(struct page *page)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199{
David S. Miller7a591cf2006-02-26 19:44:50 -0800200 BUG_ON(tlb_type == hypervisor);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201#ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes);
203#endif
204
205#ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page),
207 ((tlb_type == spitfire) &&
208 page_mapping(page) != NULL));
209#else
210 if (page_mapping(page) != NULL &&
211 tlb_type == spitfire)
212 __flush_icache_page(__pa(page_address(page)));
213#endif
214}
215
216#define PG_dcache_dirty PG_arch_1
David S. Miller22adb352007-05-26 01:14:43 -0700217#define PG_dcache_cpu_shift 32UL
218#define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220
221#define dcache_dirty_cpu(page) \
David S. Miller48b0e542005-07-27 16:08:44 -0700222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223
David S. Millerd979f172007-10-27 00:13:04 -0700224static inline void set_dcache_dirty(struct page *page, int this_cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225{
226 unsigned long mask = this_cpu;
David S. Miller48b0e542005-07-27 16:08:44 -0700227 unsigned long non_cpu_bits;
228
229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
231
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 __asm__ __volatile__("1:\n\t"
233 "ldx [%2], %%g7\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
237 "cmp %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
David S. Millerb445e262005-06-27 15:42:04 -0700239 " nop"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 : /* no outputs */
241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
242 : "g1", "g7");
243}
244
David S. Millerd979f172007-10-27 00:13:04 -0700245static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246{
247 unsigned long mask = (1UL << PG_dcache_dirty);
248
249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
250 "1:\n\t"
251 "ldx [%2], %%g7\n\t"
David S. Miller48b0e542005-07-27 16:08:44 -0700252 "srlx %%g7, %4, %%g1\n\t"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 "and %%g1, %3, %%g1\n\t"
254 "cmp %%g1, %0\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
258 "cmp %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
David S. Millerb445e262005-06-27 15:42:04 -0700260 " nop\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 "2:"
262 : /* no outputs */
263 : "r" (cpu), "r" (mask), "r" (&page->flags),
David S. Miller48b0e542005-07-27 16:08:44 -0700264 "i" (PG_dcache_cpu_mask),
265 "i" (PG_dcache_cpu_shift)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266 : "g1", "g7");
267}
268
David S. Miller517af332006-02-01 15:55:21 -0800269static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
270{
271 unsigned long tsb_addr = (unsigned long) ent;
272
David S. Miller3b3ab2e2006-02-17 09:54:42 -0800273 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
David S. Miller517af332006-02-01 15:55:21 -0800274 tsb_addr = __pa(tsb_addr);
275
276 __tsb_insert(tsb_addr, tag, pte);
277}
278
David S. Millerc4bce902006-02-11 21:57:54 -0800279unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
David S. Millerc4bce902006-02-11 21:57:54 -0800280
Sam Ravnborgff9aefb2009-01-06 12:51:26 -0800281static void flush_dcache(unsigned long pfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282{
Sam Ravnborgff9aefb2009-01-06 12:51:26 -0800283 struct page *page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284
Sam Ravnborgff9aefb2009-01-06 12:51:26 -0800285 page = pfn_to_page(pfn);
David S. Miller1a78ced2009-10-12 03:20:57 -0700286 if (page) {
David S. Miller7a591cf2006-02-26 19:44:50 -0800287 unsigned long pg_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288
Sam Ravnborgff9aefb2009-01-06 12:51:26 -0800289 pg_flags = page->flags;
290 if (pg_flags & (1UL << PG_dcache_dirty)) {
David S. Miller7a591cf2006-02-26 19:44:50 -0800291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
292 PG_dcache_cpu_mask);
293 int this_cpu = get_cpu();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294
David S. Miller7a591cf2006-02-26 19:44:50 -0800295 /* This is just to optimize away some function calls
296 * in the SMP case.
297 */
298 if (cpu == this_cpu)
299 flush_dcache_page_impl(page);
300 else
301 smp_flush_dcache_page_impl(page, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302
David S. Miller7a591cf2006-02-26 19:44:50 -0800303 clear_dcache_dirty_cpu(page, cpu);
304
305 put_cpu();
306 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 }
Sam Ravnborgff9aefb2009-01-06 12:51:26 -0800308}
309
David Miller9e695d22012-10-08 16:34:29 -0700310/* mm->context.lock must be held */
311static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
312 unsigned long tsb_hash_shift, unsigned long address,
313 unsigned long tte)
314{
315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
316 unsigned long tag;
317
David S. Millerbcd896b2013-02-19 13:20:08 -0800318 if (unlikely(!tsb))
319 return;
320
David Miller9e695d22012-10-08 16:34:29 -0700321 tsb += ((address >> tsb_hash_shift) &
322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
323 tag = (address >> 22UL);
324 tsb_insert(tsb, tag, tte);
325}
326
Nitin Guptac7d9f772017-02-01 16:16:36 -0800327#ifdef CONFIG_HUGETLB_PAGE
328static int __init setup_hugepagesz(char *string)
329{
330 unsigned long long hugepage_size;
331 unsigned int hugepage_shift;
332 unsigned short hv_pgsz_idx;
333 unsigned int hv_pgsz_mask;
334 int rc = 0;
335
336 hugepage_size = memparse(string, &string);
337 hugepage_shift = ilog2(hugepage_size);
338
339 switch (hugepage_shift) {
340 case HPAGE_256MB_SHIFT:
341 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
342 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
343 break;
344 case HPAGE_SHIFT:
345 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
346 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
347 break;
Nitin Guptadcd19122017-02-06 12:33:26 -0800348 case HPAGE_64K_SHIFT:
349 hv_pgsz_mask = HV_PGSZ_MASK_64K;
350 hv_pgsz_idx = HV_PGSZ_IDX_64K;
351 break;
Nitin Guptac7d9f772017-02-01 16:16:36 -0800352 default:
353 hv_pgsz_mask = 0;
354 }
355
356 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) {
357 pr_warn("hugepagesz=%llu not supported by MMU.\n",
358 hugepage_size);
359 goto out;
360 }
361
362 hugetlb_add_hstate(hugepage_shift - PAGE_SHIFT);
363 rc = 1;
364
365out:
366 return rc;
367}
368__setup("hugepagesz=", setup_hugepagesz);
369#endif /* CONFIG_HUGETLB_PAGE */
370
Russell King4b3073e2009-12-18 16:40:18 +0000371void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
Sam Ravnborgff9aefb2009-01-06 12:51:26 -0800372{
373 struct mm_struct *mm;
David S. Millerbcd896b2013-02-19 13:20:08 -0800374 unsigned long flags;
Russell King4b3073e2009-12-18 16:40:18 +0000375 pte_t pte = *ptep;
Sam Ravnborgff9aefb2009-01-06 12:51:26 -0800376
377 if (tlb_type != hypervisor) {
378 unsigned long pfn = pte_pfn(pte);
379
380 if (pfn_valid(pfn))
381 flush_dcache(pfn);
382 }
David S. Millerbd407912006-01-31 18:31:38 -0800383
384 mm = vma->vm_mm;
David S. Miller7a1ac522006-03-16 02:02:32 -0800385
David S. Miller18f38132014-08-04 16:34:01 -0700386 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
387 if (!pte_accessible(mm, pte))
388 return;
389
David S. Miller7a1ac522006-03-16 02:02:32 -0800390 spin_lock_irqsave(&mm->context.lock, flags);
391
David Miller9e695d22012-10-08 16:34:29 -0700392#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
Mike Kravetzaf1b1a92016-07-15 13:08:42 -0700393 if ((mm->context.hugetlb_pte_count || mm->context.thp_pte_count) &&
Nitin Guptac7d9f772017-02-01 16:16:36 -0800394 is_hugetlb_pmd(__pmd(pte_val(pte)))) {
Nitin Gupta7bc37772016-07-29 00:54:21 -0700395 /* We are fabricating 8MB pages using 4MB real hw pages. */
396 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
David S. Miller37b3a8f2013-09-25 13:48:49 -0700397 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
David S. Millerbcd896b2013-02-19 13:20:08 -0800398 address, pte_val(pte));
Nitin Gupta7bc37772016-07-29 00:54:21 -0700399 } else
David S. Millerdcc1e8d2006-03-22 00:49:59 -0800400#endif
David S. Millerbcd896b2013-02-19 13:20:08 -0800401 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
402 address, pte_val(pte));
David S. Miller7a1ac522006-03-16 02:02:32 -0800403
404 spin_unlock_irqrestore(&mm->context.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405}
406
407void flush_dcache_page(struct page *page)
408{
David S. Millera9546f52005-04-17 18:03:09 -0700409 struct address_space *mapping;
410 int this_cpu;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411
David S. Miller7a591cf2006-02-26 19:44:50 -0800412 if (tlb_type == hypervisor)
413 return;
414
David S. Millera9546f52005-04-17 18:03:09 -0700415 /* Do not bother with the expensive D-cache flush if it
416 * is merely the zero page. The 'bigcore' testcase in GDB
417 * causes this case to run millions of times.
418 */
419 if (page == ZERO_PAGE(0))
420 return;
421
422 this_cpu = get_cpu();
423
424 mapping = page_mapping(page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 if (mapping && !mapping_mapped(mapping)) {
David S. Millera9546f52005-04-17 18:03:09 -0700426 int dirty = test_bit(PG_dcache_dirty, &page->flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427 if (dirty) {
David S. Millera9546f52005-04-17 18:03:09 -0700428 int dirty_cpu = dcache_dirty_cpu(page);
429
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 if (dirty_cpu == this_cpu)
431 goto out;
432 smp_flush_dcache_page_impl(page, dirty_cpu);
433 }
434 set_dcache_dirty(page, this_cpu);
435 } else {
436 /* We could delay the flush for the !page_mapping
437 * case too. But that case is for exec env/arg
438 * pages and those are %99 certainly going to get
439 * faulted into the tlb (and thus flushed) anyways.
440 */
441 flush_dcache_page_impl(page);
442 }
443
444out:
445 put_cpu();
446}
Sam Ravnborg917c3662009-01-08 16:58:20 -0800447EXPORT_SYMBOL(flush_dcache_page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
Prasanna S Panchamukhi05e14cb2005-09-06 15:19:30 -0700449void __kprobes flush_icache_range(unsigned long start, unsigned long end)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450{
David S. Millera43fe0e2006-02-04 03:10:53 -0800451 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 if (tlb_type == spitfire) {
453 unsigned long kaddr;
454
David S. Millera94aa252007-03-15 15:50:11 -0700455 /* This code only runs on Spitfire cpus so this is
456 * why we can assume _PAGE_PADDR_4U.
457 */
458 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
459 unsigned long paddr, mask = _PAGE_PADDR_4U;
460
461 if (kaddr >= PAGE_OFFSET)
462 paddr = kaddr & mask;
463 else {
464 pgd_t *pgdp = pgd_offset_k(kaddr);
465 pud_t *pudp = pud_offset(pgdp, kaddr);
466 pmd_t *pmdp = pmd_offset(pudp, kaddr);
467 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
468
469 paddr = pte_val(*ptep) & mask;
470 }
471 __flush_icache_page(paddr);
472 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 }
474}
Sam Ravnborg917c3662009-01-08 16:58:20 -0800475EXPORT_SYMBOL(flush_icache_range);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477void mmu_info(struct seq_file *m)
478{
David S. Millerce33fdc2012-09-06 19:01:25 -0700479 static const char *pgsz_strings[] = {
480 "8K", "64K", "512K", "4MB", "32MB",
481 "256MB", "2GB", "16GB",
482 };
483 int i, printed;
484
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485 if (tlb_type == cheetah)
486 seq_printf(m, "MMU Type\t: Cheetah\n");
487 else if (tlb_type == cheetah_plus)
488 seq_printf(m, "MMU Type\t: Cheetah+\n");
489 else if (tlb_type == spitfire)
490 seq_printf(m, "MMU Type\t: Spitfire\n");
David S. Millera43fe0e2006-02-04 03:10:53 -0800491 else if (tlb_type == hypervisor)
492 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 else
494 seq_printf(m, "MMU Type\t: ???\n");
495
David S. Millerce33fdc2012-09-06 19:01:25 -0700496 seq_printf(m, "MMU PGSZs\t: ");
497 printed = 0;
498 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
499 if (cpu_pgsz_mask & (1UL << i)) {
500 seq_printf(m, "%s%s",
501 printed ? "," : "", pgsz_strings[i]);
502 printed++;
503 }
504 }
505 seq_putc(m, '\n');
506
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507#ifdef CONFIG_DEBUG_DCFLUSH
508 seq_printf(m, "DCPageFlushes\t: %d\n",
509 atomic_read(&dcpage_flushes));
510#ifdef CONFIG_SMP
511 seq_printf(m, "DCPageFlushesXC\t: %d\n",
512 atomic_read(&dcpage_flushes_xcall));
513#endif /* CONFIG_SMP */
514#endif /* CONFIG_DEBUG_DCFLUSH */
515}
516
David S. Millera94aa252007-03-15 15:50:11 -0700517struct linux_prom_translation prom_trans[512] __read_mostly;
518unsigned int prom_trans_ents __read_mostly;
519
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520unsigned long kern_locked_tte_data;
521
David S. Miller405599b2005-09-22 00:12:35 -0700522/* The obp translations are saved based on 8k pagesize, since obp can
523 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
David S. Miller74bf4312006-01-31 18:29:18 -0800524 * HI_OBP_ADDRESS range are handled in ktlb.S.
David S. Miller405599b2005-09-22 00:12:35 -0700525 */
David S. Miller5085b4a2005-09-22 00:45:41 -0700526static inline int in_obp_range(unsigned long vaddr)
527{
528 return (vaddr >= LOW_OBP_ADDRESS &&
529 vaddr < HI_OBP_ADDRESS);
530}
531
David S. Millerc9c10832005-10-12 12:22:46 -0700532static int cmp_ptrans(const void *a, const void *b)
David S. Miller405599b2005-09-22 00:12:35 -0700533{
David S. Millerc9c10832005-10-12 12:22:46 -0700534 const struct linux_prom_translation *x = a, *y = b;
David S. Miller405599b2005-09-22 00:12:35 -0700535
David S. Millerc9c10832005-10-12 12:22:46 -0700536 if (x->virt > y->virt)
537 return 1;
538 if (x->virt < y->virt)
539 return -1;
540 return 0;
David S. Miller405599b2005-09-22 00:12:35 -0700541}
542
David S. Millerc9c10832005-10-12 12:22:46 -0700543/* Read OBP translations property into 'prom_trans[]'. */
David S. Miller9ad98c52005-10-05 15:12:00 -0700544static void __init read_obp_translations(void)
David S. Miller405599b2005-09-22 00:12:35 -0700545{
David S. Millerc9c10832005-10-12 12:22:46 -0700546 int n, node, ents, first, last, i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547
548 node = prom_finddevice("/virtual-memory");
549 n = prom_getproplen(node, "translations");
David S. Miller405599b2005-09-22 00:12:35 -0700550 if (unlikely(n == 0 || n == -1)) {
David S. Millerb206fc42005-09-21 22:31:13 -0700551 prom_printf("prom_mappings: Couldn't get size.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552 prom_halt();
553 }
David S. Miller405599b2005-09-22 00:12:35 -0700554 if (unlikely(n > sizeof(prom_trans))) {
Akinobu Mita5da444a2012-09-29 03:14:49 +0000555 prom_printf("prom_mappings: Size %d is too big.\n", n);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 prom_halt();
557 }
David S. Miller405599b2005-09-22 00:12:35 -0700558
David S. Millerb206fc42005-09-21 22:31:13 -0700559 if ((n = prom_getproperty(node, "translations",
David S. Miller405599b2005-09-22 00:12:35 -0700560 (char *)&prom_trans[0],
561 sizeof(prom_trans))) == -1) {
David S. Millerb206fc42005-09-21 22:31:13 -0700562 prom_printf("prom_mappings: Couldn't get property.\n");
563 prom_halt();
564 }
David S. Miller9ad98c52005-10-05 15:12:00 -0700565
David S. Millerb206fc42005-09-21 22:31:13 -0700566 n = n / sizeof(struct linux_prom_translation);
David S. Miller9ad98c52005-10-05 15:12:00 -0700567
David S. Millerc9c10832005-10-12 12:22:46 -0700568 ents = n;
569
570 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
571 cmp_ptrans, NULL);
572
573 /* Now kick out all the non-OBP entries. */
574 for (i = 0; i < ents; i++) {
575 if (in_obp_range(prom_trans[i].virt))
576 break;
577 }
578 first = i;
579 for (; i < ents; i++) {
580 if (!in_obp_range(prom_trans[i].virt))
581 break;
582 }
583 last = i;
584
585 for (i = 0; i < (last - first); i++) {
586 struct linux_prom_translation *src = &prom_trans[i + first];
587 struct linux_prom_translation *dest = &prom_trans[i];
588
589 *dest = *src;
590 }
591 for (; i < ents; i++) {
592 struct linux_prom_translation *dest = &prom_trans[i];
593 dest->virt = dest->size = dest->data = 0x0UL;
594 }
595
596 prom_trans_ents = last - first;
597
598 if (tlb_type == spitfire) {
599 /* Clear diag TTE bits. */
600 for (i = 0; i < prom_trans_ents; i++)
601 prom_trans[i].data &= ~0x0003fe0000000000UL;
602 }
David S. Millerf4142cb2011-09-29 12:18:59 -0700603
604 /* Force execute bit on. */
605 for (i = 0; i < prom_trans_ents; i++)
606 prom_trans[i].data |= (tlb_type == hypervisor ?
607 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
David S. Miller405599b2005-09-22 00:12:35 -0700608}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609
David S. Millerd82ace72006-02-09 02:52:44 -0800610static void __init hypervisor_tlb_lock(unsigned long vaddr,
611 unsigned long pte,
612 unsigned long mmu)
613{
David S. Miller7db35f32007-05-29 02:22:14 -0700614 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
David S. Millerd82ace72006-02-09 02:52:44 -0800615
David S. Miller7db35f32007-05-29 02:22:14 -0700616 if (ret != 0) {
Akinobu Mita5da444a2012-09-29 03:14:49 +0000617 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
David S. Miller7db35f32007-05-29 02:22:14 -0700618 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
David S. Miller12e126a2006-02-17 14:40:30 -0800619 prom_halt();
620 }
David S. Millerd82ace72006-02-09 02:52:44 -0800621}
622
David S. Millerc4bce902006-02-11 21:57:54 -0800623static unsigned long kern_large_tte(unsigned long paddr);
624
David S. Miller898cf0e2005-09-23 11:59:44 -0700625static void __init remap_kernel(void)
David S. Miller405599b2005-09-22 00:12:35 -0700626{
627 unsigned long phys_page, tte_vaddr, tte_data;
David S. Miller64658742008-03-21 17:01:38 -0700628 int i, tlb_ent = sparc64_highest_locked_tlbent();
David S. Miller405599b2005-09-22 00:12:35 -0700629
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630 tte_vaddr = (unsigned long) KERNBASE;
David S. Miller0eef3312014-05-03 22:52:50 -0700631 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
David S. Millerc4bce902006-02-11 21:57:54 -0800632 tte_data = kern_large_tte(phys_page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633
634 kern_locked_tte_data = tte_data;
635
David S. Millerd82ace72006-02-09 02:52:44 -0800636 /* Now lock us into the TLBs via Hypervisor or OBP. */
637 if (tlb_type == hypervisor) {
David S. Miller64658742008-03-21 17:01:38 -0700638 for (i = 0; i < num_kernel_image_mappings; i++) {
David S. Millerd82ace72006-02-09 02:52:44 -0800639 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
640 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
David S. Miller64658742008-03-21 17:01:38 -0700641 tte_vaddr += 0x400000;
642 tte_data += 0x400000;
David S. Millerd82ace72006-02-09 02:52:44 -0800643 }
644 } else {
David S. Miller64658742008-03-21 17:01:38 -0700645 for (i = 0; i < num_kernel_image_mappings; i++) {
646 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
647 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
648 tte_vaddr += 0x400000;
649 tte_data += 0x400000;
David S. Millerd82ace72006-02-09 02:52:44 -0800650 }
David S. Miller64658742008-03-21 17:01:38 -0700651 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 }
David S. Miller0835ae02005-10-04 15:23:20 -0700653 if (tlb_type == cheetah_plus) {
654 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
655 CTX_CHEETAH_PLUS_NUC);
656 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
657 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
658 }
David S. Miller405599b2005-09-22 00:12:35 -0700659}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660
David S. Miller405599b2005-09-22 00:12:35 -0700661
David S. Millerc9c10832005-10-12 12:22:46 -0700662static void __init inherit_prom_mappings(void)
David S. Miller9ad98c52005-10-05 15:12:00 -0700663{
David S. Miller405599b2005-09-22 00:12:35 -0700664 /* Now fixup OBP's idea about where we really are mapped. */
David S. Miller3c62a2d2008-02-17 23:22:50 -0800665 printk("Remapping the kernel... ");
David S. Miller405599b2005-09-22 00:12:35 -0700666 remap_kernel();
David S. Miller3c62a2d2008-02-17 23:22:50 -0800667 printk("done.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668}
669
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670void prom_world(int enter)
671{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672 if (!enter)
Al Virodff933d2012-09-26 01:21:14 -0400673 set_fs(get_fs());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674
David S. Miller3487d1d2006-01-31 18:33:25 -0800675 __asm__ __volatile__("flushw");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676}
677
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678void __flush_dcache_range(unsigned long start, unsigned long end)
679{
680 unsigned long va;
681
682 if (tlb_type == spitfire) {
683 int n = 0;
684
685 for (va = start; va < end; va += 32) {
686 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
687 if (++n >= 512)
688 break;
689 }
David S. Millera43fe0e2006-02-04 03:10:53 -0800690 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 start = __pa(start);
692 end = __pa(end);
693 for (va = start; va < end; va += 32)
694 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
695 "membar #Sync"
696 : /* no outputs */
697 : "r" (va),
698 "i" (ASI_DCACHE_INVALIDATE));
699 }
700}
Sam Ravnborg917c3662009-01-08 16:58:20 -0800701EXPORT_SYMBOL(__flush_dcache_range);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702
David S. Miller85f1e1f2007-03-15 17:51:26 -0700703/* get_new_mmu_context() uses "cache + 1". */
704DEFINE_SPINLOCK(ctx_alloc_lock);
705unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
706#define MAX_CTX_NR (1UL << CTX_NR_BITS)
707#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
708DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
709
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710/* Caller does TLB context flushing on local CPU if necessary.
711 * The caller also ensures that CTX_VALID(mm->context) is false.
712 *
713 * We must be careful about boundary cases so that we never
714 * let the user have CTX 0 (nucleus) or we ever use a CTX
715 * version of zero (and thus NO_CONTEXT would not be caught
716 * by version mis-match tests in mmu_context.h).
David S. Millera0663a72006-02-23 14:19:28 -0800717 *
718 * Always invoked with interrupts disabled.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 */
720void get_new_mmu_context(struct mm_struct *mm)
721{
722 unsigned long ctx, new_ctx;
723 unsigned long orig_pgsz_bits;
David S. Millera0663a72006-02-23 14:19:28 -0800724 int new_version;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725
Kirill Tkhai07df8412013-04-09 00:29:46 +0400726 spin_lock(&ctx_alloc_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
728 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
729 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
David S. Millera0663a72006-02-23 14:19:28 -0800730 new_version = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731 if (new_ctx >= (1 << CTX_NR_BITS)) {
732 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
733 if (new_ctx >= ctx) {
734 int i;
735 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
736 CTX_FIRST_VERSION;
737 if (new_ctx == 1)
738 new_ctx = CTX_FIRST_VERSION;
739
740 /* Don't call memset, for 16 entries that's just
741 * plain silly...
742 */
743 mmu_context_bmap[0] = 3;
744 mmu_context_bmap[1] = 0;
745 mmu_context_bmap[2] = 0;
746 mmu_context_bmap[3] = 0;
747 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
748 mmu_context_bmap[i + 0] = 0;
749 mmu_context_bmap[i + 1] = 0;
750 mmu_context_bmap[i + 2] = 0;
751 mmu_context_bmap[i + 3] = 0;
752 }
David S. Millera0663a72006-02-23 14:19:28 -0800753 new_version = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754 goto out;
755 }
756 }
757 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
758 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
759out:
760 tlb_context_cache = new_ctx;
761 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
Kirill Tkhai07df8412013-04-09 00:29:46 +0400762 spin_unlock(&ctx_alloc_lock);
David S. Millera0663a72006-02-23 14:19:28 -0800763
764 if (unlikely(new_version))
765 smp_new_mmu_context_version();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766}
767
David S. Miller919ee672008-04-23 05:40:25 -0700768static int numa_enabled = 1;
769static int numa_debug;
770
771static int __init early_numa(char *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772{
David S. Miller919ee672008-04-23 05:40:25 -0700773 if (!p)
774 return 0;
David S. Millerd1112012006-03-08 02:16:07 -0800775
David S. Miller919ee672008-04-23 05:40:25 -0700776 if (strstr(p, "off"))
777 numa_enabled = 0;
David S. Millerd1112012006-03-08 02:16:07 -0800778
David S. Miller919ee672008-04-23 05:40:25 -0700779 if (strstr(p, "debug"))
780 numa_debug = 1;
781
782 return 0;
David S. Millerd1112012006-03-08 02:16:07 -0800783}
David S. Miller919ee672008-04-23 05:40:25 -0700784early_param("numa", early_numa);
785
786#define numadbg(f, a...) \
787do { if (numa_debug) \
788 printk(KERN_INFO f, ## a); \
789} while (0)
David S. Millerd1112012006-03-08 02:16:07 -0800790
David S. Miller4e82c9a2008-02-13 18:00:03 -0800791static void __init find_ramdisk(unsigned long phys_base)
792{
793#ifdef CONFIG_BLK_DEV_INITRD
794 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
795 unsigned long ramdisk_image;
796
797 /* Older versions of the bootloader only supported a
798 * 32-bit physical address for the ramdisk image
799 * location, stored at sparc_ramdisk_image. Newer
800 * SILO versions set sparc_ramdisk_image to zero and
801 * provide a full 64-bit physical address at
802 * sparc_ramdisk_image64.
803 */
804 ramdisk_image = sparc_ramdisk_image;
805 if (!ramdisk_image)
806 ramdisk_image = sparc_ramdisk_image64;
807
808 /* Another bootloader quirk. The bootloader normalizes
809 * the physical address to KERNBASE, so we have to
810 * factor that back out and add in the lowest valid
811 * physical page address to get the true physical address.
812 */
813 ramdisk_image -= KERNBASE;
814 ramdisk_image += phys_base;
815
David S. Miller919ee672008-04-23 05:40:25 -0700816 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
817 ramdisk_image, sparc_ramdisk_size);
818
David S. Miller4e82c9a2008-02-13 18:00:03 -0800819 initrd_start = ramdisk_image;
820 initrd_end = ramdisk_image + sparc_ramdisk_size;
David S. Miller3b2a7e22008-02-13 18:13:20 -0800821
Yinghai Lu95f72d12010-07-12 14:36:09 +1000822 memblock_reserve(initrd_start, sparc_ramdisk_size);
David S. Millerd45100f2008-05-06 15:19:54 -0700823
824 initrd_start += PAGE_OFFSET;
825 initrd_end += PAGE_OFFSET;
David S. Miller4e82c9a2008-02-13 18:00:03 -0800826 }
827#endif
828}
829
David S. Miller919ee672008-04-23 05:40:25 -0700830struct node_mem_mask {
831 unsigned long mask;
832 unsigned long val;
David S. Miller919ee672008-04-23 05:40:25 -0700833};
834static struct node_mem_mask node_masks[MAX_NUMNODES];
835static int num_node_masks;
836
Sam Ravnborg48d37212014-05-16 23:26:12 +0200837#ifdef CONFIG_NEED_MULTIPLE_NODES
838
David S. Miller919ee672008-04-23 05:40:25 -0700839int numa_cpu_lookup_table[NR_CPUS];
840cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
841
David S. Miller919ee672008-04-23 05:40:25 -0700842struct mdesc_mblock {
843 u64 base;
844 u64 size;
845 u64 offset; /* RA-to-PA */
846};
847static struct mdesc_mblock *mblocks;
848static int num_mblocks;
Thomas Tai74a5ed52016-11-03 09:19:01 -0700849static int find_numa_node_for_addr(unsigned long pa,
850 struct node_mem_mask *pnode_mask);
David S. Miller919ee672008-04-23 05:40:25 -0700851
Thomas Tai87a349f2016-11-11 16:41:00 -0800852static unsigned long __init ra_to_pa(unsigned long addr)
David S. Millerd1112012006-03-08 02:16:07 -0800853{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854 int i;
855
David S. Miller919ee672008-04-23 05:40:25 -0700856 for (i = 0; i < num_mblocks; i++) {
857 struct mdesc_mblock *m = &mblocks[i];
David S. Miller6fc5bae2006-12-28 21:00:23 -0800858
David S. Miller919ee672008-04-23 05:40:25 -0700859 if (addr >= m->base &&
860 addr < (m->base + m->size)) {
861 addr += m->offset;
862 break;
863 }
864 }
865 return addr;
866}
867
Thomas Tai87a349f2016-11-11 16:41:00 -0800868static int __init find_node(unsigned long addr)
David S. Miller919ee672008-04-23 05:40:25 -0700869{
Thomas Tai74a5ed52016-11-03 09:19:01 -0700870 static bool search_mdesc = true;
871 static struct node_mem_mask last_mem_mask = { ~0UL, ~0UL };
872 static int last_index;
David S. Miller919ee672008-04-23 05:40:25 -0700873 int i;
874
875 addr = ra_to_pa(addr);
876 for (i = 0; i < num_node_masks; i++) {
877 struct node_mem_mask *p = &node_masks[i];
878
879 if ((addr & p->mask) == p->val)
880 return i;
881 }
Thomas Tai74a5ed52016-11-03 09:19:01 -0700882 /* The following condition has been observed on LDOM guests because
883 * node_masks only contains the best latency mask and value.
884 * LDOM guest's mdesc can contain a single latency group to
885 * cover multiple address range. Print warning message only if the
886 * address cannot be found in node_masks nor mdesc.
887 */
888 if ((search_mdesc) &&
889 ((addr & last_mem_mask.mask) != last_mem_mask.val)) {
890 /* find the available node in the mdesc */
891 last_index = find_numa_node_for_addr(addr, &last_mem_mask);
892 numadbg("find_node: latency group for address 0x%lx is %d\n",
893 addr, last_index);
894 if ((last_index < 0) || (last_index >= num_node_masks)) {
895 /* WARN_ONCE() and use default group 0 */
896 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node rule. Some physical memory will be owned by node 0.");
897 search_mdesc = false;
898 last_index = 0;
899 }
900 }
901
902 return last_index;
David S. Miller919ee672008-04-23 05:40:25 -0700903}
904
Thomas Tai87a349f2016-11-11 16:41:00 -0800905static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
David S. Miller919ee672008-04-23 05:40:25 -0700906{
907 *nid = find_node(start);
908 start += PAGE_SIZE;
909 while (start < end) {
910 int n = find_node(start);
911
912 if (n != *nid)
913 break;
914 start += PAGE_SIZE;
915 }
916
David S. Millerc918dcc2008-08-14 01:41:39 -0700917 if (start > end)
918 start = end;
919
David S. Miller919ee672008-04-23 05:40:25 -0700920 return start;
921}
David S. Miller919ee672008-04-23 05:40:25 -0700922#endif
923
924/* This must be invoked after performing all of the necessary
Tejun Heo2a4814d2011-12-08 10:22:08 -0800925 * memblock_set_node() calls for 'nid'. We need to be able to get
David S. Miller919ee672008-04-23 05:40:25 -0700926 * correct data from get_pfn_range_for_nid().
927 */
928static void __init allocate_node_data(int nid)
929{
David S. Miller919ee672008-04-23 05:40:25 -0700930 struct pglist_data *p;
Paul Gortmakeraa6f0792012-05-09 20:44:29 -0400931 unsigned long start_pfn, end_pfn;
David S. Miller919ee672008-04-23 05:40:25 -0700932#ifdef CONFIG_NEED_MULTIPLE_NODES
Paul Gortmakeraa6f0792012-05-09 20:44:29 -0400933 unsigned long paddr;
934
Benjamin Herrenschmidt9d1e2492010-07-06 15:39:17 -0700935 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
David S. Miller919ee672008-04-23 05:40:25 -0700936 if (!paddr) {
937 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
938 prom_halt();
939 }
940 NODE_DATA(nid) = __va(paddr);
941 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
942
David S. Miller625d6932012-04-25 13:13:43 -0700943 NODE_DATA(nid)->node_id = nid;
David S. Miller919ee672008-04-23 05:40:25 -0700944#endif
945
946 p = NODE_DATA(nid);
947
948 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
949 p->node_start_pfn = start_pfn;
950 p->node_spanned_pages = end_pfn - start_pfn;
David S. Miller919ee672008-04-23 05:40:25 -0700951}
952
953static void init_node_masks_nonnuma(void)
954{
Sam Ravnborg48d37212014-05-16 23:26:12 +0200955#ifdef CONFIG_NEED_MULTIPLE_NODES
David S. Miller919ee672008-04-23 05:40:25 -0700956 int i;
Sam Ravnborg48d37212014-05-16 23:26:12 +0200957#endif
David S. Miller919ee672008-04-23 05:40:25 -0700958
959 numadbg("Initializing tables for non-numa.\n");
960
961 node_masks[0].mask = node_masks[0].val = 0;
962 num_node_masks = 1;
963
Sam Ravnborg48d37212014-05-16 23:26:12 +0200964#ifdef CONFIG_NEED_MULTIPLE_NODES
David S. Miller919ee672008-04-23 05:40:25 -0700965 for (i = 0; i < NR_CPUS; i++)
966 numa_cpu_lookup_table[i] = 0;
967
KOSAKI Motohirofb1fece2011-05-16 13:38:07 -0700968 cpumask_setall(&numa_cpumask_lookup_table[0]);
Sam Ravnborg48d37212014-05-16 23:26:12 +0200969#endif
David S. Miller919ee672008-04-23 05:40:25 -0700970}
971
972#ifdef CONFIG_NEED_MULTIPLE_NODES
973struct pglist_data *node_data[MAX_NUMNODES];
974
975EXPORT_SYMBOL(numa_cpu_lookup_table);
976EXPORT_SYMBOL(numa_cpumask_lookup_table);
977EXPORT_SYMBOL(node_data);
978
979struct mdesc_mlgroup {
980 u64 node;
981 u64 latency;
982 u64 match;
983 u64 mask;
984};
985static struct mdesc_mlgroup *mlgroups;
986static int num_mlgroups;
987
988static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
989 u32 cfg_handle)
990{
991 u64 arc;
992
993 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
994 u64 target = mdesc_arc_target(md, arc);
995 const u64 *val;
996
997 val = mdesc_get_property(md, target,
998 "cfg-handle", NULL);
999 if (val && *val == cfg_handle)
1000 return 0;
1001 }
1002 return -ENODEV;
1003}
1004
1005static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1006 u32 cfg_handle)
1007{
1008 u64 arc, candidate, best_latency = ~(u64)0;
1009
1010 candidate = MDESC_NODE_NULL;
1011 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1012 u64 target = mdesc_arc_target(md, arc);
1013 const char *name = mdesc_node_name(md, target);
1014 const u64 *val;
1015
1016 if (strcmp(name, "pio-latency-group"))
1017 continue;
1018
1019 val = mdesc_get_property(md, target, "latency", NULL);
1020 if (!val)
1021 continue;
1022
1023 if (*val < best_latency) {
1024 candidate = target;
1025 best_latency = *val;
1026 }
1027 }
1028
1029 if (candidate == MDESC_NODE_NULL)
1030 return -ENODEV;
1031
1032 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1033}
1034
1035int of_node_to_nid(struct device_node *dp)
1036{
1037 const struct linux_prom64_registers *regs;
1038 struct mdesc_handle *md;
1039 u32 cfg_handle;
1040 int count, nid;
1041 u64 grp;
1042
David S. Miller072bd412008-08-18 20:36:17 -07001043 /* This is the right thing to do on currently supported
1044 * SUN4U NUMA platforms as well, as the PCI controller does
1045 * not sit behind any particular memory controller.
1046 */
David S. Miller919ee672008-04-23 05:40:25 -07001047 if (!mlgroups)
1048 return -1;
1049
1050 regs = of_get_property(dp, "reg", NULL);
1051 if (!regs)
1052 return -1;
1053
1054 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1055
1056 md = mdesc_grab();
1057
1058 count = 0;
1059 nid = -1;
1060 mdesc_for_each_node_by_name(md, grp, "group") {
1061 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1062 nid = count;
1063 break;
1064 }
1065 count++;
1066 }
1067
1068 mdesc_release(md);
1069
1070 return nid;
1071}
1072
David S. Miller01c453812009-04-07 01:05:22 -07001073static void __init add_node_ranges(void)
David S. Miller919ee672008-04-23 05:40:25 -07001074{
Benjamin Herrenschmidt08b84792010-08-04 13:43:31 +10001075 struct memblock_region *reg;
David S. Miller919ee672008-04-23 05:40:25 -07001076
Benjamin Herrenschmidt08b84792010-08-04 13:43:31 +10001077 for_each_memblock(memory, reg) {
1078 unsigned long size = reg->size;
David S. Miller919ee672008-04-23 05:40:25 -07001079 unsigned long start, end;
1080
Benjamin Herrenschmidt08b84792010-08-04 13:43:31 +10001081 start = reg->base;
David S. Miller919ee672008-04-23 05:40:25 -07001082 end = start + size;
1083 while (start < end) {
1084 unsigned long this_end;
1085 int nid;
1086
Benjamin Herrenschmidt35a1f0b2010-07-06 15:38:58 -07001087 this_end = memblock_nid_range(start, end, &nid);
David S. Miller919ee672008-04-23 05:40:25 -07001088
Tejun Heo2a4814d2011-12-08 10:22:08 -08001089 numadbg("Setting memblock NUMA node nid[%d] "
David S. Miller919ee672008-04-23 05:40:25 -07001090 "start[%lx] end[%lx]\n",
1091 nid, start, this_end);
1092
Tang Chene7e8de52014-01-21 15:49:26 -08001093 memblock_set_node(start, this_end - start,
1094 &memblock.memory, nid);
David S. Miller919ee672008-04-23 05:40:25 -07001095 start = this_end;
1096 }
1097 }
1098}
1099
1100static int __init grab_mlgroups(struct mdesc_handle *md)
1101{
1102 unsigned long paddr;
1103 int count = 0;
1104 u64 node;
1105
1106 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1107 count++;
1108 if (!count)
1109 return -ENOENT;
1110
Yinghai Lu95f72d12010-07-12 14:36:09 +10001111 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
David S. Miller919ee672008-04-23 05:40:25 -07001112 SMP_CACHE_BYTES);
1113 if (!paddr)
1114 return -ENOMEM;
1115
1116 mlgroups = __va(paddr);
1117 num_mlgroups = count;
1118
1119 count = 0;
1120 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1121 struct mdesc_mlgroup *m = &mlgroups[count++];
1122 const u64 *val;
1123
1124 m->node = node;
1125
1126 val = mdesc_get_property(md, node, "latency", NULL);
1127 m->latency = *val;
1128 val = mdesc_get_property(md, node, "address-match", NULL);
1129 m->match = *val;
1130 val = mdesc_get_property(md, node, "address-mask", NULL);
1131 m->mask = *val;
1132
Sam Ravnborg90181132009-01-06 13:19:28 -08001133 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1134 "match[%llx] mask[%llx]\n",
David S. Miller919ee672008-04-23 05:40:25 -07001135 count - 1, m->node, m->latency, m->match, m->mask);
1136 }
1137
1138 return 0;
1139}
1140
1141static int __init grab_mblocks(struct mdesc_handle *md)
1142{
1143 unsigned long paddr;
1144 int count = 0;
1145 u64 node;
1146
1147 mdesc_for_each_node_by_name(md, node, "mblock")
1148 count++;
1149 if (!count)
1150 return -ENOENT;
1151
Yinghai Lu95f72d12010-07-12 14:36:09 +10001152 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
David S. Miller919ee672008-04-23 05:40:25 -07001153 SMP_CACHE_BYTES);
1154 if (!paddr)
1155 return -ENOMEM;
1156
1157 mblocks = __va(paddr);
1158 num_mblocks = count;
1159
1160 count = 0;
1161 mdesc_for_each_node_by_name(md, node, "mblock") {
1162 struct mdesc_mblock *m = &mblocks[count++];
1163 const u64 *val;
1164
1165 val = mdesc_get_property(md, node, "base", NULL);
1166 m->base = *val;
1167 val = mdesc_get_property(md, node, "size", NULL);
1168 m->size = *val;
1169 val = mdesc_get_property(md, node,
1170 "address-congruence-offset", NULL);
bob picco771a37f2013-06-11 14:54:51 -04001171
1172 /* The address-congruence-offset property is optional.
1173 * Explicity zero it be identifty this.
1174 */
1175 if (val)
1176 m->offset = *val;
1177 else
1178 m->offset = 0UL;
David S. Miller919ee672008-04-23 05:40:25 -07001179
Sam Ravnborg90181132009-01-06 13:19:28 -08001180 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
David S. Miller919ee672008-04-23 05:40:25 -07001181 count - 1, m->base, m->size, m->offset);
1182 }
1183
1184 return 0;
1185}
1186
1187static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1188 u64 grp, cpumask_t *mask)
1189{
1190 u64 arc;
1191
KOSAKI Motohirofb1fece2011-05-16 13:38:07 -07001192 cpumask_clear(mask);
David S. Miller919ee672008-04-23 05:40:25 -07001193
1194 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1195 u64 target = mdesc_arc_target(md, arc);
1196 const char *name = mdesc_node_name(md, target);
1197 const u64 *id;
1198
1199 if (strcmp(name, "cpu"))
1200 continue;
1201 id = mdesc_get_property(md, target, "id", NULL);
Rusty Russelle305cb8f2009-03-16 14:40:23 +10301202 if (*id < nr_cpu_ids)
KOSAKI Motohirofb1fece2011-05-16 13:38:07 -07001203 cpumask_set_cpu(*id, mask);
David S. Miller919ee672008-04-23 05:40:25 -07001204 }
1205}
1206
1207static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1208{
1209 int i;
1210
1211 for (i = 0; i < num_mlgroups; i++) {
1212 struct mdesc_mlgroup *m = &mlgroups[i];
1213 if (m->node == node)
1214 return m;
1215 }
1216 return NULL;
1217}
1218
Nitin Gupta52708d62015-11-02 16:30:24 -05001219int __node_distance(int from, int to)
1220{
1221 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1222 pr_warn("Returning default NUMA distance value for %d->%d\n",
1223 from, to);
1224 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1225 }
1226 return numa_latency[from][to];
1227}
1228
Thomas Tai74a5ed52016-11-03 09:19:01 -07001229static int find_numa_node_for_addr(unsigned long pa,
1230 struct node_mem_mask *pnode_mask)
1231{
1232 struct mdesc_handle *md = mdesc_grab();
1233 u64 node, arc;
1234 int i = 0;
1235
1236 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1237 if (node == MDESC_NODE_NULL)
1238 goto out;
1239
1240 mdesc_for_each_node_by_name(md, node, "group") {
1241 mdesc_for_each_arc(arc, md, node, MDESC_ARC_TYPE_FWD) {
1242 u64 target = mdesc_arc_target(md, arc);
1243 struct mdesc_mlgroup *m = find_mlgroup(target);
1244
1245 if (!m)
1246 continue;
1247 if ((pa & m->mask) == m->match) {
1248 if (pnode_mask) {
1249 pnode_mask->mask = m->mask;
1250 pnode_mask->val = m->match;
1251 }
1252 mdesc_release(md);
1253 return i;
1254 }
1255 }
1256 i++;
1257 }
1258
1259out:
1260 mdesc_release(md);
1261 return -1;
1262}
1263
Paul Gortmakerbdf2f592016-08-06 00:31:48 -04001264static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
Nitin Gupta52708d62015-11-02 16:30:24 -05001265{
1266 int i;
1267
1268 for (i = 0; i < MAX_NUMNODES; i++) {
1269 struct node_mem_mask *n = &node_masks[i];
1270
1271 if ((grp->mask == n->mask) && (grp->match == n->val))
1272 break;
1273 }
1274 return i;
1275}
1276
Paul Gortmakerbdf2f592016-08-06 00:31:48 -04001277static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1278 u64 grp, int index)
Nitin Gupta52708d62015-11-02 16:30:24 -05001279{
1280 u64 arc;
1281
1282 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1283 int tnode;
1284 u64 target = mdesc_arc_target(md, arc);
1285 struct mdesc_mlgroup *m = find_mlgroup(target);
1286
1287 if (!m)
1288 continue;
1289 tnode = find_best_numa_node_for_mlgroup(m);
1290 if (tnode == MAX_NUMNODES)
1291 continue;
1292 numa_latency[index][tnode] = m->latency;
1293 }
1294}
1295
David S. Miller919ee672008-04-23 05:40:25 -07001296static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1297 int index)
1298{
1299 struct mdesc_mlgroup *candidate = NULL;
1300 u64 arc, best_latency = ~(u64)0;
1301 struct node_mem_mask *n;
1302
1303 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1304 u64 target = mdesc_arc_target(md, arc);
1305 struct mdesc_mlgroup *m = find_mlgroup(target);
1306 if (!m)
1307 continue;
1308 if (m->latency < best_latency) {
1309 candidate = m;
1310 best_latency = m->latency;
1311 }
1312 }
1313 if (!candidate)
1314 return -ENOENT;
1315
1316 if (num_node_masks != index) {
1317 printk(KERN_ERR "Inconsistent NUMA state, "
1318 "index[%d] != num_node_masks[%d]\n",
1319 index, num_node_masks);
1320 return -EINVAL;
1321 }
1322
1323 n = &node_masks[num_node_masks++];
1324
1325 n->mask = candidate->mask;
1326 n->val = candidate->match;
1327
Sam Ravnborg90181132009-01-06 13:19:28 -08001328 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
David S. Miller919ee672008-04-23 05:40:25 -07001329 index, n->mask, n->val, candidate->latency);
1330
1331 return 0;
1332}
1333
1334static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1335 int index)
1336{
1337 cpumask_t mask;
1338 int cpu;
1339
1340 numa_parse_mdesc_group_cpus(md, grp, &mask);
1341
KOSAKI Motohirofb1fece2011-05-16 13:38:07 -07001342 for_each_cpu(cpu, &mask)
David S. Miller919ee672008-04-23 05:40:25 -07001343 numa_cpu_lookup_table[cpu] = index;
KOSAKI Motohirofb1fece2011-05-16 13:38:07 -07001344 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
David S. Miller919ee672008-04-23 05:40:25 -07001345
1346 if (numa_debug) {
1347 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
KOSAKI Motohirofb1fece2011-05-16 13:38:07 -07001348 for_each_cpu(cpu, &mask)
David S. Miller919ee672008-04-23 05:40:25 -07001349 printk("%d ", cpu);
1350 printk("]\n");
1351 }
1352
1353 return numa_attach_mlgroup(md, grp, index);
1354}
1355
1356static int __init numa_parse_mdesc(void)
1357{
1358 struct mdesc_handle *md = mdesc_grab();
Nitin Gupta52708d62015-11-02 16:30:24 -05001359 int i, j, err, count;
David S. Miller919ee672008-04-23 05:40:25 -07001360 u64 node;
1361
1362 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1363 if (node == MDESC_NODE_NULL) {
1364 mdesc_release(md);
1365 return -ENOENT;
1366 }
1367
1368 err = grab_mblocks(md);
1369 if (err < 0)
1370 goto out;
1371
1372 err = grab_mlgroups(md);
1373 if (err < 0)
1374 goto out;
1375
1376 count = 0;
1377 mdesc_for_each_node_by_name(md, node, "group") {
1378 err = numa_parse_mdesc_group(md, node, count);
1379 if (err < 0)
1380 break;
1381 count++;
1382 }
1383
Nitin Gupta52708d62015-11-02 16:30:24 -05001384 count = 0;
1385 mdesc_for_each_node_by_name(md, node, "group") {
1386 find_numa_latencies_for_group(md, node, count);
1387 count++;
1388 }
1389
1390 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1391 for (i = 0; i < MAX_NUMNODES; i++) {
1392 u64 self_latency = numa_latency[i][i];
1393
1394 for (j = 0; j < MAX_NUMNODES; j++) {
1395 numa_latency[i][j] =
1396 (numa_latency[i][j] * LOCAL_DISTANCE) /
1397 self_latency;
1398 }
1399 }
1400
David S. Miller919ee672008-04-23 05:40:25 -07001401 add_node_ranges();
1402
1403 for (i = 0; i < num_node_masks; i++) {
1404 allocate_node_data(i);
1405 node_set_online(i);
1406 }
1407
1408 err = 0;
1409out:
1410 mdesc_release(md);
1411 return err;
1412}
1413
David S. Miller072bd412008-08-18 20:36:17 -07001414static int __init numa_parse_jbus(void)
1415{
1416 unsigned long cpu, index;
1417
1418 /* NUMA node id is encoded in bits 36 and higher, and there is
1419 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1420 */
1421 index = 0;
1422 for_each_present_cpu(cpu) {
1423 numa_cpu_lookup_table[cpu] = index;
KOSAKI Motohirofb1fece2011-05-16 13:38:07 -07001424 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
David S. Miller072bd412008-08-18 20:36:17 -07001425 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1426 node_masks[index].val = cpu << 36UL;
1427
1428 index++;
1429 }
1430 num_node_masks = index;
1431
1432 add_node_ranges();
1433
1434 for (index = 0; index < num_node_masks; index++) {
1435 allocate_node_data(index);
1436 node_set_online(index);
1437 }
1438
1439 return 0;
1440}
1441
David S. Miller919ee672008-04-23 05:40:25 -07001442static int __init numa_parse_sun4u(void)
1443{
David S. Miller072bd412008-08-18 20:36:17 -07001444 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1445 unsigned long ver;
1446
1447 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1448 if ((ver >> 32UL) == __JALAPENO_ID ||
1449 (ver >> 32UL) == __SERRANO_ID)
1450 return numa_parse_jbus();
1451 }
David S. Miller919ee672008-04-23 05:40:25 -07001452 return -1;
1453}
1454
1455static int __init bootmem_init_numa(void)
1456{
Nitin Gupta36beca62016-01-05 22:35:35 -08001457 int i, j;
David S. Miller919ee672008-04-23 05:40:25 -07001458 int err = -1;
1459
1460 numadbg("bootmem_init_numa()\n");
1461
Nitin Gupta36beca62016-01-05 22:35:35 -08001462 /* Some sane defaults for numa latency values */
1463 for (i = 0; i < MAX_NUMNODES; i++) {
1464 for (j = 0; j < MAX_NUMNODES; j++)
1465 numa_latency[i][j] = (i == j) ?
1466 LOCAL_DISTANCE : REMOTE_DISTANCE;
1467 }
1468
David S. Miller919ee672008-04-23 05:40:25 -07001469 if (numa_enabled) {
1470 if (tlb_type == hypervisor)
1471 err = numa_parse_mdesc();
1472 else
1473 err = numa_parse_sun4u();
1474 }
1475 return err;
1476}
1477
1478#else
1479
1480static int bootmem_init_numa(void)
1481{
1482 return -1;
1483}
1484
1485#endif
1486
1487static void __init bootmem_init_nonnuma(void)
1488{
Yinghai Lu95f72d12010-07-12 14:36:09 +10001489 unsigned long top_of_ram = memblock_end_of_DRAM();
1490 unsigned long total_ram = memblock_phys_mem_size();
David S. Miller919ee672008-04-23 05:40:25 -07001491
1492 numadbg("bootmem_init_nonnuma()\n");
1493
1494 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1495 top_of_ram, total_ram);
1496 printk(KERN_INFO "Memory hole size: %ldMB\n",
1497 (top_of_ram - total_ram) >> 20);
1498
1499 init_node_masks_nonnuma();
Tang Chene7e8de52014-01-21 15:49:26 -08001500 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
David S. Miller919ee672008-04-23 05:40:25 -07001501 allocate_node_data(0);
David S. Miller919ee672008-04-23 05:40:25 -07001502 node_set_online(0);
1503}
1504
David S. Miller919ee672008-04-23 05:40:25 -07001505static unsigned long __init bootmem_init(unsigned long phys_base)
1506{
1507 unsigned long end_pfn;
David S. Miller919ee672008-04-23 05:40:25 -07001508
Yinghai Lu95f72d12010-07-12 14:36:09 +10001509 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001510 max_pfn = max_low_pfn = end_pfn;
David S. Millerd1112012006-03-08 02:16:07 -08001511 min_low_pfn = (phys_base >> PAGE_SHIFT);
1512
David S. Miller919ee672008-04-23 05:40:25 -07001513 if (bootmem_init_numa() < 0)
1514 bootmem_init_nonnuma();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001515
David S. Miller625d6932012-04-25 13:13:43 -07001516 /* Dump memblock with node info. */
1517 memblock_dump_all();
1518
David S. Miller919ee672008-04-23 05:40:25 -07001519 /* XXX cpu notifier XXX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001520
David S. Miller625d6932012-04-25 13:13:43 -07001521 sparse_memory_present_with_active_regions(MAX_NUMNODES);
David S. Millerd1112012006-03-08 02:16:07 -08001522 sparse_init();
1523
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524 return end_pfn;
1525}
1526
David S. Miller9cc3a1a2006-02-21 20:51:13 -08001527static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1528static int pall_ents __initdata;
1529
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001530static unsigned long max_phys_bits = 40;
1531
1532bool kern_addr_valid(unsigned long addr)
1533{
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001534 pgd_t *pgd;
1535 pud_t *pud;
1536 pmd_t *pmd;
1537 pte_t *pte;
1538
David S. Millerbb4e6e82014-09-27 11:05:21 -07001539 if ((long)addr < 0L) {
1540 unsigned long pa = __pa(addr);
1541
1542 if ((addr >> max_phys_bits) != 0UL)
1543 return false;
1544
1545 return pfn_valid(pa >> PAGE_SHIFT);
1546 }
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001547
1548 if (addr >= (unsigned long) KERNBASE &&
1549 addr < (unsigned long)&_end)
1550 return true;
1551
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001552 pgd = pgd_offset_k(addr);
1553 if (pgd_none(*pgd))
1554 return 0;
1555
1556 pud = pud_offset(pgd, addr);
1557 if (pud_none(*pud))
1558 return 0;
1559
1560 if (pud_large(*pud))
1561 return pfn_valid(pud_pfn(*pud));
1562
1563 pmd = pmd_offset(pud, addr);
1564 if (pmd_none(*pmd))
1565 return 0;
1566
1567 if (pmd_large(*pmd))
1568 return pfn_valid(pmd_pfn(*pmd));
1569
1570 pte = pte_offset_kernel(pmd, addr);
1571 if (pte_none(*pte))
1572 return 0;
1573
1574 return pfn_valid(pte_pfn(*pte));
1575}
1576EXPORT_SYMBOL(kern_addr_valid);
1577
1578static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1579 unsigned long vend,
1580 pud_t *pud)
1581{
1582 const unsigned long mask16gb = (1UL << 34) - 1UL;
1583 u64 pte_val = vstart;
1584
1585 /* Each PUD is 8GB */
1586 if ((vstart & mask16gb) ||
1587 (vend - vstart <= mask16gb)) {
1588 pte_val ^= kern_linear_pte_xor[2];
1589 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1590
1591 return vstart + PUD_SIZE;
1592 }
1593
1594 pte_val ^= kern_linear_pte_xor[3];
1595 pte_val |= _PAGE_PUD_HUGE;
1596
1597 vend = vstart + mask16gb + 1UL;
1598 while (vstart < vend) {
1599 pud_val(*pud) = pte_val;
1600
1601 pte_val += PUD_SIZE;
1602 vstart += PUD_SIZE;
1603 pud++;
1604 }
1605 return vstart;
1606}
1607
1608static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1609 bool guard)
1610{
1611 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1612 return true;
1613
1614 return false;
1615}
1616
1617static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1618 unsigned long vend,
1619 pmd_t *pmd)
1620{
1621 const unsigned long mask256mb = (1UL << 28) - 1UL;
1622 const unsigned long mask2gb = (1UL << 31) - 1UL;
1623 u64 pte_val = vstart;
1624
1625 /* Each PMD is 8MB */
1626 if ((vstart & mask256mb) ||
1627 (vend - vstart <= mask256mb)) {
1628 pte_val ^= kern_linear_pte_xor[0];
1629 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1630
1631 return vstart + PMD_SIZE;
1632 }
1633
1634 if ((vstart & mask2gb) ||
1635 (vend - vstart <= mask2gb)) {
1636 pte_val ^= kern_linear_pte_xor[1];
1637 pte_val |= _PAGE_PMD_HUGE;
1638 vend = vstart + mask256mb + 1UL;
1639 } else {
1640 pte_val ^= kern_linear_pte_xor[2];
1641 pte_val |= _PAGE_PMD_HUGE;
1642 vend = vstart + mask2gb + 1UL;
1643 }
1644
1645 while (vstart < vend) {
1646 pmd_val(*pmd) = pte_val;
1647
1648 pte_val += PMD_SIZE;
1649 vstart += PMD_SIZE;
1650 pmd++;
1651 }
1652
1653 return vstart;
1654}
1655
1656static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1657 bool guard)
1658{
1659 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1660 return true;
1661
1662 return false;
1663}
1664
Sam Ravnborg896aef42008-02-24 19:49:52 -08001665static unsigned long __ref kernel_map_range(unsigned long pstart,
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001666 unsigned long pend, pgprot_t prot,
1667 bool use_huge)
David S. Miller56425302005-09-25 16:46:57 -07001668{
1669 unsigned long vstart = PAGE_OFFSET + pstart;
1670 unsigned long vend = PAGE_OFFSET + pend;
1671 unsigned long alloc_bytes = 0UL;
1672
1673 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
David S. Miller13edad72005-09-29 17:58:26 -07001674 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
David S. Miller56425302005-09-25 16:46:57 -07001675 vstart, vend);
1676 prom_halt();
1677 }
1678
1679 while (vstart < vend) {
1680 unsigned long this_end, paddr = __pa(vstart);
1681 pgd_t *pgd = pgd_offset_k(vstart);
1682 pud_t *pud;
1683 pmd_t *pmd;
1684 pte_t *pte;
1685
David S. Millerac55c762014-09-26 21:19:46 -07001686 if (pgd_none(*pgd)) {
1687 pud_t *new;
1688
1689 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1690 alloc_bytes += PAGE_SIZE;
1691 pgd_populate(&init_mm, pgd, new);
1692 }
David S. Miller56425302005-09-25 16:46:57 -07001693 pud = pud_offset(pgd, vstart);
1694 if (pud_none(*pud)) {
1695 pmd_t *new;
1696
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001697 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1698 vstart = kernel_map_hugepud(vstart, vend, pud);
1699 continue;
1700 }
David S. Miller56425302005-09-25 16:46:57 -07001701 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1702 alloc_bytes += PAGE_SIZE;
1703 pud_populate(&init_mm, pud, new);
1704 }
1705
1706 pmd = pmd_offset(pud, vstart);
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001707 if (pmd_none(*pmd)) {
David S. Miller56425302005-09-25 16:46:57 -07001708 pte_t *new;
1709
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001710 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1711 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1712 continue;
1713 }
David S. Miller56425302005-09-25 16:46:57 -07001714 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1715 alloc_bytes += PAGE_SIZE;
1716 pmd_populate_kernel(&init_mm, pmd, new);
1717 }
1718
1719 pte = pte_offset_kernel(pmd, vstart);
1720 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1721 if (this_end > vend)
1722 this_end = vend;
1723
1724 while (vstart < this_end) {
1725 pte_val(*pte) = (paddr | pgprot_val(prot));
1726
1727 vstart += PAGE_SIZE;
1728 paddr += PAGE_SIZE;
1729 pte++;
1730 }
1731 }
1732
1733 return alloc_bytes;
1734}
1735
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001736static void __init flush_all_kernel_tsbs(void)
1737{
1738 int i;
1739
1740 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1741 struct tsb *ent = &swapper_tsb[i];
1742
1743 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1744 }
1745#ifndef CONFIG_DEBUG_PAGEALLOC
1746 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1747 struct tsb *ent = &swapper_4m_tsb[i];
1748
1749 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1750 }
1751#endif
1752}
1753
David S. Miller56425302005-09-25 16:46:57 -07001754extern unsigned int kvmap_linear_patch[1];
David S. Miller9cc3a1a2006-02-21 20:51:13 -08001755
David S. Miller8f3614532007-12-13 06:13:38 -08001756static void __init kernel_physical_mapping_init(void)
1757{
David S. Miller8f3614532007-12-13 06:13:38 -08001758 unsigned long i, mem_alloced = 0UL;
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001759 bool use_huge = true;
David S. Miller8f3614532007-12-13 06:13:38 -08001760
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001761#ifdef CONFIG_DEBUG_PAGEALLOC
1762 use_huge = false;
1763#endif
David S. Miller8f3614532007-12-13 06:13:38 -08001764 for (i = 0; i < pall_ents; i++) {
1765 unsigned long phys_start, phys_end;
1766
1767 phys_start = pall[i].phys_addr;
1768 phys_end = phys_start + pall[i].reg_size;
1769
David S. Miller56425302005-09-25 16:46:57 -07001770 mem_alloced += kernel_map_range(phys_start, phys_end,
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001771 PAGE_KERNEL, use_huge);
David S. Miller56425302005-09-25 16:46:57 -07001772 }
1773
1774 printk("Allocated %ld bytes for kernel page tables.\n",
1775 mem_alloced);
1776
1777 kvmap_linear_patch[0] = 0x01000000; /* nop */
1778 flushi(&kvmap_linear_patch[0]);
1779
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001780 flush_all_kernel_tsbs();
1781
David S. Miller56425302005-09-25 16:46:57 -07001782 __flush_tlb_all();
1783}
1784
David S. Miller9cc3a1a2006-02-21 20:51:13 -08001785#ifdef CONFIG_DEBUG_PAGEALLOC
Joonsoo Kim031bc572014-12-12 16:55:52 -08001786void __kernel_map_pages(struct page *page, int numpages, int enable)
David S. Miller56425302005-09-25 16:46:57 -07001787{
1788 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1789 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1790
1791 kernel_map_range(phys_start, phys_end,
David S. Miller0dd5b7b2014-09-24 20:56:11 -07001792 (enable ? PAGE_KERNEL : __pgprot(0)), false);
David S. Miller56425302005-09-25 16:46:57 -07001793
David S. Miller74bf4312006-01-31 18:29:18 -08001794 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1795 PAGE_OFFSET + phys_end);
1796
David S. Miller56425302005-09-25 16:46:57 -07001797 /* we should perform an IPI and flush all tlbs,
1798 * but that can deadlock->flush only current cpu.
1799 */
1800 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1801 PAGE_OFFSET + phys_end);
1802}
1803#endif
1804
David S. Miller10147572005-09-28 21:46:43 -07001805unsigned long __init find_ecache_flush_span(unsigned long size)
1806{
David S. Miller13edad72005-09-29 17:58:26 -07001807 int i;
David S. Miller10147572005-09-28 21:46:43 -07001808
David S. Miller13edad72005-09-29 17:58:26 -07001809 for (i = 0; i < pavail_ents; i++) {
1810 if (pavail[i].reg_size >= size)
1811 return pavail[i].phys_addr;
David S. Miller10147572005-09-28 21:46:43 -07001812 }
1813
1814 return ~0UL;
1815}
1816
David S. Millerb2d43832013-09-20 21:50:41 -07001817unsigned long PAGE_OFFSET;
1818EXPORT_SYMBOL(PAGE_OFFSET);
1819
David S. Millerbb4e6e82014-09-27 11:05:21 -07001820unsigned long VMALLOC_END = 0x0000010000000000UL;
1821EXPORT_SYMBOL(VMALLOC_END);
1822
David S. Miller4397bed2014-09-26 21:58:33 -07001823unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1824unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1825
David S. Millerb2d43832013-09-20 21:50:41 -07001826static void __init setup_page_offset(void)
1827{
David S. Millerb2d43832013-09-20 21:50:41 -07001828 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
David S. Miller4397bed2014-09-26 21:58:33 -07001829 /* Cheetah/Panther support a full 64-bit virtual
1830 * address, so we can use all that our page tables
1831 * support.
1832 */
1833 sparc64_va_hole_top = 0xfff0000000000000UL;
1834 sparc64_va_hole_bottom = 0x0010000000000000UL;
1835
David S. Millerb2d43832013-09-20 21:50:41 -07001836 max_phys_bits = 42;
1837 } else if (tlb_type == hypervisor) {
1838 switch (sun4v_chip_type) {
1839 case SUN4V_CHIP_NIAGARA1:
1840 case SUN4V_CHIP_NIAGARA2:
David S. Miller4397bed2014-09-26 21:58:33 -07001841 /* T1 and T2 support 48-bit virtual addresses. */
1842 sparc64_va_hole_top = 0xffff800000000000UL;
1843 sparc64_va_hole_bottom = 0x0000800000000000UL;
1844
David S. Millerb2d43832013-09-20 21:50:41 -07001845 max_phys_bits = 39;
1846 break;
1847 case SUN4V_CHIP_NIAGARA3:
David S. Miller4397bed2014-09-26 21:58:33 -07001848 /* T3 supports 48-bit virtual addresses. */
1849 sparc64_va_hole_top = 0xffff800000000000UL;
1850 sparc64_va_hole_bottom = 0x0000800000000000UL;
1851
David S. Millerb2d43832013-09-20 21:50:41 -07001852 max_phys_bits = 43;
1853 break;
1854 case SUN4V_CHIP_NIAGARA4:
1855 case SUN4V_CHIP_NIAGARA5:
1856 case SUN4V_CHIP_SPARC64X:
David S. Miller7c0fa0f2014-09-24 21:49:29 -07001857 case SUN4V_CHIP_SPARC_M6:
David S. Miller4397bed2014-09-26 21:58:33 -07001858 /* T4 and later support 52-bit virtual addresses. */
1859 sparc64_va_hole_top = 0xfff8000000000000UL;
1860 sparc64_va_hole_bottom = 0x0008000000000000UL;
David S. Millerb2d43832013-09-20 21:50:41 -07001861 max_phys_bits = 47;
1862 break;
David S. Miller7c0fa0f2014-09-24 21:49:29 -07001863 case SUN4V_CHIP_SPARC_M7:
Khalid Azizc5b8b5b2016-04-19 11:12:54 -06001864 case SUN4V_CHIP_SPARC_SN:
David S. Miller7c0fa0f2014-09-24 21:49:29 -07001865 default:
1866 /* M7 and later support 52-bit virtual addresses. */
1867 sparc64_va_hole_top = 0xfff8000000000000UL;
1868 sparc64_va_hole_bottom = 0x0008000000000000UL;
1869 max_phys_bits = 49;
1870 break;
David S. Millerb2d43832013-09-20 21:50:41 -07001871 }
1872 }
1873
1874 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1875 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1876 max_phys_bits);
1877 prom_halt();
1878 }
1879
David S. Millerbb4e6e82014-09-27 11:05:21 -07001880 PAGE_OFFSET = sparc64_va_hole_top;
1881 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1882 (sparc64_va_hole_bottom >> 2));
David S. Millerb2d43832013-09-20 21:50:41 -07001883
David S. Millerbb4e6e82014-09-27 11:05:21 -07001884 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
David S. Millerb2d43832013-09-20 21:50:41 -07001885 PAGE_OFFSET, max_phys_bits);
David S. Millerbb4e6e82014-09-27 11:05:21 -07001886 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1887 VMALLOC_START, VMALLOC_END);
1888 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1889 VMEMMAP_BASE, VMEMMAP_BASE << 1);
David S. Millerb2d43832013-09-20 21:50:41 -07001890}
1891
David S. Miller517af332006-02-01 15:55:21 -08001892static void __init tsb_phys_patch(void)
1893{
David S. Millerd257d5d2006-02-06 23:44:37 -08001894 struct tsb_ldquad_phys_patch_entry *pquad;
David S. Miller517af332006-02-01 15:55:21 -08001895 struct tsb_phys_patch_entry *p;
1896
David S. Millerd257d5d2006-02-06 23:44:37 -08001897 pquad = &__tsb_ldquad_phys_patch;
1898 while (pquad < &__tsb_ldquad_phys_patch_end) {
1899 unsigned long addr = pquad->addr;
1900
1901 if (tlb_type == hypervisor)
1902 *(unsigned int *) addr = pquad->sun4v_insn;
1903 else
1904 *(unsigned int *) addr = pquad->sun4u_insn;
1905 wmb();
1906 __asm__ __volatile__("flush %0"
1907 : /* no outputs */
1908 : "r" (addr));
1909
1910 pquad++;
1911 }
1912
David S. Miller517af332006-02-01 15:55:21 -08001913 p = &__tsb_phys_patch;
1914 while (p < &__tsb_phys_patch_end) {
1915 unsigned long addr = p->addr;
1916
1917 *(unsigned int *) addr = p->insn;
1918 wmb();
1919 __asm__ __volatile__("flush %0"
1920 : /* no outputs */
1921 : "r" (addr));
1922
1923 p++;
1924 }
1925}
1926
David S. Miller490384e2006-02-11 14:41:18 -08001927/* Don't mark as init, we give this to the Hypervisor. */
David S. Millerd1acb422007-03-16 17:20:28 -07001928#ifndef CONFIG_DEBUG_PAGEALLOC
1929#define NUM_KTSB_DESCR 2
1930#else
1931#define NUM_KTSB_DESCR 1
1932#endif
1933static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
David S. Miller490384e2006-02-11 14:41:18 -08001934
David S. Miller8c82dc02014-09-17 10:14:56 -07001935/* The swapper TSBs are loaded with a base sequence of:
1936 *
1937 * sethi %uhi(SYMBOL), REG1
1938 * sethi %hi(SYMBOL), REG2
1939 * or REG1, %ulo(SYMBOL), REG1
1940 * or REG2, %lo(SYMBOL), REG2
1941 * sllx REG1, 32, REG1
1942 * or REG1, REG2, REG1
1943 *
1944 * When we use physical addressing for the TSB accesses, we patch the
1945 * first four instructions in the above sequence.
1946 */
1947
David S. Miller9076d0e2011-08-05 00:53:57 -07001948static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1949{
David S. Miller8c82dc02014-09-17 10:14:56 -07001950 unsigned long high_bits, low_bits;
1951
1952 high_bits = (pa >> 32) & 0xffffffff;
1953 low_bits = (pa >> 0) & 0xffffffff;
David S. Miller9076d0e2011-08-05 00:53:57 -07001954
1955 while (start < end) {
1956 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1957
David S. Miller8c82dc02014-09-17 10:14:56 -07001958 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
David S. Miller9076d0e2011-08-05 00:53:57 -07001959 __asm__ __volatile__("flush %0" : : "r" (ia));
1960
David S. Miller8c82dc02014-09-17 10:14:56 -07001961 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
David S. Miller9076d0e2011-08-05 00:53:57 -07001962 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1963
David S. Miller8c82dc02014-09-17 10:14:56 -07001964 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1965 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
1966
1967 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1968 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
1969
David S. Miller9076d0e2011-08-05 00:53:57 -07001970 start++;
1971 }
1972}
1973
1974static void ktsb_phys_patch(void)
1975{
1976 extern unsigned int __swapper_tsb_phys_patch;
1977 extern unsigned int __swapper_tsb_phys_patch_end;
David S. Miller9076d0e2011-08-05 00:53:57 -07001978 unsigned long ktsb_pa;
1979
1980 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1981 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1982 &__swapper_tsb_phys_patch_end, ktsb_pa);
1983#ifndef CONFIG_DEBUG_PAGEALLOC
David S. Miller0785a8e2011-08-06 05:26:35 -07001984 {
1985 extern unsigned int __swapper_4m_tsb_phys_patch;
1986 extern unsigned int __swapper_4m_tsb_phys_patch_end;
David S. Miller9076d0e2011-08-05 00:53:57 -07001987 ktsb_pa = (kern_base +
1988 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1989 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1990 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
David S. Miller0785a8e2011-08-06 05:26:35 -07001991 }
David S. Miller9076d0e2011-08-05 00:53:57 -07001992#endif
1993}
1994
David S. Miller490384e2006-02-11 14:41:18 -08001995static void __init sun4v_ktsb_init(void)
1996{
1997 unsigned long ktsb_pa;
1998
David S. Millerd7744a02006-02-21 22:31:11 -08001999 /* First KTSB for PAGE_SIZE mappings. */
David S. Miller490384e2006-02-11 14:41:18 -08002000 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2001
2002 switch (PAGE_SIZE) {
2003 case 8 * 1024:
2004 default:
2005 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2006 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2007 break;
2008
2009 case 64 * 1024:
2010 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2011 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2012 break;
2013
2014 case 512 * 1024:
2015 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2016 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2017 break;
2018
2019 case 4 * 1024 * 1024:
2020 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2021 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2022 break;
Joe Perches6cb79b32011-06-03 14:45:23 +00002023 }
David S. Miller490384e2006-02-11 14:41:18 -08002024
David S. Miller3f19a842006-02-17 12:03:20 -08002025 ktsb_descr[0].assoc = 1;
David S. Miller490384e2006-02-11 14:41:18 -08002026 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2027 ktsb_descr[0].ctx_idx = 0;
2028 ktsb_descr[0].tsb_base = ktsb_pa;
2029 ktsb_descr[0].resv = 0;
2030
David S. Millerd1acb422007-03-16 17:20:28 -07002031#ifndef CONFIG_DEBUG_PAGEALLOC
David S. Miller4f93d212012-09-06 18:13:58 -07002032 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
David S. Millerd7744a02006-02-21 22:31:11 -08002033 ktsb_pa = (kern_base +
2034 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2035
2036 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
David S. Millerc69ad0a2012-09-06 20:35:36 -07002037 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2038 HV_PGSZ_MASK_256MB |
2039 HV_PGSZ_MASK_2GB |
2040 HV_PGSZ_MASK_16GB) &
2041 cpu_pgsz_mask);
David S. Millerd7744a02006-02-21 22:31:11 -08002042 ktsb_descr[1].assoc = 1;
2043 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2044 ktsb_descr[1].ctx_idx = 0;
2045 ktsb_descr[1].tsb_base = ktsb_pa;
2046 ktsb_descr[1].resv = 0;
David S. Millerd1acb422007-03-16 17:20:28 -07002047#endif
David S. Miller490384e2006-02-11 14:41:18 -08002048}
2049
Paul Gortmaker2066aad2013-06-17 15:43:14 -04002050void sun4v_ktsb_register(void)
David S. Miller490384e2006-02-11 14:41:18 -08002051{
David S. Miller7db35f32007-05-29 02:22:14 -07002052 unsigned long pa, ret;
David S. Miller490384e2006-02-11 14:41:18 -08002053
2054 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2055
David S. Miller7db35f32007-05-29 02:22:14 -07002056 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2057 if (ret != 0) {
2058 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2059 "errors with %lx\n", pa, ret);
2060 prom_halt();
2061 }
David S. Miller490384e2006-02-11 14:41:18 -08002062}
2063
David S. Millerc69ad0a2012-09-06 20:35:36 -07002064static void __init sun4u_linear_pte_xor_finalize(void)
2065{
2066#ifndef CONFIG_DEBUG_PAGEALLOC
2067 /* This is where we would add Panther support for
2068 * 32MB and 256MB pages.
2069 */
2070#endif
2071}
2072
2073static void __init sun4v_linear_pte_xor_finalize(void)
2074{
Khalid Aziz494e5b62015-05-27 10:00:46 -06002075 unsigned long pagecv_flag;
2076
2077 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2078 * enables MCD error. Do not set bit 9 on M7 processor.
2079 */
2080 switch (sun4v_chip_type) {
2081 case SUN4V_CHIP_SPARC_M7:
Khalid Azizc5b8b5b2016-04-19 11:12:54 -06002082 case SUN4V_CHIP_SPARC_SN:
Khalid Aziz494e5b62015-05-27 10:00:46 -06002083 pagecv_flag = 0x00;
2084 break;
2085 default:
2086 pagecv_flag = _PAGE_CV_4V;
2087 break;
2088 }
David S. Millerc69ad0a2012-09-06 20:35:36 -07002089#ifndef CONFIG_DEBUG_PAGEALLOC
2090 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2091 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
David S. Miller922631b2013-09-18 12:00:00 -07002092 PAGE_OFFSET;
Khalid Aziz494e5b62015-05-27 10:00:46 -06002093 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
David S. Millerc69ad0a2012-09-06 20:35:36 -07002094 _PAGE_P_4V | _PAGE_W_4V);
2095 } else {
2096 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2097 }
2098
2099 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2100 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
David S. Miller922631b2013-09-18 12:00:00 -07002101 PAGE_OFFSET;
Khalid Aziz494e5b62015-05-27 10:00:46 -06002102 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
David S. Millerc69ad0a2012-09-06 20:35:36 -07002103 _PAGE_P_4V | _PAGE_W_4V);
2104 } else {
2105 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2106 }
2107
2108 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2109 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
David S. Miller922631b2013-09-18 12:00:00 -07002110 PAGE_OFFSET;
Khalid Aziz494e5b62015-05-27 10:00:46 -06002111 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
David S. Millerc69ad0a2012-09-06 20:35:36 -07002112 _PAGE_P_4V | _PAGE_W_4V);
2113 } else {
2114 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2115 }
2116#endif
2117}
2118
Linus Torvalds1da177e2005-04-16 15:20:36 -07002119/* paging_init() sets up the page tables */
2120
Linus Torvalds1da177e2005-04-16 15:20:36 -07002121static unsigned long last_valid_pfn;
David S. Millerac55c762014-09-26 21:19:46 -07002122
David S. Millerc4bce902006-02-11 21:57:54 -08002123static void sun4u_pgprot_init(void);
2124static void sun4v_pgprot_init(void);
2125
bob picco7c21d532014-09-16 09:29:54 -04002126static phys_addr_t __init available_memory(void)
2127{
2128 phys_addr_t available = 0ULL;
2129 phys_addr_t pa_start, pa_end;
2130 u64 i;
2131
Tony Luckfc6daaf2015-06-24 16:58:09 -07002132 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2133 &pa_end, NULL)
bob picco7c21d532014-09-16 09:29:54 -04002134 available = available + (pa_end - pa_start);
2135
2136 return available;
2137}
2138
Khalid Aziz494e5b62015-05-27 10:00:46 -06002139#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2140#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2141#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2142#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2143#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2144#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2145
bob picco7c21d532014-09-16 09:29:54 -04002146/* We need to exclude reserved regions. This exclusion will include
2147 * vmlinux and initrd. To be more precise the initrd size could be used to
2148 * compute a new lower limit because it is freed later during initialization.
2149 */
2150static void __init reduce_memory(phys_addr_t limit_ram)
2151{
2152 phys_addr_t avail_ram = available_memory();
2153 phys_addr_t pa_start, pa_end;
2154 u64 i;
2155
2156 if (limit_ram >= avail_ram)
2157 return;
2158
Tony Luckfc6daaf2015-06-24 16:58:09 -07002159 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2160 &pa_end, NULL) {
bob picco7c21d532014-09-16 09:29:54 -04002161 phys_addr_t region_size = pa_end - pa_start;
2162 phys_addr_t clip_start = pa_start;
2163
2164 avail_ram = avail_ram - region_size;
2165 /* Are we consuming too much? */
2166 if (avail_ram < limit_ram) {
2167 phys_addr_t give_back = limit_ram - avail_ram;
2168
2169 region_size = region_size - give_back;
2170 clip_start = clip_start + give_back;
2171 }
2172
2173 memblock_remove(clip_start, region_size);
2174
2175 if (avail_ram <= limit_ram)
2176 break;
2177 i = 0UL;
2178 }
2179}
2180
Linus Torvalds1da177e2005-04-16 15:20:36 -07002181void __init paging_init(void)
2182{
David S. Miller919ee672008-04-23 05:40:25 -07002183 unsigned long end_pfn, shift, phys_base;
David S. Miller0836a0e2005-09-28 21:38:08 -07002184 unsigned long real_end, i;
2185
David S. Millerb2d43832013-09-20 21:50:41 -07002186 setup_page_offset();
2187
David S. Miller22adb352007-05-26 01:14:43 -07002188 /* These build time checkes make sure that the dcache_dirty_cpu()
2189 * page->flags usage will work.
2190 *
2191 * When a page gets marked as dcache-dirty, we store the
2192 * cpu number starting at bit 32 in the page->flags. Also,
2193 * functions like clear_dcache_dirty_cpu use the cpu mask
2194 * in 13-bit signed-immediate instruction fields.
2195 */
Christoph Lameter9223b412008-04-28 02:12:48 -07002196
2197 /*
2198 * Page flags must not reach into upper 32 bits that are used
2199 * for the cpu number
2200 */
2201 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2202
2203 /*
2204 * The bit fields placed in the high range must not reach below
2205 * the 32 bit boundary. Otherwise we cannot place the cpu field
2206 * at the 32 bit boundary.
2207 */
David S. Miller22adb352007-05-26 01:14:43 -07002208 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
Christoph Lameter9223b412008-04-28 02:12:48 -07002209 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2210
David S. Miller22adb352007-05-26 01:14:43 -07002211 BUILD_BUG_ON(NR_CPUS > 4096);
2212
David S. Miller0eef3312014-05-03 22:52:50 -07002213 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
David S. Miller481295f2006-02-07 21:51:08 -08002214 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2215
David S. Millerd7744a02006-02-21 22:31:11 -08002216 /* Invalidate both kernel TSBs. */
David S. Miller8b234272006-02-17 18:01:02 -08002217 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
David S. Millerd1acb422007-03-16 17:20:28 -07002218#ifndef CONFIG_DEBUG_PAGEALLOC
David S. Millerd7744a02006-02-21 22:31:11 -08002219 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
David S. Millerd1acb422007-03-16 17:20:28 -07002220#endif
David S. Miller8b234272006-02-17 18:01:02 -08002221
Khalid Aziz494e5b62015-05-27 10:00:46 -06002222 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2223 * bit on M7 processor. This is a conflicting usage of the same
2224 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2225 * Detection error on all pages and this will lead to problems
2226 * later. Kernel does not run with MCD enabled and hence rest
2227 * of the required steps to fully configure memory corruption
2228 * detection are not taken. We need to ensure TTE.mcde is not
2229 * set on M7 processor. Compute the value of cacheability
2230 * flag for use later taking this into consideration.
2231 */
2232 switch (sun4v_chip_type) {
2233 case SUN4V_CHIP_SPARC_M7:
Khalid Azizc5b8b5b2016-04-19 11:12:54 -06002234 case SUN4V_CHIP_SPARC_SN:
Khalid Aziz494e5b62015-05-27 10:00:46 -06002235 page_cache4v_flag = _PAGE_CP_4V;
2236 break;
2237 default:
2238 page_cache4v_flag = _PAGE_CACHE_4V;
2239 break;
2240 }
2241
David S. Millerc4bce902006-02-11 21:57:54 -08002242 if (tlb_type == hypervisor)
2243 sun4v_pgprot_init();
2244 else
2245 sun4u_pgprot_init();
2246
David S. Millerd257d5d2006-02-06 23:44:37 -08002247 if (tlb_type == cheetah_plus ||
David S. Miller9076d0e2011-08-05 00:53:57 -07002248 tlb_type == hypervisor) {
David S. Miller517af332006-02-01 15:55:21 -08002249 tsb_phys_patch();
David S. Miller9076d0e2011-08-05 00:53:57 -07002250 ktsb_phys_patch();
2251 }
David S. Miller517af332006-02-01 15:55:21 -08002252
David S. Millerc69ad0a2012-09-06 20:35:36 -07002253 if (tlb_type == hypervisor)
David S. Millerd257d5d2006-02-06 23:44:37 -08002254 sun4v_patch_tlb_handlers();
2255
David S. Millera94a1722008-05-11 21:04:48 -07002256 /* Find available physical memory...
2257 *
2258 * Read it twice in order to work around a bug in openfirmware.
2259 * The call to grab this table itself can cause openfirmware to
2260 * allocate memory, which in turn can take away some space from
2261 * the list of available memory. Reading it twice makes sure
2262 * we really do get the final value.
2263 */
2264 read_obp_translations();
2265 read_obp_memory("reg", &pall[0], &pall_ents);
2266 read_obp_memory("available", &pavail[0], &pavail_ents);
David S. Miller13edad72005-09-29 17:58:26 -07002267 read_obp_memory("available", &pavail[0], &pavail_ents);
David S. Miller0836a0e2005-09-28 21:38:08 -07002268
2269 phys_base = 0xffffffffffffffffUL;
David S. Miller3b2a7e22008-02-13 18:13:20 -08002270 for (i = 0; i < pavail_ents; i++) {
David S. Miller13edad72005-09-29 17:58:26 -07002271 phys_base = min(phys_base, pavail[i].phys_addr);
Yinghai Lu95f72d12010-07-12 14:36:09 +10002272 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
David S. Miller3b2a7e22008-02-13 18:13:20 -08002273 }
2274
Yinghai Lu95f72d12010-07-12 14:36:09 +10002275 memblock_reserve(kern_base, kern_size);
David S. Miller0836a0e2005-09-28 21:38:08 -07002276
David S. Miller4e82c9a2008-02-13 18:00:03 -08002277 find_ramdisk(phys_base);
2278
bob picco7c21d532014-09-16 09:29:54 -04002279 if (cmdline_memory_size)
2280 reduce_memory(cmdline_memory_size);
David S. Miller25b0c652008-02-13 18:20:14 -08002281
Tejun Heo1aadc052011-12-08 10:22:08 -08002282 memblock_allow_resize();
Yinghai Lu95f72d12010-07-12 14:36:09 +10002283 memblock_dump_all();
David S. Miller3b2a7e22008-02-13 18:13:20 -08002284
Linus Torvalds1da177e2005-04-16 15:20:36 -07002285 set_bit(0, mmu_context_bmap);
2286
David S. Miller2bdb3cb2005-09-22 01:08:57 -07002287 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2288
Linus Torvalds1da177e2005-04-16 15:20:36 -07002289 real_end = (unsigned long)_end;
David S. Miller0eef3312014-05-03 22:52:50 -07002290 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
David S. Miller64658742008-03-21 17:01:38 -07002291 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2292 num_kernel_image_mappings);
David S. Miller2bdb3cb2005-09-22 01:08:57 -07002293
2294 /* Set kernel pgd to upper alias so physical page computations
Linus Torvalds1da177e2005-04-16 15:20:36 -07002295 * work.
2296 */
2297 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2298
David S. Millerd195b712014-09-27 21:30:57 -07002299 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
David S. Miller0dd5b7b2014-09-24 20:56:11 -07002300
David S. Millerc9c10832005-10-12 12:22:46 -07002301 inherit_prom_mappings();
David S. Miller5085b4a2005-09-22 00:45:41 -07002302
David S. Millera8b900d2006-01-31 18:33:37 -08002303 /* Ok, we can use our TLB miss and window trap handlers safely. */
2304 setup_tba();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002305
David S. Millerc9c10832005-10-12 12:22:46 -07002306 __flush_tlb_all();
David S. Miller9ad98c52005-10-05 15:12:00 -07002307
David S. Millerad072002008-02-13 19:21:51 -08002308 prom_build_devicetree();
David S. Millerb696fdc2009-05-26 22:37:25 -07002309 of_populate_present_mask();
David S. Millerb99c6eb2009-06-18 01:44:19 -07002310#ifndef CONFIG_SMP
2311 of_fill_in_cpu_data();
2312#endif
David S. Millerad072002008-02-13 19:21:51 -08002313
David S. Miller890db402009-04-01 03:13:15 -07002314 if (tlb_type == hypervisor) {
David S. Miller4a283332008-02-13 19:22:23 -08002315 sun4v_mdesc_init();
Stephen Rothwell6ac5c612009-06-15 03:06:18 -07002316 mdesc_populate_present_mask(cpu_all_mask);
David S. Millerb99c6eb2009-06-18 01:44:19 -07002317#ifndef CONFIG_SMP
2318 mdesc_fill_in_cpu_data(cpu_all_mask);
2319#endif
David S. Millerce33fdc2012-09-06 19:01:25 -07002320 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
David S. Millerc69ad0a2012-09-06 20:35:36 -07002321
2322 sun4v_linear_pte_xor_finalize();
2323
2324 sun4v_ktsb_init();
2325 sun4v_ktsb_register();
David S. Millerce33fdc2012-09-06 19:01:25 -07002326 } else {
2327 unsigned long impl, ver;
2328
2329 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2330 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2331
2332 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2333 impl = ((ver >> 32) & 0xffff);
2334 if (impl == PANTHER_IMPL)
2335 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2336 HV_PGSZ_MASK_256MB);
David S. Millerc69ad0a2012-09-06 20:35:36 -07002337
2338 sun4u_linear_pte_xor_finalize();
David S. Miller890db402009-04-01 03:13:15 -07002339 }
David S. Miller4a283332008-02-13 19:22:23 -08002340
David S. Millerc69ad0a2012-09-06 20:35:36 -07002341 /* Flush the TLBs and the 4M TSB so that the updated linear
2342 * pte XOR settings are realized for all mappings.
2343 */
2344 __flush_tlb_all();
2345#ifndef CONFIG_DEBUG_PAGEALLOC
2346 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2347#endif
2348 __flush_tlb_all();
2349
David S. Miller2bdb3cb2005-09-22 01:08:57 -07002350 /* Setup bootmem... */
David S. Miller919ee672008-04-23 05:40:25 -07002351 last_valid_pfn = end_pfn = bootmem_init(phys_base);
David S. Millerd1112012006-03-08 02:16:07 -08002352
David S. Miller56425302005-09-25 16:46:57 -07002353 kernel_physical_mapping_init();
David S. Miller56425302005-09-25 16:46:57 -07002354
Linus Torvalds1da177e2005-04-16 15:20:36 -07002355 {
David S. Miller919ee672008-04-23 05:40:25 -07002356 unsigned long max_zone_pfns[MAX_NR_ZONES];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002357
David S. Miller919ee672008-04-23 05:40:25 -07002358 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002359
David S. Miller919ee672008-04-23 05:40:25 -07002360 max_zone_pfns[ZONE_NORMAL] = end_pfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002361
David S. Miller919ee672008-04-23 05:40:25 -07002362 free_area_init_nodes(max_zone_pfns);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002363 }
2364
David S. Miller3c62a2d2008-02-17 23:22:50 -08002365 printk("Booting Linux...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002366}
2367
Greg Kroah-Hartman7c9503b2012-12-21 14:03:26 -08002368int page_in_phys_avail(unsigned long paddr)
David S. Miller919ee672008-04-23 05:40:25 -07002369{
2370 int i;
2371
2372 paddr &= PAGE_MASK;
2373
2374 for (i = 0; i < pavail_ents; i++) {
2375 unsigned long start, end;
2376
2377 start = pavail[i].phys_addr;
2378 end = start + pavail[i].reg_size;
2379
2380 if (paddr >= start && paddr < end)
2381 return 1;
2382 }
2383 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2384 return 1;
2385#ifdef CONFIG_BLK_DEV_INITRD
2386 if (paddr >= __pa(initrd_start) &&
2387 paddr < __pa(PAGE_ALIGN(initrd_end)))
2388 return 1;
2389#endif
2390
2391 return 0;
2392}
2393
Yinghai Lu961f8fa2012-11-16 19:39:21 -08002394static void __init register_page_bootmem_info(void)
2395{
2396#ifdef CONFIG_NEED_MULTIPLE_NODES
2397 int i;
2398
2399 for_each_online_node(i)
2400 if (NODE_DATA(i)->node_spanned_pages)
2401 register_page_bootmem_info_node(NODE_DATA(i));
2402#endif
2403}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002404void __init mem_init(void)
2405{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002406 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2407
Yinghai Lu961f8fa2012-11-16 19:39:21 -08002408 register_page_bootmem_info();
Jiang Liu0c988532013-07-03 15:03:24 -07002409 free_all_bootmem();
David S. Miller919ee672008-04-23 05:40:25 -07002410
Linus Torvalds1da177e2005-04-16 15:20:36 -07002411 /*
2412 * Set up the zero page, mark it reserved, so that page count
2413 * is not manipulated when freeing the page from user ptes.
2414 */
2415 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2416 if (mem_map_zero == NULL) {
2417 prom_printf("paging_init: Cannot alloc zero page.\n");
2418 prom_halt();
2419 }
Jiang Liu70affe42013-05-07 16:18:08 -07002420 mark_page_reserved(mem_map_zero);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002421
Jiang Liudceccbe2013-07-03 15:04:14 -07002422 mem_init_print_info(NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002423
2424 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2425 cheetah_ecache_flush_init();
2426}
2427
David S. Miller898cf0e2005-09-23 11:59:44 -07002428void free_initmem(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002429{
2430 unsigned long addr, initend;
David S. Millerf2b60792008-08-14 01:45:41 -07002431 int do_free = 1;
2432
2433 /* If the physical memory maps were trimmed by kernel command
2434 * line options, don't even try freeing this initmem stuff up.
2435 * The kernel image could have been in the trimmed out region
2436 * and if so the freeing below will free invalid page structs.
2437 */
2438 if (cmdline_memory_size)
2439 do_free = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002440
2441 /*
2442 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2443 */
2444 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2445 initend = (unsigned long)(__init_end) & PAGE_MASK;
2446 for (; addr < initend; addr += PAGE_SIZE) {
2447 unsigned long page;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002448
2449 page = (addr +
2450 ((unsigned long) __va(kern_base)) -
2451 ((unsigned long) KERNBASE));
Randy Dunlapc9cf5522006-06-27 02:53:52 -07002452 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002453
Jiang Liu70affe42013-05-07 16:18:08 -07002454 if (do_free)
2455 free_reserved_page(virt_to_page(page));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002456 }
2457}
2458
2459#ifdef CONFIG_BLK_DEV_INITRD
2460void free_initrd_mem(unsigned long start, unsigned long end)
2461{
Jiang Liudceccbe2013-07-03 15:04:14 -07002462 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2463 "initrd");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002464}
2465#endif
David S. Millerc4bce902006-02-11 21:57:54 -08002466
David S. Millerc4bce902006-02-11 21:57:54 -08002467pgprot_t PAGE_KERNEL __read_mostly;
2468EXPORT_SYMBOL(PAGE_KERNEL);
2469
2470pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2471pgprot_t PAGE_COPY __read_mostly;
David S. Miller0f159522006-02-18 12:43:16 -08002472
2473pgprot_t PAGE_SHARED __read_mostly;
2474EXPORT_SYMBOL(PAGE_SHARED);
2475
David S. Millerc4bce902006-02-11 21:57:54 -08002476unsigned long pg_iobits __read_mostly;
2477
2478unsigned long _PAGE_IE __read_mostly;
David S. Miller987c74f2006-06-25 01:34:43 -07002479EXPORT_SYMBOL(_PAGE_IE);
David S. Millerb2bef442006-02-23 01:55:55 -08002480
David S. Millerc4bce902006-02-11 21:57:54 -08002481unsigned long _PAGE_E __read_mostly;
David S. Millerb2bef442006-02-23 01:55:55 -08002482EXPORT_SYMBOL(_PAGE_E);
2483
David S. Millerc4bce902006-02-11 21:57:54 -08002484unsigned long _PAGE_CACHE __read_mostly;
David S. Millerb2bef442006-02-23 01:55:55 -08002485EXPORT_SYMBOL(_PAGE_CACHE);
David S. Millerc4bce902006-02-11 21:57:54 -08002486
David Miller46644c22007-10-16 01:24:16 -07002487#ifdef CONFIG_SPARSEMEM_VMEMMAP
Johannes Weiner0aad8182013-04-29 15:07:50 -07002488int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2489 int node)
David Miller46644c22007-10-16 01:24:16 -07002490{
David Miller46644c22007-10-16 01:24:16 -07002491 unsigned long pte_base;
2492
2493 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2494 _PAGE_CP_4U | _PAGE_CV_4U |
2495 _PAGE_P_4U | _PAGE_W_4U);
2496 if (tlb_type == hypervisor)
2497 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
Khalid Aziz494e5b62015-05-27 10:00:46 -06002498 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
David Miller46644c22007-10-16 01:24:16 -07002499
David S. Millerc06240c2014-09-24 21:20:14 -07002500 pte_base |= _PAGE_PMD_HUGE;
David Miller46644c22007-10-16 01:24:16 -07002501
David S. Millerc06240c2014-09-24 21:20:14 -07002502 vstart = vstart & PMD_MASK;
2503 vend = ALIGN(vend, PMD_SIZE);
2504 for (; vstart < vend; vstart += PMD_SIZE) {
2505 pgd_t *pgd = pgd_offset_k(vstart);
2506 unsigned long pte;
2507 pud_t *pud;
2508 pmd_t *pmd;
2509
2510 if (pgd_none(*pgd)) {
2511 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2512
2513 if (!new)
2514 return -ENOMEM;
2515 pgd_populate(&init_mm, pgd, new);
2516 }
2517
2518 pud = pud_offset(pgd, vstart);
2519 if (pud_none(*pud)) {
2520 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2521
2522 if (!new)
2523 return -ENOMEM;
2524 pud_populate(&init_mm, pud, new);
2525 }
2526
2527 pmd = pmd_offset(pud, vstart);
2528
2529 pte = pmd_val(*pmd);
2530 if (!(pte & _PAGE_VALID)) {
2531 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2532
David Miller46644c22007-10-16 01:24:16 -07002533 if (!block)
2534 return -ENOMEM;
2535
David S. Millerc06240c2014-09-24 21:20:14 -07002536 pmd_val(*pmd) = pte_base | __pa(block);
David Miller46644c22007-10-16 01:24:16 -07002537 }
2538 }
David S. Miller2856cc22012-08-15 00:37:29 -07002539
David S. Millerc06240c2014-09-24 21:20:14 -07002540 return 0;
David S. Miller2856cc22012-08-15 00:37:29 -07002541}
Yasuaki Ishimatsu46723bf2013-02-22 16:33:00 -08002542
Johannes Weiner0aad8182013-04-29 15:07:50 -07002543void vmemmap_free(unsigned long start, unsigned long end)
Tang Chen01975182013-02-22 16:33:08 -08002544{
2545}
David Miller46644c22007-10-16 01:24:16 -07002546#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2547
David S. Millerc4bce902006-02-11 21:57:54 -08002548static void prot_init_common(unsigned long page_none,
2549 unsigned long page_shared,
2550 unsigned long page_copy,
2551 unsigned long page_readonly,
2552 unsigned long page_exec_bit)
2553{
2554 PAGE_COPY = __pgprot(page_copy);
David S. Miller0f159522006-02-18 12:43:16 -08002555 PAGE_SHARED = __pgprot(page_shared);
David S. Millerc4bce902006-02-11 21:57:54 -08002556
2557 protection_map[0x0] = __pgprot(page_none);
2558 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2559 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2560 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2561 protection_map[0x4] = __pgprot(page_readonly);
2562 protection_map[0x5] = __pgprot(page_readonly);
2563 protection_map[0x6] = __pgprot(page_copy);
2564 protection_map[0x7] = __pgprot(page_copy);
2565 protection_map[0x8] = __pgprot(page_none);
2566 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2567 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2568 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2569 protection_map[0xc] = __pgprot(page_readonly);
2570 protection_map[0xd] = __pgprot(page_readonly);
2571 protection_map[0xe] = __pgprot(page_shared);
2572 protection_map[0xf] = __pgprot(page_shared);
2573}
2574
2575static void __init sun4u_pgprot_init(void)
2576{
2577 unsigned long page_none, page_shared, page_copy, page_readonly;
2578 unsigned long page_exec_bit;
David S. Miller4f93d212012-09-06 18:13:58 -07002579 int i;
David S. Millerc4bce902006-02-11 21:57:54 -08002580
2581 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2582 _PAGE_CACHE_4U | _PAGE_P_4U |
2583 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2584 _PAGE_EXEC_4U);
2585 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2586 _PAGE_CACHE_4U | _PAGE_P_4U |
2587 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2588 _PAGE_EXEC_4U | _PAGE_L_4U);
David S. Millerc4bce902006-02-11 21:57:54 -08002589
2590 _PAGE_IE = _PAGE_IE_4U;
2591 _PAGE_E = _PAGE_E_4U;
2592 _PAGE_CACHE = _PAGE_CACHE_4U;
2593
2594 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2595 __ACCESS_BITS_4U | _PAGE_E_4U);
2596
David S. Millerd1acb422007-03-16 17:20:28 -07002597#ifdef CONFIG_DEBUG_PAGEALLOC
David S. Miller922631b2013-09-18 12:00:00 -07002598 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
David S. Millerd1acb422007-03-16 17:20:28 -07002599#else
David S. Miller9cc3a1a2006-02-21 20:51:13 -08002600 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
David S. Miller922631b2013-09-18 12:00:00 -07002601 PAGE_OFFSET;
David S. Millerd1acb422007-03-16 17:20:28 -07002602#endif
David S. Miller9cc3a1a2006-02-21 20:51:13 -08002603 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2604 _PAGE_P_4U | _PAGE_W_4U);
2605
David S. Miller4f93d212012-09-06 18:13:58 -07002606 for (i = 1; i < 4; i++)
2607 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
David S. Millerc4bce902006-02-11 21:57:54 -08002608
David S. Millerc4bce902006-02-11 21:57:54 -08002609 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2610 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2611 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2612
2613
2614 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2615 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2616 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2617 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2618 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2619 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2620 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2621
2622 page_exec_bit = _PAGE_EXEC_4U;
2623
2624 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2625 page_exec_bit);
2626}
2627
2628static void __init sun4v_pgprot_init(void)
2629{
2630 unsigned long page_none, page_shared, page_copy, page_readonly;
2631 unsigned long page_exec_bit;
David S. Miller4f93d212012-09-06 18:13:58 -07002632 int i;
David S. Millerc4bce902006-02-11 21:57:54 -08002633
2634 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
Khalid Aziz494e5b62015-05-27 10:00:46 -06002635 page_cache4v_flag | _PAGE_P_4V |
David S. Millerc4bce902006-02-11 21:57:54 -08002636 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2637 _PAGE_EXEC_4V);
2638 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
David S. Millerc4bce902006-02-11 21:57:54 -08002639
2640 _PAGE_IE = _PAGE_IE_4V;
2641 _PAGE_E = _PAGE_E_4V;
Khalid Aziz494e5b62015-05-27 10:00:46 -06002642 _PAGE_CACHE = page_cache4v_flag;
David S. Millerc4bce902006-02-11 21:57:54 -08002643
David S. Millerd1acb422007-03-16 17:20:28 -07002644#ifdef CONFIG_DEBUG_PAGEALLOC
David S. Miller922631b2013-09-18 12:00:00 -07002645 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
David S. Millerd1acb422007-03-16 17:20:28 -07002646#else
David S. Miller9cc3a1a2006-02-21 20:51:13 -08002647 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
David S. Miller922631b2013-09-18 12:00:00 -07002648 PAGE_OFFSET;
David S. Millerd1acb422007-03-16 17:20:28 -07002649#endif
Khalid Aziz494e5b62015-05-27 10:00:46 -06002650 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2651 _PAGE_W_4V);
David S. Miller9cc3a1a2006-02-21 20:51:13 -08002652
David S. Millerc69ad0a2012-09-06 20:35:36 -07002653 for (i = 1; i < 4; i++)
2654 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
David S. Miller4f93d212012-09-06 18:13:58 -07002655
David S. Millerc4bce902006-02-11 21:57:54 -08002656 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2657 __ACCESS_BITS_4V | _PAGE_E_4V);
2658
David S. Millerc4bce902006-02-11 21:57:54 -08002659 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2660 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2661 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2662 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2663
Khalid Aziz494e5b62015-05-27 10:00:46 -06002664 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2665 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
David S. Millerc4bce902006-02-11 21:57:54 -08002666 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
Khalid Aziz494e5b62015-05-27 10:00:46 -06002667 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
David S. Millerc4bce902006-02-11 21:57:54 -08002668 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
Khalid Aziz494e5b62015-05-27 10:00:46 -06002669 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
David S. Millerc4bce902006-02-11 21:57:54 -08002670 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2671
2672 page_exec_bit = _PAGE_EXEC_4V;
2673
2674 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2675 page_exec_bit);
2676}
2677
2678unsigned long pte_sz_bits(unsigned long sz)
2679{
2680 if (tlb_type == hypervisor) {
2681 switch (sz) {
2682 case 8 * 1024:
2683 default:
2684 return _PAGE_SZ8K_4V;
2685 case 64 * 1024:
2686 return _PAGE_SZ64K_4V;
2687 case 512 * 1024:
2688 return _PAGE_SZ512K_4V;
2689 case 4 * 1024 * 1024:
2690 return _PAGE_SZ4MB_4V;
Joe Perches6cb79b32011-06-03 14:45:23 +00002691 }
David S. Millerc4bce902006-02-11 21:57:54 -08002692 } else {
2693 switch (sz) {
2694 case 8 * 1024:
2695 default:
2696 return _PAGE_SZ8K_4U;
2697 case 64 * 1024:
2698 return _PAGE_SZ64K_4U;
2699 case 512 * 1024:
2700 return _PAGE_SZ512K_4U;
2701 case 4 * 1024 * 1024:
2702 return _PAGE_SZ4MB_4U;
Joe Perches6cb79b32011-06-03 14:45:23 +00002703 }
David S. Millerc4bce902006-02-11 21:57:54 -08002704 }
2705}
2706
2707pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2708{
2709 pte_t pte;
David S. Millercf627152006-02-12 21:10:07 -08002710
2711 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
David S. Millerc4bce902006-02-11 21:57:54 -08002712 pte_val(pte) |= (((unsigned long)space) << 32);
2713 pte_val(pte) |= pte_sz_bits(page_size);
David S. Millercf627152006-02-12 21:10:07 -08002714
David S. Millerc4bce902006-02-11 21:57:54 -08002715 return pte;
2716}
2717
David S. Millerc4bce902006-02-11 21:57:54 -08002718static unsigned long kern_large_tte(unsigned long paddr)
2719{
2720 unsigned long val;
2721
2722 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2723 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2724 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2725 if (tlb_type == hypervisor)
2726 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
Khalid Aziz494e5b62015-05-27 10:00:46 -06002727 page_cache4v_flag | _PAGE_P_4V |
David S. Millerc4bce902006-02-11 21:57:54 -08002728 _PAGE_EXEC_4V | _PAGE_W_4V);
2729
2730 return val | paddr;
2731}
2732
David S. Millerc4bce902006-02-11 21:57:54 -08002733/* If not locked, zap it. */
2734void __flush_tlb_all(void)
2735{
2736 unsigned long pstate;
2737 int i;
2738
2739 __asm__ __volatile__("flushw\n\t"
2740 "rdpr %%pstate, %0\n\t"
2741 "wrpr %0, %1, %%pstate"
2742 : "=r" (pstate)
2743 : "i" (PSTATE_IE));
David S. Miller8f3614532007-12-13 06:13:38 -08002744 if (tlb_type == hypervisor) {
2745 sun4v_mmu_demap_all();
2746 } else if (tlb_type == spitfire) {
David S. Millerc4bce902006-02-11 21:57:54 -08002747 for (i = 0; i < 64; i++) {
2748 /* Spitfire Errata #32 workaround */
2749 /* NOTE: Always runs on spitfire, so no
2750 * cheetah+ page size encodings.
2751 */
2752 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2753 "flush %%g6"
2754 : /* No outputs */
2755 : "r" (0),
2756 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2757
2758 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2759 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2760 "membar #Sync"
2761 : /* no outputs */
2762 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2763 spitfire_put_dtlb_data(i, 0x0UL);
2764 }
2765
2766 /* Spitfire Errata #32 workaround */
2767 /* NOTE: Always runs on spitfire, so no
2768 * cheetah+ page size encodings.
2769 */
2770 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2771 "flush %%g6"
2772 : /* No outputs */
2773 : "r" (0),
2774 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2775
2776 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2777 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2778 "membar #Sync"
2779 : /* no outputs */
2780 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2781 spitfire_put_itlb_data(i, 0x0UL);
2782 }
2783 }
2784 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2785 cheetah_flush_dtlb_all();
2786 cheetah_flush_itlb_all();
2787 }
2788 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2789 : : "r" (pstate));
2790}
David Millerc460bec2012-10-08 16:34:22 -07002791
David Millerc460bec2012-10-08 16:34:22 -07002792pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2793 unsigned long address)
2794{
Michal Hocko32d6bd92016-06-24 14:48:47 -07002795 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
David S. Miller37b3a8f2013-09-25 13:48:49 -07002796 pte_t *pte = NULL;
David Millerc460bec2012-10-08 16:34:22 -07002797
David Millerc460bec2012-10-08 16:34:22 -07002798 if (page)
2799 pte = (pte_t *) page_address(page);
2800
2801 return pte;
2802}
2803
2804pgtable_t pte_alloc_one(struct mm_struct *mm,
2805 unsigned long address)
2806{
Michal Hocko32d6bd92016-06-24 14:48:47 -07002807 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
Kirill A. Shutemov1ae9ae52013-11-14 14:31:42 -08002808 if (!page)
2809 return NULL;
2810 if (!pgtable_page_ctor(page)) {
2811 free_hot_cold_page(page, 0);
2812 return NULL;
David Millerc460bec2012-10-08 16:34:22 -07002813 }
Kirill A. Shutemov1ae9ae52013-11-14 14:31:42 -08002814 return (pte_t *) page_address(page);
David Millerc460bec2012-10-08 16:34:22 -07002815}
2816
2817void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2818{
David S. Miller37b3a8f2013-09-25 13:48:49 -07002819 free_page((unsigned long)pte);
David Millerc460bec2012-10-08 16:34:22 -07002820}
2821
2822static void __pte_free(pgtable_t pte)
2823{
2824 struct page *page = virt_to_page(pte);
David S. Miller37b3a8f2013-09-25 13:48:49 -07002825
2826 pgtable_page_dtor(page);
2827 __free_page(page);
David Millerc460bec2012-10-08 16:34:22 -07002828}
2829
2830void pte_free(struct mm_struct *mm, pgtable_t pte)
2831{
2832 __pte_free(pte);
2833}
2834
2835void pgtable_free(void *table, bool is_page)
2836{
2837 if (is_page)
2838 __pte_free(table);
2839 else
2840 kmem_cache_free(pgtable_cache, table);
2841}
David Miller9e695d22012-10-08 16:34:29 -07002842
2843#ifdef CONFIG_TRANSPARENT_HUGEPAGE
David Miller9e695d22012-10-08 16:34:29 -07002844void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2845 pmd_t *pmd)
2846{
2847 unsigned long pte, flags;
2848 struct mm_struct *mm;
2849 pmd_t entry = *pmd;
David Miller9e695d22012-10-08 16:34:29 -07002850
2851 if (!pmd_large(entry) || !pmd_young(entry))
2852 return;
2853
David S. Millera7b94032013-09-26 13:45:15 -07002854 pte = pmd_val(entry);
David Miller9e695d22012-10-08 16:34:29 -07002855
David S. Miller18f38132014-08-04 16:34:01 -07002856 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2857 if (!(pte & _PAGE_VALID))
2858 return;
2859
David S. Miller37b3a8f2013-09-25 13:48:49 -07002860 /* We are fabricating 8MB pages using 4MB real hw pages. */
2861 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
David Miller9e695d22012-10-08 16:34:29 -07002862
2863 mm = vma->vm_mm;
2864
2865 spin_lock_irqsave(&mm->context.lock, flags);
2866
2867 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
David S. Miller37b3a8f2013-09-25 13:48:49 -07002868 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
David Miller9e695d22012-10-08 16:34:29 -07002869 addr, pte);
2870
2871 spin_unlock_irqrestore(&mm->context.lock, flags);
2872}
2873#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2874
2875#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2876static void context_reload(void *__data)
2877{
2878 struct mm_struct *mm = __data;
2879
2880 if (mm == current->mm)
2881 load_secondary_context(mm);
2882}
2883
David S. Miller0fbebed2013-02-19 22:34:10 -08002884void hugetlb_setup(struct pt_regs *regs)
David Miller9e695d22012-10-08 16:34:29 -07002885{
David S. Miller0fbebed2013-02-19 22:34:10 -08002886 struct mm_struct *mm = current->mm;
2887 struct tsb_config *tp;
David Miller9e695d22012-10-08 16:34:29 -07002888
David Hildenbrand70ffdb92015-05-11 17:52:11 +02002889 if (faulthandler_disabled() || !mm) {
David S. Miller0fbebed2013-02-19 22:34:10 -08002890 const struct exception_table_entry *entry;
David Miller9e695d22012-10-08 16:34:29 -07002891
David S. Miller0fbebed2013-02-19 22:34:10 -08002892 entry = search_exception_tables(regs->tpc);
2893 if (entry) {
2894 regs->tpc = entry->fixup;
2895 regs->tnpc = regs->tpc + 4;
2896 return;
2897 }
2898 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2899 die_if_kernel("HugeTSB in atomic", regs);
2900 }
2901
2902 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2903 if (likely(tp->tsb == NULL))
2904 tsb_grow(mm, MM_TSB_HUGE, 0);
2905
David Miller9e695d22012-10-08 16:34:29 -07002906 tsb_context_switch(mm);
2907 smp_tsb_sync(mm);
2908
2909 /* On UltraSPARC-III+ and later, configure the second half of
2910 * the Data-TLB for huge pages.
2911 */
2912 if (tlb_type == cheetah_plus) {
David S. Miller9ea46abe2016-05-25 12:51:20 -07002913 bool need_context_reload = false;
David Miller9e695d22012-10-08 16:34:29 -07002914 unsigned long ctx;
2915
David S. Miller9ea46abe2016-05-25 12:51:20 -07002916 spin_lock_irq(&ctx_alloc_lock);
David Miller9e695d22012-10-08 16:34:29 -07002917 ctx = mm->context.sparc64_ctx_val;
2918 ctx &= ~CTX_PGSZ_MASK;
2919 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2920 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2921
2922 if (ctx != mm->context.sparc64_ctx_val) {
2923 /* When changing the page size fields, we
2924 * must perform a context flush so that no
2925 * stale entries match. This flush must
2926 * occur with the original context register
2927 * settings.
2928 */
2929 do_flush_tlb_mm(mm);
2930
2931 /* Reload the context register of all processors
2932 * also executing in this address space.
2933 */
2934 mm->context.sparc64_ctx_val = ctx;
David S. Miller9ea46abe2016-05-25 12:51:20 -07002935 need_context_reload = true;
David Miller9e695d22012-10-08 16:34:29 -07002936 }
David S. Miller9ea46abe2016-05-25 12:51:20 -07002937 spin_unlock_irq(&ctx_alloc_lock);
2938
2939 if (need_context_reload)
2940 on_each_cpu(context_reload, mm, 0);
David Miller9e695d22012-10-08 16:34:29 -07002941 }
2942}
2943#endif
bob piccof6d4fb52014-03-03 11:54:42 -05002944
2945static struct resource code_resource = {
2946 .name = "Kernel code",
Toshi Kani35d98e92016-01-26 21:57:22 +01002947 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
bob piccof6d4fb52014-03-03 11:54:42 -05002948};
2949
2950static struct resource data_resource = {
2951 .name = "Kernel data",
Toshi Kani35d98e92016-01-26 21:57:22 +01002952 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
bob piccof6d4fb52014-03-03 11:54:42 -05002953};
2954
2955static struct resource bss_resource = {
2956 .name = "Kernel bss",
Toshi Kani35d98e92016-01-26 21:57:22 +01002957 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
bob piccof6d4fb52014-03-03 11:54:42 -05002958};
2959
2960static inline resource_size_t compute_kern_paddr(void *addr)
2961{
2962 return (resource_size_t) (addr - KERNBASE + kern_base);
2963}
2964
2965static void __init kernel_lds_init(void)
2966{
2967 code_resource.start = compute_kern_paddr(_text);
2968 code_resource.end = compute_kern_paddr(_etext - 1);
2969 data_resource.start = compute_kern_paddr(_etext);
2970 data_resource.end = compute_kern_paddr(_edata - 1);
2971 bss_resource.start = compute_kern_paddr(__bss_start);
2972 bss_resource.end = compute_kern_paddr(_end - 1);
2973}
2974
2975static int __init report_memory(void)
2976{
2977 int i;
2978 struct resource *res;
2979
2980 kernel_lds_init();
2981
2982 for (i = 0; i < pavail_ents; i++) {
2983 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2984
2985 if (!res) {
2986 pr_warn("Failed to allocate source.\n");
2987 break;
2988 }
2989
2990 res->name = "System RAM";
2991 res->start = pavail[i].phys_addr;
2992 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
Toshi Kani35d98e92016-01-26 21:57:22 +01002993 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
bob piccof6d4fb52014-03-03 11:54:42 -05002994
2995 if (insert_resource(&iomem_resource, res) < 0) {
2996 pr_warn("Resource insertion failed.\n");
2997 break;
2998 }
2999
3000 insert_resource(res, &code_resource);
3001 insert_resource(res, &data_resource);
3002 insert_resource(res, &bss_resource);
3003 }
3004
3005 return 0;
3006}
David S. Miller3c081582015-03-18 19:15:28 -07003007arch_initcall(report_memory);
David S. Millere9011d02014-08-05 18:57:18 -07003008
David S. Miller4ca9a232014-08-04 20:07:37 -07003009#ifdef CONFIG_SMP
3010#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3011#else
3012#define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3013#endif
3014
3015void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3016{
3017 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3018 if (start < LOW_OBP_ADDRESS) {
3019 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3020 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3021 }
3022 if (end > HI_OBP_ADDRESS) {
David S. Miller473ad7f2014-10-04 21:05:14 -07003023 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3024 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
David S. Miller4ca9a232014-08-04 20:07:37 -07003025 }
3026 } else {
3027 flush_tsb_kernel_range(start, end);
3028 do_flush_tlb_kernel_range(start, end);
3029 }
3030}