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Vimal Singh67ce04b2009-05-12 13:47:03 -07001/*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
Russell King763e7352012-04-25 00:16:00 +010012#include <linux/dmaengine.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070013#include <linux/dma-mapping.h>
14#include <linux/delay.h>
Paul Gortmakera0e5cc52011-07-03 15:17:31 -040015#include <linux/module.h>
Sukumar Ghorai4e070372011-01-28 15:42:06 +053016#include <linux/interrupt.h>
vimal singhc276aca2009-06-27 11:07:06 +053017#include <linux/jiffies.h>
18#include <linux/sched.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070019#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
Russell King763e7352012-04-25 00:16:00 +010022#include <linux/omap-dma.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070023#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Philip Avinash62116e52013-01-04 13:26:51 +053025#include <linux/of.h>
26#include <linux/of_device.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070027
Pekon Gupta32d42a82013-10-24 18:20:23 +053028#include <linux/mtd/nand_bch.h>
Philip Avinash62116e52013-01-04 13:26:51 +053029#include <linux/platform_data/elm.h>
Ivan Djelic0e618ef2012-04-30 12:17:18 +020030
Arnd Bergmann22037472012-08-24 15:21:06 +020031#include <linux/platform_data/mtd-nand-omap2.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070032
Vimal Singh67ce04b2009-05-12 13:47:03 -070033#define DRIVER_NAME "omap2-nand"
Sukumar Ghorai4e070372011-01-28 15:42:06 +053034#define OMAP_NAND_TIMEOUT_MS 5000
Vimal Singh67ce04b2009-05-12 13:47:03 -070035
Vimal Singh67ce04b2009-05-12 13:47:03 -070036#define NAND_Ecc_P1e (1 << 0)
37#define NAND_Ecc_P2e (1 << 1)
38#define NAND_Ecc_P4e (1 << 2)
39#define NAND_Ecc_P8e (1 << 3)
40#define NAND_Ecc_P16e (1 << 4)
41#define NAND_Ecc_P32e (1 << 5)
42#define NAND_Ecc_P64e (1 << 6)
43#define NAND_Ecc_P128e (1 << 7)
44#define NAND_Ecc_P256e (1 << 8)
45#define NAND_Ecc_P512e (1 << 9)
46#define NAND_Ecc_P1024e (1 << 10)
47#define NAND_Ecc_P2048e (1 << 11)
48
49#define NAND_Ecc_P1o (1 << 16)
50#define NAND_Ecc_P2o (1 << 17)
51#define NAND_Ecc_P4o (1 << 18)
52#define NAND_Ecc_P8o (1 << 19)
53#define NAND_Ecc_P16o (1 << 20)
54#define NAND_Ecc_P32o (1 << 21)
55#define NAND_Ecc_P64o (1 << 22)
56#define NAND_Ecc_P128o (1 << 23)
57#define NAND_Ecc_P256o (1 << 24)
58#define NAND_Ecc_P512o (1 << 25)
59#define NAND_Ecc_P1024o (1 << 26)
60#define NAND_Ecc_P2048o (1 << 27)
61
62#define TF(value) (value ? 1 : 0)
63
64#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72
73#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81
82#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90
91#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99
100#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700103#define PREFETCH_CONFIG1_CS_SHIFT 24
104#define ECC_CONFIG_CS_SHIFT 1
105#define CS_MASK 0x7
106#define ENABLE_PREFETCH (0x1 << 7)
107#define DMA_MPU_MODE_SHIFT 2
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +0530108#define ECCSIZE0_SHIFT 12
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700109#define ECCSIZE1_SHIFT 22
110#define ECC1RESULTSIZE 0x1
111#define ECCCLEAR 0x100
112#define ECC1 0x1
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530113#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117#define STATUS_BUFF_EMPTY 0x00000001
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700118
Lokesh Vutlad5e7c862012-10-15 14:03:51 -0700119#define OMAP24XX_DMA_GPMC 4
120
Philip Avinashc3e4b992013-01-04 13:26:49 +0530121#define BCH8_MAX_ERROR 8 /* upto 8 bit correctable */
122#define BCH4_MAX_ERROR 4 /* upto 4 bit correctable */
123
Philip Avinash62116e52013-01-04 13:26:51 +0530124#define SECTOR_BYTES 512
125/* 4 bit padding to make byte aligned, 56 = 52 + 4 */
126#define BCH4_BIT_PAD 4
127#define BCH8_ECC_MAX ((SECTOR_BYTES + BCH8_ECC_OOB_BYTES) * 8)
128#define BCH4_ECC_MAX ((SECTOR_BYTES + BCH4_ECC_OOB_BYTES) * 8)
129
130/* GPMC ecc engine settings for read */
131#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
132#define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
133#define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
134#define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
135#define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
136
137/* GPMC ecc engine settings for write */
138#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
139#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
140#define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
141
Pekon Guptab491da72013-10-24 18:20:22 +0530142#define BADBLOCK_MARKER_LENGTH 2
Pekon Guptaa919e512013-10-24 18:20:21 +0530143
Philip Avinash62116e52013-01-04 13:26:51 +0530144#ifdef CONFIG_MTD_NAND_OMAP_BCH
145static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
146 0xac, 0x6b, 0xff, 0x99, 0x7b};
147static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
148#endif
149
Sukumar Ghoraif040d332011-01-28 15:42:09 +0530150/* oob info generated runtime depending on ecc algorithm and layout selected */
151static struct nand_ecclayout omap_oobinfo;
vimal singh59e9c5a2009-07-13 16:26:24 +0530152
Vimal Singh67ce04b2009-05-12 13:47:03 -0700153struct omap_nand_info {
154 struct nand_hw_control controller;
155 struct omap_nand_platform_data *pdata;
156 struct mtd_info mtd;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700157 struct nand_chip nand;
158 struct platform_device *pdev;
159
160 int gpmc_cs;
161 unsigned long phys_base;
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -0700162 unsigned long mem_size;
Pekon Gupta4e558072014-03-18 18:56:42 +0530163 enum omap_ecc ecc_opt;
vimal singhdfe32892009-07-13 16:29:16 +0530164 struct completion comp;
Russell King763e7352012-04-25 00:16:00 +0100165 struct dma_chan *dma;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700166 int gpmc_irq_fifo;
167 int gpmc_irq_count;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530168 enum {
169 OMAP_NAND_IO_READ = 0, /* read */
170 OMAP_NAND_IO_WRITE, /* write */
171 } iomode;
172 u_char *buf;
173 int buf_len;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700174 struct gpmc_nand_regs reg;
Pekon Guptaa919e512013-10-24 18:20:21 +0530175 /* fields specific for BCHx_HW ECC scheme */
Philip Avinash62116e52013-01-04 13:26:51 +0530176 bool is_elm_used;
177 struct device *elm_dev;
178 struct device_node *of_node;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700179};
180
181/**
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700182 * omap_prefetch_enable - configures and starts prefetch transfer
183 * @cs: cs (chip select) number
184 * @fifo_th: fifo threshold to be used for read/ write
185 * @dma_mode: dma mode enable (1) or disable (0)
186 * @u32_count: number of bytes to be transferred
187 * @is_write: prefetch read(0) or write post(1) mode
188 */
189static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
190 unsigned int u32_count, int is_write, struct omap_nand_info *info)
191{
192 u32 val;
193
194 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
195 return -1;
196
197 if (readl(info->reg.gpmc_prefetch_control))
198 return -EBUSY;
199
200 /* Set the amount of bytes to be prefetched */
201 writel(u32_count, info->reg.gpmc_prefetch_config2);
202
203 /* Set dma/mpu mode, the prefetch read / post write and
204 * enable the engine. Set which cs is has requested for.
205 */
206 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
207 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
208 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
209 writel(val, info->reg.gpmc_prefetch_config1);
210
211 /* Start the prefetch engine */
212 writel(0x1, info->reg.gpmc_prefetch_control);
213
214 return 0;
215}
216
217/**
218 * omap_prefetch_reset - disables and stops the prefetch engine
219 */
220static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
221{
222 u32 config1;
223
224 /* check if the same module/cs is trying to reset */
225 config1 = readl(info->reg.gpmc_prefetch_config1);
226 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
227 return -EINVAL;
228
229 /* Stop the PFPW engine */
230 writel(0x0, info->reg.gpmc_prefetch_control);
231
232 /* Reset/disable the PFPW engine */
233 writel(0x0, info->reg.gpmc_prefetch_config1);
234
235 return 0;
236}
237
238/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700239 * omap_hwcontrol - hardware specific access to control-lines
240 * @mtd: MTD device structure
241 * @cmd: command to device
242 * @ctrl:
243 * NAND_NCE: bit 0 -> don't care
244 * NAND_CLE: bit 1 -> Command Latch
245 * NAND_ALE: bit 2 -> Address Latch
246 *
247 * NOTE: boards may use different bits for these!!
248 */
249static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
250{
251 struct omap_nand_info *info = container_of(mtd,
252 struct omap_nand_info, mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700253
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000254 if (cmd != NAND_CMD_NONE) {
255 if (ctrl & NAND_CLE)
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700256 writeb(cmd, info->reg.gpmc_nand_command);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700257
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000258 else if (ctrl & NAND_ALE)
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700259 writeb(cmd, info->reg.gpmc_nand_address);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000260
261 else /* NAND_NCE */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700262 writeb(cmd, info->reg.gpmc_nand_data);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700263 }
Vimal Singh67ce04b2009-05-12 13:47:03 -0700264}
265
266/**
vimal singh59e9c5a2009-07-13 16:26:24 +0530267 * omap_read_buf8 - read data from NAND controller into buffer
268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
271 */
272static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
273{
274 struct nand_chip *nand = mtd->priv;
275
276 ioread8_rep(nand->IO_ADDR_R, buf, len);
277}
278
279/**
280 * omap_write_buf8 - write buffer to NAND controller
281 * @mtd: MTD device structure
282 * @buf: data buffer
283 * @len: number of bytes to write
284 */
285static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
286{
287 struct omap_nand_info *info = container_of(mtd,
288 struct omap_nand_info, mtd);
289 u_char *p = (u_char *)buf;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000290 u32 status = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530291
292 while (len--) {
293 iowrite8(*p++, info->nand.IO_ADDR_W);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000294 /* wait until buffer is available for write */
295 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700296 status = readl(info->reg.gpmc_status) &
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530297 STATUS_BUFF_EMPTY;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000298 } while (!status);
vimal singh59e9c5a2009-07-13 16:26:24 +0530299 }
300}
301
302/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700303 * omap_read_buf16 - read data from NAND controller into buffer
304 * @mtd: MTD device structure
305 * @buf: buffer to store date
306 * @len: number of bytes to read
307 */
308static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
309{
310 struct nand_chip *nand = mtd->priv;
311
vimal singh59e9c5a2009-07-13 16:26:24 +0530312 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700313}
314
315/**
316 * omap_write_buf16 - write buffer to NAND controller
317 * @mtd: MTD device structure
318 * @buf: data buffer
319 * @len: number of bytes to write
320 */
321static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
322{
323 struct omap_nand_info *info = container_of(mtd,
324 struct omap_nand_info, mtd);
325 u16 *p = (u16 *) buf;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000326 u32 status = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700327 /* FIXME try bursts of writesw() or DMA ... */
328 len >>= 1;
329
330 while (len--) {
vimal singh59e9c5a2009-07-13 16:26:24 +0530331 iowrite16(*p++, info->nand.IO_ADDR_W);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000332 /* wait until buffer is available for write */
333 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700334 status = readl(info->reg.gpmc_status) &
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530335 STATUS_BUFF_EMPTY;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000336 } while (!status);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700337 }
338}
vimal singh59e9c5a2009-07-13 16:26:24 +0530339
340/**
341 * omap_read_buf_pref - read data from NAND controller into buffer
342 * @mtd: MTD device structure
343 * @buf: buffer to store date
344 * @len: number of bytes to read
345 */
346static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
347{
348 struct omap_nand_info *info = container_of(mtd,
349 struct omap_nand_info, mtd);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000350 uint32_t r_count = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530351 int ret = 0;
352 u32 *p = (u32 *)buf;
353
354 /* take care of subpage reads */
Vimal Singhc3341d02010-01-07 12:16:26 +0530355 if (len % 4) {
356 if (info->nand.options & NAND_BUSWIDTH_16)
357 omap_read_buf16(mtd, buf, len % 4);
358 else
359 omap_read_buf8(mtd, buf, len % 4);
360 p = (u32 *) (buf + len % 4);
361 len -= len % 4;
vimal singh59e9c5a2009-07-13 16:26:24 +0530362 }
vimal singh59e9c5a2009-07-13 16:26:24 +0530363
364 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700365 ret = omap_prefetch_enable(info->gpmc_cs,
366 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530367 if (ret) {
368 /* PFPW engine is busy, use cpu copy method */
369 if (info->nand.options & NAND_BUSWIDTH_16)
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530370 omap_read_buf16(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530371 else
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530372 omap_read_buf8(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530373 } else {
374 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700375 r_count = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530376 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000377 r_count = r_count >> 2;
378 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
vimal singh59e9c5a2009-07-13 16:26:24 +0530379 p += r_count;
380 len -= r_count << 2;
381 } while (len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530382 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700383 omap_prefetch_reset(info->gpmc_cs, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530384 }
385}
386
387/**
388 * omap_write_buf_pref - write buffer to NAND controller
389 * @mtd: MTD device structure
390 * @buf: data buffer
391 * @len: number of bytes to write
392 */
393static void omap_write_buf_pref(struct mtd_info *mtd,
394 const u_char *buf, int len)
395{
396 struct omap_nand_info *info = container_of(mtd,
397 struct omap_nand_info, mtd);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530398 uint32_t w_count = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530399 int i = 0, ret = 0;
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530400 u16 *p = (u16 *)buf;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530401 unsigned long tim, limit;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700402 u32 val;
vimal singh59e9c5a2009-07-13 16:26:24 +0530403
404 /* take care of subpage writes */
405 if (len % 2 != 0) {
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000406 writeb(*buf, info->nand.IO_ADDR_W);
vimal singh59e9c5a2009-07-13 16:26:24 +0530407 p = (u16 *)(buf + 1);
408 len--;
409 }
410
411 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700412 ret = omap_prefetch_enable(info->gpmc_cs,
413 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530414 if (ret) {
415 /* PFPW engine is busy, use cpu copy method */
416 if (info->nand.options & NAND_BUSWIDTH_16)
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530417 omap_write_buf16(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530418 else
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530419 omap_write_buf8(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530420 } else {
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000421 while (len) {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700422 w_count = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530423 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000424 w_count = w_count >> 1;
vimal singh59e9c5a2009-07-13 16:26:24 +0530425 for (i = 0; (i < w_count) && len; i++, len -= 2)
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000426 iowrite16(*p++, info->nand.IO_ADDR_W);
vimal singh59e9c5a2009-07-13 16:26:24 +0530427 }
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000428 /* wait for data to flushed-out before reset the prefetch */
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530429 tim = 0;
430 limit = (loops_per_jiffy *
431 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700432 do {
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530433 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700434 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530435 val = PREFETCH_STATUS_COUNT(val);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700436 } while (val && (tim++ < limit));
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530437
vimal singh59e9c5a2009-07-13 16:26:24 +0530438 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700439 omap_prefetch_reset(info->gpmc_cs, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530440 }
441}
442
vimal singhdfe32892009-07-13 16:29:16 +0530443/*
Russell King2df41d02012-04-25 00:19:39 +0100444 * omap_nand_dma_callback: callback on the completion of dma transfer
vimal singhdfe32892009-07-13 16:29:16 +0530445 * @data: pointer to completion data structure
446 */
Russell King763e7352012-04-25 00:16:00 +0100447static void omap_nand_dma_callback(void *data)
448{
449 complete((struct completion *) data);
450}
vimal singhdfe32892009-07-13 16:29:16 +0530451
452/*
Peter Meerwald4cacbe22012-07-19 13:21:04 +0200453 * omap_nand_dma_transfer: configure and start dma transfer
vimal singhdfe32892009-07-13 16:29:16 +0530454 * @mtd: MTD device structure
455 * @addr: virtual address in RAM of source/destination
456 * @len: number of data bytes to be transferred
457 * @is_write: flag for read/write operation
458 */
459static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
460 unsigned int len, int is_write)
461{
462 struct omap_nand_info *info = container_of(mtd,
463 struct omap_nand_info, mtd);
Russell King2df41d02012-04-25 00:19:39 +0100464 struct dma_async_tx_descriptor *tx;
vimal singhdfe32892009-07-13 16:29:16 +0530465 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
466 DMA_FROM_DEVICE;
Russell King2df41d02012-04-25 00:19:39 +0100467 struct scatterlist sg;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530468 unsigned long tim, limit;
Russell King2df41d02012-04-25 00:19:39 +0100469 unsigned n;
470 int ret;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700471 u32 val;
vimal singhdfe32892009-07-13 16:29:16 +0530472
473 if (addr >= high_memory) {
474 struct page *p1;
475
476 if (((size_t)addr & PAGE_MASK) !=
477 ((size_t)(addr + len - 1) & PAGE_MASK))
478 goto out_copy;
479 p1 = vmalloc_to_page(addr);
480 if (!p1)
481 goto out_copy;
482 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
483 }
484
Russell King2df41d02012-04-25 00:19:39 +0100485 sg_init_one(&sg, addr, len);
486 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
487 if (n == 0) {
vimal singhdfe32892009-07-13 16:29:16 +0530488 dev_err(&info->pdev->dev,
489 "Couldn't DMA map a %d byte buffer\n", len);
490 goto out_copy;
491 }
492
Russell King2df41d02012-04-25 00:19:39 +0100493 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
494 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
495 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
496 if (!tx)
497 goto out_copy_unmap;
498
499 tx->callback = omap_nand_dma_callback;
500 tx->callback_param = &info->comp;
501 dmaengine_submit(tx);
502
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700503 /* configure and start prefetch transfer */
504 ret = omap_prefetch_enable(info->gpmc_cs,
505 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
vimal singhdfe32892009-07-13 16:29:16 +0530506 if (ret)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530507 /* PFPW engine is busy, use cpu copy method */
Grazvydas Ignotasd7efe222012-04-11 04:04:34 +0300508 goto out_copy_unmap;
vimal singhdfe32892009-07-13 16:29:16 +0530509
510 init_completion(&info->comp);
Russell King2df41d02012-04-25 00:19:39 +0100511 dma_async_issue_pending(info->dma);
vimal singhdfe32892009-07-13 16:29:16 +0530512
513 /* setup and start DMA using dma_addr */
514 wait_for_completion(&info->comp);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530515 tim = 0;
516 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700517
518 do {
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530519 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700520 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530521 val = PREFETCH_STATUS_COUNT(val);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700522 } while (val && (tim++ < limit));
vimal singhdfe32892009-07-13 16:29:16 +0530523
vimal singhdfe32892009-07-13 16:29:16 +0530524 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700525 omap_prefetch_reset(info->gpmc_cs, info);
vimal singhdfe32892009-07-13 16:29:16 +0530526
Russell King2df41d02012-04-25 00:19:39 +0100527 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
vimal singhdfe32892009-07-13 16:29:16 +0530528 return 0;
529
Grazvydas Ignotasd7efe222012-04-11 04:04:34 +0300530out_copy_unmap:
Russell King2df41d02012-04-25 00:19:39 +0100531 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
vimal singhdfe32892009-07-13 16:29:16 +0530532out_copy:
533 if (info->nand.options & NAND_BUSWIDTH_16)
534 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
535 : omap_write_buf16(mtd, (u_char *) addr, len);
536 else
537 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
538 : omap_write_buf8(mtd, (u_char *) addr, len);
539 return 0;
540}
vimal singhdfe32892009-07-13 16:29:16 +0530541
542/**
543 * omap_read_buf_dma_pref - read data from NAND controller into buffer
544 * @mtd: MTD device structure
545 * @buf: buffer to store date
546 * @len: number of bytes to read
547 */
548static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
549{
550 if (len <= mtd->oobsize)
551 omap_read_buf_pref(mtd, buf, len);
552 else
553 /* start transfer in DMA mode */
554 omap_nand_dma_transfer(mtd, buf, len, 0x0);
555}
556
557/**
558 * omap_write_buf_dma_pref - write buffer to NAND controller
559 * @mtd: MTD device structure
560 * @buf: data buffer
561 * @len: number of bytes to write
562 */
563static void omap_write_buf_dma_pref(struct mtd_info *mtd,
564 const u_char *buf, int len)
565{
566 if (len <= mtd->oobsize)
567 omap_write_buf_pref(mtd, buf, len);
568 else
569 /* start transfer in DMA mode */
Vimal Singhbdaefc42010-01-05 12:49:24 +0530570 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
vimal singhdfe32892009-07-13 16:29:16 +0530571}
572
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530573/*
Peter Meerwald4cacbe22012-07-19 13:21:04 +0200574 * omap_nand_irq - GPMC irq handler
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530575 * @this_irq: gpmc irq number
576 * @dev: omap_nand_info structure pointer is passed here
577 */
578static irqreturn_t omap_nand_irq(int this_irq, void *dev)
579{
580 struct omap_nand_info *info = (struct omap_nand_info *) dev;
581 u32 bytes;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530582
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700583 bytes = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530584 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530585 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
586 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
Afzal Mohammed5c468452012-08-30 12:53:24 -0700587 if (this_irq == info->gpmc_irq_count)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530588 goto done;
589
590 if (info->buf_len && (info->buf_len < bytes))
591 bytes = info->buf_len;
592 else if (!info->buf_len)
593 bytes = 0;
594 iowrite32_rep(info->nand.IO_ADDR_W,
595 (u32 *)info->buf, bytes >> 2);
596 info->buf = info->buf + bytes;
597 info->buf_len -= bytes;
598
599 } else {
600 ioread32_rep(info->nand.IO_ADDR_R,
601 (u32 *)info->buf, bytes >> 2);
602 info->buf = info->buf + bytes;
603
Afzal Mohammed5c468452012-08-30 12:53:24 -0700604 if (this_irq == info->gpmc_irq_count)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530605 goto done;
606 }
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530607
608 return IRQ_HANDLED;
609
610done:
611 complete(&info->comp);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530612
Afzal Mohammed5c468452012-08-30 12:53:24 -0700613 disable_irq_nosync(info->gpmc_irq_fifo);
614 disable_irq_nosync(info->gpmc_irq_count);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530615
616 return IRQ_HANDLED;
617}
618
619/*
620 * omap_read_buf_irq_pref - read data from NAND controller into buffer
621 * @mtd: MTD device structure
622 * @buf: buffer to store date
623 * @len: number of bytes to read
624 */
625static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
626{
627 struct omap_nand_info *info = container_of(mtd,
628 struct omap_nand_info, mtd);
629 int ret = 0;
630
631 if (len <= mtd->oobsize) {
632 omap_read_buf_pref(mtd, buf, len);
633 return;
634 }
635
636 info->iomode = OMAP_NAND_IO_READ;
637 info->buf = buf;
638 init_completion(&info->comp);
639
640 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700641 ret = omap_prefetch_enable(info->gpmc_cs,
642 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530643 if (ret)
644 /* PFPW engine is busy, use cpu copy method */
645 goto out_copy;
646
647 info->buf_len = len;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700648
649 enable_irq(info->gpmc_irq_count);
650 enable_irq(info->gpmc_irq_fifo);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530651
652 /* waiting for read to complete */
653 wait_for_completion(&info->comp);
654
655 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700656 omap_prefetch_reset(info->gpmc_cs, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530657 return;
658
659out_copy:
660 if (info->nand.options & NAND_BUSWIDTH_16)
661 omap_read_buf16(mtd, buf, len);
662 else
663 omap_read_buf8(mtd, buf, len);
664}
665
666/*
667 * omap_write_buf_irq_pref - write buffer to NAND controller
668 * @mtd: MTD device structure
669 * @buf: data buffer
670 * @len: number of bytes to write
671 */
672static void omap_write_buf_irq_pref(struct mtd_info *mtd,
673 const u_char *buf, int len)
674{
675 struct omap_nand_info *info = container_of(mtd,
676 struct omap_nand_info, mtd);
677 int ret = 0;
678 unsigned long tim, limit;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700679 u32 val;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530680
681 if (len <= mtd->oobsize) {
682 omap_write_buf_pref(mtd, buf, len);
683 return;
684 }
685
686 info->iomode = OMAP_NAND_IO_WRITE;
687 info->buf = (u_char *) buf;
688 init_completion(&info->comp);
689
Sukumar Ghorai317379a2011-01-28 15:42:07 +0530690 /* configure and start prefetch transfer : size=24 */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700691 ret = omap_prefetch_enable(info->gpmc_cs,
692 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530693 if (ret)
694 /* PFPW engine is busy, use cpu copy method */
695 goto out_copy;
696
697 info->buf_len = len;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700698
699 enable_irq(info->gpmc_irq_count);
700 enable_irq(info->gpmc_irq_fifo);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530701
702 /* waiting for write to complete */
703 wait_for_completion(&info->comp);
Afzal Mohammed5c468452012-08-30 12:53:24 -0700704
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530705 /* wait for data to flushed-out before reset the prefetch */
706 tim = 0;
707 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700708 do {
709 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530710 val = PREFETCH_STATUS_COUNT(val);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530711 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700712 } while (val && (tim++ < limit));
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530713
714 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700715 omap_prefetch_reset(info->gpmc_cs, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530716 return;
717
718out_copy:
719 if (info->nand.options & NAND_BUSWIDTH_16)
720 omap_write_buf16(mtd, buf, len);
721 else
722 omap_write_buf8(mtd, buf, len);
723}
724
Vimal Singh67ce04b2009-05-12 13:47:03 -0700725/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700726 * gen_true_ecc - This function will generate true ECC value
727 * @ecc_buf: buffer to store ecc code
728 *
729 * This generated true ECC value can be used when correcting
730 * data read from NAND flash memory core
731 */
732static void gen_true_ecc(u8 *ecc_buf)
733{
734 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
735 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
736
737 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
738 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
739 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
740 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
741 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
742 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
743}
744
745/**
746 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
747 * @ecc_data1: ecc code from nand spare area
748 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
749 * @page_data: page data
750 *
751 * This function compares two ECC's and indicates if there is an error.
752 * If the error can be corrected it will be corrected to the buffer.
John Ogness74f1b722011-02-28 13:12:46 +0100753 * If there is no error, %0 is returned. If there is an error but it
754 * was corrected, %1 is returned. Otherwise, %-1 is returned.
Vimal Singh67ce04b2009-05-12 13:47:03 -0700755 */
756static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
757 u8 *ecc_data2, /* read from register */
758 u8 *page_data)
759{
760 uint i;
761 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
762 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
763 u8 ecc_bit[24];
764 u8 ecc_sum = 0;
765 u8 find_bit = 0;
766 uint find_byte = 0;
767 int isEccFF;
768
769 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
770
771 gen_true_ecc(ecc_data1);
772 gen_true_ecc(ecc_data2);
773
774 for (i = 0; i <= 2; i++) {
775 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
776 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
777 }
778
779 for (i = 0; i < 8; i++) {
780 tmp0_bit[i] = *ecc_data1 % 2;
781 *ecc_data1 = *ecc_data1 / 2;
782 }
783
784 for (i = 0; i < 8; i++) {
785 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
786 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
787 }
788
789 for (i = 0; i < 8; i++) {
790 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
791 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
792 }
793
794 for (i = 0; i < 8; i++) {
795 comp0_bit[i] = *ecc_data2 % 2;
796 *ecc_data2 = *ecc_data2 / 2;
797 }
798
799 for (i = 0; i < 8; i++) {
800 comp1_bit[i] = *(ecc_data2 + 1) % 2;
801 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
802 }
803
804 for (i = 0; i < 8; i++) {
805 comp2_bit[i] = *(ecc_data2 + 2) % 2;
806 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
807 }
808
809 for (i = 0; i < 6; i++)
810 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
811
812 for (i = 0; i < 8; i++)
813 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
814
815 for (i = 0; i < 8; i++)
816 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
817
818 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
819 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
820
821 for (i = 0; i < 24; i++)
822 ecc_sum += ecc_bit[i];
823
824 switch (ecc_sum) {
825 case 0:
826 /* Not reached because this function is not called if
827 * ECC values are equal
828 */
829 return 0;
830
831 case 1:
832 /* Uncorrectable error */
Brian Norris289c0522011-07-19 10:06:09 -0700833 pr_debug("ECC UNCORRECTED_ERROR 1\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700834 return -1;
835
836 case 11:
837 /* UN-Correctable error */
Brian Norris289c0522011-07-19 10:06:09 -0700838 pr_debug("ECC UNCORRECTED_ERROR B\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700839 return -1;
840
841 case 12:
842 /* Correctable error */
843 find_byte = (ecc_bit[23] << 8) +
844 (ecc_bit[21] << 7) +
845 (ecc_bit[19] << 6) +
846 (ecc_bit[17] << 5) +
847 (ecc_bit[15] << 4) +
848 (ecc_bit[13] << 3) +
849 (ecc_bit[11] << 2) +
850 (ecc_bit[9] << 1) +
851 ecc_bit[7];
852
853 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
854
Brian Norris0a32a102011-07-19 10:06:10 -0700855 pr_debug("Correcting single bit ECC error at offset: "
856 "%d, bit: %d\n", find_byte, find_bit);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700857
858 page_data[find_byte] ^= (1 << find_bit);
859
John Ogness74f1b722011-02-28 13:12:46 +0100860 return 1;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700861 default:
862 if (isEccFF) {
863 if (ecc_data2[0] == 0 &&
864 ecc_data2[1] == 0 &&
865 ecc_data2[2] == 0)
866 return 0;
867 }
Brian Norris289c0522011-07-19 10:06:09 -0700868 pr_debug("UNCORRECTED_ERROR default\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700869 return -1;
870 }
871}
872
873/**
874 * omap_correct_data - Compares the ECC read with HW generated ECC
875 * @mtd: MTD device structure
876 * @dat: page data
877 * @read_ecc: ecc read from nand flash
878 * @calc_ecc: ecc read from HW ECC registers
879 *
880 * Compares the ecc read from nand spare area with ECC registers values
John Ogness74f1b722011-02-28 13:12:46 +0100881 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
882 * detection and correction. If there are no errors, %0 is returned. If
883 * there were errors and all of the errors were corrected, the number of
884 * corrected errors is returned. If uncorrectable errors exist, %-1 is
885 * returned.
Vimal Singh67ce04b2009-05-12 13:47:03 -0700886 */
887static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
888 u_char *read_ecc, u_char *calc_ecc)
889{
890 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
891 mtd);
892 int blockCnt = 0, i = 0, ret = 0;
John Ogness74f1b722011-02-28 13:12:46 +0100893 int stat = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700894
895 /* Ex NAND_ECC_HW12_2048 */
896 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
897 (info->nand.ecc.size == 2048))
898 blockCnt = 4;
899 else
900 blockCnt = 1;
901
902 for (i = 0; i < blockCnt; i++) {
903 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
904 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
905 if (ret < 0)
906 return ret;
John Ogness74f1b722011-02-28 13:12:46 +0100907 /* keep track of the number of corrected errors */
908 stat += ret;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700909 }
910 read_ecc += 3;
911 calc_ecc += 3;
912 dat += 512;
913 }
John Ogness74f1b722011-02-28 13:12:46 +0100914 return stat;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700915}
916
917/**
918 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
919 * @mtd: MTD device structure
920 * @dat: The pointer to data on which ecc is computed
921 * @ecc_code: The ecc_code buffer
922 *
923 * Using noninverted ECC can be considered ugly since writing a blank
924 * page ie. padding will clear the ECC bytes. This is no problem as long
925 * nobody is trying to write data on the seemingly unused page. Reading
926 * an erased page will produce an ECC mismatch between generated and read
927 * ECC bytes that has to be dealt with separately.
928 */
929static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
930 u_char *ecc_code)
931{
932 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
933 mtd);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700934 u32 val;
935
936 val = readl(info->reg.gpmc_ecc_config);
937 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
938 return -EINVAL;
939
940 /* read ecc result */
941 val = readl(info->reg.gpmc_ecc1_result);
942 *ecc_code++ = val; /* P128e, ..., P1e */
943 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
944 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
945 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
946
947 return 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700948}
949
950/**
951 * omap_enable_hwecc - This function enables the hardware ecc functionality
952 * @mtd: MTD device structure
953 * @mode: Read/Write mode
954 */
955static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
956{
957 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
958 mtd);
959 struct nand_chip *chip = mtd->priv;
960 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700961 u32 val;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700962
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700963 /* clear ecc and enable bits */
964 val = ECCCLEAR | ECC1;
965 writel(val, info->reg.gpmc_ecc_control);
966
967 /* program ecc and result sizes */
968 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
969 ECC1RESULTSIZE);
970 writel(val, info->reg.gpmc_ecc_size_config);
971
972 switch (mode) {
973 case NAND_ECC_READ:
974 case NAND_ECC_WRITE:
975 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
976 break;
977 case NAND_ECC_READSYN:
978 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
979 break;
980 default:
981 dev_info(&info->pdev->dev,
982 "error: unrecognized Mode[%d]!\n", mode);
983 break;
984 }
985
986 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
987 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
988 writel(val, info->reg.gpmc_ecc_config);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700989}
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000990
Vimal Singh67ce04b2009-05-12 13:47:03 -0700991/**
992 * omap_wait - wait until the command is done
993 * @mtd: MTD device structure
994 * @chip: NAND Chip structure
995 *
996 * Wait function is called during Program and erase operations and
997 * the way it is called from MTD layer, we should wait till the NAND
998 * chip is ready after the programming/erase operation has completed.
999 *
1000 * Erase can take up to 400ms and program up to 20ms according to
1001 * general NAND and SmartMedia specs
1002 */
1003static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1004{
1005 struct nand_chip *this = mtd->priv;
1006 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1007 mtd);
1008 unsigned long timeo = jiffies;
Ivan Djelica9c465f2012-04-17 13:11:53 +02001009 int status, state = this->state;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001010
1011 if (state == FL_ERASING)
Toan Pham4ff67722013-03-15 10:44:59 -07001012 timeo += msecs_to_jiffies(400);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001013 else
Toan Pham4ff67722013-03-15 10:44:59 -07001014 timeo += msecs_to_jiffies(20);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001015
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001016 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001017 while (time_before(jiffies, timeo)) {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001018 status = readb(info->reg.gpmc_nand_data);
vimal singhc276aca2009-06-27 11:07:06 +05301019 if (status & NAND_STATUS_READY)
Vimal Singh67ce04b2009-05-12 13:47:03 -07001020 break;
vimal singhc276aca2009-06-27 11:07:06 +05301021 cond_resched();
Vimal Singh67ce04b2009-05-12 13:47:03 -07001022 }
Ivan Djelica9c465f2012-04-17 13:11:53 +02001023
Afzal Mohammed4ea1e4b2012-09-29 11:22:21 +05301024 status = readb(info->reg.gpmc_nand_data);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001025 return status;
1026}
1027
1028/**
1029 * omap_dev_ready - calls the platform specific dev_ready function
1030 * @mtd: MTD device structure
1031 */
1032static int omap_dev_ready(struct mtd_info *mtd)
1033{
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +00001034 unsigned int val = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001035 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1036 mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001037
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001038 val = readl(info->reg.gpmc_status);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001039
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001040 if ((val & 0x100) == 0x100) {
1041 return 1;
1042 } else {
1043 return 0;
1044 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07001045}
1046
Pekon Guptaa919e512013-10-24 18:20:21 +05301047#if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001048/**
1049 * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1050 * @mtd: MTD device structure
1051 * @mode: Read/Write mode
Philip Avinash62116e52013-01-04 13:26:51 +05301052 *
1053 * When using BCH, sector size is hardcoded to 512 bytes.
1054 * Using wrapping mode 6 both for reading and writing if ELM module not uses
1055 * for error correction.
1056 * On writing,
1057 * eccsize0 = 0 (no additional protected byte in spare area)
1058 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001059 */
1060static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1061{
1062 int nerrors;
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301063 unsigned int dev_width, nsectors;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001064 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1065 mtd);
1066 struct nand_chip *chip = mtd->priv;
Philip Avinash62116e52013-01-04 13:26:51 +05301067 u32 val, wr_mode;
1068 unsigned int ecc_size1, ecc_size0;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001069
Philip Avinash62116e52013-01-04 13:26:51 +05301070 /* Using wrapping mode 6 for writing */
1071 wr_mode = BCH_WRAPMODE_6;
1072
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001073 /*
Philip Avinash62116e52013-01-04 13:26:51 +05301074 * ECC engine enabled for valid ecc_size0 nibbles
1075 * and disabled for ecc_size1 nibbles.
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001076 */
Philip Avinash62116e52013-01-04 13:26:51 +05301077 ecc_size0 = BCH_ECC_SIZE0;
1078 ecc_size1 = BCH_ECC_SIZE1;
1079
1080 /* Perform ecc calculation on 512-byte sector */
1081 nsectors = 1;
1082
1083 /* Update number of error correction */
1084 nerrors = info->nand.ecc.strength;
1085
1086 /* Multi sector reading/writing for NAND flash with page size < 4096 */
1087 if (info->is_elm_used && (mtd->writesize <= 4096)) {
1088 if (mode == NAND_ECC_READ) {
1089 /* Using wrapping mode 1 for reading */
1090 wr_mode = BCH_WRAPMODE_1;
1091
1092 /*
1093 * ECC engine enabled for ecc_size0 nibbles
1094 * and disabled for ecc_size1 nibbles.
1095 */
1096 ecc_size0 = (nerrors == 8) ?
1097 BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0;
1098 ecc_size1 = (nerrors == 8) ?
1099 BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1;
1100 }
1101
1102 /* Perform ecc calculation for one page (< 4096) */
1103 nsectors = info->nand.ecc.steps;
1104 }
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301105
1106 writel(ECC1, info->reg.gpmc_ecc_control);
1107
Philip Avinash62116e52013-01-04 13:26:51 +05301108 /* Configure ecc size for BCH */
1109 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301110 writel(val, info->reg.gpmc_ecc_size_config);
1111
Philip Avinash62116e52013-01-04 13:26:51 +05301112 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1113
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301114 /* BCH configuration */
1115 val = ((1 << 16) | /* enable BCH */
1116 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
Philip Avinash62116e52013-01-04 13:26:51 +05301117 (wr_mode << 8) | /* wrap mode */
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301118 (dev_width << 7) | /* bus width */
1119 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1120 (info->gpmc_cs << 1) | /* ECC CS */
1121 (0x1)); /* enable ECC */
1122
1123 writel(val, info->reg.gpmc_ecc_config);
1124
Philip Avinash62116e52013-01-04 13:26:51 +05301125 /* Clear ecc and enable bits */
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301126 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001127}
Pekon Guptaa919e512013-10-24 18:20:21 +05301128#endif
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001129
Pekon Guptaa919e512013-10-24 18:20:21 +05301130#ifdef CONFIG_MTD_NAND_ECC_BCH
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001131/**
1132 * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1133 * @mtd: MTD device structure
1134 * @dat: The pointer to data on which ecc is computed
1135 * @ecc_code: The ecc_code buffer
1136 */
1137static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
1138 u_char *ecc_code)
1139{
1140 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1141 mtd);
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301142 unsigned long nsectors, val1, val2;
1143 int i;
1144
1145 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1146
1147 for (i = 0; i < nsectors; i++) {
1148
1149 /* Read hw-computed remainder */
1150 val1 = readl(info->reg.gpmc_bch_result0[i]);
1151 val2 = readl(info->reg.gpmc_bch_result1[i]);
1152
1153 /*
1154 * Add constant polynomial to remainder, in order to get an ecc
1155 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1156 * left-justify the resulting polynomial.
1157 */
1158 *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1159 *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1160 *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1161 *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1162 *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1163 *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF);
1164 *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4);
1165 }
1166
1167 return 0;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001168}
1169
1170/**
1171 * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1172 * @mtd: MTD device structure
1173 * @dat: The pointer to data on which ecc is computed
1174 * @ecc_code: The ecc_code buffer
1175 */
1176static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
1177 u_char *ecc_code)
1178{
1179 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1180 mtd);
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301181 unsigned long nsectors, val1, val2, val3, val4;
1182 int i;
1183
1184 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1185
1186 for (i = 0; i < nsectors; i++) {
1187
1188 /* Read hw-computed remainder */
1189 val1 = readl(info->reg.gpmc_bch_result0[i]);
1190 val2 = readl(info->reg.gpmc_bch_result1[i]);
1191 val3 = readl(info->reg.gpmc_bch_result2[i]);
1192 val4 = readl(info->reg.gpmc_bch_result3[i]);
1193
1194 /*
1195 * Add constant polynomial to remainder, in order to get an ecc
1196 * sequence of 0xFFs for a buffer filled with 0xFFs.
1197 */
1198 *ecc_code++ = 0xef ^ (val4 & 0xFF);
1199 *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1200 *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1201 *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1202 *ecc_code++ = 0xed ^ (val3 & 0xFF);
1203 *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1204 *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1205 *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1206 *ecc_code++ = 0x97 ^ (val2 & 0xFF);
1207 *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1208 *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1209 *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1210 *ecc_code++ = 0xb5 ^ (val1 & 0xFF);
1211 }
1212
1213 return 0;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001214}
Pekon Guptaa919e512013-10-24 18:20:21 +05301215#endif /* CONFIG_MTD_NAND_ECC_BCH */
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001216
Pekon Guptaa919e512013-10-24 18:20:21 +05301217#ifdef CONFIG_MTD_NAND_OMAP_BCH
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001218/**
Philip Avinash62116e52013-01-04 13:26:51 +05301219 * omap3_calculate_ecc_bch - Generate bytes of ECC bytes
1220 * @mtd: MTD device structure
1221 * @dat: The pointer to data on which ecc is computed
1222 * @ecc_code: The ecc_code buffer
1223 *
1224 * Support calculating of BCH4/8 ecc vectors for the page
1225 */
1226static int omap3_calculate_ecc_bch(struct mtd_info *mtd, const u_char *dat,
1227 u_char *ecc_code)
1228{
1229 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1230 mtd);
1231 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1232 int i, eccbchtsel;
1233
1234 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1235 /*
1236 * find BCH scheme used
1237 * 0 -> BCH4
1238 * 1 -> BCH8
1239 */
1240 eccbchtsel = ((readl(info->reg.gpmc_ecc_config) >> 12) & 0x3);
1241
1242 for (i = 0; i < nsectors; i++) {
1243
1244 /* Read hw-computed remainder */
1245 bch_val1 = readl(info->reg.gpmc_bch_result0[i]);
1246 bch_val2 = readl(info->reg.gpmc_bch_result1[i]);
1247 if (eccbchtsel) {
1248 bch_val3 = readl(info->reg.gpmc_bch_result2[i]);
1249 bch_val4 = readl(info->reg.gpmc_bch_result3[i]);
1250 }
1251
1252 if (eccbchtsel) {
1253 /* BCH8 ecc scheme */
1254 *ecc_code++ = (bch_val4 & 0xFF);
1255 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1256 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1257 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1258 *ecc_code++ = (bch_val3 & 0xFF);
1259 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1260 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1261 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1262 *ecc_code++ = (bch_val2 & 0xFF);
1263 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1264 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1265 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1266 *ecc_code++ = (bch_val1 & 0xFF);
1267 /*
1268 * Setting 14th byte to zero to handle
1269 * erased page & maintain compatibility
1270 * with RBL
1271 */
1272 *ecc_code++ = 0x0;
1273 } else {
1274 /* BCH4 ecc scheme */
1275 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1276 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1277 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1278 ((bch_val1 >> 28) & 0xF);
1279 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1280 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1281 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1282 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1283 /*
1284 * Setting 8th byte to zero to handle
1285 * erased page
1286 */
1287 *ecc_code++ = 0x0;
1288 }
1289 }
1290
1291 return 0;
1292}
1293
1294/**
1295 * erased_sector_bitflips - count bit flips
1296 * @data: data sector buffer
1297 * @oob: oob buffer
1298 * @info: omap_nand_info
1299 *
1300 * Check the bit flips in erased page falls below correctable level.
1301 * If falls below, report the page as erased with correctable bit
1302 * flip, else report as uncorrectable page.
1303 */
1304static int erased_sector_bitflips(u_char *data, u_char *oob,
1305 struct omap_nand_info *info)
1306{
1307 int flip_bits = 0, i;
1308
1309 for (i = 0; i < info->nand.ecc.size; i++) {
1310 flip_bits += hweight8(~data[i]);
1311 if (flip_bits > info->nand.ecc.strength)
1312 return 0;
1313 }
1314
1315 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1316 flip_bits += hweight8(~oob[i]);
1317 if (flip_bits > info->nand.ecc.strength)
1318 return 0;
1319 }
1320
1321 /*
1322 * Bit flips falls in correctable level.
1323 * Fill data area with 0xFF
1324 */
1325 if (flip_bits) {
1326 memset(data, 0xFF, info->nand.ecc.size);
1327 memset(oob, 0xFF, info->nand.ecc.bytes);
1328 }
1329
1330 return flip_bits;
1331}
1332
1333/**
1334 * omap_elm_correct_data - corrects page data area in case error reported
1335 * @mtd: MTD device structure
1336 * @data: page data
1337 * @read_ecc: ecc read from nand flash
1338 * @calc_ecc: ecc read from HW ECC registers
1339 *
1340 * Calculated ecc vector reported as zero in case of non-error pages.
1341 * In case of error/erased pages non-zero error vector is reported.
1342 * In case of non-zero ecc vector, check read_ecc at fixed offset
1343 * (x = 13/7 in case of BCH8/4 == 0) to find page programmed or not.
1344 * To handle bit flips in this data, count the number of 0's in
1345 * read_ecc[x] and check if it greater than 4. If it is less, it is
1346 * programmed page, else erased page.
1347 *
1348 * 1. If page is erased, check with standard ecc vector (ecc vector
1349 * for erased page to find any bit flip). If check fails, bit flip
1350 * is present in erased page. Count the bit flips in erased page and
1351 * if it falls under correctable level, report page with 0xFF and
1352 * update the correctable bit information.
1353 * 2. If error is reported on programmed page, update elm error
1354 * vector and correct the page with ELM error correction routine.
1355 *
1356 */
1357static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1358 u_char *read_ecc, u_char *calc_ecc)
1359{
1360 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1361 mtd);
Pekon Guptade0a4d62014-03-18 18:56:43 +05301362 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
Philip Avinash62116e52013-01-04 13:26:51 +05301363 int eccsteps = info->nand.ecc.steps;
1364 int i , j, stat = 0;
Pekon Guptade0a4d62014-03-18 18:56:43 +05301365 int eccflag, actual_eccbytes;
Philip Avinash62116e52013-01-04 13:26:51 +05301366 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1367 u_char *ecc_vec = calc_ecc;
1368 u_char *spare_ecc = read_ecc;
1369 u_char *erased_ecc_vec;
1370 enum bch_ecc type;
1371 bool is_error_reported = false;
1372
Pekon Guptade0a4d62014-03-18 18:56:43 +05301373 switch (info->ecc_opt) {
1374 case OMAP_ECC_BCH4_CODE_HW:
1375 /* omit 7th ECC byte reserved for ROM code compatibility */
1376 actual_eccbytes = ecc->bytes - 1;
1377 break;
1378 case OMAP_ECC_BCH8_CODE_HW:
1379 /* omit 14th ECC byte reserved for ROM code compatibility */
1380 actual_eccbytes = ecc->bytes - 1;
1381 break;
1382 default:
1383 pr_err("invalid driver configuration\n");
1384 return -EINVAL;
1385 }
1386
Philip Avinash62116e52013-01-04 13:26:51 +05301387 /* Initialize elm error vector to zero */
1388 memset(err_vec, 0, sizeof(err_vec));
1389
1390 if (info->nand.ecc.strength == BCH8_MAX_ERROR) {
1391 type = BCH8_ECC;
1392 erased_ecc_vec = bch8_vector;
1393 } else {
1394 type = BCH4_ECC;
1395 erased_ecc_vec = bch4_vector;
1396 }
1397
Philip Avinash62116e52013-01-04 13:26:51 +05301398 for (i = 0; i < eccsteps ; i++) {
1399 eccflag = 0; /* initialize eccflag */
1400
1401 /*
1402 * Check any error reported,
1403 * In case of error, non zero ecc reported.
1404 */
Pekon Guptade0a4d62014-03-18 18:56:43 +05301405 for (j = 0; j < actual_eccbytes; j++) {
Philip Avinash62116e52013-01-04 13:26:51 +05301406 if (calc_ecc[j] != 0) {
1407 eccflag = 1; /* non zero ecc, error present */
1408 break;
1409 }
1410 }
1411
1412 if (eccflag == 1) {
1413 /*
1414 * Set threshold to minimum of 4, half of ecc.strength/2
1415 * to allow max bit flip in byte to 4
1416 */
1417 unsigned int threshold = min_t(unsigned int, 4,
1418 info->nand.ecc.strength / 2);
1419
1420 /*
1421 * Check data area is programmed by counting
1422 * number of 0's at fixed offset in spare area.
1423 * Checking count of 0's against threshold.
1424 * In case programmed page expects at least threshold
1425 * zeros in byte.
1426 * If zeros are less than threshold for programmed page/
1427 * zeros are more than threshold erased page, either
1428 * case page reported as uncorrectable.
1429 */
Pekon Guptade0a4d62014-03-18 18:56:43 +05301430 if (hweight8(~read_ecc[actual_eccbytes]) >= threshold) {
Philip Avinash62116e52013-01-04 13:26:51 +05301431 /*
1432 * Update elm error vector as
1433 * data area is programmed
1434 */
1435 err_vec[i].error_reported = true;
1436 is_error_reported = true;
1437 } else {
1438 /* Error reported in erased page */
1439 int bitflip_count;
1440 u_char *buf = &data[info->nand.ecc.size * i];
1441
Pekon Guptade0a4d62014-03-18 18:56:43 +05301442 if (memcmp(calc_ecc, erased_ecc_vec,
1443 actual_eccbytes)) {
Philip Avinash62116e52013-01-04 13:26:51 +05301444 bitflip_count = erased_sector_bitflips(
1445 buf, read_ecc, info);
1446
1447 if (bitflip_count)
1448 stat += bitflip_count;
1449 else
1450 return -EINVAL;
1451 }
1452 }
1453 }
1454
1455 /* Update the ecc vector */
Pekon Guptade0a4d62014-03-18 18:56:43 +05301456 calc_ecc += ecc->bytes;
1457 read_ecc += ecc->bytes;
Philip Avinash62116e52013-01-04 13:26:51 +05301458 }
1459
1460 /* Check if any error reported */
1461 if (!is_error_reported)
1462 return 0;
1463
1464 /* Decode BCH error using ELM module */
1465 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1466
1467 for (i = 0; i < eccsteps; i++) {
1468 if (err_vec[i].error_reported) {
1469 for (j = 0; j < err_vec[i].error_count; j++) {
1470 u32 bit_pos, byte_pos, error_max, pos;
1471
1472 if (type == BCH8_ECC)
1473 error_max = BCH8_ECC_MAX;
1474 else
1475 error_max = BCH4_ECC_MAX;
1476
1477 if (info->nand.ecc.strength == BCH8_MAX_ERROR)
1478 pos = err_vec[i].error_loc[j];
1479 else
1480 /* Add 4 to take care 4 bit padding */
1481 pos = err_vec[i].error_loc[j] +
1482 BCH4_BIT_PAD;
1483
1484 /* Calculate bit position of error */
1485 bit_pos = pos % 8;
1486
1487 /* Calculate byte position of error */
1488 byte_pos = (error_max - pos - 1) / 8;
1489
1490 if (pos < error_max) {
1491 if (byte_pos < 512)
1492 data[byte_pos] ^= 1 << bit_pos;
1493 else
1494 spare_ecc[byte_pos - 512] ^=
1495 1 << bit_pos;
1496 }
1497 /* else, not interested to correct ecc */
1498 }
1499 }
1500
1501 /* Update number of correctable errors */
1502 stat += err_vec[i].error_count;
1503
1504 /* Update page data with sector size */
1505 data += info->nand.ecc.size;
Pekon Guptade0a4d62014-03-18 18:56:43 +05301506 spare_ecc += ecc->bytes;
Philip Avinash62116e52013-01-04 13:26:51 +05301507 }
1508
1509 for (i = 0; i < eccsteps; i++)
1510 /* Return error if uncorrectable error present */
1511 if (err_vec[i].error_uncorrectable)
1512 return -EINVAL;
1513
1514 return stat;
1515}
1516
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001517/**
Philip Avinash62116e52013-01-04 13:26:51 +05301518 * omap_write_page_bch - BCH ecc based write page function for entire page
1519 * @mtd: mtd info structure
1520 * @chip: nand chip info structure
1521 * @buf: data buffer
1522 * @oob_required: must write chip->oob_poi to OOB
1523 *
1524 * Custom write page method evolved to support multi sector writing in one shot
1525 */
1526static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1527 const uint8_t *buf, int oob_required)
1528{
1529 int i;
1530 uint8_t *ecc_calc = chip->buffers->ecccalc;
1531 uint32_t *eccpos = chip->ecc.layout->eccpos;
1532
1533 /* Enable GPMC ecc engine */
1534 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1535
1536 /* Write data */
1537 chip->write_buf(mtd, buf, mtd->writesize);
1538
1539 /* Update ecc vector from GPMC result registers */
1540 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1541
1542 for (i = 0; i < chip->ecc.total; i++)
1543 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1544
1545 /* Write ecc vector to OOB area */
1546 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1547 return 0;
1548}
1549
1550/**
1551 * omap_read_page_bch - BCH ecc based page read function for entire page
1552 * @mtd: mtd info structure
1553 * @chip: nand chip info structure
1554 * @buf: buffer to store read data
1555 * @oob_required: caller requires OOB data read to chip->oob_poi
1556 * @page: page number to read
1557 *
1558 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1559 * used for error correction.
1560 * Custom method evolved to support ELM error correction & multi sector
1561 * reading. On reading page data area is read along with OOB data with
1562 * ecc engine enabled. ecc vector updated after read of OOB data.
1563 * For non error pages ecc vector reported as zero.
1564 */
1565static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1566 uint8_t *buf, int oob_required, int page)
1567{
1568 uint8_t *ecc_calc = chip->buffers->ecccalc;
1569 uint8_t *ecc_code = chip->buffers->ecccode;
1570 uint32_t *eccpos = chip->ecc.layout->eccpos;
1571 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1572 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1573 int stat;
1574 unsigned int max_bitflips = 0;
1575
1576 /* Enable GPMC ecc engine */
1577 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1578
1579 /* Read data */
1580 chip->read_buf(mtd, buf, mtd->writesize);
1581
1582 /* Read oob bytes */
1583 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1584 chip->read_buf(mtd, oob, chip->ecc.total);
1585
1586 /* Calculate ecc bytes */
1587 chip->ecc.calculate(mtd, buf, ecc_calc);
1588
1589 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1590
1591 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1592
1593 if (stat < 0) {
1594 mtd->ecc_stats.failed++;
1595 } else {
1596 mtd->ecc_stats.corrected += stat;
1597 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1598 }
1599
1600 return max_bitflips;
1601}
1602
1603/**
Pekon Guptaa919e512013-10-24 18:20:21 +05301604 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1605 * @omap_nand_info: NAND device structure containing platform data
1606 * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1607 */
1608static int is_elm_present(struct omap_nand_info *info,
1609 struct device_node *elm_node, enum bch_ecc bch_type)
1610{
1611 struct platform_device *pdev;
1612 info->is_elm_used = false;
1613 /* check whether elm-id is passed via DT */
1614 if (!elm_node) {
1615 pr_err("nand: error: ELM DT node not found\n");
1616 return -ENODEV;
1617 }
1618 pdev = of_find_device_by_node(elm_node);
1619 /* check whether ELM device is registered */
1620 if (!pdev) {
1621 pr_err("nand: error: ELM device not found\n");
1622 return -ENODEV;
1623 }
1624 /* ELM module available, now configure it */
1625 info->elm_dev = &pdev->dev;
1626 if (elm_config(info->elm_dev, bch_type))
1627 return -ENODEV;
1628 info->is_elm_used = true;
1629 return 0;
1630}
1631#endif /* CONFIG_MTD_NAND_ECC_BCH */
1632
Bill Pemberton06f25512012-11-19 13:23:07 -05001633static int omap_nand_probe(struct platform_device *pdev)
Vimal Singh67ce04b2009-05-12 13:47:03 -07001634{
1635 struct omap_nand_info *info;
1636 struct omap_nand_platform_data *pdata;
Pekon Gupta633deb52013-10-24 18:20:19 +05301637 struct mtd_info *mtd;
1638 struct nand_chip *nand_chip;
Pekon Guptab491da72013-10-24 18:20:22 +05301639 struct nand_ecclayout *ecclayout;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001640 int err;
Pekon Guptab491da72013-10-24 18:20:22 +05301641 int i;
Pekon Gupta633deb52013-10-24 18:20:19 +05301642 dma_cap_mask_t mask;
1643 unsigned sig;
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301644 unsigned oob_index;
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001645 struct resource *res;
Daniel Mackccf04c52012-12-14 11:36:41 +01001646 struct mtd_part_parser_data ppdata = {};
Vimal Singh67ce04b2009-05-12 13:47:03 -07001647
Jingoo Han453810b2013-07-30 17:18:33 +09001648 pdata = dev_get_platdata(&pdev->dev);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001649 if (pdata == NULL) {
1650 dev_err(&pdev->dev, "platform data missing\n");
1651 return -ENODEV;
1652 }
1653
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301654 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1655 GFP_KERNEL);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001656 if (!info)
1657 return -ENOMEM;
1658
1659 platform_set_drvdata(pdev, info);
1660
1661 spin_lock_init(&info->controller.lock);
1662 init_waitqueue_head(&info->controller.wq);
1663
Pekon Gupta633deb52013-10-24 18:20:19 +05301664 info->pdev = pdev;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001665 info->gpmc_cs = pdata->cs;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001666 info->reg = pdata->reg;
Pekon Guptaa919e512013-10-24 18:20:21 +05301667 info->of_node = pdata->of_node;
Pekon Gupta4e558072014-03-18 18:56:42 +05301668 info->ecc_opt = pdata->ecc_opt;
Pekon Gupta633deb52013-10-24 18:20:19 +05301669 mtd = &info->mtd;
1670 mtd->priv = &info->nand;
1671 mtd->name = dev_name(&pdev->dev);
1672 mtd->owner = THIS_MODULE;
1673 nand_chip = &info->nand;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301674 nand_chip->ecc.priv = NULL;
Pekon Gupta633deb52013-10-24 18:20:19 +05301675 nand_chip->options |= NAND_SKIP_BBTSCAN;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001676
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001677 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1678 if (res == NULL) {
1679 err = -EINVAL;
1680 dev_err(&pdev->dev, "error getting memory resource\n");
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301681 goto return_error;
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001682 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07001683
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001684 info->phys_base = res->start;
1685 info->mem_size = resource_size(res);
1686
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301687 if (!devm_request_mem_region(&pdev->dev, info->phys_base,
1688 info->mem_size, pdev->dev.driver->name)) {
Vimal Singh67ce04b2009-05-12 13:47:03 -07001689 err = -EBUSY;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301690 goto return_error;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001691 }
1692
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301693 nand_chip->IO_ADDR_R = devm_ioremap(&pdev->dev, info->phys_base,
1694 info->mem_size);
Pekon Gupta633deb52013-10-24 18:20:19 +05301695 if (!nand_chip->IO_ADDR_R) {
Vimal Singh67ce04b2009-05-12 13:47:03 -07001696 err = -ENOMEM;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301697 goto return_error;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001698 }
vimal singh59e9c5a2009-07-13 16:26:24 +05301699
Pekon Gupta633deb52013-10-24 18:20:19 +05301700 nand_chip->controller = &info->controller;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001701
Pekon Gupta633deb52013-10-24 18:20:19 +05301702 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1703 nand_chip->cmd_ctrl = omap_hwcontrol;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001704
Vimal Singh67ce04b2009-05-12 13:47:03 -07001705 /*
1706 * If RDY/BSY line is connected to OMAP then use the omap ready
Peter Meerwald4cacbe22012-07-19 13:21:04 +02001707 * function and the generic nand_wait function which reads the status
1708 * register after monitoring the RDY/BSY line. Otherwise use a standard
Vimal Singh67ce04b2009-05-12 13:47:03 -07001709 * chip delay which is slightly more than tR (AC Timing) of the NAND
1710 * device and read status register until you get a failure or success
1711 */
1712 if (pdata->dev_ready) {
Pekon Gupta633deb52013-10-24 18:20:19 +05301713 nand_chip->dev_ready = omap_dev_ready;
1714 nand_chip->chip_delay = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001715 } else {
Pekon Gupta633deb52013-10-24 18:20:19 +05301716 nand_chip->waitfunc = omap_wait;
1717 nand_chip->chip_delay = 50;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001718 }
1719
Pekon Guptaf18befb2013-10-24 18:20:20 +05301720 /* scan NAND device connected to chip controller */
1721 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1722 if (nand_scan_ident(mtd, 1, NULL)) {
1723 pr_err("nand device scan failed, may be bus-width mismatch\n");
1724 err = -ENXIO;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301725 goto return_error;
Pekon Guptaf18befb2013-10-24 18:20:20 +05301726 }
1727
Pekon Guptab491da72013-10-24 18:20:22 +05301728 /* check for small page devices */
1729 if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1730 pr_err("small page devices are not supported\n");
1731 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301732 goto return_error;
Pekon Guptab491da72013-10-24 18:20:22 +05301733 }
1734
Pekon Guptaf18befb2013-10-24 18:20:20 +05301735 /* re-populate low-level callbacks based on xfer modes */
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301736 switch (pdata->xfer_type) {
1737 case NAND_OMAP_PREFETCH_POLLED:
Pekon Gupta633deb52013-10-24 18:20:19 +05301738 nand_chip->read_buf = omap_read_buf_pref;
1739 nand_chip->write_buf = omap_write_buf_pref;
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301740 break;
vimal singhdfe32892009-07-13 16:29:16 +05301741
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301742 case NAND_OMAP_POLLED:
Brian Norriscf0e4d22013-10-30 19:39:51 -04001743 /* Use nand_base defaults for {read,write}_buf */
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301744 break;
1745
1746 case NAND_OMAP_PREFETCH_DMA:
Russell King763e7352012-04-25 00:16:00 +01001747 dma_cap_zero(mask);
1748 dma_cap_set(DMA_SLAVE, mask);
1749 sig = OMAP24XX_DMA_GPMC;
1750 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1751 if (!info->dma) {
Russell King2df41d02012-04-25 00:19:39 +01001752 dev_err(&pdev->dev, "DMA engine request failed\n");
1753 err = -ENXIO;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301754 goto return_error;
Russell King763e7352012-04-25 00:16:00 +01001755 } else {
1756 struct dma_slave_config cfg;
Russell King763e7352012-04-25 00:16:00 +01001757
1758 memset(&cfg, 0, sizeof(cfg));
1759 cfg.src_addr = info->phys_base;
1760 cfg.dst_addr = info->phys_base;
1761 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1762 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1763 cfg.src_maxburst = 16;
1764 cfg.dst_maxburst = 16;
Arnd Bergmannd680e2c2012-08-04 11:05:25 +00001765 err = dmaengine_slave_config(info->dma, &cfg);
1766 if (err) {
Russell King763e7352012-04-25 00:16:00 +01001767 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
Arnd Bergmannd680e2c2012-08-04 11:05:25 +00001768 err);
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301769 goto return_error;
Russell King763e7352012-04-25 00:16:00 +01001770 }
Pekon Gupta633deb52013-10-24 18:20:19 +05301771 nand_chip->read_buf = omap_read_buf_dma_pref;
1772 nand_chip->write_buf = omap_write_buf_dma_pref;
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301773 }
1774 break;
1775
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301776 case NAND_OMAP_PREFETCH_IRQ:
Afzal Mohammed5c468452012-08-30 12:53:24 -07001777 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1778 if (info->gpmc_irq_fifo <= 0) {
1779 dev_err(&pdev->dev, "error getting fifo irq\n");
1780 err = -ENODEV;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301781 goto return_error;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001782 }
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301783 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1784 omap_nand_irq, IRQF_SHARED,
1785 "gpmc-nand-fifo", info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301786 if (err) {
1787 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
Afzal Mohammed5c468452012-08-30 12:53:24 -07001788 info->gpmc_irq_fifo, err);
1789 info->gpmc_irq_fifo = 0;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301790 goto return_error;
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301791 }
Afzal Mohammed5c468452012-08-30 12:53:24 -07001792
1793 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1794 if (info->gpmc_irq_count <= 0) {
1795 dev_err(&pdev->dev, "error getting count irq\n");
1796 err = -ENODEV;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301797 goto return_error;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001798 }
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301799 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1800 omap_nand_irq, IRQF_SHARED,
1801 "gpmc-nand-count", info);
Afzal Mohammed5c468452012-08-30 12:53:24 -07001802 if (err) {
1803 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1804 info->gpmc_irq_count, err);
1805 info->gpmc_irq_count = 0;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301806 goto return_error;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001807 }
1808
Pekon Gupta633deb52013-10-24 18:20:19 +05301809 nand_chip->read_buf = omap_read_buf_irq_pref;
1810 nand_chip->write_buf = omap_write_buf_irq_pref;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001811
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301812 break;
1813
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301814 default:
1815 dev_err(&pdev->dev,
1816 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1817 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301818 goto return_error;
vimal singh59e9c5a2009-07-13 16:26:24 +05301819 }
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301820
Pekon Guptaa919e512013-10-24 18:20:21 +05301821 /* populate MTD interface based on ECC scheme */
Pekon Guptab491da72013-10-24 18:20:22 +05301822 nand_chip->ecc.layout = &omap_oobinfo;
1823 ecclayout = &omap_oobinfo;
Pekon Gupta4e558072014-03-18 18:56:42 +05301824 switch (info->ecc_opt) {
Pekon Guptaa919e512013-10-24 18:20:21 +05301825 case OMAP_ECC_HAM1_CODE_HW:
1826 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1827 nand_chip->ecc.mode = NAND_ECC_HW;
Pekon Gupta633deb52013-10-24 18:20:19 +05301828 nand_chip->ecc.bytes = 3;
1829 nand_chip->ecc.size = 512;
1830 nand_chip->ecc.strength = 1;
1831 nand_chip->ecc.calculate = omap_calculate_ecc;
1832 nand_chip->ecc.hwctl = omap_enable_hwecc;
1833 nand_chip->ecc.correct = omap_correct_data;
Pekon Guptab491da72013-10-24 18:20:22 +05301834 /* define ECC layout */
1835 ecclayout->eccbytes = nand_chip->ecc.bytes *
1836 (mtd->writesize /
1837 nand_chip->ecc.size);
1838 if (nand_chip->options & NAND_BUSWIDTH_16)
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301839 oob_index = BADBLOCK_MARKER_LENGTH;
Pekon Guptab491da72013-10-24 18:20:22 +05301840 else
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301841 oob_index = 1;
1842 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1843 ecclayout->eccpos[i] = oob_index;
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301844 /* no reserved-marker in ecclayout for this ecc-scheme */
1845 ecclayout->oobfree->offset =
1846 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301847 break;
1848
1849 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1850#ifdef CONFIG_MTD_NAND_ECC_BCH
1851 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1852 nand_chip->ecc.mode = NAND_ECC_HW;
1853 nand_chip->ecc.size = 512;
1854 nand_chip->ecc.bytes = 7;
1855 nand_chip->ecc.strength = 4;
1856 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301857 nand_chip->ecc.correct = nand_bch_correct_data;
Pekon Guptaa919e512013-10-24 18:20:21 +05301858 nand_chip->ecc.calculate = omap3_calculate_ecc_bch4;
Pekon Guptab491da72013-10-24 18:20:22 +05301859 /* define ECC layout */
1860 ecclayout->eccbytes = nand_chip->ecc.bytes *
1861 (mtd->writesize /
1862 nand_chip->ecc.size);
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301863 oob_index = BADBLOCK_MARKER_LENGTH;
1864 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1865 ecclayout->eccpos[i] = oob_index;
1866 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1867 oob_index++;
1868 }
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301869 /* include reserved-marker in ecclayout->oobfree calculation */
1870 ecclayout->oobfree->offset = 1 +
1871 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301872 /* software bch library is used for locating errors */
Pekon Gupta32d42a82013-10-24 18:20:23 +05301873 nand_chip->ecc.priv = nand_bch_init(mtd,
1874 nand_chip->ecc.size,
1875 nand_chip->ecc.bytes,
1876 &nand_chip->ecc.layout);
1877 if (!nand_chip->ecc.priv) {
Pekon Guptaa919e512013-10-24 18:20:21 +05301878 pr_err("nand: error: unable to use s/w BCH library\n");
1879 err = -EINVAL;
1880 }
1881 break;
1882#else
1883 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1884 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301885 goto return_error;
Pekon Guptaa919e512013-10-24 18:20:21 +05301886#endif
1887
1888 case OMAP_ECC_BCH4_CODE_HW:
1889#ifdef CONFIG_MTD_NAND_OMAP_BCH
1890 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1891 nand_chip->ecc.mode = NAND_ECC_HW;
1892 nand_chip->ecc.size = 512;
1893 /* 14th bit is kept reserved for ROM-code compatibility */
1894 nand_chip->ecc.bytes = 7 + 1;
1895 nand_chip->ecc.strength = 4;
1896 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1897 nand_chip->ecc.correct = omap_elm_correct_data;
1898 nand_chip->ecc.calculate = omap3_calculate_ecc_bch;
1899 nand_chip->ecc.read_page = omap_read_page_bch;
1900 nand_chip->ecc.write_page = omap_write_page_bch;
Pekon Guptab491da72013-10-24 18:20:22 +05301901 /* define ECC layout */
1902 ecclayout->eccbytes = nand_chip->ecc.bytes *
1903 (mtd->writesize /
1904 nand_chip->ecc.size);
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301905 oob_index = BADBLOCK_MARKER_LENGTH;
1906 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1907 ecclayout->eccpos[i] = oob_index;
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301908 /* reserved marker already included in ecclayout->eccbytes */
1909 ecclayout->oobfree->offset =
1910 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301911 /* This ECC scheme requires ELM H/W block */
1912 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1913 pr_err("nand: error: could not initialize ELM\n");
1914 err = -ENODEV;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301915 goto return_error;
Pekon Guptaa919e512013-10-24 18:20:21 +05301916 }
1917 break;
1918#else
1919 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1920 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301921 goto return_error;
Pekon Guptaa919e512013-10-24 18:20:21 +05301922#endif
1923
1924 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1925#ifdef CONFIG_MTD_NAND_ECC_BCH
1926 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1927 nand_chip->ecc.mode = NAND_ECC_HW;
1928 nand_chip->ecc.size = 512;
1929 nand_chip->ecc.bytes = 13;
1930 nand_chip->ecc.strength = 8;
1931 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301932 nand_chip->ecc.correct = nand_bch_correct_data;
Pekon Guptaa919e512013-10-24 18:20:21 +05301933 nand_chip->ecc.calculate = omap3_calculate_ecc_bch8;
Pekon Guptab491da72013-10-24 18:20:22 +05301934 /* define ECC layout */
1935 ecclayout->eccbytes = nand_chip->ecc.bytes *
1936 (mtd->writesize /
1937 nand_chip->ecc.size);
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301938 oob_index = BADBLOCK_MARKER_LENGTH;
1939 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1940 ecclayout->eccpos[i] = oob_index;
1941 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1942 oob_index++;
1943 }
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301944 /* include reserved-marker in ecclayout->oobfree calculation */
1945 ecclayout->oobfree->offset = 1 +
1946 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301947 /* software bch library is used for locating errors */
Pekon Gupta32d42a82013-10-24 18:20:23 +05301948 nand_chip->ecc.priv = nand_bch_init(mtd,
1949 nand_chip->ecc.size,
1950 nand_chip->ecc.bytes,
1951 &nand_chip->ecc.layout);
1952 if (!nand_chip->ecc.priv) {
Pekon Guptaa919e512013-10-24 18:20:21 +05301953 pr_err("nand: error: unable to use s/w BCH library\n");
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001954 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301955 goto return_error;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001956 }
Pekon Guptaa919e512013-10-24 18:20:21 +05301957 break;
1958#else
1959 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1960 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301961 goto return_error;
Pekon Guptaa919e512013-10-24 18:20:21 +05301962#endif
1963
1964 case OMAP_ECC_BCH8_CODE_HW:
1965#ifdef CONFIG_MTD_NAND_OMAP_BCH
1966 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1967 nand_chip->ecc.mode = NAND_ECC_HW;
1968 nand_chip->ecc.size = 512;
1969 /* 14th bit is kept reserved for ROM-code compatibility */
1970 nand_chip->ecc.bytes = 13 + 1;
1971 nand_chip->ecc.strength = 8;
1972 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1973 nand_chip->ecc.correct = omap_elm_correct_data;
1974 nand_chip->ecc.calculate = omap3_calculate_ecc_bch;
1975 nand_chip->ecc.read_page = omap_read_page_bch;
1976 nand_chip->ecc.write_page = omap_write_page_bch;
1977 /* This ECC scheme requires ELM H/W block */
Wei Yongjun92114392013-11-01 08:16:18 +08001978 err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC);
1979 if (err < 0) {
Pekon Guptaa919e512013-10-24 18:20:21 +05301980 pr_err("nand: error: could not initialize ELM\n");
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301981 goto return_error;
Pekon Guptaa919e512013-10-24 18:20:21 +05301982 }
Pekon Guptab491da72013-10-24 18:20:22 +05301983 /* define ECC layout */
1984 ecclayout->eccbytes = nand_chip->ecc.bytes *
1985 (mtd->writesize /
1986 nand_chip->ecc.size);
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301987 oob_index = BADBLOCK_MARKER_LENGTH;
1988 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1989 ecclayout->eccpos[i] = oob_index;
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301990 /* reserved marker already included in ecclayout->eccbytes */
1991 ecclayout->oobfree->offset =
1992 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301993 break;
1994#else
1995 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1996 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301997 goto return_error;
Pekon Guptaa919e512013-10-24 18:20:21 +05301998#endif
1999
2000 default:
2001 pr_err("nand: error: invalid or unsupported ECC scheme\n");
2002 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05302003 goto return_error;
Sukumar Ghoraif3d73f32011-01-28 15:42:08 +05302004 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07002005
Pekon Guptabb38eef2014-02-17 13:11:25 +05302006 /* all OOB bytes from oobfree->offset till end off OOB are free */
2007 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
Pekon Guptab491da72013-10-24 18:20:22 +05302008 /* check if NAND device's OOB is enough to store ECC signatures */
2009 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
2010 pr_err("not enough OOB bytes required = %d, available=%d\n",
2011 ecclayout->eccbytes, mtd->oobsize);
2012 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05302013 goto return_error;
Sukumar Ghoraif040d332011-01-28 15:42:09 +05302014 }
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05302015
Jan Weitzela80f1c12011-04-19 16:15:34 +02002016 /* second phase scan */
Pekon Gupta633deb52013-10-24 18:20:19 +05302017 if (nand_scan_tail(mtd)) {
Jan Weitzela80f1c12011-04-19 16:15:34 +02002018 err = -ENXIO;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05302019 goto return_error;
Jan Weitzela80f1c12011-04-19 16:15:34 +02002020 }
2021
Daniel Mackccf04c52012-12-14 11:36:41 +01002022 ppdata.of_node = pdata->of_node;
Pekon Gupta633deb52013-10-24 18:20:19 +05302023 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
Artem Bityutskiy42d7fbe2012-03-09 19:24:26 +02002024 pdata->nr_parts);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002025
Pekon Gupta633deb52013-10-24 18:20:19 +05302026 platform_set_drvdata(pdev, mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002027
2028 return 0;
2029
Pekon Gupta70ba6d72013-10-24 18:20:25 +05302030return_error:
Russell King763e7352012-04-25 00:16:00 +01002031 if (info->dma)
2032 dma_release_channel(info->dma);
Pekon Gupta32d42a82013-10-24 18:20:23 +05302033 if (nand_chip->ecc.priv) {
2034 nand_bch_free(nand_chip->ecc.priv);
2035 nand_chip->ecc.priv = NULL;
2036 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07002037 return err;
2038}
2039
2040static int omap_nand_remove(struct platform_device *pdev)
2041{
2042 struct mtd_info *mtd = platform_get_drvdata(pdev);
Pekon Gupta633deb52013-10-24 18:20:19 +05302043 struct nand_chip *nand_chip = mtd->priv;
Vimal Singhf35b6ed2010-01-05 16:01:08 +05302044 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2045 mtd);
Pekon Gupta32d42a82013-10-24 18:20:23 +05302046 if (nand_chip->ecc.priv) {
2047 nand_bch_free(nand_chip->ecc.priv);
2048 nand_chip->ecc.priv = NULL;
2049 }
Russell King763e7352012-04-25 00:16:00 +01002050 if (info->dma)
2051 dma_release_channel(info->dma);
Pekon Gupta633deb52013-10-24 18:20:19 +05302052 nand_release(mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002053 return 0;
2054}
2055
2056static struct platform_driver omap_nand_driver = {
2057 .probe = omap_nand_probe,
2058 .remove = omap_nand_remove,
2059 .driver = {
2060 .name = DRIVER_NAME,
2061 .owner = THIS_MODULE,
2062 },
2063};
2064
Axel Linf99640d2011-11-27 20:45:03 +08002065module_platform_driver(omap_nand_driver);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002066
Axel Linc804c732011-03-07 11:04:24 +08002067MODULE_ALIAS("platform:" DRIVER_NAME);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002068MODULE_LICENSE("GPL");
2069MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");