blob: a4860bc9b73d4ffe927d087c24b70970084ff330 [file] [log] [blame]
Carlo Caionecfb61a42014-05-01 14:29:27 +02001/*
2 * Functions and registers to access AXP20X power management chip.
3 *
4 * Copyright (C) 2013, Carlo Caione <carlo@caione.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_MFD_AXP20X_H
12#define __LINUX_MFD_AXP20X_H
13
Hans de Goede69fb4dc2015-08-01 10:39:38 +020014#include <linux/regmap.h>
15
Carlo Caionecfb61a42014-05-01 14:29:27 +020016enum {
Michal Suchanekd8d79f82015-07-11 14:59:56 +020017 AXP152_ID = 0,
18 AXP202_ID,
Carlo Caionecfb61a42014-05-01 14:29:27 +020019 AXP209_ID,
Boris BREZILLONf05be582015-04-10 12:09:01 +080020 AXP221_ID,
Chen-Yu Tsai02071f02016-02-12 10:02:44 +080021 AXP223_ID,
Jacob Panaf7e9062014-10-06 21:17:14 -070022 AXP288_ID,
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +080023 AXP806_ID,
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080024 AXP809_ID,
Jacob Panaf7e9062014-10-06 21:17:14 -070025 NR_AXP20X_VARIANTS,
Carlo Caionecfb61a42014-05-01 14:29:27 +020026};
27
28#define AXP20X_DATACACHE(m) (0x04 + (m))
29
30/* Power supply */
Michal Suchanekd8d79f82015-07-11 14:59:56 +020031#define AXP152_PWR_OP_MODE 0x01
32#define AXP152_LDO3456_DC1234_CTRL 0x12
33#define AXP152_ALDO_OP_MODE 0x13
34#define AXP152_LDO0_CTRL 0x15
35#define AXP152_DCDC2_V_OUT 0x23
36#define AXP152_DCDC2_V_SCAL 0x25
37#define AXP152_DCDC1_V_OUT 0x26
38#define AXP152_DCDC3_V_OUT 0x27
39#define AXP152_ALDO12_V_OUT 0x28
40#define AXP152_DLDO1_V_OUT 0x29
41#define AXP152_DLDO2_V_OUT 0x2a
42#define AXP152_DCDC4_V_OUT 0x2b
43#define AXP152_V_OFF 0x31
44#define AXP152_OFF_CTRL 0x32
45#define AXP152_PEK_KEY 0x36
46#define AXP152_DCDC_FREQ 0x37
47#define AXP152_DCDC_MODE 0x80
48
Carlo Caionecfb61a42014-05-01 14:29:27 +020049#define AXP20X_PWR_INPUT_STATUS 0x00
50#define AXP20X_PWR_OP_MODE 0x01
51#define AXP20X_USB_OTG_STATUS 0x02
52#define AXP20X_PWR_OUT_CTRL 0x12
53#define AXP20X_DCDC2_V_OUT 0x23
54#define AXP20X_DCDC2_LDO3_V_SCAL 0x25
55#define AXP20X_DCDC3_V_OUT 0x27
56#define AXP20X_LDO24_V_OUT 0x28
57#define AXP20X_LDO3_V_OUT 0x29
58#define AXP20X_VBUS_IPSOUT_MGMT 0x30
59#define AXP20X_V_OFF 0x31
60#define AXP20X_OFF_CTRL 0x32
61#define AXP20X_CHRG_CTRL1 0x33
62#define AXP20X_CHRG_CTRL2 0x34
63#define AXP20X_CHRG_BAK_CTRL 0x35
64#define AXP20X_PEK_KEY 0x36
65#define AXP20X_DCDC_FREQ 0x37
66#define AXP20X_V_LTF_CHRG 0x38
67#define AXP20X_V_HTF_CHRG 0x39
68#define AXP20X_APS_WARN_L1 0x3a
69#define AXP20X_APS_WARN_L2 0x3b
70#define AXP20X_V_LTF_DISCHRG 0x3c
71#define AXP20X_V_HTF_DISCHRG 0x3d
72
Boris BREZILLONf05be582015-04-10 12:09:01 +080073#define AXP22X_PWR_OUT_CTRL1 0x10
74#define AXP22X_PWR_OUT_CTRL2 0x12
75#define AXP22X_PWR_OUT_CTRL3 0x13
76#define AXP22X_DLDO1_V_OUT 0x15
77#define AXP22X_DLDO2_V_OUT 0x16
78#define AXP22X_DLDO3_V_OUT 0x17
79#define AXP22X_DLDO4_V_OUT 0x18
80#define AXP22X_ELDO1_V_OUT 0x19
81#define AXP22X_ELDO2_V_OUT 0x1a
82#define AXP22X_ELDO3_V_OUT 0x1b
83#define AXP22X_DC5LDO_V_OUT 0x1c
84#define AXP22X_DCDC1_V_OUT 0x21
85#define AXP22X_DCDC2_V_OUT 0x22
86#define AXP22X_DCDC3_V_OUT 0x23
87#define AXP22X_DCDC4_V_OUT 0x24
88#define AXP22X_DCDC5_V_OUT 0x25
89#define AXP22X_DCDC23_V_RAMP_CTRL 0x27
90#define AXP22X_ALDO1_V_OUT 0x28
91#define AXP22X_ALDO2_V_OUT 0x29
92#define AXP22X_ALDO3_V_OUT 0x2a
93#define AXP22X_CHRG_CTRL3 0x35
94
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +080095#define AXP806_STARTUP_SRC 0x00
96#define AXP806_CHIP_ID 0x03
97#define AXP806_PWR_OUT_CTRL1 0x10
98#define AXP806_PWR_OUT_CTRL2 0x11
99#define AXP806_DCDCA_V_CTRL 0x12
100#define AXP806_DCDCB_V_CTRL 0x13
101#define AXP806_DCDCC_V_CTRL 0x14
102#define AXP806_DCDCD_V_CTRL 0x15
103#define AXP806_DCDCE_V_CTRL 0x16
104#define AXP806_ALDO1_V_CTRL 0x17
105#define AXP806_ALDO2_V_CTRL 0x18
106#define AXP806_ALDO3_V_CTRL 0x19
107#define AXP806_DCDC_MODE_CTRL1 0x1a
108#define AXP806_DCDC_MODE_CTRL2 0x1b
109#define AXP806_DCDC_FREQ_CTRL 0x1c
110#define AXP806_BLDO1_V_CTRL 0x20
111#define AXP806_BLDO2_V_CTRL 0x21
112#define AXP806_BLDO3_V_CTRL 0x22
113#define AXP806_BLDO4_V_CTRL 0x23
114#define AXP806_CLDO1_V_CTRL 0x24
115#define AXP806_CLDO2_V_CTRL 0x25
116#define AXP806_CLDO3_V_CTRL 0x26
117#define AXP806_VREF_TEMP_WARN_L 0xf3
Chen-Yu Tsai34d90302016-11-11 11:29:52 +0800118#define AXP806_BUS_ADDR_EXT 0xfe
119#define AXP806_REG_ADDR_EXT 0xff
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800120
Carlo Caionecfb61a42014-05-01 14:29:27 +0200121/* Interrupt */
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200122#define AXP152_IRQ1_EN 0x40
123#define AXP152_IRQ2_EN 0x41
124#define AXP152_IRQ3_EN 0x42
125#define AXP152_IRQ1_STATE 0x48
126#define AXP152_IRQ2_STATE 0x49
127#define AXP152_IRQ3_STATE 0x4a
128
Carlo Caionecfb61a42014-05-01 14:29:27 +0200129#define AXP20X_IRQ1_EN 0x40
130#define AXP20X_IRQ2_EN 0x41
131#define AXP20X_IRQ3_EN 0x42
132#define AXP20X_IRQ4_EN 0x43
133#define AXP20X_IRQ5_EN 0x44
Jacob Panaf7e9062014-10-06 21:17:14 -0700134#define AXP20X_IRQ6_EN 0x45
Carlo Caionecfb61a42014-05-01 14:29:27 +0200135#define AXP20X_IRQ1_STATE 0x48
136#define AXP20X_IRQ2_STATE 0x49
137#define AXP20X_IRQ3_STATE 0x4a
138#define AXP20X_IRQ4_STATE 0x4b
139#define AXP20X_IRQ5_STATE 0x4c
Jacob Panaf7e9062014-10-06 21:17:14 -0700140#define AXP20X_IRQ6_STATE 0x4d
Carlo Caionecfb61a42014-05-01 14:29:27 +0200141
142/* ADC */
143#define AXP20X_ACIN_V_ADC_H 0x56
144#define AXP20X_ACIN_V_ADC_L 0x57
145#define AXP20X_ACIN_I_ADC_H 0x58
146#define AXP20X_ACIN_I_ADC_L 0x59
147#define AXP20X_VBUS_V_ADC_H 0x5a
148#define AXP20X_VBUS_V_ADC_L 0x5b
149#define AXP20X_VBUS_I_ADC_H 0x5c
150#define AXP20X_VBUS_I_ADC_L 0x5d
151#define AXP20X_TEMP_ADC_H 0x5e
152#define AXP20X_TEMP_ADC_L 0x5f
153#define AXP20X_TS_IN_H 0x62
154#define AXP20X_TS_IN_L 0x63
155#define AXP20X_GPIO0_V_ADC_H 0x64
156#define AXP20X_GPIO0_V_ADC_L 0x65
157#define AXP20X_GPIO1_V_ADC_H 0x66
158#define AXP20X_GPIO1_V_ADC_L 0x67
159#define AXP20X_PWR_BATT_H 0x70
160#define AXP20X_PWR_BATT_M 0x71
161#define AXP20X_PWR_BATT_L 0x72
162#define AXP20X_BATT_V_H 0x78
163#define AXP20X_BATT_V_L 0x79
164#define AXP20X_BATT_CHRG_I_H 0x7a
165#define AXP20X_BATT_CHRG_I_L 0x7b
166#define AXP20X_BATT_DISCHRG_I_H 0x7c
167#define AXP20X_BATT_DISCHRG_I_L 0x7d
168#define AXP20X_IPSOUT_V_HIGH_H 0x7e
169#define AXP20X_IPSOUT_V_HIGH_L 0x7f
170
171/* Power supply */
172#define AXP20X_DCDC_MODE 0x80
173#define AXP20X_ADC_EN1 0x82
174#define AXP20X_ADC_EN2 0x83
175#define AXP20X_ADC_RATE 0x84
176#define AXP20X_GPIO10_IN_RANGE 0x85
177#define AXP20X_GPIO1_ADC_IRQ_RIS 0x86
178#define AXP20X_GPIO1_ADC_IRQ_FAL 0x87
179#define AXP20X_TIMER_CTRL 0x8a
180#define AXP20X_VBUS_MON 0x8b
181#define AXP20X_OVER_TMP 0x8f
182
Boris BREZILLONf05be582015-04-10 12:09:01 +0800183#define AXP22X_PWREN_CTRL1 0x8c
184#define AXP22X_PWREN_CTRL2 0x8d
185
Carlo Caionecfb61a42014-05-01 14:29:27 +0200186/* GPIO */
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200187#define AXP152_GPIO0_CTRL 0x90
188#define AXP152_GPIO1_CTRL 0x91
189#define AXP152_GPIO2_CTRL 0x92
190#define AXP152_GPIO3_CTRL 0x93
191#define AXP152_LDOGPIO2_V_OUT 0x96
192#define AXP152_GPIO_INPUT 0x97
193#define AXP152_PWM0_FREQ_X 0x98
194#define AXP152_PWM0_FREQ_Y 0x99
195#define AXP152_PWM0_DUTY_CYCLE 0x9a
196#define AXP152_PWM1_FREQ_X 0x9b
197#define AXP152_PWM1_FREQ_Y 0x9c
198#define AXP152_PWM1_DUTY_CYCLE 0x9d
199
Carlo Caionecfb61a42014-05-01 14:29:27 +0200200#define AXP20X_GPIO0_CTRL 0x90
201#define AXP20X_LDO5_V_OUT 0x91
202#define AXP20X_GPIO1_CTRL 0x92
203#define AXP20X_GPIO2_CTRL 0x93
204#define AXP20X_GPIO20_SS 0x94
205#define AXP20X_GPIO3_CTRL 0x95
206
Boris BREZILLONf05be582015-04-10 12:09:01 +0800207#define AXP22X_LDO_IO0_V_OUT 0x91
208#define AXP22X_LDO_IO1_V_OUT 0x93
209#define AXP22X_GPIO_STATE 0x94
210#define AXP22X_GPIO_PULL_DOWN 0x95
211
Carlo Caionecfb61a42014-05-01 14:29:27 +0200212/* Battery */
213#define AXP20X_CHRG_CC_31_24 0xb0
214#define AXP20X_CHRG_CC_23_16 0xb1
215#define AXP20X_CHRG_CC_15_8 0xb2
216#define AXP20X_CHRG_CC_7_0 0xb3
217#define AXP20X_DISCHRG_CC_31_24 0xb4
218#define AXP20X_DISCHRG_CC_23_16 0xb5
219#define AXP20X_DISCHRG_CC_15_8 0xb6
220#define AXP20X_DISCHRG_CC_7_0 0xb7
221#define AXP20X_CC_CTRL 0xb8
222#define AXP20X_FG_RES 0xb9
223
Bruno Prémont553ed4b2015-08-08 17:58:40 +0200224/* OCV */
225#define AXP20X_RDC_H 0xba
226#define AXP20X_RDC_L 0xbb
227#define AXP20X_OCV(m) (0xc0 + (m))
228#define AXP20X_OCV_MAX 0xf
229
Boris BREZILLONf05be582015-04-10 12:09:01 +0800230/* AXP22X specific registers */
Icenowy Zheng3f895862016-07-01 17:29:23 +0800231#define AXP22X_PMIC_ADC_H 0x56
232#define AXP22X_PMIC_ADC_L 0x57
233#define AXP22X_TS_ADC_H 0x58
234#define AXP22X_TS_ADC_L 0x59
Boris BREZILLONf05be582015-04-10 12:09:01 +0800235#define AXP22X_BATLOW_THRES1 0xe6
236
Jacob Panaf7e9062014-10-06 21:17:14 -0700237/* AXP288 specific registers */
238#define AXP288_PMIC_ADC_H 0x56
239#define AXP288_PMIC_ADC_L 0x57
240#define AXP288_ADC_TS_PIN_CTRL 0x84
Jacob Panaf7e9062014-10-06 21:17:14 -0700241#define AXP288_PMIC_ADC_EN 0x84
Jacob Panaf7e9062014-10-06 21:17:14 -0700242
Todd E Brandt774e0b42015-01-07 13:25:52 -0800243/* Fuel Gauge */
244#define AXP288_FG_RDC1_REG 0xba
245#define AXP288_FG_RDC0_REG 0xbb
246#define AXP288_FG_OCVH_REG 0xbc
247#define AXP288_FG_OCVL_REG 0xbd
248#define AXP288_FG_OCV_CURVE_REG 0xc0
249#define AXP288_FG_DES_CAP1_REG 0xe0
250#define AXP288_FG_DES_CAP0_REG 0xe1
251#define AXP288_FG_CC_MTR1_REG 0xe2
252#define AXP288_FG_CC_MTR0_REG 0xe3
253#define AXP288_FG_OCV_CAP_REG 0xe4
254#define AXP288_FG_CC_CAP_REG 0xe5
255#define AXP288_FG_LOW_CAP_REG 0xe6
256#define AXP288_FG_TUNE0 0xe8
257#define AXP288_FG_TUNE1 0xe9
258#define AXP288_FG_TUNE2 0xea
259#define AXP288_FG_TUNE3 0xeb
260#define AXP288_FG_TUNE4 0xec
261#define AXP288_FG_TUNE5 0xed
Jacob Panaf7e9062014-10-06 21:17:14 -0700262
Carlo Caionecfb61a42014-05-01 14:29:27 +0200263/* Regulators IDs */
264enum {
265 AXP20X_LDO1 = 0,
266 AXP20X_LDO2,
267 AXP20X_LDO3,
268 AXP20X_LDO4,
269 AXP20X_LDO5,
270 AXP20X_DCDC2,
271 AXP20X_DCDC3,
272 AXP20X_REG_ID_MAX,
273};
274
Boris BREZILLONf05be582015-04-10 12:09:01 +0800275enum {
276 AXP22X_DCDC1 = 0,
277 AXP22X_DCDC2,
278 AXP22X_DCDC3,
279 AXP22X_DCDC4,
280 AXP22X_DCDC5,
281 AXP22X_DC1SW,
282 AXP22X_DC5LDO,
283 AXP22X_ALDO1,
284 AXP22X_ALDO2,
285 AXP22X_ALDO3,
286 AXP22X_ELDO1,
287 AXP22X_ELDO2,
288 AXP22X_ELDO3,
289 AXP22X_DLDO1,
290 AXP22X_DLDO2,
291 AXP22X_DLDO3,
292 AXP22X_DLDO4,
293 AXP22X_RTC_LDO,
294 AXP22X_LDO_IO0,
295 AXP22X_LDO_IO1,
296 AXP22X_REG_ID_MAX,
297};
298
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800299enum {
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800300 AXP806_DCDCA = 0,
301 AXP806_DCDCB,
302 AXP806_DCDCC,
303 AXP806_DCDCD,
304 AXP806_DCDCE,
305 AXP806_ALDO1,
306 AXP806_ALDO2,
307 AXP806_ALDO3,
308 AXP806_BLDO1,
309 AXP806_BLDO2,
310 AXP806_BLDO3,
311 AXP806_BLDO4,
312 AXP806_CLDO1,
313 AXP806_CLDO2,
314 AXP806_CLDO3,
315 AXP806_SW,
316 AXP806_REG_ID_MAX,
317};
318
319enum {
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800320 AXP809_DCDC1 = 0,
321 AXP809_DCDC2,
322 AXP809_DCDC3,
323 AXP809_DCDC4,
324 AXP809_DCDC5,
325 AXP809_DC1SW,
326 AXP809_DC5LDO,
327 AXP809_ALDO1,
328 AXP809_ALDO2,
329 AXP809_ALDO3,
330 AXP809_ELDO1,
331 AXP809_ELDO2,
332 AXP809_ELDO3,
333 AXP809_DLDO1,
334 AXP809_DLDO2,
335 AXP809_RTC_LDO,
336 AXP809_LDO_IO0,
337 AXP809_LDO_IO1,
338 AXP809_SW,
339 AXP809_REG_ID_MAX,
340};
341
Carlo Caionecfb61a42014-05-01 14:29:27 +0200342/* IRQs */
343enum {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200344 AXP152_IRQ_LDO0IN_CONNECT = 1,
345 AXP152_IRQ_LDO0IN_REMOVAL,
346 AXP152_IRQ_ALDO0IN_CONNECT,
347 AXP152_IRQ_ALDO0IN_REMOVAL,
348 AXP152_IRQ_DCDC1_V_LOW,
349 AXP152_IRQ_DCDC2_V_LOW,
350 AXP152_IRQ_DCDC3_V_LOW,
351 AXP152_IRQ_DCDC4_V_LOW,
352 AXP152_IRQ_PEK_SHORT,
353 AXP152_IRQ_PEK_LONG,
354 AXP152_IRQ_TIMER,
355 AXP152_IRQ_PEK_RIS_EDGE,
356 AXP152_IRQ_PEK_FAL_EDGE,
357 AXP152_IRQ_GPIO3_INPUT,
358 AXP152_IRQ_GPIO2_INPUT,
359 AXP152_IRQ_GPIO1_INPUT,
360 AXP152_IRQ_GPIO0_INPUT,
361};
362
363enum {
Carlo Caionecfb61a42014-05-01 14:29:27 +0200364 AXP20X_IRQ_ACIN_OVER_V = 1,
365 AXP20X_IRQ_ACIN_PLUGIN,
366 AXP20X_IRQ_ACIN_REMOVAL,
367 AXP20X_IRQ_VBUS_OVER_V,
368 AXP20X_IRQ_VBUS_PLUGIN,
369 AXP20X_IRQ_VBUS_REMOVAL,
370 AXP20X_IRQ_VBUS_V_LOW,
371 AXP20X_IRQ_BATT_PLUGIN,
372 AXP20X_IRQ_BATT_REMOVAL,
373 AXP20X_IRQ_BATT_ENT_ACT_MODE,
374 AXP20X_IRQ_BATT_EXIT_ACT_MODE,
375 AXP20X_IRQ_CHARG,
376 AXP20X_IRQ_CHARG_DONE,
377 AXP20X_IRQ_BATT_TEMP_HIGH,
378 AXP20X_IRQ_BATT_TEMP_LOW,
379 AXP20X_IRQ_DIE_TEMP_HIGH,
380 AXP20X_IRQ_CHARG_I_LOW,
381 AXP20X_IRQ_DCDC1_V_LONG,
382 AXP20X_IRQ_DCDC2_V_LONG,
383 AXP20X_IRQ_DCDC3_V_LONG,
384 AXP20X_IRQ_PEK_SHORT = 22,
385 AXP20X_IRQ_PEK_LONG,
386 AXP20X_IRQ_N_OE_PWR_ON,
387 AXP20X_IRQ_N_OE_PWR_OFF,
388 AXP20X_IRQ_VBUS_VALID,
389 AXP20X_IRQ_VBUS_NOT_VALID,
390 AXP20X_IRQ_VBUS_SESS_VALID,
391 AXP20X_IRQ_VBUS_SESS_END,
392 AXP20X_IRQ_LOW_PWR_LVL1,
393 AXP20X_IRQ_LOW_PWR_LVL2,
394 AXP20X_IRQ_TIMER,
395 AXP20X_IRQ_PEK_RIS_EDGE,
396 AXP20X_IRQ_PEK_FAL_EDGE,
397 AXP20X_IRQ_GPIO3_INPUT,
398 AXP20X_IRQ_GPIO2_INPUT,
399 AXP20X_IRQ_GPIO1_INPUT,
400 AXP20X_IRQ_GPIO0_INPUT,
401};
402
Boris BREZILLONf05be582015-04-10 12:09:01 +0800403enum axp22x_irqs {
404 AXP22X_IRQ_ACIN_OVER_V = 1,
405 AXP22X_IRQ_ACIN_PLUGIN,
406 AXP22X_IRQ_ACIN_REMOVAL,
407 AXP22X_IRQ_VBUS_OVER_V,
408 AXP22X_IRQ_VBUS_PLUGIN,
409 AXP22X_IRQ_VBUS_REMOVAL,
410 AXP22X_IRQ_VBUS_V_LOW,
411 AXP22X_IRQ_BATT_PLUGIN,
412 AXP22X_IRQ_BATT_REMOVAL,
413 AXP22X_IRQ_BATT_ENT_ACT_MODE,
414 AXP22X_IRQ_BATT_EXIT_ACT_MODE,
415 AXP22X_IRQ_CHARG,
416 AXP22X_IRQ_CHARG_DONE,
417 AXP22X_IRQ_BATT_TEMP_HIGH,
418 AXP22X_IRQ_BATT_TEMP_LOW,
419 AXP22X_IRQ_DIE_TEMP_HIGH,
420 AXP22X_IRQ_PEK_SHORT,
421 AXP22X_IRQ_PEK_LONG,
422 AXP22X_IRQ_LOW_PWR_LVL1,
423 AXP22X_IRQ_LOW_PWR_LVL2,
424 AXP22X_IRQ_TIMER,
425 AXP22X_IRQ_PEK_RIS_EDGE,
426 AXP22X_IRQ_PEK_FAL_EDGE,
427 AXP22X_IRQ_GPIO1_INPUT,
428 AXP22X_IRQ_GPIO0_INPUT,
429};
430
Jacob Panaf7e9062014-10-06 21:17:14 -0700431enum axp288_irqs {
432 AXP288_IRQ_VBUS_FALL = 2,
433 AXP288_IRQ_VBUS_RISE,
434 AXP288_IRQ_OV,
435 AXP288_IRQ_FALLING_ALT,
436 AXP288_IRQ_RISING_ALT,
437 AXP288_IRQ_OV_ALT,
438 AXP288_IRQ_DONE = 10,
439 AXP288_IRQ_CHARGING,
440 AXP288_IRQ_SAFE_QUIT,
441 AXP288_IRQ_SAFE_ENTER,
442 AXP288_IRQ_ABSENT,
443 AXP288_IRQ_APPEND,
444 AXP288_IRQ_QWBTU,
445 AXP288_IRQ_WBTU,
446 AXP288_IRQ_QWBTO,
447 AXP288_IRQ_WBTO,
448 AXP288_IRQ_QCBTU,
449 AXP288_IRQ_CBTU,
450 AXP288_IRQ_QCBTO,
451 AXP288_IRQ_CBTO,
452 AXP288_IRQ_WL2,
453 AXP288_IRQ_WL1,
454 AXP288_IRQ_GPADC,
455 AXP288_IRQ_OT = 31,
456 AXP288_IRQ_GPIO0,
457 AXP288_IRQ_GPIO1,
458 AXP288_IRQ_POKO,
459 AXP288_IRQ_POKL,
460 AXP288_IRQ_POKS,
461 AXP288_IRQ_POKN,
462 AXP288_IRQ_POKP,
463 AXP288_IRQ_TIMER,
464 AXP288_IRQ_MV_CHNG,
465 AXP288_IRQ_BC_USB_CHNG,
466};
467
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800468enum axp806_irqs {
469 AXP806_IRQ_DIE_TEMP_HIGH_LV1,
470 AXP806_IRQ_DIE_TEMP_HIGH_LV2,
471 AXP806_IRQ_DCDCA_V_LOW,
472 AXP806_IRQ_DCDCB_V_LOW,
473 AXP806_IRQ_DCDCC_V_LOW,
474 AXP806_IRQ_DCDCD_V_LOW,
475 AXP806_IRQ_DCDCE_V_LOW,
476 AXP806_IRQ_PWROK_LONG,
477 AXP806_IRQ_PWROK_SHORT,
478 AXP806_IRQ_WAKEUP,
479 AXP806_IRQ_PWROK_FALL,
480 AXP806_IRQ_PWROK_RISE,
481};
482
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800483enum axp809_irqs {
484 AXP809_IRQ_ACIN_OVER_V = 1,
485 AXP809_IRQ_ACIN_PLUGIN,
486 AXP809_IRQ_ACIN_REMOVAL,
487 AXP809_IRQ_VBUS_OVER_V,
488 AXP809_IRQ_VBUS_PLUGIN,
489 AXP809_IRQ_VBUS_REMOVAL,
490 AXP809_IRQ_VBUS_V_LOW,
491 AXP809_IRQ_BATT_PLUGIN,
492 AXP809_IRQ_BATT_REMOVAL,
493 AXP809_IRQ_BATT_ENT_ACT_MODE,
494 AXP809_IRQ_BATT_EXIT_ACT_MODE,
495 AXP809_IRQ_CHARG,
496 AXP809_IRQ_CHARG_DONE,
497 AXP809_IRQ_BATT_CHG_TEMP_HIGH,
498 AXP809_IRQ_BATT_CHG_TEMP_HIGH_END,
499 AXP809_IRQ_BATT_CHG_TEMP_LOW,
500 AXP809_IRQ_BATT_CHG_TEMP_LOW_END,
501 AXP809_IRQ_BATT_ACT_TEMP_HIGH,
502 AXP809_IRQ_BATT_ACT_TEMP_HIGH_END,
503 AXP809_IRQ_BATT_ACT_TEMP_LOW,
504 AXP809_IRQ_BATT_ACT_TEMP_LOW_END,
505 AXP809_IRQ_DIE_TEMP_HIGH,
506 AXP809_IRQ_LOW_PWR_LVL1,
507 AXP809_IRQ_LOW_PWR_LVL2,
508 AXP809_IRQ_TIMER,
509 AXP809_IRQ_PEK_RIS_EDGE,
510 AXP809_IRQ_PEK_FAL_EDGE,
511 AXP809_IRQ_PEK_SHORT,
512 AXP809_IRQ_PEK_LONG,
513 AXP809_IRQ_PEK_OVER_OFF,
514 AXP809_IRQ_GPIO1_INPUT,
515 AXP809_IRQ_GPIO0_INPUT,
516};
517
Jacob Panaf7e9062014-10-06 21:17:14 -0700518#define AXP288_TS_ADC_H 0x58
519#define AXP288_TS_ADC_L 0x59
520#define AXP288_GP_ADC_H 0x5a
521#define AXP288_GP_ADC_L 0x5b
522
Carlo Caionecfb61a42014-05-01 14:29:27 +0200523struct axp20x_dev {
524 struct device *dev;
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800525 int irq;
Carlo Caionecfb61a42014-05-01 14:29:27 +0200526 struct regmap *regmap;
527 struct regmap_irq_chip_data *regmap_irqc;
528 long variant;
Jacob Panaf7e9062014-10-06 21:17:14 -0700529 int nr_cells;
530 struct mfd_cell *cells;
531 const struct regmap_config *regmap_cfg;
532 const struct regmap_irq_chip *regmap_irq_chip;
Carlo Caionecfb61a42014-05-01 14:29:27 +0200533};
534
Todd E Brandt774e0b42015-01-07 13:25:52 -0800535#define BATTID_LEN 64
536#define OCV_CURVE_SIZE 32
537#define MAX_THERM_CURVE_SIZE 25
538#define PD_DEF_MIN_TEMP 0
539#define PD_DEF_MAX_TEMP 55
540
541struct axp20x_fg_pdata {
542 char battid[BATTID_LEN + 1];
543 int design_cap;
544 int min_volt;
545 int max_volt;
546 int max_temp;
547 int min_temp;
548 int cap1;
549 int cap0;
550 int rdc1;
551 int rdc0;
552 int ocv_curve[OCV_CURVE_SIZE];
553 int tcsz;
554 int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
555};
556
Ramakrishna Pallala843735b2015-05-04 22:16:07 +0530557struct axp20x_chrg_pdata {
558 int max_cc;
559 int max_cv;
560 int def_cc;
561 int def_cv;
562};
563
Ramakrishna Pallalaf0312372015-04-30 20:44:45 +0530564struct axp288_extcon_pdata {
565 /* GPIO pin control to switch D+/D- lines b/w PMIC and SOC */
566 struct gpio_desc *gpio_mux_cntl;
567};
568
Hans de Goede69fb4dc2015-08-01 10:39:38 +0200569/* generic helper function for reading 9-16 bit wide regs */
570static inline int axp20x_read_variable_width(struct regmap *regmap,
571 unsigned int reg, unsigned int width)
572{
573 unsigned int reg_val, result;
574 int err;
575
576 err = regmap_read(regmap, reg, &reg_val);
577 if (err)
578 return err;
579
580 result = reg_val << (width - 8);
581
582 err = regmap_read(regmap, reg + 1, &reg_val);
583 if (err)
584 return err;
585
586 result |= reg_val;
587
588 return result;
589}
590
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800591/**
592 * axp20x_match_device(): Setup axp20x variant related fields
593 *
594 * @axp20x: axp20x device to setup (.dev field must be set)
595 * @dev: device associated with this axp20x device
596 *
597 * This lets the axp20x core configure the mfd cells and register maps
598 * for later use.
599 */
600int axp20x_match_device(struct axp20x_dev *axp20x);
601
602/**
603 * axp20x_device_probe(): Probe a configured axp20x device
604 *
605 * @axp20x: axp20x device to probe (must be configured)
606 *
607 * This function lets the axp20x core register the axp20x mfd devices
608 * and irqchip. The axp20x device passed in must be fully configured
609 * with axp20x_match_device, its irq set, and regmap created.
610 */
611int axp20x_device_probe(struct axp20x_dev *axp20x);
612
613/**
614 * axp20x_device_probe(): Remove a axp20x device
615 *
616 * @axp20x: axp20x device to remove
617 *
618 * This tells the axp20x core to remove the associated mfd devices
619 */
620int axp20x_device_remove(struct axp20x_dev *axp20x);
621
Carlo Caionecfb61a42014-05-01 14:29:27 +0200622#endif /* __LINUX_MFD_AXP20X_H */