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Shawn Guo9daaf312011-10-17 08:42:17 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +080013#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +080014#include "imx51-pinfunc.h"
Shawn Guo9daaf312011-10-17 08:42:17 +080015
16/ {
17 aliases {
Shawn Guo5230f8f2012-08-05 14:01:28 +080018 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
Sascha Hauere3b73c62013-06-25 15:51:55 +020022 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 spi0 = &ecspi1;
28 spi1 = &ecspi2;
29 spi2 = &cspi;
Shawn Guo9daaf312011-10-17 08:42:17 +080030 };
31
32 tzic: tz-interrupt-controller@e0000000 {
33 compatible = "fsl,imx51-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0xe0000000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
Alexander Shiyan677e28b2013-07-27 11:19:45 +040050 clock-frequency = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +080051 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020064 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
Alexander Shiyan6acde882013-11-07 12:45:05 +040067 cpu: cpu@0 {
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020068 device_type = "cpu";
69 compatible = "arm,cortex-a8";
70 reg = <0>;
Alexander Shiyan6acde882013-11-07 12:45:05 +040071 clock-latency = <62500>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020072 clocks = <&clks 24>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020073 operating-points = <
Alexander Shiyan6acde882013-11-07 12:45:05 +040074 166000 1000000
75 600000 1050000
76 800000 1100000
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020077 >;
Alexander Shiyan6acde882013-11-07 12:45:05 +040078 voltage-tolerance = <5>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020079 };
80 };
81
Shawn Guo9daaf312011-10-17 08:42:17 +080082 soc {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "simple-bus";
86 interrupt-parent = <&tzic>;
87 ranges;
88
Alexander Shiyanda38ea32013-08-21 11:28:24 +040089 iram: iram@1ffe0000 {
90 compatible = "mmio-sram";
91 reg = <0x1ffe0000 0x20000>;
92 };
93
Sascha Hauerb5af6b12012-11-12 12:56:00 +010094 ipu: ipu@40000000 {
95 #crtc-cells = <1>;
96 compatible = "fsl,imx51-ipu";
97 reg = <0x40000000 0x20000000>;
98 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +010099 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
100 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100101 resets = <&src 2>;
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100102 };
103
Shawn Guo9daaf312011-10-17 08:42:17 +0800104 aips@70000000 { /* AIPS1 */
105 compatible = "fsl,aips-bus", "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0x70000000 0x10000000>;
109 ranges;
110
111 spba@70000000 {
112 compatible = "fsl,spba-bus", "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x70000000 0x40000>;
116 ranges;
117
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100118 esdhc1: esdhc@70004000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800119 compatible = "fsl,imx51-esdhc";
120 reg = <0x70004000 0x4000>;
121 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200122 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
123 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800124 status = "disabled";
125 };
126
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100127 esdhc2: esdhc@70008000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800128 compatible = "fsl,imx51-esdhc";
129 reg = <0x70008000 0x4000>;
130 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200131 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
132 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200133 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800134 status = "disabled";
135 };
136
Shawn Guo0c456cf2012-04-02 14:39:26 +0800137 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800138 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
139 reg = <0x7000c000 0x4000>;
140 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200141 clocks = <&clks 32>, <&clks 33>;
142 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800143 status = "disabled";
144 };
145
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100146 ecspi1: ecspi@70010000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx51-ecspi";
150 reg = <0x70010000 0x4000>;
151 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200152 clocks = <&clks 51>, <&clks 52>;
153 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800154 status = "disabled";
155 };
156
Shawn Guoa15d9f82012-05-11 13:08:46 +0800157 ssi2: ssi@70014000 {
158 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
159 reg = <0x70014000 0x4000>;
160 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200161 clocks = <&clks 49>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800162 dmas = <&sdma 24 1 0>,
163 <&sdma 25 1 0>;
164 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800165 fsl,fifo-depth = <15>;
166 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
167 status = "disabled";
168 };
169
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100170 esdhc3: esdhc@70020000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800171 compatible = "fsl,imx51-esdhc";
172 reg = <0x70020000 0x4000>;
173 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200174 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
175 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200176 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800177 status = "disabled";
178 };
179
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100180 esdhc4: esdhc@70024000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800181 compatible = "fsl,imx51-esdhc";
182 reg = <0x70024000 0x4000>;
183 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200184 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
185 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200186 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800187 status = "disabled";
188 };
189 };
190
Michael Grzeschika79025c2013-04-11 12:13:16 +0200191 usbphy0: usbphy@0 {
192 compatible = "usb-nop-xceiv";
Alexander Shiyan036e2992013-11-05 18:00:18 +0400193 clocks = <&clks 75>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200194 clock-names = "main_clk";
195 status = "okay";
196 };
197
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100198 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200199 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
200 reg = <0x73f80000 0x0200>;
201 interrupts = <18>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200202 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200203 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200204 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200205 status = "disabled";
206 };
207
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100208 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200209 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
210 reg = <0x73f80200 0x0200>;
211 interrupts = <14>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200212 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200213 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200214 status = "disabled";
215 };
216
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100217 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200218 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
219 reg = <0x73f80400 0x0200>;
220 interrupts = <16>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200221 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200222 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200223 status = "disabled";
224 };
225
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100226 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200227 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
228 reg = <0x73f80600 0x0200>;
229 interrupts = <17>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200230 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200231 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200232 status = "disabled";
233 };
234
Michael Grzeschika5735022013-04-11 12:13:14 +0200235 usbmisc: usbmisc@73f80800 {
236 #index-cells = <1>;
237 compatible = "fsl,imx51-usbmisc";
238 reg = <0x73f80800 0x200>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200239 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200240 };
241
Richard Zhao4d191862011-12-14 09:26:44 +0800242 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200243 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800244 reg = <0x73f84000 0x4000>;
245 interrupts = <50 51>;
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800249 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800250 };
251
Richard Zhao4d191862011-12-14 09:26:44 +0800252 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200253 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800254 reg = <0x73f88000 0x4000>;
255 interrupts = <52 53>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800259 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800260 };
261
Richard Zhao4d191862011-12-14 09:26:44 +0800262 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200263 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800264 reg = <0x73f8c000 0x4000>;
265 interrupts = <54 55>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800269 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800270 };
271
Richard Zhao4d191862011-12-14 09:26:44 +0800272 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200273 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800274 reg = <0x73f90000 0x4000>;
275 interrupts = <56 57>;
276 gpio-controller;
277 #gpio-cells = <2>;
278 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800279 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800280 };
281
Liu Ying60125552013-01-03 20:37:33 +0800282 kpp: kpp@73f94000 {
283 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
284 reg = <0x73f94000 0x4000>;
285 interrupts = <60>;
286 clocks = <&clks 0>;
287 status = "disabled";
288 };
289
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100290 wdog1: wdog@73f98000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800291 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
292 reg = <0x73f98000 0x4000>;
293 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200294 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800295 };
296
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100297 wdog2: wdog@73f9c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800298 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
299 reg = <0x73f9c000 0x4000>;
300 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200301 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800302 status = "disabled";
303 };
304
Sascha Hauered73c632013-03-14 13:08:59 +0100305 gpt: timer@73fa0000 {
306 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
307 reg = <0x73fa0000 0x4000>;
308 interrupts = <39>;
309 clocks = <&clks 36>, <&clks 41>;
310 clock-names = "ipg", "per";
311 };
312
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100313 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800314 compatible = "fsl,imx51-iomuxc";
315 reg = <0x73fa8000 0x4000>;
Shawn Guob72cf102012-08-13 19:45:19 +0800316 };
317
Sascha Hauer82a618d2012-11-19 00:57:08 +0100318 pwm1: pwm@73fb4000 {
319 #pwm-cells = <2>;
320 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
321 reg = <0x73fb4000 0x4000>;
322 clocks = <&clks 37>, <&clks 38>;
323 clock-names = "ipg", "per";
324 interrupts = <61>;
325 };
326
327 pwm2: pwm@73fb8000 {
328 #pwm-cells = <2>;
329 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
330 reg = <0x73fb8000 0x4000>;
331 clocks = <&clks 39>, <&clks 40>;
332 clock-names = "ipg", "per";
333 interrupts = <94>;
334 };
335
Shawn Guo0c456cf2012-04-02 14:39:26 +0800336 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800337 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
338 reg = <0x73fbc000 0x4000>;
339 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200340 clocks = <&clks 28>, <&clks 29>;
341 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800342 status = "disabled";
343 };
344
Shawn Guo0c456cf2012-04-02 14:39:26 +0800345 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800346 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
347 reg = <0x73fc0000 0x4000>;
348 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200349 clocks = <&clks 30>, <&clks 31>;
350 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800351 status = "disabled";
352 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200353
Philipp Zabel8d84c372013-03-28 17:35:23 +0100354 src: src@73fd0000 {
355 compatible = "fsl,imx51-src";
356 reg = <0x73fd0000 0x4000>;
357 #reset-cells = <1>;
358 };
359
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200360 clks: ccm@73fd4000{
361 compatible = "fsl,imx51-ccm";
362 reg = <0x73fd4000 0x4000>;
363 interrupts = <0 71 0x04 0 72 0x04>;
364 #clock-cells = <1>;
365 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800366 };
367
368 aips@80000000 { /* AIPS2 */
369 compatible = "fsl,aips-bus", "simple-bus";
370 #address-cells = <1>;
371 #size-cells = <1>;
372 reg = <0x80000000 0x10000000>;
373 ranges;
374
Sascha Hauer6510ea252013-06-25 15:51:51 +0200375 iim: iim@83f98000 {
376 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
377 reg = <0x83f98000 0x4000>;
378 interrupts = <69>;
379 clocks = <&clks 107>;
380 };
381
Alexander Shiyanad15f082013-08-21 11:28:25 +0400382 owire: owire@83fa4000 {
383 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
384 reg = <0x83fa4000 0x4000>;
385 interrupts = <88>;
386 clocks = <&clks 159>;
387 status = "disabled";
388 };
389
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100390 ecspi2: ecspi@83fac000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800391 #address-cells = <1>;
392 #size-cells = <0>;
393 compatible = "fsl,imx51-ecspi";
394 reg = <0x83fac000 0x4000>;
395 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200396 clocks = <&clks 53>, <&clks 54>;
397 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800398 status = "disabled";
399 };
400
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100401 sdma: sdma@83fb0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800402 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
403 reg = <0x83fb0000 0x4000>;
404 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200405 clocks = <&clks 56>, <&clks 56>;
406 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800407 #dma-cells = <3>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300408 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800409 };
410
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100411 cspi: cspi@83fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800412 #address-cells = <1>;
413 #size-cells = <0>;
414 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
415 reg = <0x83fc0000 0x4000>;
416 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200417 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200418 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800419 status = "disabled";
420 };
421
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100422 i2c2: i2c@83fc4000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800423 #address-cells = <1>;
424 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800425 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800426 reg = <0x83fc4000 0x4000>;
427 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200428 clocks = <&clks 35>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800429 status = "disabled";
430 };
431
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100432 i2c1: i2c@83fc8000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800433 #address-cells = <1>;
434 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800435 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800436 reg = <0x83fc8000 0x4000>;
437 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200438 clocks = <&clks 34>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800439 status = "disabled";
440 };
441
Shawn Guoa15d9f82012-05-11 13:08:46 +0800442 ssi1: ssi@83fcc000 {
443 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
444 reg = <0x83fcc000 0x4000>;
445 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200446 clocks = <&clks 48>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800447 dmas = <&sdma 28 0 0>,
448 <&sdma 29 0 0>;
449 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800450 fsl,fifo-depth = <15>;
451 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
452 status = "disabled";
453 };
454
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100455 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800456 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
457 reg = <0x83fd0000 0x4000>;
Alexander Shiyane030df92013-11-07 12:45:06 +0400458 clocks = <&clks 0>;
459 clock-names = "audmux";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800460 status = "disabled";
461 };
462
Alexander Shiyanedd05282013-07-13 08:30:57 +0400463 weim: weim@83fda000 {
464 #address-cells = <2>;
465 #size-cells = <1>;
466 compatible = "fsl,imx51-weim";
467 reg = <0x83fda000 0x1000>;
468 clocks = <&clks 57>;
469 ranges = <
470 0 0 0xb0000000 0x08000000
471 1 0 0xb8000000 0x08000000
472 2 0 0xc0000000 0x08000000
473 3 0 0xc8000000 0x04000000
474 4 0 0xcc000000 0x02000000
475 5 0 0xce000000 0x02000000
476 >;
477 status = "disabled";
478 };
479
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100480 nfc: nand@83fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200481 compatible = "fsl,imx51-nand";
482 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
483 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200484 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200485 status = "disabled";
486 };
487
Sascha Hauer718a35002013-04-04 11:25:09 +0200488 pata: pata@83fe0000 {
489 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
490 reg = <0x83fe0000 0x4000>;
491 interrupts = <70>;
Arnaud Patard (Rtp)6a030ee2013-09-07 15:23:14 +0200492 clocks = <&clks 172>;
Sascha Hauer718a35002013-04-04 11:25:09 +0200493 status = "disabled";
494 };
495
Shawn Guoa15d9f82012-05-11 13:08:46 +0800496 ssi3: ssi@83fe8000 {
497 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
498 reg = <0x83fe8000 0x4000>;
499 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200500 clocks = <&clks 50>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800501 dmas = <&sdma 46 0 0>,
502 <&sdma 47 0 0>;
503 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800504 fsl,fifo-depth = <15>;
505 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
506 status = "disabled";
507 };
508
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100509 fec: ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800510 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
511 reg = <0x83fec000 0x4000>;
512 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200513 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
514 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800515 status = "disabled";
516 };
517 };
518 };
519};