blob: 8309b11e674d8506bfeb3f05530407ede4b60642 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020029#include "radeon.h"
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/radeon_drm.h>
Marek Olšák6759a0a2012-08-09 16:34:17 +020031#include "radeon_asic.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100033#include <linux/vga_switcheroo.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Dave Airlie10ebc0b2012-09-17 14:40:31 +100035#include <linux/pm_runtime.h>
Alex Deucher78488652014-03-11 15:02:30 -040036
37#if defined(CONFIG_VGA_SWITCHEROO)
Alex Deucher90c4cde2014-04-10 22:29:01 -040038bool radeon_has_atpx(void);
Alex Deucher78488652014-03-11 15:02:30 -040039#else
Alex Deucher90c4cde2014-04-10 22:29:01 -040040static inline bool radeon_has_atpx(void) { return false; }
Alex Deucher78488652014-03-11 15:02:30 -040041#endif
42
Alex Deucherf482a142012-07-17 14:02:34 -040043/**
44 * radeon_driver_unload_kms - Main unload function for KMS.
45 *
46 * @dev: drm dev pointer
47 *
48 * This is the main unload function for KMS (all asics).
49 * It calls radeon_modeset_fini() to tear down the
50 * displays, and radeon_device_fini() to tear down
51 * the rest of the device (CP, writeback, etc.).
52 * Returns 0 on success.
53 */
Jerome Glissecf0fe452009-12-09 18:21:55 +010054int radeon_driver_unload_kms(struct drm_device *dev)
55{
56 struct radeon_device *rdev = dev->dev_private;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020057
Jerome Glissecf0fe452009-12-09 18:21:55 +010058 if (rdev == NULL)
59 return 0;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100060
Alex Deucher0cd9cb72013-04-12 19:15:52 -040061 if (rdev->rmmio == NULL)
62 goto done_free;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100063
64 pm_runtime_get_sync(dev->dev);
65
Alex Deucherc4917072012-07-31 17:14:35 -040066 radeon_acpi_fini(rdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +100067
Jerome Glissecf0fe452009-12-09 18:21:55 +010068 radeon_modeset_fini(rdev);
69 radeon_device_fini(rdev);
Alex Deucher0cd9cb72013-04-12 19:15:52 -040070
71done_free:
Jerome Glissecf0fe452009-12-09 18:21:55 +010072 kfree(rdev);
73 dev->dev_private = NULL;
74 return 0;
75}
76
Alex Deucherf482a142012-07-17 14:02:34 -040077/**
78 * radeon_driver_load_kms - Main load function for KMS.
79 *
80 * @dev: drm dev pointer
81 * @flags: device flags
82 *
83 * This is the main load function for KMS (all asics).
84 * It calls radeon_device_init() to set up the non-display
85 * parts of the chip (asic init, CP, writeback, etc.), and
86 * radeon_modeset_init() to set up the display parts
87 * (crtcs, encoders, hotplug detect, etc.).
88 * Returns 0 on success, error on failure.
89 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
91{
92 struct radeon_device *rdev;
Alberto Miloned7a29522010-07-06 11:40:24 -040093 int r, acpi_status;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020094
95 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
96 if (rdev == NULL) {
97 return -ENOMEM;
98 }
99 dev->dev_private = (void *)rdev;
100
101 /* update BUS flag */
Dave Airlie8410ea32010-12-15 03:16:38 +1000102 if (drm_pci_device_is_agp(dev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200103 flags |= RADEON_IS_AGP;
Jon Mason58b65422011-06-27 16:07:50 +0000104 } else if (pci_is_pcie(dev->pdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200105 flags |= RADEON_IS_PCIE;
106 } else {
107 flags |= RADEON_IS_PCI;
108 }
109
Alex Deucher73acacc2014-04-15 12:44:35 -0400110 if ((radeon_runtime_pm != 0) &&
111 radeon_has_atpx() &&
112 ((flags & RADEON_IS_IGP) == 0))
Alex Deucher90c4cde2014-04-10 22:29:01 -0400113 flags |= RADEON_IS_PX;
114
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200115 /* radeon_device_init should report only fatal error
116 * like memory allocation failure or iomapping failure,
117 * or memory manager initialization failure, it must
118 * properly initialize the GPU MC controller and permit
119 * VRAM allocation
120 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200121 r = radeon_device_init(rdev, dev, dev->pdev, flags);
122 if (r) {
Jerome Glissecf0fe452009-12-09 18:21:55 +0100123 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
124 goto out;
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200125 }
Alberto Miloned7a29522010-07-06 11:40:24 -0400126
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200127 /* Again modeset_init should fail only on fatal error
128 * otherwise it should provide enough functionalities
129 * for shadowfb to run
130 */
131 r = radeon_modeset_init(rdev);
Jerome Glissecf0fe452009-12-09 18:21:55 +0100132 if (r)
133 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
Luca Tettamantifda4b252012-07-30 21:20:35 +0200134
135 /* Call ACPI methods: require modeset init
136 * but failure is not fatal
137 */
138 if (!r) {
139 acpi_status = radeon_acpi_init(rdev);
140 if (acpi_status)
141 dev_dbg(&dev->pdev->dev,
142 "Error during ACPI methods call\n");
143 }
144
Alex Deucher90c4cde2014-04-10 22:29:01 -0400145 if (radeon_is_px(dev)) {
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000146 pm_runtime_use_autosuspend(dev->dev);
147 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
148 pm_runtime_set_active(dev->dev);
149 pm_runtime_allow(dev->dev);
150 pm_runtime_mark_last_busy(dev->dev);
151 pm_runtime_put_autosuspend(dev->dev);
152 }
153
Jerome Glissecf0fe452009-12-09 18:21:55 +0100154out:
155 if (r)
156 radeon_driver_unload_kms(dev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000157
158
Jerome Glissecf0fe452009-12-09 18:21:55 +0100159 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200160}
161
Alex Deucherf482a142012-07-17 14:02:34 -0400162/**
163 * radeon_set_filp_rights - Set filp right.
164 *
165 * @dev: drm dev pointer
166 * @owner: drm file
167 * @applier: drm file
168 * @value: value
169 *
170 * Sets the filp rights for the device (all asics).
171 */
Marek Olšák9eba4a92011-01-05 05:46:48 +0100172static void radeon_set_filp_rights(struct drm_device *dev,
173 struct drm_file **owner,
174 struct drm_file *applier,
175 uint32_t *value)
176{
177 mutex_lock(&dev->struct_mutex);
178 if (*value == 1) {
179 /* wants rights */
180 if (!*owner)
181 *owner = applier;
182 } else if (*value == 0) {
183 /* revokes rights */
184 if (*owner == applier)
185 *owner = NULL;
186 }
187 *value = *owner == applier ? 1 : 0;
188 mutex_unlock(&dev->struct_mutex);
189}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190
191/*
Marek Olšák9eba4a92011-01-05 05:46:48 +0100192 * Userspace get information ioctl
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200193 */
Alex Deucherf482a142012-07-17 14:02:34 -0400194/**
195 * radeon_info_ioctl - answer a device specific request.
196 *
197 * @rdev: radeon device pointer
198 * @data: request object
199 * @filp: drm filp
200 *
201 * This function is used to pass device specific parameters to the userspace
202 * drivers. Examples include: pci device id, pipeline parms, tiling params,
203 * etc. (all asics).
204 * Returns 0 on success, -EINVAL on failure.
205 */
Rashika Kheria55203452014-01-06 20:53:07 +0530206static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200207{
208 struct radeon_device *rdev = dev->dev_private;
Marek Olšák6759a0a2012-08-09 16:34:17 +0200209 struct drm_radeon_info *info = data;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200210 struct radeon_mode_info *minfo = &rdev->mode_info;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400211 uint32_t *value, value_tmp, *value_ptr, value_size;
212 uint64_t value64;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200213 struct drm_crtc *crtc;
214 int i, found;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200215
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200216 value_ptr = (uint32_t *)((unsigned long)info->value);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400217 value = &value_tmp;
218 value_size = sizeof(uint32_t);
Dr. David Alan Gilbertd8ab3552010-08-02 09:43:52 +1000219
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200220 switch (info->request) {
221 case RADEON_INFO_DEVICE_ID:
Ville Syrjäläffbab09b2013-10-04 14:53:40 +0300222 *value = dev->pdev->device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200223 break;
224 case RADEON_INFO_NUM_GB_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400225 *value = rdev->num_gb_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200226 break;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400227 case RADEON_INFO_NUM_Z_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400228 *value = rdev->num_z_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400229 break;
Jerome Glisse733289c2009-09-16 15:24:21 +0200230 case RADEON_INFO_ACCEL_WORKING:
Alex Deucher148a03b2010-06-03 19:00:03 -0400231 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
232 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400233 *value = false;
Alex Deucher148a03b2010-06-03 19:00:03 -0400234 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400235 *value = rdev->accel_working;
Jerome Glisse733289c2009-09-16 15:24:21 +0200236 break;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200237 case RADEON_INFO_CRTC_FROM_ID:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100238 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400239 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
240 return -EFAULT;
241 }
Jerome Glissebc35afd2010-05-12 18:01:13 +0200242 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
243 crtc = (struct drm_crtc *)minfo->crtcs[i];
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400244 if (crtc && crtc->base.id == *value) {
Alex Deucher0baf2d82010-07-21 14:05:35 -0400245 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400246 *value = radeon_crtc->crtc_id;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200247 found = 1;
248 break;
249 }
250 }
251 if (!found) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400252 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
Jerome Glissebc35afd2010-05-12 18:01:13 +0200253 return -EINVAL;
254 }
255 break;
Alex Deucher148a03b2010-06-03 19:00:03 -0400256 case RADEON_INFO_ACCEL_WORKING2:
Alex Deucher3c64bd22014-08-01 20:05:30 +0200257 if (rdev->family == CHIP_HAWAII) {
Andreas Boll9eb401a2014-08-01 20:05:32 +0200258 if (rdev->accel_working) {
259 if (rdev->new_fw)
260 *value = 3;
261 else
262 *value = 2;
263 } else {
Alex Deucher3c64bd22014-08-01 20:05:30 +0200264 *value = 0;
Andreas Boll9eb401a2014-08-01 20:05:32 +0200265 }
Alex Deucher3c64bd22014-08-01 20:05:30 +0200266 } else {
267 *value = rdev->accel_working;
268 }
Alex Deucher148a03b2010-06-03 19:00:03 -0400269 break;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400270 case RADEON_INFO_TILING_CONFIG:
Alex Deucher64f759c2012-07-06 17:40:32 -0400271 if (rdev->family >= CHIP_BONAIRE)
272 *value = rdev->config.cik.tile_config;
273 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400274 *value = rdev->config.si.tile_config;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400275 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400276 *value = rdev->config.cayman.tile_config;
Alex Deucherfecf1d02011-03-02 20:07:29 -0500277 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400278 *value = rdev->config.evergreen.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400279 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400280 *value = rdev->config.rv770.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400281 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400282 *value = rdev->config.r600.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400283 else {
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000284 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400285 return -EINVAL;
286 }
Alex Deucherb824b362010-08-12 08:25:47 -0400287 break;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000288 case RADEON_INFO_WANT_HYPERZ:
Marek Olšák43861f72010-08-07 03:36:34 +0200289 /* The "value" here is both an input and output parameter.
290 * If the input value is 1, filp requests hyper-z access.
291 * If the input value is 0, filp revokes its hyper-z access.
292 *
293 * When returning, the value is 1 if filp owns hyper-z access,
294 * 0 otherwise. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100295 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400296 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
297 return -EFAULT;
298 }
299 if (*value >= 2) {
300 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
Marek Olšák43861f72010-08-07 03:36:34 +0200301 return -EINVAL;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000302 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400303 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100304 break;
305 case RADEON_INFO_WANT_CMASK:
306 /* The same logic as Hyper-Z. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100307 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400308 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
309 return -EFAULT;
310 }
311 if (*value >= 2) {
312 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100313 return -EINVAL;
Marek Olšák43861f72010-08-07 03:36:34 +0200314 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400315 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400316 break;
Alex Deucher58bbf012011-01-24 17:14:26 -0500317 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
318 /* return clock value in KHz */
Alex Deucher454d2e22013-02-14 10:04:02 -0500319 if (rdev->asic->get_xclk)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400320 *value = radeon_get_xclk(rdev) * 10;
Alex Deucher454d2e22013-02-14 10:04:02 -0500321 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400322 *value = rdev->clock.spll.reference_freq * 10;
Alex Deucher58bbf012011-01-24 17:14:26 -0500323 break;
Dave Airlie486af182011-03-01 14:32:27 +1000324 case RADEON_INFO_NUM_BACKENDS:
Alex Deucher64f759c2012-07-06 17:40:32 -0400325 if (rdev->family >= CHIP_BONAIRE)
326 *value = rdev->config.cik.max_backends_per_se *
327 rdev->config.cik.max_shader_engines;
328 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400329 *value = rdev->config.si.max_backends_per_se *
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400330 rdev->config.si.max_shader_engines;
331 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400332 *value = rdev->config.cayman.max_backends_per_se *
Alex Deucherfecf1d02011-03-02 20:07:29 -0500333 rdev->config.cayman.max_shader_engines;
334 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400335 *value = rdev->config.evergreen.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000336 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400337 *value = rdev->config.rv770.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000338 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400339 *value = rdev->config.r600.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000340 else {
341 return -EINVAL;
342 }
343 break;
Alex Deucher65659452011-04-26 13:27:43 -0400344 case RADEON_INFO_NUM_TILE_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400345 if (rdev->family >= CHIP_BONAIRE)
346 *value = rdev->config.cik.max_tile_pipes;
347 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400348 *value = rdev->config.si.max_tile_pipes;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400349 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400350 *value = rdev->config.cayman.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400351 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400352 *value = rdev->config.evergreen.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400353 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400354 *value = rdev->config.rv770.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400355 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400356 *value = rdev->config.r600.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400357 else {
358 return -EINVAL;
359 }
360 break;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400361 case RADEON_INFO_FUSION_GART_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400362 *value = 1;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400363 break;
Alex Deuchere55b9422011-07-15 19:53:52 +0000364 case RADEON_INFO_BACKEND_MAP:
Alex Deucher64f759c2012-07-06 17:40:32 -0400365 if (rdev->family >= CHIP_BONAIRE)
Michel Dänzer1ddce272013-11-18 18:25:59 +0900366 *value = rdev->config.cik.backend_map;
Alex Deucher64f759c2012-07-06 17:40:32 -0400367 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400368 *value = rdev->config.si.backend_map;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400369 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400370 *value = rdev->config.cayman.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000371 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400372 *value = rdev->config.evergreen.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000373 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400374 *value = rdev->config.rv770.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000375 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400376 *value = rdev->config.r600.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000377 else {
378 return -EINVAL;
379 }
380 break;
Jerome Glisse721604a2012-01-05 22:11:05 -0500381 case RADEON_INFO_VA_START:
382 /* this is where we report if vm is supported or not */
383 if (rdev->family < CHIP_CAYMAN)
384 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400385 *value = RADEON_VA_RESERVED_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500386 break;
387 case RADEON_INFO_IB_VM_MAX_SIZE:
388 /* this is where we report if vm is supported or not */
389 if (rdev->family < CHIP_CAYMAN)
390 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400391 *value = RADEON_IB_VM_MAX_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500392 break;
Tom Stellard609c1e12012-03-20 17:17:55 -0400393 case RADEON_INFO_MAX_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400394 if (rdev->family >= CHIP_BONAIRE)
395 *value = rdev->config.cik.max_cu_per_sh;
396 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400397 *value = rdev->config.si.max_cu_per_sh;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400398 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400399 *value = rdev->config.cayman.max_pipes_per_simd;
Tom Stellard609c1e12012-03-20 17:17:55 -0400400 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400401 *value = rdev->config.evergreen.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400402 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400403 *value = rdev->config.rv770.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400404 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400405 *value = rdev->config.r600.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400406 else {
407 return -EINVAL;
408 }
409 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400410 case RADEON_INFO_TIMESTAMP:
411 if (rdev->family < CHIP_R600) {
412 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
413 return -EINVAL;
414 }
415 value = (uint32_t*)&value64;
416 value_size = sizeof(uint64_t);
417 value64 = radeon_get_gpu_clock_counter(rdev);
418 break;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500419 case RADEON_INFO_MAX_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400420 if (rdev->family >= CHIP_BONAIRE)
421 *value = rdev->config.cik.max_shader_engines;
422 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400423 *value = rdev->config.si.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500424 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400425 *value = rdev->config.cayman.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500426 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400427 *value = rdev->config.evergreen.num_ses;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500428 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400429 *value = 1;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500430 break;
431 case RADEON_INFO_MAX_SH_PER_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400432 if (rdev->family >= CHIP_BONAIRE)
433 *value = rdev->config.cik.max_sh_per_se;
434 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400435 *value = rdev->config.si.max_sh_per_se;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500436 else
437 return -EINVAL;
438 break;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400439 case RADEON_INFO_FASTFB_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400440 *value = rdev->fastfb_working;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400441 break;
Christian König902aaef2013-04-09 10:35:42 -0400442 case RADEON_INFO_RING_WORKING:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100443 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400444 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
445 return -EFAULT;
446 }
447 switch (*value) {
Christian König902aaef2013-04-09 10:35:42 -0400448 case RADEON_CS_RING_GFX:
449 case RADEON_CS_RING_COMPUTE:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400450 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400451 break;
452 case RADEON_CS_RING_DMA:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400453 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
454 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400455 break;
456 case RADEON_CS_RING_UVD:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400457 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400458 break;
Christian Königf7ba8b02014-01-27 10:16:06 -0700459 case RADEON_CS_RING_VCE:
460 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
461 break;
Christian König902aaef2013-04-09 10:35:42 -0400462 default:
463 return -EINVAL;
464 }
465 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400466 case RADEON_INFO_SI_TILE_MODE_ARRAY:
Alex Deucher64f759c2012-07-06 17:40:32 -0400467 if (rdev->family >= CHIP_BONAIRE) {
Alex Deucher39aee492013-04-10 13:41:25 -0400468 value = rdev->config.cik.tile_mode_array;
469 value_size = sizeof(uint32_t)*32;
470 } else if (rdev->family >= CHIP_TAHITI) {
471 value = rdev->config.si.tile_mode_array;
472 value_size = sizeof(uint32_t)*32;
473 } else {
474 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
Alex Deucher64f759c2012-07-06 17:40:32 -0400475 return -EINVAL;
476 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400477 break;
Michel Dänzer32f79a82013-11-18 18:26:00 +0900478 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
479 if (rdev->family >= CHIP_BONAIRE) {
480 value = rdev->config.cik.macrotile_mode_array;
481 value_size = sizeof(uint32_t)*16;
482 } else {
483 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
484 return -EINVAL;
485 }
486 break;
Tom Stellarde5b9e752013-08-16 17:47:39 -0400487 case RADEON_INFO_SI_CP_DMA_COMPUTE:
488 *value = 1;
489 break;
Marek Olšák439a1cf2013-12-22 02:18:01 +0100490 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
491 if (rdev->family >= CHIP_BONAIRE) {
492 *value = rdev->config.cik.backend_enable_mask;
493 } else if (rdev->family >= CHIP_TAHITI) {
494 *value = rdev->config.si.backend_enable_mask;
495 } else {
496 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
497 }
498 break;
Alex Deucherf5f1f892014-01-20 18:20:29 -0500499 case RADEON_INFO_MAX_SCLK:
500 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
501 rdev->pm.dpm_enabled)
502 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
503 else
504 *value = rdev->pm.default_sclk * 10;
505 break;
Christian König98ccc292014-01-23 09:50:49 -0700506 case RADEON_INFO_VCE_FW_VERSION:
507 *value = rdev->vce.fw_version;
508 break;
509 case RADEON_INFO_VCE_FB_VERSION:
510 *value = rdev->vce.fb_version;
511 break;
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100512 case RADEON_INFO_NUM_BYTES_MOVED:
513 value = (uint32_t*)&value64;
514 value_size = sizeof(uint64_t);
515 value64 = atomic64_read(&rdev->num_bytes_moved);
516 break;
517 case RADEON_INFO_VRAM_USAGE:
518 value = (uint32_t*)&value64;
519 value_size = sizeof(uint64_t);
520 value64 = atomic64_read(&rdev->vram_usage);
521 break;
522 case RADEON_INFO_GTT_USAGE:
523 value = (uint32_t*)&value64;
524 value_size = sizeof(uint64_t);
525 value64 = atomic64_read(&rdev->gtt_usage);
526 break;
Alex Deucher65fcf662014-06-02 16:13:21 -0400527 case RADEON_INFO_ACTIVE_CU_COUNT:
528 if (rdev->family >= CHIP_BONAIRE)
529 *value = rdev->config.cik.active_cus;
530 else if (rdev->family >= CHIP_TAHITI)
531 *value = rdev->config.si.active_cus;
532 else if (rdev->family >= CHIP_CAYMAN)
533 *value = rdev->config.cayman.active_simds;
534 else if (rdev->family >= CHIP_CEDAR)
535 *value = rdev->config.evergreen.active_simds;
536 else if (rdev->family >= CHIP_RV770)
537 *value = rdev->config.rv770.active_simds;
538 else if (rdev->family >= CHIP_R600)
539 *value = rdev->config.r600.active_simds;
540 else
541 *value = 1;
542 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200543 default:
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000544 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200545 return -EINVAL;
546 }
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100547 if (copy_to_user(value_ptr, (char*)value, value_size)) {
Marek Olšák6759a0a2012-08-09 16:34:17 +0200548 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200549 return -EFAULT;
550 }
551 return 0;
552}
553
554
555/*
556 * Outdated mess for old drm with Xorg being in charge (void function now).
557 */
Alex Deucherf482a142012-07-17 14:02:34 -0400558/**
Alex Deucherf482a142012-07-17 14:02:34 -0400559 * radeon_driver_firstopen_kms - drm callback for last close
560 *
561 * @dev: drm dev pointer
562 *
563 * Switch vga switcheroo state after last close (all asics).
564 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200565void radeon_driver_lastclose_kms(struct drm_device *dev)
566{
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000567 vga_switcheroo_process_delayed_switch();
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200568}
569
Alex Deucherf482a142012-07-17 14:02:34 -0400570/**
571 * radeon_driver_open_kms - drm callback for open
572 *
573 * @dev: drm dev pointer
574 * @file_priv: drm file
575 *
576 * On device open, init vm on cayman+ (all asics).
577 * Returns 0 on success, error on failure.
578 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200579int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
580{
Jerome Glisse721604a2012-01-05 22:11:05 -0500581 struct radeon_device *rdev = dev->dev_private;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000582 int r;
Jerome Glisse721604a2012-01-05 22:11:05 -0500583
584 file_priv->driver_priv = NULL;
585
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000586 r = pm_runtime_get_sync(dev->dev);
587 if (r < 0)
588 return r;
589
Jerome Glisse721604a2012-01-05 22:11:05 -0500590 /* new gpu have virtual address space support */
591 if (rdev->family >= CHIP_CAYMAN) {
592 struct radeon_fpriv *fpriv;
Christian Königcc9e67e2014-07-18 13:48:10 +0200593 struct radeon_vm *vm;
Jerome Glisse721604a2012-01-05 22:11:05 -0500594 int r;
595
596 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
597 if (unlikely(!fpriv)) {
598 return -ENOMEM;
599 }
600
Christian Königcc9e67e2014-07-18 13:48:10 +0200601 vm = &fpriv->vm;
602 r = radeon_vm_init(rdev, vm);
Quentin Casasnovas74073c92014-03-18 17:16:52 +0100603 if (r) {
604 kfree(fpriv);
Christian König6d2f2942014-02-20 13:42:17 +0100605 return r;
Quentin Casasnovas74073c92014-03-18 17:16:52 +0100606 }
Christian Königd72d43c2012-10-09 13:31:18 +0200607
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400608 if (rdev->accel_working) {
609 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
610 if (r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200611 radeon_vm_fini(rdev, vm);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400612 kfree(fpriv);
613 return r;
614 }
615
616 /* map the ib pool buffer read only into
617 * virtual address space */
Christian Königcc9e67e2014-07-18 13:48:10 +0200618 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
619 rdev->ring_tmp_bo.bo);
620 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
621 RADEON_VA_IB_OFFSET,
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400622 RADEON_VM_PAGE_READABLE |
623 RADEON_VM_PAGE_SNOOPED);
624
625 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
626 if (r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200627 radeon_vm_fini(rdev, vm);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400628 kfree(fpriv);
629 return r;
630 }
Quentin Casasnovas74073c92014-03-18 17:16:52 +0100631 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500632 file_priv->driver_priv = fpriv;
633 }
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000634
635 pm_runtime_mark_last_busy(dev->dev);
636 pm_runtime_put_autosuspend(dev->dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200637 return 0;
638}
639
Alex Deucherf482a142012-07-17 14:02:34 -0400640/**
641 * radeon_driver_postclose_kms - drm callback for post close
642 *
643 * @dev: drm dev pointer
644 * @file_priv: drm file
645 *
646 * On device post close, tear down vm on cayman+ (all asics).
647 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200648void radeon_driver_postclose_kms(struct drm_device *dev,
649 struct drm_file *file_priv)
650{
Jerome Glisse721604a2012-01-05 22:11:05 -0500651 struct radeon_device *rdev = dev->dev_private;
652
653 /* new gpu have virtual address space support */
654 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
655 struct radeon_fpriv *fpriv = file_priv->driver_priv;
Christian Königcc9e67e2014-07-18 13:48:10 +0200656 struct radeon_vm *vm = &fpriv->vm;
Christian Königd72d43c2012-10-09 13:31:18 +0200657 int r;
658
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400659 if (rdev->accel_working) {
660 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
661 if (!r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200662 if (vm->ib_bo_va)
663 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400664 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
665 }
Christian Königd72d43c2012-10-09 13:31:18 +0200666 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500667
Christian Königcc9e67e2014-07-18 13:48:10 +0200668 radeon_vm_fini(rdev, vm);
Jerome Glisse721604a2012-01-05 22:11:05 -0500669 kfree(fpriv);
670 file_priv->driver_priv = NULL;
671 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200672}
673
Alex Deucherf482a142012-07-17 14:02:34 -0400674/**
675 * radeon_driver_preclose_kms - drm callback for pre close
676 *
677 * @dev: drm dev pointer
678 * @file_priv: drm file
679 *
680 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
681 * (all asics).
682 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200683void radeon_driver_preclose_kms(struct drm_device *dev,
684 struct drm_file *file_priv)
685{
Dave Airlieab9e1f52010-07-13 11:11:11 +1000686 struct radeon_device *rdev = dev->dev_private;
687 if (rdev->hyperz_filp == file_priv)
688 rdev->hyperz_filp = NULL;
Marek Olšákdca0d612011-01-27 22:46:15 +0100689 if (rdev->cmask_filp == file_priv)
690 rdev->cmask_filp = NULL;
Christian Königf2ba57b2013-04-08 12:41:29 +0200691 radeon_uvd_free_handles(rdev, file_priv);
Christian Königd93f7932013-05-23 12:10:04 +0200692 radeon_vce_free_handles(rdev, file_priv);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200693}
694
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200695/*
696 * VBlank related functions.
697 */
Alex Deucherf482a142012-07-17 14:02:34 -0400698/**
699 * radeon_get_vblank_counter_kms - get frame count
700 *
701 * @dev: drm dev pointer
702 * @crtc: crtc to get the frame count from
703 *
704 * Gets the frame count on the requested crtc (all asics).
705 * Returns frame count on success, -EINVAL on failure.
706 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200707u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
708{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200709 struct radeon_device *rdev = dev->dev_private;
710
Dave Airlie9c950a42010-04-23 13:21:58 +1000711 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200712 DRM_ERROR("Invalid crtc %d\n", crtc);
713 return -EINVAL;
714 }
715
716 return radeon_get_vblank_counter(rdev, crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200717}
718
Alex Deucherf482a142012-07-17 14:02:34 -0400719/**
720 * radeon_enable_vblank_kms - enable vblank interrupt
721 *
722 * @dev: drm dev pointer
723 * @crtc: crtc to enable vblank interrupt for
724 *
725 * Enable the interrupt on the requested crtc (all asics).
726 * Returns 0 on success, -EINVAL on failure.
727 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200728int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
729{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200730 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200731 unsigned long irqflags;
732 int r;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200733
Dave Airlie9c950a42010-04-23 13:21:58 +1000734 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200735 DRM_ERROR("Invalid crtc %d\n", crtc);
736 return -EINVAL;
737 }
738
Christian Koenigfb982572012-05-17 01:33:30 +0200739 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200740 rdev->irq.crtc_vblank_int[crtc] = true;
Christian Koenigfb982572012-05-17 01:33:30 +0200741 r = radeon_irq_set(rdev);
742 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
743 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200744}
745
Alex Deucherf482a142012-07-17 14:02:34 -0400746/**
747 * radeon_disable_vblank_kms - disable vblank interrupt
748 *
749 * @dev: drm dev pointer
750 * @crtc: crtc to disable vblank interrupt for
751 *
752 * Disable the interrupt on the requested crtc (all asics).
753 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200754void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
755{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200756 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200757 unsigned long irqflags;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200758
Dave Airlie9c950a42010-04-23 13:21:58 +1000759 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200760 DRM_ERROR("Invalid crtc %d\n", crtc);
761 return;
762 }
763
Christian Koenigfb982572012-05-17 01:33:30 +0200764 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200765 rdev->irq.crtc_vblank_int[crtc] = false;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200766 radeon_irq_set(rdev);
Christian Koenigfb982572012-05-17 01:33:30 +0200767 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200768}
769
Alex Deucherf482a142012-07-17 14:02:34 -0400770/**
771 * radeon_get_vblank_timestamp_kms - get vblank timestamp
772 *
773 * @dev: drm dev pointer
774 * @crtc: crtc to get the timestamp for
775 * @max_error: max error
776 * @vblank_time: time value
777 * @flags: flags passed to the driver
778 *
779 * Gets the timestamp on the requested crtc based on the
780 * scanout position. (all asics).
781 * Returns postive status flags on success, negative error on failure.
782 */
Mario Kleinerf5a80202010-10-23 04:42:17 +0200783int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
784 int *max_error,
785 struct timeval *vblank_time,
786 unsigned flags)
787{
788 struct drm_crtc *drmcrtc;
789 struct radeon_device *rdev = dev->dev_private;
790
791 if (crtc < 0 || crtc >= dev->num_crtcs) {
792 DRM_ERROR("Invalid crtc %d\n", crtc);
793 return -EINVAL;
794 }
795
796 /* Get associated drm_crtc: */
797 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
798
799 /* Helper routine in DRM core does all the work: */
800 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
801 vblank_time, flags,
Ville Syrjälä7da903e2013-10-26 17:57:31 +0300802 drmcrtc, &drmcrtc->hwmode);
Mario Kleinerf5a80202010-10-23 04:42:17 +0200803}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200804
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200805#define KMS_INVALID_IOCTL(name) \
Rashika Kheriaf6e2e402014-01-06 21:06:44 +0530806static int name(struct drm_device *dev, void *data, struct drm_file \
807 *file_priv) \
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200808{ \
809 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
810 return -EINVAL; \
811}
812
813/*
814 * All these ioctls are invalid in kms world.
815 */
816KMS_INVALID_IOCTL(radeon_cp_init_kms)
817KMS_INVALID_IOCTL(radeon_cp_start_kms)
818KMS_INVALID_IOCTL(radeon_cp_stop_kms)
819KMS_INVALID_IOCTL(radeon_cp_reset_kms)
820KMS_INVALID_IOCTL(radeon_cp_idle_kms)
821KMS_INVALID_IOCTL(radeon_cp_resume_kms)
822KMS_INVALID_IOCTL(radeon_engine_reset_kms)
823KMS_INVALID_IOCTL(radeon_fullscreen_kms)
824KMS_INVALID_IOCTL(radeon_cp_swap_kms)
825KMS_INVALID_IOCTL(radeon_cp_clear_kms)
826KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
827KMS_INVALID_IOCTL(radeon_cp_indices_kms)
828KMS_INVALID_IOCTL(radeon_cp_texture_kms)
829KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
830KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
831KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
832KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
833KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
834KMS_INVALID_IOCTL(radeon_cp_flip_kms)
835KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
836KMS_INVALID_IOCTL(radeon_mem_free_kms)
837KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
838KMS_INVALID_IOCTL(radeon_irq_emit_kms)
839KMS_INVALID_IOCTL(radeon_irq_wait_kms)
840KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
841KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
842KMS_INVALID_IOCTL(radeon_surface_free_kms)
843
844
Rob Clarkbaa70942013-08-02 13:27:49 -0400845const struct drm_ioctl_desc radeon_ioctls_kms[] = {
Dave Airlie1b2f1482010-08-14 20:20:34 +1000846 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
847 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
848 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
849 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
850 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
851 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
852 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
853 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
854 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
855 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
856 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
857 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
858 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
859 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
860 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
861 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
862 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
863 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
864 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
865 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
866 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
867 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
868 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
869 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
870 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
871 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
872 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200873 /* KMS */
Christian Königf33bcab2013-08-25 18:29:03 +0200874 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
875 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
876 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
877 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Dave Airlie1b2f1482010-08-14 20:20:34 +1000878 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
879 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
Christian Königf33bcab2013-08-25 18:29:03 +0200880 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
881 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
882 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
883 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
884 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
885 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
886 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Marek Olšákbda72d52014-03-02 00:56:17 +0100887 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Christian Königf72a113a2014-08-07 09:36:00 +0200888 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200889};
Damien Lespiauf95aeb12014-06-09 14:39:49 +0100890int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);