blob: b533a53090f2c5fe6598c5a3f36e773fa2dea1fa [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
62#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020063#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020064#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010069#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020070#include "spectrum_dpipe.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020071#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020072
73static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
74static const char mlxsw_sp_driver_version[] = "1.0";
75
76/* tx_hdr_version
77 * Tx header version.
78 * Must be set to 1.
79 */
80MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
81
82/* tx_hdr_ctl
83 * Packet control type.
84 * 0 - Ethernet control (e.g. EMADs, LACP)
85 * 1 - Ethernet data
86 */
87MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
88
89/* tx_hdr_proto
90 * Packet protocol type. Must be set to 1 (Ethernet).
91 */
92MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
93
94/* tx_hdr_rx_is_router
95 * Packet is sent from the router. Valid for data packets only.
96 */
97MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
98
99/* tx_hdr_fid_valid
100 * Indicates if the 'fid' field is valid and should be used for
101 * forwarding lookup. Valid for data packets only.
102 */
103MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
104
105/* tx_hdr_swid
106 * Switch partition ID. Must be set to 0.
107 */
108MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
109
110/* tx_hdr_control_tclass
111 * Indicates if the packet should use the control TClass and not one
112 * of the data TClasses.
113 */
114MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
115
116/* tx_hdr_etclass
117 * Egress TClass to be used on the egress device on the egress port.
118 */
119MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
120
121/* tx_hdr_port_mid
122 * Destination local port for unicast packets.
123 * Destination multicast ID for multicast packets.
124 *
125 * Control packets are directed to a specific egress port, while data
126 * packets are transmitted through the CPU port (0) into the switch partition,
127 * where forwarding rules are applied.
128 */
129MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
130
131/* tx_hdr_fid
132 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
133 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
134 * Valid for data packets only.
135 */
136MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
137
138/* tx_hdr_type
139 * 0 - Data packets
140 * 6 - Control packets
141 */
142MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
143
Yotam Gigie5e5c882017-05-23 21:56:27 +0200144struct mlxsw_sp_mlxfw_dev {
145 struct mlxfw_dev mlxfw_dev;
146 struct mlxsw_sp *mlxsw_sp;
147};
148
149static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
150 u16 component_index, u32 *p_max_size,
151 u8 *p_align_bits, u16 *p_max_write_size)
152{
153 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
154 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
155 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
156 char mcqi_pl[MLXSW_REG_MCQI_LEN];
157 int err;
158
159 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
160 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
161 if (err)
162 return err;
163 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
164 p_max_write_size);
165
166 *p_align_bits = max_t(u8, *p_align_bits, 2);
167 *p_max_write_size = min_t(u16, *p_max_write_size,
168 MLXSW_REG_MCDA_MAX_DATA_LEN);
169 return 0;
170}
171
172static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
173{
174 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
175 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
176 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
177 char mcc_pl[MLXSW_REG_MCC_LEN];
178 u8 control_state;
179 int err;
180
181 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
182 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
183 if (err)
184 return err;
185
186 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
187 if (control_state != MLXFW_FSM_STATE_IDLE)
188 return -EBUSY;
189
190 mlxsw_reg_mcc_pack(mcc_pl,
191 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
192 0, *fwhandle, 0);
193 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
194}
195
196static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
197 u32 fwhandle, u16 component_index,
198 u32 component_size)
199{
200 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
201 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
202 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
203 char mcc_pl[MLXSW_REG_MCC_LEN];
204
205 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
206 component_index, fwhandle, component_size);
207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
208}
209
210static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
211 u32 fwhandle, u8 *data, u16 size,
212 u32 offset)
213{
214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
217 char mcda_pl[MLXSW_REG_MCDA_LEN];
218
219 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
220 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
221}
222
223static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
224 u32 fwhandle, u16 component_index)
225{
226 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
227 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
228 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
229 char mcc_pl[MLXSW_REG_MCC_LEN];
230
231 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
232 component_index, fwhandle, 0);
233 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
234}
235
236static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
237{
238 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
239 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
240 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
241 char mcc_pl[MLXSW_REG_MCC_LEN];
242
243 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
244 fwhandle, 0);
245 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
246}
247
248static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
249 enum mlxfw_fsm_state *fsm_state,
250 enum mlxfw_fsm_state_err *fsm_state_err)
251{
252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
255 char mcc_pl[MLXSW_REG_MCC_LEN];
256 u8 control_state;
257 u8 error_code;
258 int err;
259
260 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
261 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
262 if (err)
263 return err;
264
265 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
266 *fsm_state = control_state;
267 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
268 MLXFW_FSM_STATE_ERR_MAX);
269 return 0;
270}
271
272static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
273{
274 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
275 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
276 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
277 char mcc_pl[MLXSW_REG_MCC_LEN];
278
279 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
280 fwhandle, 0);
281 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
282}
283
284static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
285{
286 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
287 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
288 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
289 char mcc_pl[MLXSW_REG_MCC_LEN];
290
291 mlxsw_reg_mcc_pack(mcc_pl,
292 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
293 fwhandle, 0);
294 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
295}
296
297static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
298 .component_query = mlxsw_sp_component_query,
299 .fsm_lock = mlxsw_sp_fsm_lock,
300 .fsm_component_update = mlxsw_sp_fsm_component_update,
301 .fsm_block_download = mlxsw_sp_fsm_block_download,
302 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
303 .fsm_activate = mlxsw_sp_fsm_activate,
304 .fsm_query_state = mlxsw_sp_fsm_query_state,
305 .fsm_cancel = mlxsw_sp_fsm_cancel,
306 .fsm_release = mlxsw_sp_fsm_release
307};
308
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100309int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
310 unsigned int counter_index, u64 *packets,
311 u64 *bytes)
312{
313 char mgpc_pl[MLXSW_REG_MGPC_LEN];
314 int err;
315
316 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
317 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
318 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
319 if (err)
320 return err;
321 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
322 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
323 return 0;
324}
325
326static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
327 unsigned int counter_index)
328{
329 char mgpc_pl[MLXSW_REG_MGPC_LEN];
330
331 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
332 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
333 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
334}
335
336int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
337 unsigned int *p_counter_index)
338{
339 int err;
340
341 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
342 p_counter_index);
343 if (err)
344 return err;
345 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
346 if (err)
347 goto err_counter_clear;
348 return 0;
349
350err_counter_clear:
351 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
352 *p_counter_index);
353 return err;
354}
355
356void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
357 unsigned int counter_index)
358{
359 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
360 counter_index);
361}
362
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200363static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
364 const struct mlxsw_tx_info *tx_info)
365{
366 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
367
368 memset(txhdr, 0, MLXSW_TXHDR_LEN);
369
370 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
371 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
372 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
373 mlxsw_tx_hdr_swid_set(txhdr, 0);
374 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
375 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
376 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
377}
378
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200379int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
380 u8 state)
381{
382 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
383 enum mlxsw_reg_spms_state spms_state;
384 char *spms_pl;
385 int err;
386
387 switch (state) {
388 case BR_STATE_FORWARDING:
389 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
390 break;
391 case BR_STATE_LEARNING:
392 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
393 break;
394 case BR_STATE_LISTENING: /* fall-through */
395 case BR_STATE_DISABLED: /* fall-through */
396 case BR_STATE_BLOCKING:
397 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
398 break;
399 default:
400 BUG();
401 }
402
403 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
404 if (!spms_pl)
405 return -ENOMEM;
406 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
407 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
408
409 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
410 kfree(spms_pl);
411 return err;
412}
413
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200414static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
415{
Elad Raz5b090742016-10-28 21:35:46 +0200416 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200417 int err;
418
419 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
420 if (err)
421 return err;
422 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
423 return 0;
424}
425
Yotam Gigi763b4b72016-07-21 12:03:17 +0200426static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
427{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200428 int i;
429
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200430 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200431 return -EIO;
432
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200433 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
434 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200435 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
436 sizeof(struct mlxsw_sp_span_entry),
437 GFP_KERNEL);
438 if (!mlxsw_sp->span.entries)
439 return -ENOMEM;
440
441 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
442 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
443
444 return 0;
445}
446
447static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
448{
449 int i;
450
451 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
452 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
453
454 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
455 }
456 kfree(mlxsw_sp->span.entries);
457}
458
459static struct mlxsw_sp_span_entry *
460mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
461{
462 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
463 struct mlxsw_sp_span_entry *span_entry;
464 char mpat_pl[MLXSW_REG_MPAT_LEN];
465 u8 local_port = port->local_port;
466 int index;
467 int i;
468 int err;
469
470 /* find a free entry to use */
471 index = -1;
472 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
473 if (!mlxsw_sp->span.entries[i].used) {
474 index = i;
475 span_entry = &mlxsw_sp->span.entries[i];
476 break;
477 }
478 }
479 if (index < 0)
480 return NULL;
481
482 /* create a new port analayzer entry for local_port */
483 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
484 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
485 if (err)
486 return NULL;
487
488 span_entry->used = true;
489 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100490 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200491 span_entry->local_port = local_port;
492 return span_entry;
493}
494
495static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
496 struct mlxsw_sp_span_entry *span_entry)
497{
498 u8 local_port = span_entry->local_port;
499 char mpat_pl[MLXSW_REG_MPAT_LEN];
500 int pa_id = span_entry->id;
501
502 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
503 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
504 span_entry->used = false;
505}
506
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200507static struct mlxsw_sp_span_entry *
508mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200509{
510 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
511 int i;
512
513 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
514 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
515
516 if (curr->used && curr->local_port == port->local_port)
517 return curr;
518 }
519 return NULL;
520}
521
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200522static struct mlxsw_sp_span_entry
523*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200524{
525 struct mlxsw_sp_span_entry *span_entry;
526
527 span_entry = mlxsw_sp_span_entry_find(port);
528 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100529 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200530 span_entry->ref_count++;
531 return span_entry;
532 }
533
534 return mlxsw_sp_span_entry_create(port);
535}
536
537static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
538 struct mlxsw_sp_span_entry *span_entry)
539{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100540 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200541 if (--span_entry->ref_count == 0)
542 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
543 return 0;
544}
545
546static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
547{
548 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
549 struct mlxsw_sp_span_inspected_port *p;
550 int i;
551
552 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
553 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
554
555 list_for_each_entry(p, &curr->bound_ports_list, list)
556 if (p->local_port == port->local_port &&
557 p->type == MLXSW_SP_SPAN_EGRESS)
558 return true;
559 }
560
561 return false;
562}
563
Ido Schimmel18281f22017-03-24 08:02:51 +0100564static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
565 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200566{
Ido Schimmel18281f22017-03-24 08:02:51 +0100567 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200568}
569
570static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
571{
572 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
573 char sbib_pl[MLXSW_REG_SBIB_LEN];
574 int err;
575
576 /* If port is egress mirrored, the shared buffer size should be
577 * updated according to the mtu value
578 */
579 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100580 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
581
582 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200583 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
584 if (err) {
585 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
586 return err;
587 }
588 }
589
590 return 0;
591}
592
593static struct mlxsw_sp_span_inspected_port *
594mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
595 struct mlxsw_sp_span_entry *span_entry)
596{
597 struct mlxsw_sp_span_inspected_port *p;
598
599 list_for_each_entry(p, &span_entry->bound_ports_list, list)
600 if (port->local_port == p->local_port)
601 return p;
602 return NULL;
603}
604
605static int
606mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
607 struct mlxsw_sp_span_entry *span_entry,
608 enum mlxsw_sp_span_type type)
609{
610 struct mlxsw_sp_span_inspected_port *inspected_port;
611 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
612 char mpar_pl[MLXSW_REG_MPAR_LEN];
613 char sbib_pl[MLXSW_REG_SBIB_LEN];
614 int pa_id = span_entry->id;
615 int err;
616
617 /* if it is an egress SPAN, bind a shared buffer to it */
618 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100619 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
620 port->dev->mtu);
621
622 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200623 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
624 if (err) {
625 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
626 return err;
627 }
628 }
629
630 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200631 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
632 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200633 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
634 if (err)
635 goto err_mpar_reg_write;
636
637 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
638 if (!inspected_port) {
639 err = -ENOMEM;
640 goto err_inspected_port_alloc;
641 }
642 inspected_port->local_port = port->local_port;
643 inspected_port->type = type;
644 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
645
646 return 0;
647
648err_mpar_reg_write:
649err_inspected_port_alloc:
650 if (type == MLXSW_SP_SPAN_EGRESS) {
651 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
652 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
653 }
654 return err;
655}
656
657static void
658mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
659 struct mlxsw_sp_span_entry *span_entry,
660 enum mlxsw_sp_span_type type)
661{
662 struct mlxsw_sp_span_inspected_port *inspected_port;
663 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
664 char mpar_pl[MLXSW_REG_MPAR_LEN];
665 char sbib_pl[MLXSW_REG_SBIB_LEN];
666 int pa_id = span_entry->id;
667
668 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
669 if (!inspected_port)
670 return;
671
672 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200673 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
674 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200675 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
676
677 /* remove the SBIB buffer if it was egress SPAN */
678 if (type == MLXSW_SP_SPAN_EGRESS) {
679 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
680 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
681 }
682
683 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
684
685 list_del(&inspected_port->list);
686 kfree(inspected_port);
687}
688
689static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
690 struct mlxsw_sp_port *to,
691 enum mlxsw_sp_span_type type)
692{
693 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
694 struct mlxsw_sp_span_entry *span_entry;
695 int err;
696
697 span_entry = mlxsw_sp_span_entry_get(to);
698 if (!span_entry)
699 return -ENOENT;
700
701 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
702 span_entry->id);
703
704 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
705 if (err)
706 goto err_port_bind;
707
708 return 0;
709
710err_port_bind:
711 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
712 return err;
713}
714
715static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
716 struct mlxsw_sp_port *to,
717 enum mlxsw_sp_span_type type)
718{
719 struct mlxsw_sp_span_entry *span_entry;
720
721 span_entry = mlxsw_sp_span_entry_find(to);
722 if (!span_entry) {
723 netdev_err(from->dev, "no span entry found\n");
724 return;
725 }
726
727 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
728 span_entry->id);
729 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
730}
731
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100732static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
733 bool enable, u32 rate)
734{
735 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
736 char mpsc_pl[MLXSW_REG_MPSC_LEN];
737
738 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
739 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
740}
741
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200742static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
743 bool is_up)
744{
745 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
746 char paos_pl[MLXSW_REG_PAOS_LEN];
747
748 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
749 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
750 MLXSW_PORT_ADMIN_STATUS_DOWN);
751 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
752}
753
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200754static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
755 unsigned char *addr)
756{
757 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
758 char ppad_pl[MLXSW_REG_PPAD_LEN];
759
760 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
761 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
762 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
763}
764
765static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
766{
767 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
768 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
769
770 ether_addr_copy(addr, mlxsw_sp->base_mac);
771 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
772 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
773}
774
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200775static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
776{
777 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
778 char pmtu_pl[MLXSW_REG_PMTU_LEN];
779 int max_mtu;
780 int err;
781
782 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
783 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
784 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
785 if (err)
786 return err;
787 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
788
789 if (mtu > max_mtu)
790 return -EINVAL;
791
792 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
793 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
794}
795
Ido Schimmelbe945352016-06-09 09:51:39 +0200796static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
797 u8 swid)
798{
799 char pspa_pl[MLXSW_REG_PSPA_LEN];
800
801 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
802 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
803}
804
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200805static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
806{
807 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200808
Ido Schimmelbe945352016-06-09 09:51:39 +0200809 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
810 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200811}
812
813static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
814 bool enable)
815{
816 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
817 char svpe_pl[MLXSW_REG_SVPE_LEN];
818
819 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
820 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
821}
822
823int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
824 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
825 u16 vid)
826{
827 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
828 char svfa_pl[MLXSW_REG_SVFA_LEN];
829
830 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
831 fid, vid);
832 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
833}
834
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200835int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
836 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200837{
838 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
839 char *spvmlr_pl;
840 int err;
841
842 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
843 if (!spvmlr_pl)
844 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200845 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
846 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200847 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
848 kfree(spvmlr_pl);
849 return err;
850}
851
Ido Schimmelb02eae92017-05-16 19:38:34 +0200852static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
853 u16 vid)
854{
855 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
856 char spvid_pl[MLXSW_REG_SPVID_LEN];
857
858 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
859 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
860}
861
862static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
863 bool allow)
864{
865 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
866 char spaft_pl[MLXSW_REG_SPAFT_LEN];
867
868 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
869 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
870}
871
872int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
873{
874 int err;
875
876 if (!vid) {
877 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
878 if (err)
879 return err;
880 } else {
881 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
882 if (err)
883 return err;
884 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
885 if (err)
886 goto err_port_allow_untagged_set;
887 }
888
889 mlxsw_sp_port->pvid = vid;
890 return 0;
891
892err_port_allow_untagged_set:
893 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
894 return err;
895}
896
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897static int
898mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
899{
900 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
901 char sspr_pl[MLXSW_REG_SSPR_LEN];
902
903 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
904 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
905}
906
Ido Schimmeld664b412016-06-09 09:51:40 +0200907static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
908 u8 local_port, u8 *p_module,
909 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200910{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200911 char pmlp_pl[MLXSW_REG_PMLP_LEN];
912 int err;
913
Ido Schimmel558c2d52016-02-26 17:32:29 +0100914 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200915 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
916 if (err)
917 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100918 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
919 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200920 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200921 return 0;
922}
923
Ido Schimmel18f1e702016-02-26 17:32:31 +0100924static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
925 u8 module, u8 width, u8 lane)
926{
927 char pmlp_pl[MLXSW_REG_PMLP_LEN];
928 int i;
929
930 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
931 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
932 for (i = 0; i < width; i++) {
933 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
934 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
935 }
936
937 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
938}
939
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100940static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
941{
942 char pmlp_pl[MLXSW_REG_PMLP_LEN];
943
944 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
945 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
946 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
947}
948
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200949static int mlxsw_sp_port_open(struct net_device *dev)
950{
951 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
952 int err;
953
954 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
955 if (err)
956 return err;
957 netif_start_queue(dev);
958 return 0;
959}
960
961static int mlxsw_sp_port_stop(struct net_device *dev)
962{
963 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
964
965 netif_stop_queue(dev);
966 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
967}
968
969static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
970 struct net_device *dev)
971{
972 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
973 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
974 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
975 const struct mlxsw_tx_info tx_info = {
976 .local_port = mlxsw_sp_port->local_port,
977 .is_emad = false,
978 };
979 u64 len;
980 int err;
981
Jiri Pirko307c2432016-04-08 19:11:22 +0200982 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200983 return NETDEV_TX_BUSY;
984
985 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
986 struct sk_buff *skb_orig = skb;
987
988 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
989 if (!skb) {
990 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
991 dev_kfree_skb_any(skb_orig);
992 return NETDEV_TX_OK;
993 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100994 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200995 }
996
997 if (eth_skb_pad(skb)) {
998 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
999 return NETDEV_TX_OK;
1000 }
1001
1002 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001003 /* TX header is consumed by HW on the way so we shouldn't count its
1004 * bytes as being sent.
1005 */
1006 len = skb->len - MLXSW_TXHDR_LEN;
1007
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001008 /* Due to a race we might fail here because of a full queue. In that
1009 * unlikely case we simply drop the packet.
1010 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001011 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001012
1013 if (!err) {
1014 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1015 u64_stats_update_begin(&pcpu_stats->syncp);
1016 pcpu_stats->tx_packets++;
1017 pcpu_stats->tx_bytes += len;
1018 u64_stats_update_end(&pcpu_stats->syncp);
1019 } else {
1020 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1021 dev_kfree_skb_any(skb);
1022 }
1023 return NETDEV_TX_OK;
1024}
1025
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001026static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1027{
1028}
1029
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001030static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1031{
1032 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1033 struct sockaddr *addr = p;
1034 int err;
1035
1036 if (!is_valid_ether_addr(addr->sa_data))
1037 return -EADDRNOTAVAIL;
1038
1039 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1040 if (err)
1041 return err;
1042 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1043 return 0;
1044}
1045
Ido Schimmel18281f22017-03-24 08:02:51 +01001046static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1047 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001048{
Ido Schimmel18281f22017-03-24 08:02:51 +01001049 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001050}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001051
Ido Schimmelf417f042017-03-24 08:02:50 +01001052#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001053
1054static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1055 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001056{
Ido Schimmel18281f22017-03-24 08:02:51 +01001057 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1058 BITS_PER_BYTE));
1059 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1060 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001061}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001062
Ido Schimmel18281f22017-03-24 08:02:51 +01001063/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001064 * Assumes 100m cable and maximum MTU.
1065 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001066#define MLXSW_SP_PAUSE_DELAY 58752
1067
1068static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1069 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001070{
1071 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001072 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001073 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001074 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001075 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001076 return 0;
1077}
1078
1079static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1080 bool lossy)
1081{
1082 if (lossy)
1083 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1084 else
1085 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1086 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001087}
1088
1089int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001090 u8 *prio_tc, bool pause_en,
1091 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001092{
1093 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001094 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1095 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001096 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001097 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001098
1099 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1100 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1101 if (err)
1102 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001103
1104 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1105 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001106 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001107 bool lossy;
1108 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001109
1110 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1111 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001112 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001113 configure = true;
1114 break;
1115 }
1116 }
1117
1118 if (!configure)
1119 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001120
1121 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001122 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1123 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1124 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001125 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001126 }
1127
Ido Schimmelff6551e2016-04-06 17:10:03 +02001128 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1129}
1130
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001131static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001132 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001133{
1134 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1135 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001136 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001137 u8 *prio_tc;
1138
1139 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001140 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001141
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001142 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001143 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001144}
1145
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001146static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1147{
1148 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001149 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001150 int err;
1151
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001152 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001153 if (err)
1154 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001155 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1156 if (err)
1157 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001158 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1159 if (err)
1160 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001161 dev->mtu = mtu;
1162 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001163
1164err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001165 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1166err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001167 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001168 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001169}
1170
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001171static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001172mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1173 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001174{
1175 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1176 struct mlxsw_sp_port_pcpu_stats *p;
1177 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1178 u32 tx_dropped = 0;
1179 unsigned int start;
1180 int i;
1181
1182 for_each_possible_cpu(i) {
1183 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1184 do {
1185 start = u64_stats_fetch_begin_irq(&p->syncp);
1186 rx_packets = p->rx_packets;
1187 rx_bytes = p->rx_bytes;
1188 tx_packets = p->tx_packets;
1189 tx_bytes = p->tx_bytes;
1190 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1191
1192 stats->rx_packets += rx_packets;
1193 stats->rx_bytes += rx_bytes;
1194 stats->tx_packets += tx_packets;
1195 stats->tx_bytes += tx_bytes;
1196 /* tx_dropped is u32, updated without syncp protection. */
1197 tx_dropped += p->tx_dropped;
1198 }
1199 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001200 return 0;
1201}
1202
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001203static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001204{
1205 switch (attr_id) {
1206 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1207 return true;
1208 }
1209
1210 return false;
1211}
1212
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001213static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1214 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001215{
1216 switch (attr_id) {
1217 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1218 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1219 }
1220
1221 return -EINVAL;
1222}
1223
1224static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1225 int prio, char *ppcnt_pl)
1226{
1227 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1228 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1229
1230 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1231 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1232}
1233
1234static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1235 struct rtnl_link_stats64 *stats)
1236{
1237 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1238 int err;
1239
1240 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1241 0, ppcnt_pl);
1242 if (err)
1243 goto out;
1244
1245 stats->tx_packets =
1246 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1247 stats->rx_packets =
1248 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1249 stats->tx_bytes =
1250 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1251 stats->rx_bytes =
1252 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1253 stats->multicast =
1254 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1255
1256 stats->rx_crc_errors =
1257 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1258 stats->rx_frame_errors =
1259 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1260
1261 stats->rx_length_errors = (
1262 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1263 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1264 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1265
1266 stats->rx_errors = (stats->rx_crc_errors +
1267 stats->rx_frame_errors + stats->rx_length_errors);
1268
1269out:
1270 return err;
1271}
1272
1273static void update_stats_cache(struct work_struct *work)
1274{
1275 struct mlxsw_sp_port *mlxsw_sp_port =
1276 container_of(work, struct mlxsw_sp_port,
1277 hw_stats.update_dw.work);
1278
1279 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1280 goto out;
1281
1282 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1283 mlxsw_sp_port->hw_stats.cache);
1284
1285out:
1286 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1287 MLXSW_HW_STATS_UPDATE_TIME);
1288}
1289
1290/* Return the stats from a cache that is updated periodically,
1291 * as this function might get called in an atomic context.
1292 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001293static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001294mlxsw_sp_port_get_stats64(struct net_device *dev,
1295 struct rtnl_link_stats64 *stats)
1296{
1297 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1298
1299 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001300}
1301
Jiri Pirko93cd0812017-04-18 16:55:35 +02001302static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1303 u16 vid_begin, u16 vid_end,
1304 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001305{
1306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1307 char *spvm_pl;
1308 int err;
1309
1310 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1311 if (!spvm_pl)
1312 return -ENOMEM;
1313
1314 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1315 vid_end, is_member, untagged);
1316 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1317 kfree(spvm_pl);
1318 return err;
1319}
1320
Jiri Pirko93cd0812017-04-18 16:55:35 +02001321int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1322 u16 vid_end, bool is_member, bool untagged)
1323{
1324 u16 vid, vid_e;
1325 int err;
1326
1327 for (vid = vid_begin; vid <= vid_end;
1328 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1329 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1330 vid_end);
1331
1332 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1333 is_member, untagged);
1334 if (err)
1335 return err;
1336 }
1337
1338 return 0;
1339}
1340
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001341static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1342{
1343 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1344 u16 vid, last_visited_vid;
1345 int err;
1346
1347 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1348 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
1349 vid);
1350 if (err) {
1351 last_visited_vid = vid;
1352 goto err_port_vid_to_fid_set;
1353 }
1354 }
1355
1356 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
1357 if (err) {
1358 last_visited_vid = VLAN_N_VID;
1359 goto err_port_vid_to_fid_set;
1360 }
1361
1362 return 0;
1363
1364err_port_vid_to_fid_set:
1365 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1366 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1367 vid);
1368 return err;
1369}
1370
1371static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1372{
1373 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1374 u16 vid;
1375 int err;
1376
1377 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1378 if (err)
1379 return err;
1380
1381 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1382 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1383 vid, vid);
1384 if (err)
1385 return err;
1386 }
1387
1388 return 0;
1389}
1390
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001391static struct mlxsw_sp_port *
Ido Schimmel0355b592016-06-20 23:04:13 +02001392mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001393{
1394 struct mlxsw_sp_port *mlxsw_sp_vport;
1395
1396 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1397 if (!mlxsw_sp_vport)
1398 return NULL;
1399
1400 /* dev will be set correctly after the VLAN device is linked
1401 * with the real device. In case of bridge SELF invocation, dev
1402 * will remain as is.
1403 */
1404 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1405 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1406 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1407 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +01001408 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1409 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel0355b592016-06-20 23:04:13 +02001410 mlxsw_sp_vport->vport.vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001411
1412 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1413
1414 return mlxsw_sp_vport;
1415}
1416
1417static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1418{
1419 list_del(&mlxsw_sp_vport->vport.list);
1420 kfree(mlxsw_sp_vport);
1421}
1422
Ido Schimmel05978482016-08-17 16:39:30 +02001423static int mlxsw_sp_port_add_vid(struct net_device *dev,
1424 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001425{
1426 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001427 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel52697a92016-07-02 11:00:09 +02001428 bool untagged = vid == 1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001429 int err;
1430
1431 /* VLAN 0 is added to HW filter when device goes up, but it is
1432 * reserved in our case, so simply return.
1433 */
1434 if (!vid)
1435 return 0;
1436
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001437 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001438 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001439
Ido Schimmel0355b592016-06-20 23:04:13 +02001440 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001441 if (!mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02001442 return -ENOMEM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001443
1444 /* When adding the first VLAN interface on a bridged port we need to
1445 * transition all the active 802.1Q bridge VLANs to use explicit
1446 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1447 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001448 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001449 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001450 if (err)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001451 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001452 }
1453
Ido Schimmel52697a92016-07-02 11:00:09 +02001454 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001455 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001456 goto err_port_add_vid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001457
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001458 return 0;
1459
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001460err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001461 if (list_is_singular(&mlxsw_sp_port->vports_list))
1462 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1463err_port_vp_mode_trans:
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001464 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001465 return err;
1466}
1467
Ido Schimmel32d863f2016-07-02 11:00:10 +02001468static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1469 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001470{
1471 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001472 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel1c800752016-06-20 23:04:20 +02001473 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001474
1475 /* VLAN 0 is removed from HW filter when device goes down, but
1476 * it is reserved in our case, so simply return.
1477 */
1478 if (!vid)
1479 return 0;
1480
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001481 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel7a355832016-08-17 16:39:28 +02001482 if (WARN_ON(!mlxsw_sp_vport))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001483 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001484
Ido Schimmel7a355832016-08-17 16:39:28 +02001485 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001486
Ido Schimmel1c800752016-06-20 23:04:20 +02001487 /* Drop FID reference. If this was the last reference the
1488 * resources will be freed.
1489 */
1490 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1491 if (f && !WARN_ON(!f->leave))
1492 f->leave(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001493
1494 /* When removing the last VLAN interface on a bridged port we need to
1495 * transition all active 802.1Q bridge VLANs to use VID to FID
1496 * mappings and set port's mode to VLAN mode.
1497 */
Ido Schimmel7a355832016-08-17 16:39:28 +02001498 if (list_is_singular(&mlxsw_sp_port->vports_list))
1499 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001500
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001501 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1502
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001503 return 0;
1504}
1505
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001506static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1507 size_t len)
1508{
1509 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001510 u8 module = mlxsw_sp_port->mapping.module;
1511 u8 width = mlxsw_sp_port->mapping.width;
1512 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001513 int err;
1514
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001515 if (!mlxsw_sp_port->split)
1516 err = snprintf(name, len, "p%d", module + 1);
1517 else
1518 err = snprintf(name, len, "p%ds%d", module + 1,
1519 lane / width);
1520
1521 if (err >= len)
1522 return -EINVAL;
1523
1524 return 0;
1525}
1526
Yotam Gigi763b4b72016-07-21 12:03:17 +02001527static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001528mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1529 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001530 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1531
1532 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1533 if (mall_tc_entry->cookie == cookie)
1534 return mall_tc_entry;
1535
1536 return NULL;
1537}
1538
1539static int
1540mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001541 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001542 const struct tc_action *a,
1543 bool ingress)
1544{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001545 struct net *net = dev_net(mlxsw_sp_port->dev);
1546 enum mlxsw_sp_span_type span_type;
1547 struct mlxsw_sp_port *to_port;
1548 struct net_device *to_dev;
1549 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001550
1551 ifindex = tcf_mirred_ifindex(a);
1552 to_dev = __dev_get_by_index(net, ifindex);
1553 if (!to_dev) {
1554 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1555 return -EINVAL;
1556 }
1557
1558 if (!mlxsw_sp_port_dev_check(to_dev)) {
1559 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001560 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001561 }
1562 to_port = netdev_priv(to_dev);
1563
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001564 mirror->to_local_port = to_port->local_port;
1565 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001566 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001567 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1568}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001569
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001570static void
1571mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1572 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1573{
1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1575 enum mlxsw_sp_span_type span_type;
1576 struct mlxsw_sp_port *to_port;
1577
1578 to_port = mlxsw_sp->ports[mirror->to_local_port];
1579 span_type = mirror->ingress ?
1580 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1581 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001582}
1583
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001584static int
1585mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1586 struct tc_cls_matchall_offload *cls,
1587 const struct tc_action *a,
1588 bool ingress)
1589{
1590 int err;
1591
1592 if (!mlxsw_sp_port->sample)
1593 return -EOPNOTSUPP;
1594 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1595 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1596 return -EEXIST;
1597 }
1598 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1599 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1600 return -EOPNOTSUPP;
1601 }
1602
1603 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1604 tcf_sample_psample_group(a));
1605 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1606 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1607 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1608
1609 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1610 if (err)
1611 goto err_port_sample_set;
1612 return 0;
1613
1614err_port_sample_set:
1615 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1616 return err;
1617}
1618
1619static void
1620mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1621{
1622 if (!mlxsw_sp_port->sample)
1623 return;
1624
1625 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1626 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1627}
1628
Yotam Gigi763b4b72016-07-21 12:03:17 +02001629static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1630 __be16 protocol,
1631 struct tc_cls_matchall_offload *cls,
1632 bool ingress)
1633{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001634 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001635 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001636 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001637 int err;
1638
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001639 if (!tc_single_action(cls->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001640 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001641 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001642 }
1643
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001644 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1645 if (!mall_tc_entry)
1646 return -ENOMEM;
1647 mall_tc_entry->cookie = cls->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001648
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001649 tcf_exts_to_list(cls->exts, &actions);
1650 a = list_first_entry(&actions, struct tc_action, list);
1651
1652 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1653 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1654
1655 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1656 mirror = &mall_tc_entry->mirror;
1657 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1658 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001659 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1660 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1661 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1662 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001663 } else {
1664 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001665 }
1666
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001667 if (err)
1668 goto err_add_action;
1669
1670 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001671 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001672
1673err_add_action:
1674 kfree(mall_tc_entry);
1675 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001676}
1677
1678static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1679 struct tc_cls_matchall_offload *cls)
1680{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001681 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001682
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001683 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1684 cls->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001685 if (!mall_tc_entry) {
1686 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1687 return;
1688 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001689 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001690
1691 switch (mall_tc_entry->type) {
1692 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001693 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1694 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001695 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001696 case MLXSW_SP_PORT_MALL_SAMPLE:
1697 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1698 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001699 default:
1700 WARN_ON(1);
1701 }
1702
Yotam Gigi763b4b72016-07-21 12:03:17 +02001703 kfree(mall_tc_entry);
1704}
1705
1706static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1707 __be16 proto, struct tc_to_netdev *tc)
1708{
1709 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1710 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1711
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001712 switch (tc->type) {
1713 case TC_SETUP_MATCHALL:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001714 switch (tc->cls_mall->command) {
1715 case TC_CLSMATCHALL_REPLACE:
1716 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1717 proto,
1718 tc->cls_mall,
1719 ingress);
1720 case TC_CLSMATCHALL_DESTROY:
1721 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1722 tc->cls_mall);
1723 return 0;
1724 default:
Or Gerlitzabbdf4b2017-03-17 09:38:01 +01001725 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001726 }
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001727 case TC_SETUP_CLSFLOWER:
1728 switch (tc->cls_flower->command) {
1729 case TC_CLSFLOWER_REPLACE:
1730 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1731 proto, tc->cls_flower);
1732 case TC_CLSFLOWER_DESTROY:
1733 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1734 tc->cls_flower);
1735 return 0;
Arkadi Sharshevsky7c1b8eb2017-03-11 09:42:59 +01001736 case TC_CLSFLOWER_STATS:
1737 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1738 tc->cls_flower);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001739 default:
1740 return -EOPNOTSUPP;
1741 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001742 }
1743
Yotam Gigie915ac62017-01-09 11:25:48 +01001744 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001745}
1746
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001747static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1748 .ndo_open = mlxsw_sp_port_open,
1749 .ndo_stop = mlxsw_sp_port_stop,
1750 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001751 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001752 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001753 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1754 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1755 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001756 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1757 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001758 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1759 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1760 .ndo_fdb_add = switchdev_port_fdb_add,
1761 .ndo_fdb_del = switchdev_port_fdb_del,
1762 .ndo_fdb_dump = switchdev_port_fdb_dump,
1763 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1764 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1765 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001766 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001767};
1768
1769static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1770 struct ethtool_drvinfo *drvinfo)
1771{
1772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1773 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1774
1775 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1776 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1777 sizeof(drvinfo->version));
1778 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1779 "%d.%d.%d",
1780 mlxsw_sp->bus_info->fw_rev.major,
1781 mlxsw_sp->bus_info->fw_rev.minor,
1782 mlxsw_sp->bus_info->fw_rev.subminor);
1783 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1784 sizeof(drvinfo->bus_info));
1785}
1786
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001787static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1788 struct ethtool_pauseparam *pause)
1789{
1790 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1791
1792 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1793 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1794}
1795
1796static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1797 struct ethtool_pauseparam *pause)
1798{
1799 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1800
1801 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1802 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1803 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1804
1805 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1806 pfcc_pl);
1807}
1808
1809static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1810 struct ethtool_pauseparam *pause)
1811{
1812 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1813 bool pause_en = pause->tx_pause || pause->rx_pause;
1814 int err;
1815
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001816 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1817 netdev_err(dev, "PFC already enabled on port\n");
1818 return -EINVAL;
1819 }
1820
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001821 if (pause->autoneg) {
1822 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1823 return -EINVAL;
1824 }
1825
1826 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1827 if (err) {
1828 netdev_err(dev, "Failed to configure port's headroom\n");
1829 return err;
1830 }
1831
1832 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1833 if (err) {
1834 netdev_err(dev, "Failed to set PAUSE parameters\n");
1835 goto err_port_pause_configure;
1836 }
1837
1838 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1839 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1840
1841 return 0;
1842
1843err_port_pause_configure:
1844 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1845 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1846 return err;
1847}
1848
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001849struct mlxsw_sp_port_hw_stats {
1850 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001851 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001852 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001853};
1854
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001855static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001856 {
1857 .str = "a_frames_transmitted_ok",
1858 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1859 },
1860 {
1861 .str = "a_frames_received_ok",
1862 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1863 },
1864 {
1865 .str = "a_frame_check_sequence_errors",
1866 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1867 },
1868 {
1869 .str = "a_alignment_errors",
1870 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1871 },
1872 {
1873 .str = "a_octets_transmitted_ok",
1874 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1875 },
1876 {
1877 .str = "a_octets_received_ok",
1878 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1879 },
1880 {
1881 .str = "a_multicast_frames_xmitted_ok",
1882 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1883 },
1884 {
1885 .str = "a_broadcast_frames_xmitted_ok",
1886 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1887 },
1888 {
1889 .str = "a_multicast_frames_received_ok",
1890 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1891 },
1892 {
1893 .str = "a_broadcast_frames_received_ok",
1894 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1895 },
1896 {
1897 .str = "a_in_range_length_errors",
1898 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1899 },
1900 {
1901 .str = "a_out_of_range_length_field",
1902 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1903 },
1904 {
1905 .str = "a_frame_too_long_errors",
1906 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1907 },
1908 {
1909 .str = "a_symbol_error_during_carrier",
1910 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1911 },
1912 {
1913 .str = "a_mac_control_frames_transmitted",
1914 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1915 },
1916 {
1917 .str = "a_mac_control_frames_received",
1918 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1919 },
1920 {
1921 .str = "a_unsupported_opcodes_received",
1922 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1923 },
1924 {
1925 .str = "a_pause_mac_ctrl_frames_received",
1926 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1927 },
1928 {
1929 .str = "a_pause_mac_ctrl_frames_xmitted",
1930 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1931 },
1932};
1933
1934#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1935
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001936static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1937 {
1938 .str = "rx_octets_prio",
1939 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1940 },
1941 {
1942 .str = "rx_frames_prio",
1943 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1944 },
1945 {
1946 .str = "tx_octets_prio",
1947 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1948 },
1949 {
1950 .str = "tx_frames_prio",
1951 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1952 },
1953 {
1954 .str = "rx_pause_prio",
1955 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1956 },
1957 {
1958 .str = "rx_pause_duration_prio",
1959 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1960 },
1961 {
1962 .str = "tx_pause_prio",
1963 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1964 },
1965 {
1966 .str = "tx_pause_duration_prio",
1967 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1968 },
1969};
1970
1971#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1972
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001973static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1974 {
1975 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001976 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1977 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001978 },
1979 {
1980 .str = "tc_no_buffer_discard_uc_tc",
1981 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1982 },
1983};
1984
1985#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1986
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001987#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001988 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1989 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001990 IEEE_8021QAZ_MAX_TCS)
1991
1992static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1993{
1994 int i;
1995
1996 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1997 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1998 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1999 *p += ETH_GSTRING_LEN;
2000 }
2001}
2002
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002003static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2004{
2005 int i;
2006
2007 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2008 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2009 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2010 *p += ETH_GSTRING_LEN;
2011 }
2012}
2013
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002014static void mlxsw_sp_port_get_strings(struct net_device *dev,
2015 u32 stringset, u8 *data)
2016{
2017 u8 *p = data;
2018 int i;
2019
2020 switch (stringset) {
2021 case ETH_SS_STATS:
2022 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2023 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2024 ETH_GSTRING_LEN);
2025 p += ETH_GSTRING_LEN;
2026 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002027
2028 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2029 mlxsw_sp_port_get_prio_strings(&p, i);
2030
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002031 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2032 mlxsw_sp_port_get_tc_strings(&p, i);
2033
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002034 break;
2035 }
2036}
2037
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002038static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2039 enum ethtool_phys_id_state state)
2040{
2041 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2042 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2043 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2044 bool active;
2045
2046 switch (state) {
2047 case ETHTOOL_ID_ACTIVE:
2048 active = true;
2049 break;
2050 case ETHTOOL_ID_INACTIVE:
2051 active = false;
2052 break;
2053 default:
2054 return -EOPNOTSUPP;
2055 }
2056
2057 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2058 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2059}
2060
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002061static int
2062mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2063 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2064{
2065 switch (grp) {
2066 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2067 *p_hw_stats = mlxsw_sp_port_hw_stats;
2068 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2069 break;
2070 case MLXSW_REG_PPCNT_PRIO_CNT:
2071 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2072 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2073 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002074 case MLXSW_REG_PPCNT_TC_CNT:
2075 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2076 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2077 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002078 default:
2079 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002080 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002081 }
2082 return 0;
2083}
2084
2085static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2086 enum mlxsw_reg_ppcnt_grp grp, int prio,
2087 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002088{
Ido Schimmel18281f22017-03-24 08:02:51 +01002089 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002091 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002092 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002093 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002094 int err;
2095
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002096 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2097 if (err)
2098 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002099 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002100 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002101 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002102 if (!hw_stats[i].cells_bytes)
2103 continue;
2104 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2105 data[data_index + i]);
2106 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002107}
2108
2109static void mlxsw_sp_port_get_stats(struct net_device *dev,
2110 struct ethtool_stats *stats, u64 *data)
2111{
2112 int i, data_index = 0;
2113
2114 /* IEEE 802.3 Counters */
2115 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2116 data, data_index);
2117 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2118
2119 /* Per-Priority Counters */
2120 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2121 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2122 data, data_index);
2123 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2124 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002125
2126 /* Per-TC Counters */
2127 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2128 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2129 data, data_index);
2130 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2131 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002132}
2133
2134static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2135{
2136 switch (sset) {
2137 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002138 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002139 default:
2140 return -EOPNOTSUPP;
2141 }
2142}
2143
2144struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002145 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002146 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002147 u32 speed;
2148};
2149
2150static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2151 {
2152 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002153 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2154 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002155 },
2156 {
2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2158 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002159 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2160 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002161 },
2162 {
2163 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002164 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2165 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002166 },
2167 {
2168 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2169 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002170 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2171 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002172 },
2173 {
2174 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2175 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2176 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2177 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002178 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2179 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002180 },
2181 {
2182 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002183 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2184 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002185 },
2186 {
2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002188 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2189 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002190 },
2191 {
2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002193 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2194 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002195 },
2196 {
2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002198 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2199 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002200 },
2201 {
2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002203 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2204 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002205 },
2206 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002207 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2208 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2209 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002210 },
2211 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002212 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2213 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2214 .speed = SPEED_25000,
2215 },
2216 {
2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2218 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2219 .speed = SPEED_25000,
2220 },
2221 {
2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2223 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2224 .speed = SPEED_25000,
2225 },
2226 {
2227 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2228 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2229 .speed = SPEED_50000,
2230 },
2231 {
2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2233 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2234 .speed = SPEED_50000,
2235 },
2236 {
2237 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2238 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2239 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002240 },
2241 {
2242 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002243 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2244 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002245 },
2246 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002247 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2248 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2249 .speed = SPEED_56000,
2250 },
2251 {
2252 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2253 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2254 .speed = SPEED_56000,
2255 },
2256 {
2257 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2258 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2259 .speed = SPEED_56000,
2260 },
2261 {
2262 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2263 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2264 .speed = SPEED_100000,
2265 },
2266 {
2267 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2268 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2269 .speed = SPEED_100000,
2270 },
2271 {
2272 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2273 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2274 .speed = SPEED_100000,
2275 },
2276 {
2277 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2278 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2279 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002280 },
2281};
2282
2283#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2284
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002285static void
2286mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2287 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002288{
2289 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2290 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2291 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2292 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2293 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2294 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002295 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002296
2297 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2298 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2299 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2300 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2301 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002302 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002303}
2304
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002305static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002306{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002307 int i;
2308
2309 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2310 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002311 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2312 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002313 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002314}
2315
2316static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002317 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002318{
2319 u32 speed = SPEED_UNKNOWN;
2320 u8 duplex = DUPLEX_UNKNOWN;
2321 int i;
2322
2323 if (!carrier_ok)
2324 goto out;
2325
2326 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2327 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2328 speed = mlxsw_sp_port_link_mode[i].speed;
2329 duplex = DUPLEX_FULL;
2330 break;
2331 }
2332 }
2333out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002334 cmd->base.speed = speed;
2335 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002336}
2337
2338static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2339{
2340 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2341 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2342 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2343 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2344 return PORT_FIBRE;
2345
2346 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2347 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2348 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2349 return PORT_DA;
2350
2351 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2352 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2353 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2354 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2355 return PORT_NONE;
2356
2357 return PORT_OTHER;
2358}
2359
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002360static u32
2361mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002362{
2363 u32 ptys_proto = 0;
2364 int i;
2365
2366 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002367 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2368 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002369 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2370 }
2371 return ptys_proto;
2372}
2373
2374static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2375{
2376 u32 ptys_proto = 0;
2377 int i;
2378
2379 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2380 if (speed == mlxsw_sp_port_link_mode[i].speed)
2381 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2382 }
2383 return ptys_proto;
2384}
2385
Ido Schimmel18f1e702016-02-26 17:32:31 +01002386static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2387{
2388 u32 ptys_proto = 0;
2389 int i;
2390
2391 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2392 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2393 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2394 }
2395 return ptys_proto;
2396}
2397
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002398static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2399 struct ethtool_link_ksettings *cmd)
2400{
2401 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2402 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2403 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2404
2405 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2406 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2407}
2408
2409static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2410 struct ethtool_link_ksettings *cmd)
2411{
2412 if (!autoneg)
2413 return;
2414
2415 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2416 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2417}
2418
2419static void
2420mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2421 struct ethtool_link_ksettings *cmd)
2422{
2423 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2424 return;
2425
2426 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2427 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2428}
2429
2430static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2431 struct ethtool_link_ksettings *cmd)
2432{
2433 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2434 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2435 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2436 char ptys_pl[MLXSW_REG_PTYS_LEN];
2437 u8 autoneg_status;
2438 bool autoneg;
2439 int err;
2440
2441 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002442 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002443 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2444 if (err)
2445 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002446 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2447 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002448
2449 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2450
2451 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2452
2453 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2454 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2455 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2456
2457 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2458 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2459 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2460 cmd);
2461
2462 return 0;
2463}
2464
2465static int
2466mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2467 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002468{
2469 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2470 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2471 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002472 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002473 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002474 int err;
2475
Elad Raz401c8b42016-10-28 21:35:52 +02002476 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002477 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002478 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002479 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002480 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002481
2482 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2483 eth_proto_new = autoneg ?
2484 mlxsw_sp_to_ptys_advert_link(cmd) :
2485 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002486
2487 eth_proto_new = eth_proto_new & eth_proto_cap;
2488 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002489 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002490 return -EINVAL;
2491 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002492
Elad Raz401c8b42016-10-28 21:35:52 +02002493 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2494 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002495 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002496 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002497 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002498
Ido Schimmel6277d462016-07-15 11:14:58 +02002499 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002500 return 0;
2501
Ido Schimmel0c83f882016-09-12 13:26:23 +02002502 mlxsw_sp_port->link.autoneg = autoneg;
2503
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002504 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2505 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002506
2507 return 0;
2508}
2509
2510static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2511 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2512 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002513 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2514 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002515 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002516 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002517 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2518 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002519 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2520 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002521};
2522
Ido Schimmel18f1e702016-02-26 17:32:31 +01002523static int
2524mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2525{
2526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2527 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2528 char ptys_pl[MLXSW_REG_PTYS_LEN];
2529 u32 eth_proto_admin;
2530
2531 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002532 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2533 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002534 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2535}
2536
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002537int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2538 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2539 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002540{
2541 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2542 char qeec_pl[MLXSW_REG_QEEC_LEN];
2543
2544 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2545 next_index);
2546 mlxsw_reg_qeec_de_set(qeec_pl, true);
2547 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2548 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2549 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2550}
2551
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002552int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2553 enum mlxsw_reg_qeec_hr hr, u8 index,
2554 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002555{
2556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2557 char qeec_pl[MLXSW_REG_QEEC_LEN];
2558
2559 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2560 next_index);
2561 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2562 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2563 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2564}
2565
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002566int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2567 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002568{
2569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2570 char qtct_pl[MLXSW_REG_QTCT_LEN];
2571
2572 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2573 tclass);
2574 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2575}
2576
2577static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2578{
2579 int err, i;
2580
2581 /* Setup the elements hierarcy, so that each TC is linked to
2582 * one subgroup, which are all member in the same group.
2583 */
2584 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2585 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2586 0);
2587 if (err)
2588 return err;
2589 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2590 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2591 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2592 0, false, 0);
2593 if (err)
2594 return err;
2595 }
2596 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2597 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2598 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2599 false, 0);
2600 if (err)
2601 return err;
2602 }
2603
2604 /* Make sure the max shaper is disabled in all hierarcies that
2605 * support it.
2606 */
2607 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2608 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2609 MLXSW_REG_QEEC_MAS_DIS);
2610 if (err)
2611 return err;
2612 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2613 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2614 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2615 i, 0,
2616 MLXSW_REG_QEEC_MAS_DIS);
2617 if (err)
2618 return err;
2619 }
2620 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2621 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2622 MLXSW_REG_QEEC_HIERARCY_TC,
2623 i, i,
2624 MLXSW_REG_QEEC_MAS_DIS);
2625 if (err)
2626 return err;
2627 }
2628
2629 /* Map all priorities to traffic class 0. */
2630 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2631 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2632 if (err)
2633 return err;
2634 }
2635
2636 return 0;
2637}
2638
Ido Schimmel05978482016-08-17 16:39:30 +02002639static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2640{
2641 mlxsw_sp_port->pvid = 1;
2642
2643 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2644}
2645
2646static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2647{
2648 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2649}
2650
Jiri Pirko67963a32016-10-28 21:35:55 +02002651static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2652 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002653{
2654 struct mlxsw_sp_port *mlxsw_sp_port;
2655 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002656 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002657 int err;
2658
2659 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2660 if (!dev)
2661 return -ENOMEM;
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002662 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002663 mlxsw_sp_port = netdev_priv(dev);
2664 mlxsw_sp_port->dev = dev;
2665 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2666 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002667 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002668 mlxsw_sp_port->mapping.module = module;
2669 mlxsw_sp_port->mapping.width = width;
2670 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002671 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002672 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2673 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2674 if (!mlxsw_sp_port->active_vlans) {
2675 err = -ENOMEM;
2676 goto err_port_active_vlans_alloc;
2677 }
Elad Razfc1273a2016-01-06 13:01:11 +01002678 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2679 if (!mlxsw_sp_port->untagged_vlans) {
2680 err = -ENOMEM;
2681 goto err_port_untagged_vlans_alloc;
2682 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002683 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002684 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002685
2686 mlxsw_sp_port->pcpu_stats =
2687 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2688 if (!mlxsw_sp_port->pcpu_stats) {
2689 err = -ENOMEM;
2690 goto err_alloc_stats;
2691 }
2692
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002693 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2694 GFP_KERNEL);
2695 if (!mlxsw_sp_port->sample) {
2696 err = -ENOMEM;
2697 goto err_alloc_sample;
2698 }
2699
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002700 mlxsw_sp_port->hw_stats.cache =
2701 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2702
2703 if (!mlxsw_sp_port->hw_stats.cache) {
2704 err = -ENOMEM;
2705 goto err_alloc_hw_stats;
2706 }
2707 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2708 &update_stats_cache);
2709
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002710 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2711 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2712
Ido Schimmel3247ff22016-09-08 08:16:02 +02002713 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2714 if (err) {
2715 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2716 mlxsw_sp_port->local_port);
2717 goto err_port_swid_set;
2718 }
2719
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002720 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2721 if (err) {
2722 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2723 mlxsw_sp_port->local_port);
2724 goto err_dev_addr_init;
2725 }
2726
2727 netif_carrier_off(dev);
2728
2729 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002730 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2731 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002732
Jarod Wilsond894be52016-10-20 13:55:16 -04002733 dev->min_mtu = 0;
2734 dev->max_mtu = ETH_MAX_MTU;
2735
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002736 /* Each packet needs to have a Tx header (metadata) on top all other
2737 * headers.
2738 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002739 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002740
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002741 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2742 if (err) {
2743 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2744 mlxsw_sp_port->local_port);
2745 goto err_port_system_port_mapping_set;
2746 }
2747
Ido Schimmel18f1e702016-02-26 17:32:31 +01002748 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2749 if (err) {
2750 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2751 mlxsw_sp_port->local_port);
2752 goto err_port_speed_by_width_set;
2753 }
2754
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002755 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2756 if (err) {
2757 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2758 mlxsw_sp_port->local_port);
2759 goto err_port_mtu_set;
2760 }
2761
2762 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2763 if (err)
2764 goto err_port_admin_status_set;
2765
2766 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2767 if (err) {
2768 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2769 mlxsw_sp_port->local_port);
2770 goto err_port_buffers_init;
2771 }
2772
Ido Schimmel90183b92016-04-06 17:10:08 +02002773 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2774 if (err) {
2775 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2776 mlxsw_sp_port->local_port);
2777 goto err_port_ets_init;
2778 }
2779
Ido Schimmelf00817d2016-04-06 17:10:09 +02002780 /* ETS and buffers must be initialized before DCB. */
2781 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2782 if (err) {
2783 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2784 mlxsw_sp_port->local_port);
2785 goto err_port_dcb_init;
2786 }
2787
Ido Schimmel45a4a162017-05-16 19:38:35 +02002788 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2789 if (err) {
2790 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set non-virtual mode\n",
2791 mlxsw_sp_port->local_port);
2792 goto err_port_vp_mode_set;
2793 }
2794
Ido Schimmel05978482016-08-17 16:39:30 +02002795 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2796 if (err) {
2797 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2798 mlxsw_sp_port->local_port);
2799 goto err_port_pvid_vport_create;
2800 }
2801
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002802 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002803 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002804 err = register_netdev(dev);
2805 if (err) {
2806 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2807 mlxsw_sp_port->local_port);
2808 goto err_register_netdev;
2809 }
2810
Elad Razd808c7e2016-10-28 21:35:57 +02002811 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2812 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2813 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002814 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002815 return 0;
2816
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002817err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002818 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002819 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002820 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2821err_port_pvid_vport_create:
Ido Schimmel45a4a162017-05-16 19:38:35 +02002822err_port_vp_mode_set:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002823 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002824err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002825err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002826err_port_buffers_init:
2827err_port_admin_status_set:
2828err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002829err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002830err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002831err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002832 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2833err_port_swid_set:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002834 kfree(mlxsw_sp_port->hw_stats.cache);
2835err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002836 kfree(mlxsw_sp_port->sample);
2837err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002838 free_percpu(mlxsw_sp_port->pcpu_stats);
2839err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01002840 kfree(mlxsw_sp_port->untagged_vlans);
2841err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002842 kfree(mlxsw_sp_port->active_vlans);
2843err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002844 free_netdev(dev);
2845 return err;
2846}
2847
Jiri Pirko67963a32016-10-28 21:35:55 +02002848static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2849 bool split, u8 module, u8 width, u8 lane)
2850{
2851 int err;
2852
2853 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2854 if (err) {
2855 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2856 local_port);
2857 return err;
2858 }
Ido Schimmel9a60c902016-12-16 19:29:03 +01002859 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
Jiri Pirko67963a32016-10-28 21:35:55 +02002860 module, width, lane);
2861 if (err)
2862 goto err_port_create;
2863 return 0;
2864
2865err_port_create:
2866 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2867 return err;
2868}
2869
2870static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002871{
2872 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2873
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002874 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002875 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002876 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002877 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002878 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002879 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002880 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002881 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2882 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002883 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002884 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002885 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01002886 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002887 kfree(mlxsw_sp_port->active_vlans);
Ido Schimmel32d863f2016-07-02 11:00:10 +02002888 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002889 free_netdev(mlxsw_sp_port->dev);
2890}
2891
Jiri Pirko67963a32016-10-28 21:35:55 +02002892static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2893{
2894 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2895 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2896}
2897
Jiri Pirkof83e2102016-10-28 21:35:49 +02002898static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2899{
2900 return mlxsw_sp->ports[local_port] != NULL;
2901}
2902
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002903static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2904{
2905 int i;
2906
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002907 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002908 if (mlxsw_sp_port_created(mlxsw_sp, i))
2909 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002910 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002911 kfree(mlxsw_sp->ports);
2912}
2913
2914static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2915{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002916 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002917 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002918 size_t alloc_size;
2919 int i;
2920 int err;
2921
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002922 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002923 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2924 if (!mlxsw_sp->ports)
2925 return -ENOMEM;
2926
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002927 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
2928 if (!mlxsw_sp->port_to_module) {
2929 err = -ENOMEM;
2930 goto err_port_to_module_alloc;
2931 }
2932
2933 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01002934 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002935 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01002936 if (err)
2937 goto err_port_module_info_get;
2938 if (!width)
2939 continue;
2940 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02002941 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2942 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002943 if (err)
2944 goto err_port_create;
2945 }
2946 return 0;
2947
2948err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01002949err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002950 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002951 if (mlxsw_sp_port_created(mlxsw_sp, i))
2952 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002953 kfree(mlxsw_sp->port_to_module);
2954err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002955 kfree(mlxsw_sp->ports);
2956 return err;
2957}
2958
Ido Schimmel18f1e702016-02-26 17:32:31 +01002959static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2960{
2961 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2962
2963 return local_port - offset;
2964}
2965
Ido Schimmelbe945352016-06-09 09:51:39 +02002966static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2967 u8 module, unsigned int count)
2968{
2969 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2970 int err, i;
2971
2972 for (i = 0; i < count; i++) {
2973 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2974 width, i * width);
2975 if (err)
2976 goto err_port_module_map;
2977 }
2978
2979 for (i = 0; i < count; i++) {
2980 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2981 if (err)
2982 goto err_port_swid_set;
2983 }
2984
2985 for (i = 0; i < count; i++) {
2986 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02002987 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02002988 if (err)
2989 goto err_port_create;
2990 }
2991
2992 return 0;
2993
2994err_port_create:
2995 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002996 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2997 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02002998 i = count;
2999err_port_swid_set:
3000 for (i--; i >= 0; i--)
3001 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
3002 MLXSW_PORT_SWID_DISABLED_PORT);
3003 i = count;
3004err_port_module_map:
3005 for (i--; i >= 0; i--)
3006 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
3007 return err;
3008}
3009
3010static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3011 u8 base_port, unsigned int count)
3012{
3013 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3014 int i;
3015
3016 /* Split by four means we need to re-create two ports, otherwise
3017 * only one.
3018 */
3019 count = count / 2;
3020
3021 for (i = 0; i < count; i++) {
3022 local_port = base_port + i * 2;
3023 module = mlxsw_sp->port_to_module[local_port];
3024
3025 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
3026 0);
3027 }
3028
3029 for (i = 0; i < count; i++)
3030 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
3031
3032 for (i = 0; i < count; i++) {
3033 local_port = base_port + i * 2;
3034 module = mlxsw_sp->port_to_module[local_port];
3035
3036 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003037 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003038 }
3039}
3040
Jiri Pirkob2f10572016-04-08 19:11:23 +02003041static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3042 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003043{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003044 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003045 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003046 u8 module, cur_width, base_port;
3047 int i;
3048 int err;
3049
3050 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3051 if (!mlxsw_sp_port) {
3052 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3053 local_port);
3054 return -EINVAL;
3055 }
3056
Ido Schimmeld664b412016-06-09 09:51:40 +02003057 module = mlxsw_sp_port->mapping.module;
3058 cur_width = mlxsw_sp_port->mapping.width;
3059
Ido Schimmel18f1e702016-02-26 17:32:31 +01003060 if (count != 2 && count != 4) {
3061 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3062 return -EINVAL;
3063 }
3064
Ido Schimmel18f1e702016-02-26 17:32:31 +01003065 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3066 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3067 return -EINVAL;
3068 }
3069
3070 /* Make sure we have enough slave (even) ports for the split. */
3071 if (count == 2) {
3072 base_port = local_port;
3073 if (mlxsw_sp->ports[base_port + 1]) {
3074 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3075 return -EINVAL;
3076 }
3077 } else {
3078 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3079 if (mlxsw_sp->ports[base_port + 1] ||
3080 mlxsw_sp->ports[base_port + 3]) {
3081 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3082 return -EINVAL;
3083 }
3084 }
3085
3086 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003087 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3088 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003089
Ido Schimmelbe945352016-06-09 09:51:39 +02003090 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3091 if (err) {
3092 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3093 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003094 }
3095
3096 return 0;
3097
Ido Schimmelbe945352016-06-09 09:51:39 +02003098err_port_split_create:
3099 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003100 return err;
3101}
3102
Jiri Pirkob2f10572016-04-08 19:11:23 +02003103static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003104{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003105 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003106 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003107 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003108 unsigned int count;
3109 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003110
3111 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3112 if (!mlxsw_sp_port) {
3113 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3114 local_port);
3115 return -EINVAL;
3116 }
3117
3118 if (!mlxsw_sp_port->split) {
3119 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3120 return -EINVAL;
3121 }
3122
Ido Schimmeld664b412016-06-09 09:51:40 +02003123 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003124 count = cur_width == 1 ? 4 : 2;
3125
3126 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3127
3128 /* Determine which ports to remove. */
3129 if (count == 2 && local_port >= base_port + 2)
3130 base_port = base_port + 2;
3131
3132 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003133 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3134 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003135
Ido Schimmelbe945352016-06-09 09:51:39 +02003136 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003137
3138 return 0;
3139}
3140
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003141static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3142 char *pude_pl, void *priv)
3143{
3144 struct mlxsw_sp *mlxsw_sp = priv;
3145 struct mlxsw_sp_port *mlxsw_sp_port;
3146 enum mlxsw_reg_pude_oper_status status;
3147 u8 local_port;
3148
3149 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3150 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003151 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003152 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003153
3154 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3155 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3156 netdev_info(mlxsw_sp_port->dev, "link up\n");
3157 netif_carrier_on(mlxsw_sp_port->dev);
3158 } else {
3159 netdev_info(mlxsw_sp_port->dev, "link down\n");
3160 netif_carrier_off(mlxsw_sp_port->dev);
3161 }
3162}
3163
Nogah Frankel14eeda92016-11-25 10:33:32 +01003164static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3165 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003166{
3167 struct mlxsw_sp *mlxsw_sp = priv;
3168 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3169 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3170
3171 if (unlikely(!mlxsw_sp_port)) {
3172 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3173 local_port);
3174 return;
3175 }
3176
3177 skb->dev = mlxsw_sp_port->dev;
3178
3179 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3180 u64_stats_update_begin(&pcpu_stats->syncp);
3181 pcpu_stats->rx_packets++;
3182 pcpu_stats->rx_bytes += skb->len;
3183 u64_stats_update_end(&pcpu_stats->syncp);
3184
3185 skb->protocol = eth_type_trans(skb, skb->dev);
3186 netif_receive_skb(skb);
3187}
3188
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003189static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3190 void *priv)
3191{
3192 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003193 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003194}
3195
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003196static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3197 void *priv)
3198{
3199 struct mlxsw_sp *mlxsw_sp = priv;
3200 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3201 struct psample_group *psample_group;
3202 u32 size;
3203
3204 if (unlikely(!mlxsw_sp_port)) {
3205 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3206 local_port);
3207 goto out;
3208 }
3209 if (unlikely(!mlxsw_sp_port->sample)) {
3210 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3211 local_port);
3212 goto out;
3213 }
3214
3215 size = mlxsw_sp_port->sample->truncate ?
3216 mlxsw_sp_port->sample->trunc_size : skb->len;
3217
3218 rcu_read_lock();
3219 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3220 if (!psample_group)
3221 goto out_unlock;
3222 psample_sample_packet(psample_group, skb, size,
3223 mlxsw_sp_port->dev->ifindex, 0,
3224 mlxsw_sp_port->sample->rate);
3225out_unlock:
3226 rcu_read_unlock();
3227out:
3228 consume_skb(skb);
3229}
3230
Nogah Frankel117b0da2016-11-25 10:33:44 +01003231#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003232 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003233 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003234
Nogah Frankel117b0da2016-11-25 10:33:44 +01003235#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003236 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003237 _is_ctrl, SP_##_trap_group, DISCARD)
3238
3239#define MLXSW_SP_EVENTL(_func, _trap_id) \
3240 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003241
Nogah Frankel45449132016-11-25 10:33:35 +01003242static const struct mlxsw_listener mlxsw_sp_listener[] = {
3243 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003244 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003245 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003246 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3247 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3248 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3249 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3250 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3251 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3252 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3253 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3254 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3255 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3256 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003257 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003258 /* L3 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003259 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3260 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3261 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3262 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
3263 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3264 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3265 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
3266 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003267 /* PKT Sample trap */
3268 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3269 false, SP_IP2ME, DISCARD)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003270};
3271
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003272static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3273{
3274 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3275 enum mlxsw_reg_qpcr_ir_units ir_units;
3276 int max_cpu_policers;
3277 bool is_bytes;
3278 u8 burst_size;
3279 u32 rate;
3280 int i, err;
3281
3282 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3283 return -EIO;
3284
3285 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3286
3287 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3288 for (i = 0; i < max_cpu_policers; i++) {
3289 is_bytes = false;
3290 switch (i) {
3291 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3292 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3293 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3294 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3295 rate = 128;
3296 burst_size = 7;
3297 break;
3298 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3299 rate = 16 * 1024;
3300 burst_size = 10;
3301 break;
3302 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3303 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3304 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3305 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3306 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3307 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3308 rate = 1024;
3309 burst_size = 7;
3310 break;
3311 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3312 is_bytes = true;
3313 rate = 4 * 1024;
3314 burst_size = 4;
3315 break;
3316 default:
3317 continue;
3318 }
3319
3320 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3321 burst_size);
3322 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3323 if (err)
3324 return err;
3325 }
3326
3327 return 0;
3328}
3329
Nogah Frankel579c82e2016-11-25 10:33:42 +01003330static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003331{
3332 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003333 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003334 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003335 int max_trap_groups;
3336 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003337 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003338 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003339
3340 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3341 return -EIO;
3342
3343 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003344 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003345
3346 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003347 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003348 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003349 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3350 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3351 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3352 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3353 priority = 5;
3354 tc = 5;
3355 break;
3356 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3357 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3358 priority = 4;
3359 tc = 4;
3360 break;
3361 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3362 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3363 priority = 3;
3364 tc = 3;
3365 break;
3366 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3367 priority = 2;
3368 tc = 2;
3369 break;
3370 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3371 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3372 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3373 priority = 1;
3374 tc = 1;
3375 break;
3376 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003377 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3378 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003379 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003380 break;
3381 default:
3382 continue;
3383 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003384
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003385 if (max_cpu_policers <= policer_id &&
3386 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3387 return -EIO;
3388
3389 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003390 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3391 if (err)
3392 return err;
3393 }
3394
3395 return 0;
3396}
3397
3398static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3399{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003400 int i;
3401 int err;
3402
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003403 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3404 if (err)
3405 return err;
3406
Nogah Frankel579c82e2016-11-25 10:33:42 +01003407 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003408 if (err)
3409 return err;
3410
Nogah Frankel45449132016-11-25 10:33:35 +01003411 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003412 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003413 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003414 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003415 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003416 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003417
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003418 }
3419 return 0;
3420
Nogah Frankel45449132016-11-25 10:33:35 +01003421err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003422 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003423 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003424 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003425 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003426 }
3427 return err;
3428}
3429
3430static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3431{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003432 int i;
3433
Nogah Frankel45449132016-11-25 10:33:35 +01003434 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003435 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003436 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003437 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003438 }
3439}
3440
3441static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
3442 enum mlxsw_reg_sfgc_type type,
3443 enum mlxsw_reg_sfgc_bridge_type bridge_type)
3444{
3445 enum mlxsw_flood_table_type table_type;
3446 enum mlxsw_sp_flood_table flood_table;
3447 char sfgc_pl[MLXSW_REG_SFGC_LEN];
3448
Ido Schimmel19ae6122015-12-15 16:03:39 +01003449 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003450 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003451 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003452 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003453
Nogah Frankel71c365b2017-02-09 14:54:46 +01003454 switch (type) {
3455 case MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST:
Ido Schimmel19ae6122015-12-15 16:03:39 +01003456 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003457 break;
3458 case MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4:
Nogah Frankel71c365b2017-02-09 14:54:46 +01003459 flood_table = MLXSW_SP_FLOOD_TABLE_MC;
3460 break;
3461 default:
3462 flood_table = MLXSW_SP_FLOOD_TABLE_BC;
3463 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003464
3465 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
3466 flood_table);
3467 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
3468}
3469
3470static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
3471{
3472 int type, err;
3473
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003474 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
3475 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
3476 continue;
3477
3478 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3479 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
3480 if (err)
3481 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003482
3483 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3484 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
3485 if (err)
3486 return err;
3487 }
3488
3489 return 0;
3490}
3491
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003492static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3493{
3494 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003495 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003496
3497 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3498 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3499 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3500 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3501 MLXSW_REG_SLCR_LAG_HASH_SIP |
3502 MLXSW_REG_SLCR_LAG_HASH_DIP |
3503 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3504 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3505 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003506 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3507 if (err)
3508 return err;
3509
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003510 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3511 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003512 return -EIO;
3513
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003514 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003515 sizeof(struct mlxsw_sp_upper),
3516 GFP_KERNEL);
3517 if (!mlxsw_sp->lags)
3518 return -ENOMEM;
3519
3520 return 0;
3521}
3522
3523static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3524{
3525 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003526}
3527
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003528static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3529{
3530 char htgt_pl[MLXSW_REG_HTGT_LEN];
3531
Nogah Frankel579c82e2016-11-25 10:33:42 +01003532 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3533 MLXSW_REG_HTGT_INVALID_POLICER,
3534 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3535 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003536 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3537}
3538
Jiri Pirko202d6f42017-04-18 16:55:33 +02003539static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create);
3540
3541static int mlxsw_sp_dummy_fid_init(struct mlxsw_sp *mlxsw_sp)
3542{
3543 return mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, true);
3544}
3545
3546static void mlxsw_sp_dummy_fid_fini(struct mlxsw_sp *mlxsw_sp)
3547{
3548 mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, false);
3549}
3550
Jiri Pirkob2f10572016-04-08 19:11:23 +02003551static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003552 const struct mlxsw_bus_info *mlxsw_bus_info)
3553{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003554 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003555 int err;
3556
3557 mlxsw_sp->core = mlxsw_core;
3558 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel14d39462016-06-20 23:04:15 +02003559 INIT_LIST_HEAD(&mlxsw_sp->fids);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003560 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003561
3562 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3563 if (err) {
3564 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3565 return err;
3566 }
3567
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003568 err = mlxsw_sp_traps_init(mlxsw_sp);
3569 if (err) {
Nogah Frankel45449132016-11-25 10:33:35 +01003570 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3571 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003572 }
3573
3574 err = mlxsw_sp_flood_init(mlxsw_sp);
3575 if (err) {
3576 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3577 goto err_flood_init;
3578 }
3579
3580 err = mlxsw_sp_buffers_init(mlxsw_sp);
3581 if (err) {
3582 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3583 goto err_buffers_init;
3584 }
3585
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003586 err = mlxsw_sp_lag_init(mlxsw_sp);
3587 if (err) {
3588 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3589 goto err_lag_init;
3590 }
3591
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003592 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3593 if (err) {
3594 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3595 goto err_switchdev_init;
3596 }
3597
Ido Schimmel464dce12016-07-02 11:00:15 +02003598 err = mlxsw_sp_router_init(mlxsw_sp);
3599 if (err) {
3600 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3601 goto err_router_init;
3602 }
3603
Yotam Gigi763b4b72016-07-21 12:03:17 +02003604 err = mlxsw_sp_span_init(mlxsw_sp);
3605 if (err) {
3606 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3607 goto err_span_init;
3608 }
3609
Jiri Pirko22a67762017-02-03 10:29:07 +01003610 err = mlxsw_sp_acl_init(mlxsw_sp);
3611 if (err) {
3612 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3613 goto err_acl_init;
3614 }
3615
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003616 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3617 if (err) {
3618 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3619 goto err_counter_pool_init;
3620 }
3621
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003622 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3623 if (err) {
3624 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3625 goto err_dpipe_init;
3626 }
3627
Jiri Pirko202d6f42017-04-18 16:55:33 +02003628 err = mlxsw_sp_dummy_fid_init(mlxsw_sp);
3629 if (err) {
3630 dev_err(mlxsw_sp->bus_info->dev, "Failed to init dummy FID\n");
3631 goto err_dummy_fid_init;
3632 }
3633
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003634 err = mlxsw_sp_ports_create(mlxsw_sp);
3635 if (err) {
3636 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3637 goto err_ports_create;
3638 }
3639
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003640 return 0;
3641
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003642err_ports_create:
Jiri Pirko202d6f42017-04-18 16:55:33 +02003643 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
3644err_dummy_fid_init:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003645 mlxsw_sp_dpipe_fini(mlxsw_sp);
3646err_dpipe_init:
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003647 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3648err_counter_pool_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003649 mlxsw_sp_acl_fini(mlxsw_sp);
3650err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003651 mlxsw_sp_span_fini(mlxsw_sp);
3652err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003653 mlxsw_sp_router_fini(mlxsw_sp);
3654err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003655 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003656err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003657 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003658err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003659 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003660err_buffers_init:
3661err_flood_init:
3662 mlxsw_sp_traps_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003663 return err;
3664}
3665
Jiri Pirkob2f10572016-04-08 19:11:23 +02003666static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003667{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003668 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003669
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003670 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko202d6f42017-04-18 16:55:33 +02003671 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003672 mlxsw_sp_dpipe_fini(mlxsw_sp);
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003673 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003674 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003675 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003676 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003677 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003678 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003679 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003680 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003681 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
Ido Schimmel14d39462016-06-20 23:04:15 +02003682 WARN_ON(!list_empty(&mlxsw_sp->fids));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003683}
3684
3685static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3686 .used_max_vepa_channels = 1,
3687 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003688 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003689 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003690 .used_max_pgt = 1,
3691 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003692 .used_flood_tables = 1,
3693 .used_flood_mode = 1,
3694 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003695 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003696 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003697 .max_fid_flood_tables = 3,
Ido Schimmel19ae6122015-12-15 16:03:39 +01003698 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003699 .used_max_ib_mc = 1,
3700 .max_ib_mc = 0,
3701 .used_max_pkey = 1,
3702 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003703 .used_kvd_split_data = 1,
3704 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3705 .kvd_hash_single_parts = 2,
3706 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003707 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003708 .swid_config = {
3709 {
3710 .used_type = 1,
3711 .type = MLXSW_PORT_SWID_TYPE_ETH,
3712 }
3713 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003714 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003715};
3716
3717static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003718 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003719 .priv_size = sizeof(struct mlxsw_sp),
3720 .init = mlxsw_sp_init,
3721 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003722 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003723 .port_split = mlxsw_sp_port_split,
3724 .port_unsplit = mlxsw_sp_port_unsplit,
3725 .sb_pool_get = mlxsw_sp_sb_pool_get,
3726 .sb_pool_set = mlxsw_sp_sb_pool_set,
3727 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3728 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3729 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3730 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3731 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3732 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3733 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3734 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3735 .txhdr_construct = mlxsw_sp_txhdr_construct,
3736 .txhdr_len = MLXSW_TXHDR_LEN,
3737 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003738};
3739
Jiri Pirko22a67762017-02-03 10:29:07 +01003740bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003741{
3742 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3743}
3744
Jiri Pirko1182e532017-03-06 21:25:20 +01003745static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003746{
Jiri Pirko1182e532017-03-06 21:25:20 +01003747 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003748 int ret = 0;
3749
3750 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003751 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003752 ret = 1;
3753 }
3754
3755 return ret;
3756}
3757
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003758static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3759{
Jiri Pirko1182e532017-03-06 21:25:20 +01003760 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003761
3762 if (mlxsw_sp_port_dev_check(dev))
3763 return netdev_priv(dev);
3764
Jiri Pirko1182e532017-03-06 21:25:20 +01003765 mlxsw_sp_port = NULL;
3766 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003767
Jiri Pirko1182e532017-03-06 21:25:20 +01003768 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003769}
3770
Ido Schimmel4724ba562017-03-10 08:53:39 +01003771struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003772{
3773 struct mlxsw_sp_port *mlxsw_sp_port;
3774
3775 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3776 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3777}
3778
3779static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3780{
Jiri Pirko1182e532017-03-06 21:25:20 +01003781 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003782
3783 if (mlxsw_sp_port_dev_check(dev))
3784 return netdev_priv(dev);
3785
Jiri Pirko1182e532017-03-06 21:25:20 +01003786 mlxsw_sp_port = NULL;
3787 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3788 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003789
Jiri Pirko1182e532017-03-06 21:25:20 +01003790 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003791}
3792
3793struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3794{
3795 struct mlxsw_sp_port *mlxsw_sp_port;
3796
3797 rcu_read_lock();
3798 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3799 if (mlxsw_sp_port)
3800 dev_hold(mlxsw_sp_port->dev);
3801 rcu_read_unlock();
3802 return mlxsw_sp_port;
3803}
3804
3805void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3806{
3807 dev_put(mlxsw_sp_port->dev);
3808}
3809
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003810static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3811 u16 fid)
3812{
3813 if (mlxsw_sp_fid_is_vfid(fid))
3814 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3815 else
3816 return test_bit(fid, lag_port->active_vlans);
3817}
3818
3819static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3820 u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003821{
3822 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003823 u8 local_port = mlxsw_sp_port->local_port;
3824 u16 lag_id = mlxsw_sp_port->lag_id;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003825 u64 max_lag_members;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003826 int i, count = 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003827
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003828 if (!mlxsw_sp_port->lagged)
3829 return true;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003830
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003831 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3832 MAX_LAG_MEMBERS);
3833 for (i = 0; i < max_lag_members; i++) {
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003834 struct mlxsw_sp_port *lag_port;
3835
3836 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3837 if (!lag_port || lag_port->local_port == local_port)
3838 continue;
3839 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3840 count++;
3841 }
3842
3843 return !count;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003844}
3845
3846static int
3847mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3848 u16 fid)
3849{
3850 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3851 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3852
3853 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3854 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3855 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3856 mlxsw_sp_port->local_port);
3857
Ido Schimmel22305372016-06-20 23:04:21 +02003858 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3859 mlxsw_sp_port->local_port, fid);
3860
Ido Schimmel039c49a2016-01-27 15:20:18 +01003861 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3862}
3863
3864static int
Ido Schimmel039c49a2016-01-27 15:20:18 +01003865mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3866 u16 fid)
3867{
3868 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3869 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3870
3871 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3872 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3873 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3874
Ido Schimmel22305372016-06-20 23:04:21 +02003875 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3876 mlxsw_sp_port->lag_id, fid);
3877
Ido Schimmel039c49a2016-01-27 15:20:18 +01003878 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3879}
3880
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003881int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003882{
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003883 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3884 return 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003885
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003886 if (mlxsw_sp_port->lagged)
3887 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003888 fid);
3889 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003890 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
Ido Schimmel039c49a2016-01-27 15:20:18 +01003891}
3892
Ido Schimmel701b1862016-07-04 08:23:16 +02003893static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3894{
3895 struct mlxsw_sp_fid *f, *tmp;
3896
3897 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3898 if (--f->ref_count == 0)
3899 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3900 else
3901 WARN_ON_ONCE(1);
3902}
3903
Ido Schimmel7117a572016-06-20 23:04:06 +02003904static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3905 struct net_device *br_dev)
3906{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02003907 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3908
3909 return !master_bridge->dev || master_bridge->dev == br_dev;
Ido Schimmel7117a572016-06-20 23:04:06 +02003910}
3911
3912static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3913 struct net_device *br_dev)
3914{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02003915 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3916
3917 master_bridge->dev = br_dev;
3918 master_bridge->ref_count++;
Ido Schimmel7117a572016-06-20 23:04:06 +02003919}
3920
3921static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3922{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02003923 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3924
3925 if (--master_bridge->ref_count == 0) {
3926 master_bridge->dev = NULL;
Ido Schimmel701b1862016-07-04 08:23:16 +02003927 /* It's possible upper VLAN devices are still holding
3928 * references to underlying FIDs. Drop the reference
3929 * and release the resources if it was the last one.
3930 * If it wasn't, then something bad happened.
3931 */
3932 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3933 }
Ido Schimmel7117a572016-06-20 23:04:06 +02003934}
3935
3936static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3937 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003938{
3939 struct net_device *dev = mlxsw_sp_port->dev;
3940 int err;
3941
3942 /* When port is not bridged untagged packets are tagged with
3943 * PVID=VID=1, thereby creating an implicit VLAN interface in
3944 * the device. Remove it and let bridge code take care of its
3945 * own VLANs.
3946 */
3947 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003948 if (err)
3949 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003950
Ido Schimmel7117a572016-06-20 23:04:06 +02003951 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3952
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003953 mlxsw_sp_port->learning = 1;
3954 mlxsw_sp_port->learning_sync = 1;
3955 mlxsw_sp_port->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003956 mlxsw_sp_port->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01003957 mlxsw_sp_port->mc_router = 0;
3958 mlxsw_sp_port->mc_disabled = 1;
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003959 mlxsw_sp_port->bridged = 1;
3960
3961 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003962}
3963
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003964static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003965{
3966 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01003967
Ido Schimmel28a01d22016-02-18 11:30:02 +01003968 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3969
Ido Schimmel7117a572016-06-20 23:04:06 +02003970 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3971
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003972 mlxsw_sp_port->learning = 0;
3973 mlxsw_sp_port->learning_sync = 0;
3974 mlxsw_sp_port->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003975 mlxsw_sp_port->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01003976 mlxsw_sp_port->mc_router = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01003977 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003978
3979 /* Add implicit VLAN interface in the device, so that untagged
3980 * packets will be classified to the default vFID.
3981 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02003982 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003983}
3984
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003985static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003986{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003987 char sldr_pl[MLXSW_REG_SLDR_LEN];
3988
3989 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3990 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3991}
3992
3993static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3994{
3995 char sldr_pl[MLXSW_REG_SLDR_LEN];
3996
3997 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3998 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3999}
4000
4001static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4002 u16 lag_id, u8 port_index)
4003{
4004 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4005 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4006
4007 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4008 lag_id, port_index);
4009 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4010}
4011
4012static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4013 u16 lag_id)
4014{
4015 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4016 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4017
4018 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4019 lag_id);
4020 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4021}
4022
4023static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4024 u16 lag_id)
4025{
4026 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4027 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4028
4029 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4030 lag_id);
4031 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4032}
4033
4034static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4035 u16 lag_id)
4036{
4037 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4038 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4039
4040 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4041 lag_id);
4042 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4043}
4044
4045static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4046 struct net_device *lag_dev,
4047 u16 *p_lag_id)
4048{
4049 struct mlxsw_sp_upper *lag;
4050 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004051 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004052 int i;
4053
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004054 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4055 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004056 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4057 if (lag->ref_count) {
4058 if (lag->dev == lag_dev) {
4059 *p_lag_id = i;
4060 return 0;
4061 }
4062 } else if (free_lag_id < 0) {
4063 free_lag_id = i;
4064 }
4065 }
4066 if (free_lag_id < 0)
4067 return -EBUSY;
4068 *p_lag_id = free_lag_id;
4069 return 0;
4070}
4071
4072static bool
4073mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4074 struct net_device *lag_dev,
4075 struct netdev_lag_upper_info *lag_upper_info)
4076{
4077 u16 lag_id;
4078
4079 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
4080 return false;
4081 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
4082 return false;
4083 return true;
4084}
4085
4086static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4087 u16 lag_id, u8 *p_port_index)
4088{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004089 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004090 int i;
4091
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004092 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4093 MAX_LAG_MEMBERS);
4094 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004095 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4096 *p_port_index = i;
4097 return 0;
4098 }
4099 }
4100 return -EBUSY;
4101}
4102
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004103static void
4104mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel186962e2017-03-10 08:53:36 +01004105 struct net_device *lag_dev, u16 lag_id)
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004106{
4107 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02004108 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004109
4110 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4111 if (WARN_ON(!mlxsw_sp_vport))
4112 return;
4113
Ido Schimmel11943ff2016-07-02 11:00:12 +02004114 /* If vPort is assigned a RIF, then leave it since it's no
4115 * longer valid.
4116 */
4117 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4118 if (f)
4119 f->leave(mlxsw_sp_vport);
4120
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004121 mlxsw_sp_vport->lag_id = lag_id;
4122 mlxsw_sp_vport->lagged = 1;
Ido Schimmel186962e2017-03-10 08:53:36 +01004123 mlxsw_sp_vport->dev = lag_dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004124}
4125
4126static void
4127mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4128{
4129 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02004130 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004131
4132 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4133 if (WARN_ON(!mlxsw_sp_vport))
4134 return;
4135
Ido Schimmel11943ff2016-07-02 11:00:12 +02004136 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4137 if (f)
4138 f->leave(mlxsw_sp_vport);
4139
Ido Schimmel186962e2017-03-10 08:53:36 +01004140 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004141 mlxsw_sp_vport->lagged = 0;
4142}
4143
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004144static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4145 struct net_device *lag_dev)
4146{
4147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4148 struct mlxsw_sp_upper *lag;
4149 u16 lag_id;
4150 u8 port_index;
4151 int err;
4152
4153 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4154 if (err)
4155 return err;
4156 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4157 if (!lag->ref_count) {
4158 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4159 if (err)
4160 return err;
4161 lag->dev = lag_dev;
4162 }
4163
4164 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4165 if (err)
4166 return err;
4167 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4168 if (err)
4169 goto err_col_port_add;
4170 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4171 if (err)
4172 goto err_col_port_enable;
4173
4174 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4175 mlxsw_sp_port->local_port);
4176 mlxsw_sp_port->lag_id = lag_id;
4177 mlxsw_sp_port->lagged = 1;
4178 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004179
Ido Schimmel186962e2017-03-10 08:53:36 +01004180 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_dev, lag_id);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004181
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004182 return 0;
4183
Ido Schimmel51554db2016-05-06 22:18:39 +02004184err_col_port_enable:
4185 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004186err_col_port_add:
4187 if (!lag->ref_count)
4188 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004189 return err;
4190}
4191
Ido Schimmel82e6db02016-06-20 23:04:04 +02004192static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4193 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004194{
4195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004196 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004197 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004198
4199 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004200 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004201 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4202 WARN_ON(lag->ref_count == 0);
4203
Ido Schimmel82e6db02016-06-20 23:04:04 +02004204 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4205 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004206
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004207 if (mlxsw_sp_port->bridged) {
4208 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004209 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004210 }
4211
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004212 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004213 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004214
4215 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4216 mlxsw_sp_port->local_port);
4217 mlxsw_sp_port->lagged = 0;
4218 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004219
4220 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004221}
4222
Jiri Pirko74581202015-12-03 12:12:30 +01004223static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4224 u16 lag_id)
4225{
4226 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4227 char sldr_pl[MLXSW_REG_SLDR_LEN];
4228
4229 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4230 mlxsw_sp_port->local_port);
4231 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4232}
4233
4234static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4235 u16 lag_id)
4236{
4237 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4238 char sldr_pl[MLXSW_REG_SLDR_LEN];
4239
4240 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4241 mlxsw_sp_port->local_port);
4242 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4243}
4244
4245static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4246 bool lag_tx_enabled)
4247{
4248 if (lag_tx_enabled)
4249 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4250 mlxsw_sp_port->lag_id);
4251 else
4252 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4253 mlxsw_sp_port->lag_id);
4254}
4255
4256static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4257 struct netdev_lag_lower_state_info *info)
4258{
4259 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4260}
4261
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004262static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4263 struct net_device *vlan_dev)
4264{
4265 struct mlxsw_sp_port *mlxsw_sp_vport;
4266 u16 vid = vlan_dev_vlan_id(vlan_dev);
4267
4268 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02004269 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004270 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004271
4272 mlxsw_sp_vport->dev = vlan_dev;
4273
4274 return 0;
4275}
4276
Ido Schimmel82e6db02016-06-20 23:04:04 +02004277static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4278 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004279{
4280 struct mlxsw_sp_port *mlxsw_sp_vport;
4281 u16 vid = vlan_dev_vlan_id(vlan_dev);
4282
4283 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02004284 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02004285 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004286
4287 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004288}
4289
Jiri Pirko2b94e582017-04-18 16:55:37 +02004290static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4291 bool enable)
4292{
4293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4294 enum mlxsw_reg_spms_state spms_state;
4295 char *spms_pl;
4296 u16 vid;
4297 int err;
4298
4299 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4300 MLXSW_REG_SPMS_STATE_DISCARDING;
4301
4302 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4303 if (!spms_pl)
4304 return -ENOMEM;
4305 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4306
4307 for (vid = 0; vid < VLAN_N_VID; vid++)
4308 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4309
4310 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4311 kfree(spms_pl);
4312 return err;
4313}
4314
4315static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4316{
4317 int err;
4318
4319 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4320 if (err)
4321 return err;
4322 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4323 true, false);
4324 if (err)
4325 goto err_port_vlan_set;
4326 return 0;
4327
4328err_port_vlan_set:
4329 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4330 return err;
4331}
4332
4333static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4334{
4335 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4336 false, false);
4337 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4338}
4339
Jiri Pirko74581202015-12-03 12:12:30 +01004340static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4341 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004342{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004343 struct netdev_notifier_changeupper_info *info;
4344 struct mlxsw_sp_port *mlxsw_sp_port;
4345 struct net_device *upper_dev;
4346 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004347 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004348
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004349 mlxsw_sp_port = netdev_priv(dev);
4350 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4351 info = ptr;
4352
4353 switch (event) {
4354 case NETDEV_PRECHANGEUPPER:
4355 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004356 if (!is_vlan_dev(upper_dev) &&
4357 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004358 !netif_is_bridge_master(upper_dev) &&
Jiri Pirko2b94e582017-04-18 16:55:37 +02004359 !netif_is_ovs_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004360 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004361 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004362 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004363 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004364 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004365 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004366 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004367 if (netif_is_lag_master(upper_dev) &&
4368 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4369 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004370 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004371 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4372 return -EINVAL;
4373 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4374 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4375 return -EINVAL;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004376 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4377 return -EINVAL;
4378 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4379 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004380 break;
4381 case NETDEV_CHANGEUPPER:
4382 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004383 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004384 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004385 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4386 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004387 else
Jiri Pirkob51df792017-04-18 16:55:31 +02004388 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4389 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004390 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004391 if (info->linking)
4392 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4393 upper_dev);
4394 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004395 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004396 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004397 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004398 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4399 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004400 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004401 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4402 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004403 } else if (netif_is_ovs_master(upper_dev)) {
4404 if (info->linking)
4405 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4406 else
4407 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004408 } else {
4409 err = -EINVAL;
4410 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004411 }
4412 break;
4413 }
4414
Ido Schimmel80bedf12016-06-20 23:03:59 +02004415 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004416}
4417
Jiri Pirko74581202015-12-03 12:12:30 +01004418static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4419 unsigned long event, void *ptr)
4420{
4421 struct netdev_notifier_changelowerstate_info *info;
4422 struct mlxsw_sp_port *mlxsw_sp_port;
4423 int err;
4424
4425 mlxsw_sp_port = netdev_priv(dev);
4426 info = ptr;
4427
4428 switch (event) {
4429 case NETDEV_CHANGELOWERSTATE:
4430 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4431 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4432 info->lower_state_info);
4433 if (err)
4434 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4435 }
4436 break;
4437 }
4438
Ido Schimmel80bedf12016-06-20 23:03:59 +02004439 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004440}
4441
4442static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4443 unsigned long event, void *ptr)
4444{
4445 switch (event) {
4446 case NETDEV_PRECHANGEUPPER:
4447 case NETDEV_CHANGEUPPER:
4448 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4449 case NETDEV_CHANGELOWERSTATE:
4450 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4451 }
4452
Ido Schimmel80bedf12016-06-20 23:03:59 +02004453 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004454}
4455
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004456static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4457 unsigned long event, void *ptr)
4458{
4459 struct net_device *dev;
4460 struct list_head *iter;
4461 int ret;
4462
4463 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4464 if (mlxsw_sp_port_dev_check(dev)) {
4465 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004466 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004467 return ret;
4468 }
4469 }
4470
Ido Schimmel80bedf12016-06-20 23:03:59 +02004471 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004472}
4473
Ido Schimmel701b1862016-07-04 08:23:16 +02004474static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4475 struct net_device *vlan_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004476{
Ido Schimmel701b1862016-07-04 08:23:16 +02004477 u16 fid = vlan_dev_vlan_id(vlan_dev);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004478 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004479
Ido Schimmel701b1862016-07-04 08:23:16 +02004480 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4481 if (!f) {
4482 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4483 if (IS_ERR(f))
4484 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004485 }
4486
Ido Schimmel701b1862016-07-04 08:23:16 +02004487 f->ref_count++;
4488
4489 return 0;
4490}
4491
4492static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4493 struct net_device *vlan_dev)
4494{
4495 u16 fid = vlan_dev_vlan_id(vlan_dev);
4496 struct mlxsw_sp_fid *f;
4497
4498 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004499 if (f && f->rif)
4500 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel701b1862016-07-04 08:23:16 +02004501 if (f && --f->ref_count == 0)
4502 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4503}
4504
4505static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4506 unsigned long event, void *ptr)
4507{
4508 struct netdev_notifier_changeupper_info *info;
4509 struct net_device *upper_dev;
4510 struct mlxsw_sp *mlxsw_sp;
Ido Schimmelb4149702017-03-10 08:53:34 +01004511 int err = 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004512
4513 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4514 if (!mlxsw_sp)
4515 return 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004516
4517 info = ptr;
4518
4519 switch (event) {
Ido Schimmelb4149702017-03-10 08:53:34 +01004520 case NETDEV_PRECHANGEUPPER:
Ido Schimmel701b1862016-07-04 08:23:16 +02004521 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004522 if (!is_vlan_dev(upper_dev))
Ido Schimmelb4149702017-03-10 08:53:34 +01004523 return -EINVAL;
4524 if (is_vlan_dev(upper_dev) &&
Ido Schimmel5f6935c2017-05-16 19:38:26 +02004525 br_dev != mlxsw_sp_master_bridge(mlxsw_sp)->dev)
Ido Schimmelb4149702017-03-10 08:53:34 +01004526 return -EINVAL;
4527 break;
4528 case NETDEV_CHANGEUPPER:
4529 upper_dev = info->upper_dev;
4530 if (is_vlan_dev(upper_dev)) {
4531 if (info->linking)
4532 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4533 upper_dev);
4534 else
4535 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp,
4536 upper_dev);
Ido Schimmel701b1862016-07-04 08:23:16 +02004537 } else {
Ido Schimmelb4149702017-03-10 08:53:34 +01004538 err = -EINVAL;
4539 WARN_ON(1);
Ido Schimmel701b1862016-07-04 08:23:16 +02004540 }
4541 break;
4542 }
4543
Ido Schimmelb4149702017-03-10 08:53:34 +01004544 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004545}
4546
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004547static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004548{
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004549 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
Ido Schimmel99724c12016-07-04 08:23:14 +02004550 MLXSW_SP_VFID_MAX);
4551}
4552
4553static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
4554{
4555 char sfmr_pl[MLXSW_REG_SFMR_LEN];
4556
4557 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4558 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004559}
4560
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004561static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel1c800752016-06-20 23:04:20 +02004562
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004563static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4564 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004565{
4566 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004567 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004568 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004569 int err;
4570
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004571 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004572 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004573 dev_err(dev, "No available vFIDs\n");
4574 return ERR_PTR(-ERANGE);
4575 }
4576
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004577 fid = mlxsw_sp_vfid_to_fid(vfid);
4578 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004579 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004580 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004581 return ERR_PTR(err);
4582 }
4583
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004584 f = kzalloc(sizeof(*f), GFP_KERNEL);
4585 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004586 goto err_allocate_vfid;
4587
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004588 f->leave = mlxsw_sp_vport_vfid_leave;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004589 f->fid = fid;
4590 f->dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004591
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004592 list_add(&f->list, &mlxsw_sp->vfids.list);
4593 set_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004594
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004595 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004596
4597err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004598 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004599 return ERR_PTR(-ENOMEM);
4600}
4601
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004602static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4603 struct mlxsw_sp_fid *f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004604{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004605 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004606 u16 fid = f->fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004607
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004608 clear_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004609 list_del(&f->list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004610
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004611 if (f->rif)
4612 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004613
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004614 kfree(f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004615
4616 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004617}
4618
Ido Schimmel99724c12016-07-04 08:23:14 +02004619static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4620 bool valid)
4621{
4622 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4623 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4624
4625 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4626 vid);
4627}
4628
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004629static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4630 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004631{
Ido Schimmel0355b592016-06-20 23:04:13 +02004632 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004633 int err;
4634
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004635 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004636 if (!f) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004637 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004638 if (IS_ERR(f))
4639 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004640 }
4641
Ido Schimmel0355b592016-06-20 23:04:13 +02004642 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4643 if (err)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004644 goto err_vport_flood_set;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004645
Ido Schimmel0355b592016-06-20 23:04:13 +02004646 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4647 if (err)
4648 goto err_vport_fid_map;
Ido Schimmel6a9863a2016-02-15 13:19:54 +01004649
Ido Schimmel41b996c2016-06-20 23:04:17 +02004650 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004651 f->ref_count++;
Ido Schimmel039c49a2016-01-27 15:20:18 +01004652
Ido Schimmel22305372016-06-20 23:04:21 +02004653 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4654
Ido Schimmel0355b592016-06-20 23:04:13 +02004655 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004656
Ido Schimmel9c4d4422016-06-20 23:04:10 +02004657err_vport_fid_map:
Ido Schimmel0355b592016-06-20 23:04:13 +02004658 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4659err_vport_flood_set:
4660 if (!f->ref_count)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004661 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004662 return err;
4663}
4664
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004665static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004666{
Ido Schimmel41b996c2016-06-20 23:04:17 +02004667 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004668
Ido Schimmel22305372016-06-20 23:04:21 +02004669 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4670
Ido Schimmel0355b592016-06-20 23:04:13 +02004671 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
4672
4673 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4674
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004675 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4676
Ido Schimmel41b996c2016-06-20 23:04:17 +02004677 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
Ido Schimmel0355b592016-06-20 23:04:13 +02004678 if (--f->ref_count == 0)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004679 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004680}
4681
4682static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4683 struct net_device *br_dev)
4684{
Ido Schimmel99724c12016-07-04 08:23:14 +02004685 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004686 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4687 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004688 int err;
4689
Ido Schimmel99724c12016-07-04 08:23:14 +02004690 if (f && !WARN_ON(!f->leave))
4691 f->leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004692
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004693 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004694 if (err) {
Ido Schimmel0355b592016-06-20 23:04:13 +02004695 netdev_err(dev, "Failed to join vFID\n");
Ido Schimmel99724c12016-07-04 08:23:14 +02004696 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004697 }
4698
4699 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4700 if (err) {
4701 netdev_err(dev, "Failed to enable learning\n");
4702 goto err_port_vid_learning_set;
4703 }
4704
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004705 mlxsw_sp_vport->learning = 1;
4706 mlxsw_sp_vport->learning_sync = 1;
4707 mlxsw_sp_vport->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004708 mlxsw_sp_vport->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004709 mlxsw_sp_vport->mc_router = 0;
4710 mlxsw_sp_vport->mc_disabled = 1;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004711 mlxsw_sp_vport->bridged = 1;
4712
4713 return 0;
4714
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004715err_port_vid_learning_set:
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004716 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004717 return err;
4718}
4719
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004720static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004721{
4722 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004723
4724 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4725
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004726 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004727
Ido Schimmel0355b592016-06-20 23:04:13 +02004728 mlxsw_sp_vport->learning = 0;
4729 mlxsw_sp_vport->learning_sync = 0;
4730 mlxsw_sp_vport->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004731 mlxsw_sp_vport->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004732 mlxsw_sp_vport->mc_router = 0;
Ido Schimmel0355b592016-06-20 23:04:13 +02004733 mlxsw_sp_vport->bridged = 0;
4734}
4735
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004736static bool
4737mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4738 const struct net_device *br_dev)
4739{
4740 struct mlxsw_sp_port *mlxsw_sp_vport;
4741
4742 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4743 vport.list) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004744 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
Ido Schimmel56918b62016-06-20 23:04:18 +02004745
4746 if (dev && dev == br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004747 return false;
4748 }
4749
4750 return true;
4751}
4752
4753static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4754 unsigned long event, void *ptr,
4755 u16 vid)
4756{
4757 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4758 struct netdev_notifier_changeupper_info *info = ptr;
4759 struct mlxsw_sp_port *mlxsw_sp_vport;
4760 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004761 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004762
4763 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel1f880612017-03-10 08:53:35 +01004764 if (!mlxsw_sp_vport)
4765 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004766
4767 switch (event) {
4768 case NETDEV_PRECHANGEUPPER:
4769 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004770 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004771 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02004772 if (!info->linking)
4773 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004774 /* We can't have multiple VLAN interfaces configured on
4775 * the same port and being members in the same bridge.
4776 */
Ido Schimmel7179eb52017-03-16 09:08:18 +01004777 if (netif_is_bridge_master(upper_dev) &&
4778 !mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004779 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004780 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004781 break;
4782 case NETDEV_CHANGEUPPER:
4783 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004784 if (netif_is_bridge_master(upper_dev)) {
4785 if (info->linking)
4786 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4787 upper_dev);
4788 else
4789 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004790 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004791 err = -EINVAL;
4792 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004793 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004794 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004795 }
4796
Ido Schimmel80bedf12016-06-20 23:03:59 +02004797 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004798}
4799
Ido Schimmel272c4472015-12-15 16:03:47 +01004800static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4801 unsigned long event, void *ptr,
4802 u16 vid)
4803{
4804 struct net_device *dev;
4805 struct list_head *iter;
4806 int ret;
4807
4808 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4809 if (mlxsw_sp_port_dev_check(dev)) {
4810 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4811 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004812 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004813 return ret;
4814 }
4815 }
4816
Ido Schimmel80bedf12016-06-20 23:03:59 +02004817 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004818}
4819
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004820static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4821 unsigned long event, void *ptr)
4822{
4823 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4824 u16 vid = vlan_dev_vlan_id(vlan_dev);
4825
Ido Schimmel272c4472015-12-15 16:03:47 +01004826 if (mlxsw_sp_port_dev_check(real_dev))
4827 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4828 vid);
4829 else if (netif_is_lag_master(real_dev))
4830 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4831 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004832
Ido Schimmel80bedf12016-06-20 23:03:59 +02004833 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004834}
4835
Ido Schimmelb1e45522017-04-30 19:47:14 +03004836static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4837{
4838 struct netdev_notifier_changeupper_info *info = ptr;
4839
4840 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4841 return false;
4842 return netif_is_l3_master(info->upper_dev);
4843}
4844
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004845static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4846 unsigned long event, void *ptr)
4847{
4848 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004849 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004850
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004851 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4852 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004853 else if (mlxsw_sp_is_vrf_event(event, ptr))
4854 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004855 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004856 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4857 else if (netif_is_lag_master(dev))
4858 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
Ido Schimmel701b1862016-07-04 08:23:16 +02004859 else if (netif_is_bridge_master(dev))
4860 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004861 else if (is_vlan_dev(dev))
4862 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004863
Ido Schimmel80bedf12016-06-20 23:03:59 +02004864 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004865}
4866
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004867static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4868 .notifier_call = mlxsw_sp_netdevice_event,
4869};
4870
Ido Schimmel99724c12016-07-04 08:23:14 +02004871static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4872 .notifier_call = mlxsw_sp_inetaddr_event,
4873 .priority = 10, /* Must be called before FIB notifier block */
4874};
4875
Jiri Pirkoe7322632016-09-01 10:37:43 +02004876static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4877 .notifier_call = mlxsw_sp_router_netevent_event,
4878};
4879
Jiri Pirko1d20d232016-10-27 15:12:59 +02004880static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4881 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4882 {0, },
4883};
4884
4885static struct pci_driver mlxsw_sp_pci_driver = {
4886 .name = mlxsw_sp_driver_name,
4887 .id_table = mlxsw_sp_pci_id_table,
4888};
4889
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004890static int __init mlxsw_sp_module_init(void)
4891{
4892 int err;
4893
4894 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004895 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004896 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4897
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004898 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4899 if (err)
4900 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004901
4902 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4903 if (err)
4904 goto err_pci_driver_register;
4905
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004906 return 0;
4907
Jiri Pirko1d20d232016-10-27 15:12:59 +02004908err_pci_driver_register:
4909 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004910err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02004911 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004912 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004913 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4914 return err;
4915}
4916
4917static void __exit mlxsw_sp_module_exit(void)
4918{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004919 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004920 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004921 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004922 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004923 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4924}
4925
4926module_init(mlxsw_sp_module_init);
4927module_exit(mlxsw_sp_module_exit);
4928
4929MODULE_LICENSE("Dual BSD/GPL");
4930MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4931MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004932MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);