Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 1 | /* |
| 2 | * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC |
| 3 | * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, |
| 4 | * AT91SAM9X25, AT91SAM9X35 SoC |
| 5 | * |
| 6 | * Copyright (C) 2012 Atmel, |
| 7 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> |
| 8 | * |
| 9 | * Licensed under GPLv2 or later. |
| 10 | */ |
| 11 | |
Jean-Christophe PLAGNIOL-VILLARD | 6db64d2 | 2013-05-15 01:21:50 +0800 | [diff] [blame] | 12 | #include "skeleton.dtsi" |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 13 | #include <dt-bindings/dma/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 14 | #include <dt-bindings/pinctrl/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 16 | #include <dt-bindings/gpio/gpio.h> |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 17 | |
| 18 | / { |
| 19 | model = "Atmel AT91SAM9x5 family SoC"; |
| 20 | compatible = "atmel,at91sam9x5"; |
| 21 | interrupt-parent = <&aic>; |
| 22 | |
| 23 | aliases { |
| 24 | serial0 = &dbgu; |
| 25 | serial1 = &usart0; |
| 26 | serial2 = &usart1; |
| 27 | serial3 = &usart2; |
| 28 | gpio0 = &pioA; |
| 29 | gpio1 = &pioB; |
| 30 | gpio2 = &pioC; |
| 31 | gpio3 = &pioD; |
| 32 | tcb0 = &tcb0; |
| 33 | tcb1 = &tcb1; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 34 | i2c0 = &i2c0; |
| 35 | i2c1 = &i2c1; |
| 36 | i2c2 = &i2c2; |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 37 | ssc0 = &ssc0; |
Bo Shen | f3ab052 | 2013-12-19 11:59:17 +0800 | [diff] [blame] | 38 | pwm0 = &pwm0; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 39 | }; |
| 40 | cpus { |
Lorenzo Pieralisi | e757a6e | 2013-04-18 18:31:35 +0100 | [diff] [blame] | 41 | #address-cells = <0>; |
| 42 | #size-cells = <0>; |
| 43 | |
| 44 | cpu { |
| 45 | compatible = "arm,arm926ej-s"; |
| 46 | device_type = "cpu"; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 47 | }; |
| 48 | }; |
| 49 | |
Ludovic Desroches | dcce6ce | 2012-04-02 20:44:20 +0200 | [diff] [blame] | 50 | memory { |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 51 | reg = <0x20000000 0x10000000>; |
| 52 | }; |
| 53 | |
| 54 | ahb { |
| 55 | compatible = "simple-bus"; |
| 56 | #address-cells = <1>; |
| 57 | #size-cells = <1>; |
| 58 | ranges; |
| 59 | |
| 60 | apb { |
| 61 | compatible = "simple-bus"; |
| 62 | #address-cells = <1>; |
| 63 | #size-cells = <1>; |
| 64 | ranges; |
| 65 | |
| 66 | aic: interrupt-controller@fffff000 { |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 67 | #interrupt-cells = <3>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 68 | compatible = "atmel,at91rm9200-aic"; |
| 69 | interrupt-controller; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 70 | reg = <0xfffff000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | c657394 | 2012-04-09 19:36:36 +0800 | [diff] [blame] | 71 | atmel,external-irqs = <31>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 72 | }; |
| 73 | |
Jean-Christophe PLAGNIOL-VILLARD | a7776ec | 2012-03-02 20:54:37 +0800 | [diff] [blame] | 74 | ramc0: ramc@ffffe800 { |
| 75 | compatible = "atmel,at91sam9g45-ddramc"; |
| 76 | reg = <0xffffe800 0x200>; |
| 77 | }; |
| 78 | |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 79 | pmc: pmc@fffffc00 { |
| 80 | compatible = "atmel,at91rm9200-pmc"; |
| 81 | reg = <0xfffffc00 0x100>; |
| 82 | }; |
| 83 | |
Jean-Christophe PLAGNIOL-VILLARD | c8082d3 | 2012-03-03 03:16:27 +0800 | [diff] [blame] | 84 | rstc@fffffe00 { |
| 85 | compatible = "atmel,at91sam9g45-rstc"; |
| 86 | reg = <0xfffffe00 0x10>; |
| 87 | }; |
| 88 | |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 89 | shdwc@fffffe10 { |
| 90 | compatible = "atmel,at91sam9x5-shdwc"; |
| 91 | reg = <0xfffffe10 0x10>; |
| 92 | }; |
| 93 | |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 94 | pit: timer@fffffe30 { |
| 95 | compatible = "atmel,at91sam9260-pit"; |
| 96 | reg = <0xfffffe30 0xf>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 97 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 98 | }; |
| 99 | |
| 100 | tcb0: timer@f8008000 { |
| 101 | compatible = "atmel,at91sam9x5-tcb"; |
| 102 | reg = <0xf8008000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 103 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | tcb1: timer@f800c000 { |
| 107 | compatible = "atmel,at91sam9x5-tcb"; |
| 108 | reg = <0xf800c000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 109 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 110 | }; |
| 111 | |
| 112 | dma0: dma-controller@ffffec00 { |
| 113 | compatible = "atmel,at91sam9g45-dma"; |
| 114 | reg = <0xffffec00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 115 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 980ce7d | 2013-04-16 15:03:06 +0200 | [diff] [blame] | 116 | #dma-cells = <2>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | dma1: dma-controller@ffffee00 { |
| 120 | compatible = "atmel,at91sam9g45-dma"; |
| 121 | reg = <0xffffee00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 122 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 980ce7d | 2013-04-16 15:03:06 +0200 | [diff] [blame] | 123 | #dma-cells = <2>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 124 | }; |
| 125 | |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 126 | pinctrl@fffff400 { |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 127 | #address-cells = <1>; |
| 128 | #size-cells = <1>; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 129 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 130 | ranges = <0xfffff400 0xfffff400 0x800>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 131 | |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 132 | /* shared pinctrl settings */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 133 | dbgu { |
| 134 | pinctrl_dbgu: dbgu-0 { |
| 135 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 136 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ |
| 137 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 138 | }; |
| 139 | }; |
| 140 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 141 | usart0 { |
| 142 | pinctrl_usart0: usart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 143 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 144 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */ |
| 145 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 146 | }; |
| 147 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 148 | pinctrl_usart0_rts: usart0_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 149 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 150 | <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 151 | }; |
| 152 | |
| 153 | pinctrl_usart0_cts: usart0_cts-0 { |
| 154 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 155 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 156 | }; |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 157 | |
| 158 | pinctrl_usart0_sck: usart0_sck-0 { |
| 159 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 160 | <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 161 | }; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 162 | }; |
| 163 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 164 | usart1 { |
| 165 | pinctrl_usart1: usart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 166 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 167 | <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */ |
| 168 | AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 169 | }; |
| 170 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 171 | pinctrl_usart1_rts: usart1_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 172 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 173 | <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 174 | }; |
| 175 | |
| 176 | pinctrl_usart1_cts: usart1_cts-0 { |
| 177 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 178 | <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 179 | }; |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 180 | |
| 181 | pinctrl_usart1_sck: usart1_sck-0 { |
| 182 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 183 | <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */ |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 184 | }; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 185 | }; |
| 186 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 187 | usart2 { |
| 188 | pinctrl_usart2: usart2-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 189 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 190 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 191 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 192 | }; |
| 193 | |
Jiri Prchal | df923c1 | 2013-09-19 14:28:39 +0200 | [diff] [blame] | 194 | pinctrl_usart2_rts: usart2_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 195 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 196 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 197 | }; |
| 198 | |
Jiri Prchal | df923c1 | 2013-09-19 14:28:39 +0200 | [diff] [blame] | 199 | pinctrl_usart2_cts: usart2_cts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 200 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 201 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 202 | }; |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 203 | |
| 204 | pinctrl_usart2_sck: usart2_sck-0 { |
| 205 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 206 | <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 207 | }; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 208 | }; |
| 209 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 210 | uart0 { |
| 211 | pinctrl_uart0: uart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 212 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 213 | <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */ |
| 214 | AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 215 | }; |
| 216 | }; |
| 217 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 218 | uart1 { |
| 219 | pinctrl_uart1: uart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 220 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 221 | <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */ |
| 222 | AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 223 | }; |
| 224 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 225 | |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 226 | nand { |
| 227 | pinctrl_nand: nand-0 { |
| 228 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 229 | <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */ |
| 230 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */ |
| 231 | AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */ |
| 232 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */ |
| 233 | AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */ |
| 234 | AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */ |
| 235 | AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */ |
| 236 | AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */ |
| 237 | AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */ |
| 238 | AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */ |
| 239 | AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */ |
| 240 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */ |
| 241 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */ |
| 242 | AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */ |
Richard Genoud | 7f06472 | 2013-03-11 15:12:40 +0100 | [diff] [blame] | 243 | }; |
| 244 | |
| 245 | pinctrl_nand_16bits: nand_16bits-0 { |
| 246 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 247 | <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */ |
| 248 | AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */ |
| 249 | AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */ |
| 250 | AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */ |
| 251 | AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */ |
| 252 | AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */ |
| 253 | AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */ |
| 254 | AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */ |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 255 | }; |
| 256 | }; |
| 257 | |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 258 | mmc0 { |
| 259 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 260 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 261 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 262 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
| 263 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 264 | }; |
| 265 | |
| 266 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 267 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 268 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| 269 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ |
| 270 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 271 | }; |
| 272 | }; |
| 273 | |
| 274 | mmc1 { |
| 275 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { |
| 276 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 277 | <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */ |
| 278 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ |
| 279 | AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 280 | }; |
| 281 | |
| 282 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { |
| 283 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 284 | <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */ |
| 285 | AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */ |
| 286 | AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 287 | }; |
| 288 | }; |
| 289 | |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 290 | ssc0 { |
| 291 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 292 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 293 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 294 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 295 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 296 | }; |
| 297 | |
| 298 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 299 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 300 | <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 301 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 302 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 303 | }; |
| 304 | }; |
| 305 | |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 306 | spi0 { |
| 307 | pinctrl_spi0: spi0-0 { |
| 308 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 309 | <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ |
| 310 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ |
| 311 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 312 | }; |
| 313 | }; |
| 314 | |
| 315 | spi1 { |
| 316 | pinctrl_spi1: spi1-0 { |
| 317 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 318 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ |
| 319 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ |
| 320 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 321 | }; |
| 322 | }; |
| 323 | |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 324 | i2c0 { |
| 325 | pinctrl_i2c0: i2c0-0 { |
| 326 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 327 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */ |
| 328 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */ |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 329 | }; |
| 330 | }; |
| 331 | |
| 332 | i2c1 { |
| 333 | pinctrl_i2c1: i2c1-0 { |
| 334 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 335 | <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */ |
| 336 | AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */ |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 337 | }; |
| 338 | }; |
| 339 | |
| 340 | i2c2 { |
| 341 | pinctrl_i2c2: i2c2-0 { |
| 342 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 343 | <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */ |
| 344 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */ |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 345 | }; |
| 346 | }; |
| 347 | |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 348 | i2c_gpio0 { |
| 349 | pinctrl_i2c_gpio0: i2c_gpio0-0 { |
| 350 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 351 | <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */ |
| 352 | AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */ |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 353 | }; |
| 354 | }; |
| 355 | |
| 356 | i2c_gpio1 { |
| 357 | pinctrl_i2c_gpio1: i2c_gpio1-0 { |
| 358 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 359 | <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */ |
| 360 | AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */ |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 361 | }; |
| 362 | }; |
| 363 | |
| 364 | i2c_gpio2 { |
| 365 | pinctrl_i2c_gpio2: i2c_gpio2-0 { |
| 366 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 367 | <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */ |
| 368 | AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */ |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 369 | }; |
| 370 | }; |
| 371 | |
Boris BREZILLON | 028633c | 2013-05-24 10:05:56 +0000 | [diff] [blame] | 372 | tcb0 { |
| 373 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { |
| 374 | atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 375 | }; |
| 376 | |
| 377 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { |
| 378 | atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 379 | }; |
| 380 | |
| 381 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { |
| 382 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 383 | }; |
| 384 | |
| 385 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { |
| 386 | atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 387 | }; |
| 388 | |
| 389 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { |
| 390 | atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 391 | }; |
| 392 | |
| 393 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { |
| 394 | atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 395 | }; |
| 396 | |
| 397 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { |
| 398 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 399 | }; |
| 400 | |
| 401 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { |
| 402 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 403 | }; |
| 404 | |
| 405 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { |
| 406 | atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 407 | }; |
| 408 | }; |
| 409 | |
| 410 | tcb1 { |
| 411 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { |
| 412 | atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 413 | }; |
| 414 | |
| 415 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { |
| 416 | atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 417 | }; |
| 418 | |
| 419 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { |
| 420 | atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 421 | }; |
| 422 | |
| 423 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { |
| 424 | atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 425 | }; |
| 426 | |
| 427 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { |
| 428 | atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 429 | }; |
| 430 | |
| 431 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { |
| 432 | atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 433 | }; |
| 434 | |
| 435 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { |
| 436 | atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 437 | }; |
| 438 | |
| 439 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { |
| 440 | atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 441 | }; |
| 442 | |
| 443 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { |
| 444 | atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 445 | }; |
| 446 | }; |
| 447 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 448 | pioA: gpio@fffff400 { |
| 449 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 450 | reg = <0xfffff400 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 451 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 452 | #gpio-cells = <2>; |
| 453 | gpio-controller; |
| 454 | interrupt-controller; |
| 455 | #interrupt-cells = <2>; |
| 456 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 457 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 458 | pioB: gpio@fffff600 { |
| 459 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 460 | reg = <0xfffff600 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 461 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 462 | #gpio-cells = <2>; |
| 463 | gpio-controller; |
Jean-Christophe PLAGNIOL-VILLARD | fc33ff4 | 2012-07-14 15:26:08 +0800 | [diff] [blame] | 464 | #gpio-lines = <19>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 465 | interrupt-controller; |
| 466 | #interrupt-cells = <2>; |
| 467 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 468 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 469 | pioC: gpio@fffff800 { |
| 470 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 471 | reg = <0xfffff800 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 472 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 473 | #gpio-cells = <2>; |
| 474 | gpio-controller; |
| 475 | interrupt-controller; |
| 476 | #interrupt-cells = <2>; |
| 477 | }; |
| 478 | |
| 479 | pioD: gpio@fffffa00 { |
| 480 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 481 | reg = <0xfffffa00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 482 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 483 | #gpio-cells = <2>; |
| 484 | gpio-controller; |
Jean-Christophe PLAGNIOL-VILLARD | fc33ff4 | 2012-07-14 15:26:08 +0800 | [diff] [blame] | 485 | #gpio-lines = <22>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 486 | interrupt-controller; |
| 487 | #interrupt-cells = <2>; |
| 488 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 489 | }; |
| 490 | |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 491 | ssc0: ssc@f0010000 { |
| 492 | compatible = "atmel,at91sam9g45-ssc"; |
| 493 | reg = <0xf0010000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 494 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; |
Richard Genoud | 7da49ad | 2013-08-12 14:30:59 +0200 | [diff] [blame] | 495 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, |
| 496 | <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; |
| 497 | dma-names = "tx", "rx"; |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 498 | pinctrl-names = "default"; |
| 499 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 500 | status = "disabled"; |
| 501 | }; |
| 502 | |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 503 | mmc0: mmc@f0008000 { |
| 504 | compatible = "atmel,hsmci"; |
| 505 | reg = <0xf0008000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 506 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 507 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 508 | dma-names = "rxtx"; |
Nicolas Ferre | e7cca25 | 2013-09-19 15:22:57 +0200 | [diff] [blame] | 509 | pinctrl-names = "default"; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 510 | #address-cells = <1>; |
| 511 | #size-cells = <0>; |
| 512 | status = "disabled"; |
| 513 | }; |
| 514 | |
| 515 | mmc1: mmc@f000c000 { |
| 516 | compatible = "atmel,hsmci"; |
| 517 | reg = <0xf000c000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 518 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 519 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 520 | dma-names = "rxtx"; |
Nicolas Ferre | e7cca25 | 2013-09-19 15:22:57 +0200 | [diff] [blame] | 521 | pinctrl-names = "default"; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 522 | #address-cells = <1>; |
| 523 | #size-cells = <0>; |
| 524 | status = "disabled"; |
| 525 | }; |
| 526 | |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 527 | dbgu: serial@fffff200 { |
| 528 | compatible = "atmel,at91sam9260-usart"; |
| 529 | reg = <0xfffff200 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 530 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 531 | pinctrl-names = "default"; |
| 532 | pinctrl-0 = <&pinctrl_dbgu>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 533 | status = "disabled"; |
| 534 | }; |
| 535 | |
| 536 | usart0: serial@f801c000 { |
| 537 | compatible = "atmel,at91sam9260-usart"; |
| 538 | reg = <0xf801c000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 539 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 540 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 541 | pinctrl-0 = <&pinctrl_usart0>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 542 | status = "disabled"; |
| 543 | }; |
| 544 | |
| 545 | usart1: serial@f8020000 { |
| 546 | compatible = "atmel,at91sam9260-usart"; |
| 547 | reg = <0xf8020000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 548 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 549 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 550 | pinctrl-0 = <&pinctrl_usart1>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 551 | status = "disabled"; |
| 552 | }; |
| 553 | |
| 554 | usart2: serial@f8024000 { |
| 555 | compatible = "atmel,at91sam9260-usart"; |
| 556 | reg = <0xf8024000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 557 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 558 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 559 | pinctrl-0 = <&pinctrl_usart2>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 560 | status = "disabled"; |
| 561 | }; |
| 562 | |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 563 | i2c0: i2c@f8010000 { |
| 564 | compatible = "atmel,at91sam9x5-i2c"; |
| 565 | reg = <0xf8010000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 566 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 567 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, |
| 568 | <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 569 | dma-names = "tx", "rx"; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 570 | #address-cells = <1>; |
| 571 | #size-cells = <0>; |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 572 | pinctrl-names = "default"; |
| 573 | pinctrl-0 = <&pinctrl_i2c0>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 574 | status = "disabled"; |
| 575 | }; |
| 576 | |
| 577 | i2c1: i2c@f8014000 { |
| 578 | compatible = "atmel,at91sam9x5-i2c"; |
| 579 | reg = <0xf8014000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 580 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 581 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, |
| 582 | <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 583 | dma-names = "tx", "rx"; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 584 | #address-cells = <1>; |
| 585 | #size-cells = <0>; |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 586 | pinctrl-names = "default"; |
| 587 | pinctrl-0 = <&pinctrl_i2c1>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 588 | status = "disabled"; |
| 589 | }; |
| 590 | |
| 591 | i2c2: i2c@f8018000 { |
| 592 | compatible = "atmel,at91sam9x5-i2c"; |
| 593 | reg = <0xf8018000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 594 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 595 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, |
| 596 | <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 597 | dma-names = "tx", "rx"; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 598 | #address-cells = <1>; |
| 599 | #size-cells = <0>; |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 600 | pinctrl-names = "default"; |
| 601 | pinctrl-0 = <&pinctrl_i2c2>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 602 | status = "disabled"; |
| 603 | }; |
| 604 | |
Nicolas Ferre | 06723db | 2013-04-18 10:52:45 +0200 | [diff] [blame] | 605 | uart0: serial@f8040000 { |
| 606 | compatible = "atmel,at91sam9260-usart"; |
| 607 | reg = <0xf8040000 0x200>; |
| 608 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
| 609 | pinctrl-names = "default"; |
| 610 | pinctrl-0 = <&pinctrl_uart0>; |
| 611 | status = "disabled"; |
| 612 | }; |
| 613 | |
| 614 | uart1: serial@f8044000 { |
| 615 | compatible = "atmel,at91sam9260-usart"; |
| 616 | reg = <0xf8044000 0x200>; |
| 617 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 618 | pinctrl-names = "default"; |
| 619 | pinctrl-0 = <&pinctrl_uart1>; |
| 620 | status = "disabled"; |
| 621 | }; |
| 622 | |
Maxime Ripard | d029f37 | 2012-05-11 15:35:39 +0200 | [diff] [blame] | 623 | adc0: adc@f804c000 { |
| 624 | compatible = "atmel,at91sam9260-adc"; |
| 625 | reg = <0xf804c000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 626 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; |
Maxime Ripard | d029f37 | 2012-05-11 15:35:39 +0200 | [diff] [blame] | 627 | atmel,adc-use-external; |
| 628 | atmel,adc-channels-used = <0xffff>; |
| 629 | atmel,adc-vref = <3300>; |
| 630 | atmel,adc-num-channels = <12>; |
| 631 | atmel,adc-startup-time = <40>; |
| 632 | atmel,adc-channel-base = <0x50>; |
| 633 | atmel,adc-drdy-mask = <0x1000000>; |
| 634 | atmel,adc-status-register = <0x30>; |
| 635 | atmel,adc-trigger-register = <0xc0>; |
Ludovic Desroches | 4b50da6 | 2013-03-29 10:13:19 +0100 | [diff] [blame] | 636 | atmel,adc-res = <8 10>; |
| 637 | atmel,adc-res-names = "lowres", "highres"; |
| 638 | atmel,adc-use-res = "highres"; |
Maxime Ripard | d029f37 | 2012-05-11 15:35:39 +0200 | [diff] [blame] | 639 | |
| 640 | trigger@0 { |
| 641 | trigger-name = "external-rising"; |
| 642 | trigger-value = <0x1>; |
| 643 | trigger-external; |
| 644 | }; |
| 645 | |
| 646 | trigger@1 { |
| 647 | trigger-name = "external-falling"; |
| 648 | trigger-value = <0x2>; |
| 649 | trigger-external; |
| 650 | }; |
| 651 | |
| 652 | trigger@2 { |
| 653 | trigger-name = "external-any"; |
| 654 | trigger-value = <0x3>; |
| 655 | trigger-external; |
| 656 | }; |
| 657 | |
| 658 | trigger@3 { |
| 659 | trigger-name = "continuous"; |
| 660 | trigger-value = <0x6>; |
| 661 | }; |
| 662 | }; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 663 | |
| 664 | spi0: spi@f0000000 { |
| 665 | #address-cells = <1>; |
| 666 | #size-cells = <0>; |
| 667 | compatible = "atmel,at91rm9200-spi"; |
| 668 | reg = <0xf0000000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 669 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
Richard Genoud | 6b2a999 | 2013-05-31 17:02:00 +0200 | [diff] [blame] | 670 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, |
| 671 | <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; |
| 672 | dma-names = "tx", "rx"; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 673 | pinctrl-names = "default"; |
| 674 | pinctrl-0 = <&pinctrl_spi0>; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 675 | status = "disabled"; |
| 676 | }; |
| 677 | |
| 678 | spi1: spi@f0004000 { |
| 679 | #address-cells = <1>; |
| 680 | #size-cells = <0>; |
| 681 | compatible = "atmel,at91rm9200-spi"; |
| 682 | reg = <0xf0004000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 683 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
Richard Genoud | 6b2a999 | 2013-05-31 17:02:00 +0200 | [diff] [blame] | 684 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, |
| 685 | <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; |
| 686 | dma-names = "tx", "rx"; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 687 | pinctrl-names = "default"; |
| 688 | pinctrl-0 = <&pinctrl_spi1>; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 689 | status = "disabled"; |
| 690 | }; |
Linus Torvalds | dfab34a | 2013-05-02 09:28:03 -0700 | [diff] [blame] | 691 | |
Jean-Christophe PLAGNIOL-VILLARD | aecca65 | 2013-05-03 20:49:51 +0800 | [diff] [blame] | 692 | usb2: gadget@f803c000 { |
| 693 | #address-cells = <1>; |
| 694 | #size-cells = <0>; |
| 695 | compatible = "atmel,at91sam9rl-udc"; |
| 696 | reg = <0x00500000 0x80000 |
| 697 | 0xf803c000 0x400>; |
| 698 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; |
| 699 | status = "disabled"; |
| 700 | |
| 701 | ep0 { |
| 702 | reg = <0>; |
| 703 | atmel,fifo-size = <64>; |
| 704 | atmel,nb-banks = <1>; |
| 705 | }; |
| 706 | |
| 707 | ep1 { |
| 708 | reg = <1>; |
| 709 | atmel,fifo-size = <1024>; |
| 710 | atmel,nb-banks = <2>; |
| 711 | atmel,can-dma; |
| 712 | atmel,can-isoc; |
| 713 | }; |
| 714 | |
| 715 | ep2 { |
| 716 | reg = <2>; |
| 717 | atmel,fifo-size = <1024>; |
| 718 | atmel,nb-banks = <2>; |
| 719 | atmel,can-dma; |
| 720 | atmel,can-isoc; |
| 721 | }; |
| 722 | |
| 723 | ep3 { |
| 724 | reg = <3>; |
| 725 | atmel,fifo-size = <1024>; |
| 726 | atmel,nb-banks = <3>; |
| 727 | atmel,can-dma; |
| 728 | }; |
| 729 | |
| 730 | ep4 { |
| 731 | reg = <4>; |
| 732 | atmel,fifo-size = <1024>; |
| 733 | atmel,nb-banks = <3>; |
| 734 | atmel,can-dma; |
| 735 | }; |
| 736 | |
| 737 | ep5 { |
| 738 | reg = <5>; |
| 739 | atmel,fifo-size = <1024>; |
| 740 | atmel,nb-banks = <3>; |
| 741 | atmel,can-dma; |
| 742 | atmel,can-isoc; |
| 743 | }; |
| 744 | |
| 745 | ep6 { |
| 746 | reg = <6>; |
| 747 | atmel,fifo-size = <1024>; |
| 748 | atmel,nb-banks = <3>; |
| 749 | atmel,can-dma; |
| 750 | atmel,can-isoc; |
| 751 | }; |
| 752 | }; |
| 753 | |
Wenyou Yang | 136d355 | 2013-05-31 11:10:02 +0800 | [diff] [blame] | 754 | watchdog@fffffe40 { |
| 755 | compatible = "atmel,at91sam9260-wdt"; |
| 756 | reg = <0xfffffe40 0x10>; |
Boris BREZILLON | fe46aa6 | 2013-10-04 09:24:14 +0200 | [diff] [blame] | 757 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 758 | atmel,watchdog-type = "hardware"; |
| 759 | atmel,reset-type = "all"; |
| 760 | atmel,dbg-halt; |
| 761 | atmel,idle-halt; |
Wenyou Yang | 136d355 | 2013-05-31 11:10:02 +0800 | [diff] [blame] | 762 | status = "disabled"; |
| 763 | }; |
| 764 | |
Nicolas Ferre | b909c6c | 2013-03-22 10:16:56 +0100 | [diff] [blame] | 765 | rtc@fffffeb0 { |
Nicolas Ferre | 23fb05c | 2013-04-18 10:13:21 +0200 | [diff] [blame] | 766 | compatible = "atmel,at91sam9x5-rtc"; |
Nicolas Ferre | b909c6c | 2013-03-22 10:16:56 +0100 | [diff] [blame] | 767 | reg = <0xfffffeb0 0x40>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 768 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Nicolas Ferre | b909c6c | 2013-03-22 10:16:56 +0100 | [diff] [blame] | 769 | status = "disabled"; |
| 770 | }; |
Bo Shen | f3ab052 | 2013-12-19 11:59:17 +0800 | [diff] [blame] | 771 | |
| 772 | pwm0: pwm@f8034000 { |
| 773 | compatible = "atmel,at91sam9rl-pwm"; |
| 774 | reg = <0xf8034000 0x300>; |
| 775 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; |
| 776 | #pwm-cells = <3>; |
| 777 | status = "disabled"; |
| 778 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 779 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 86a89f4 | 2012-02-21 21:38:18 +0800 | [diff] [blame] | 780 | |
| 781 | nand0: nand@40000000 { |
| 782 | compatible = "atmel,at91rm9200-nand"; |
| 783 | #address-cells = <1>; |
| 784 | #size-cells = <1>; |
| 785 | reg = <0x40000000 0x10000000 |
Josh Wu | 5314bc2 | 2013-01-23 20:47:09 +0800 | [diff] [blame] | 786 | 0xffffe000 0x600 /* PMECC Registers */ |
| 787 | 0xffffe600 0x200 /* PMECC Error Location Registers */ |
| 788 | 0x00108000 0x18000 /* PMECC looup table in ROM code */ |
Jean-Christophe PLAGNIOL-VILLARD | 86a89f4 | 2012-02-21 21:38:18 +0800 | [diff] [blame] | 789 | >; |
Josh Wu | 5314bc2 | 2013-01-23 20:47:09 +0800 | [diff] [blame] | 790 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
Jean-Christophe PLAGNIOL-VILLARD | 86a89f4 | 2012-02-21 21:38:18 +0800 | [diff] [blame] | 791 | atmel,nand-addr-offset = <21>; |
| 792 | atmel,nand-cmd-offset = <22>; |
Nicolas Ferre | e8b2da6 | 2013-07-01 17:05:18 +0200 | [diff] [blame^] | 793 | atmel,nand-has-dma; |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 794 | pinctrl-names = "default"; |
| 795 | pinctrl-0 = <&pinctrl_nand>; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 796 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
| 797 | &pioD 4 GPIO_ACTIVE_HIGH |
Jean-Christophe PLAGNIOL-VILLARD | 86a89f4 | 2012-02-21 21:38:18 +0800 | [diff] [blame] | 798 | 0 |
| 799 | >; |
| 800 | status = "disabled"; |
| 801 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 802 | |
| 803 | usb0: ohci@00600000 { |
| 804 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 805 | reg = <0x00600000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 806 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 807 | status = "disabled"; |
| 808 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 809 | |
| 810 | usb1: ehci@00700000 { |
| 811 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 812 | reg = <0x00700000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 813 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 814 | status = "disabled"; |
| 815 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 816 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 817 | |
| 818 | i2c@0 { |
| 819 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 820 | gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ |
| 821 | &pioA 31 GPIO_ACTIVE_HIGH /* scl */ |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 822 | >; |
| 823 | i2c-gpio,sda-open-drain; |
| 824 | i2c-gpio,scl-open-drain; |
| 825 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 826 | #address-cells = <1>; |
| 827 | #size-cells = <0>; |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 828 | pinctrl-names = "default"; |
| 829 | pinctrl-0 = <&pinctrl_i2c_gpio0>; |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 830 | status = "disabled"; |
| 831 | }; |
| 832 | |
| 833 | i2c@1 { |
| 834 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 835 | gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ |
| 836 | &pioC 1 GPIO_ACTIVE_HIGH /* scl */ |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 837 | >; |
| 838 | i2c-gpio,sda-open-drain; |
| 839 | i2c-gpio,scl-open-drain; |
| 840 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 841 | #address-cells = <1>; |
| 842 | #size-cells = <0>; |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 843 | pinctrl-names = "default"; |
| 844 | pinctrl-0 = <&pinctrl_i2c_gpio1>; |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 845 | status = "disabled"; |
| 846 | }; |
| 847 | |
| 848 | i2c@2 { |
| 849 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 850 | gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ |
| 851 | &pioB 5 GPIO_ACTIVE_HIGH /* scl */ |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 852 | >; |
| 853 | i2c-gpio,sda-open-drain; |
| 854 | i2c-gpio,scl-open-drain; |
| 855 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 856 | #address-cells = <1>; |
| 857 | #size-cells = <0>; |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 858 | pinctrl-names = "default"; |
| 859 | pinctrl-0 = <&pinctrl_i2c_gpio2>; |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 860 | status = "disabled"; |
| 861 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 862 | }; |