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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBMNP405H_H__
12#define __ASM_IBMNP405H_H__
13
14#include <linux/config.h>
15
16/* ibm405.h at bottom of this file */
17
18#define PPC405_PCI_CONFIG_ADDR 0xeec00000
19#define PPC405_PCI_CONFIG_DATA 0xeec00004
20#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
21 /* setbat */
22#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
23#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
24#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
25
26#define PPC405_PCI_LOWER_MEM 0x00000000 /* hose_a->mem_space.start */
27#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
28#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
29#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
30
31#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
32
33#define PPC4xx_PCI_IO_ADDR ((uint)PPC405_PCI_PHY_IO_BASE)
34#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
35#define PPC4xx_PCI_CFG_ADDR ((uint)PPC405_PCI_CONFIG_ADDR)
36#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
37#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000)
38#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
39#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000)
40#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
41
42/* serial port defines */
43#define RS_TABLE_SIZE 4
44
45#define UART0_INT 0
46#define UART1_INT 1
47#define PCIL0_BASE 0xEF400000
48#define UART0_IO_BASE 0xEF600300
49#define UART1_IO_BASE 0xEF600400
50#define OPB0_BASE 0xEF600600
51#define EMAC0_BASE 0xEF600800
52
53#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
54
55#define STD_UART_OP(num) \
56 { 0, BASE_BAUD, 0, UART##num##_INT, \
57 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
58 iomem_base:(u8 *) UART##num##_IO_BASE, \
59 io_type: SERIAL_IO_MEM},
60
61#if defined(CONFIG_UART0_TTYS0)
62#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
63#define SERIAL_PORT_DFNS \
64 STD_UART_OP(0) \
65 STD_UART_OP(1)
66#endif
67
68#if defined(CONFIG_UART0_TTYS1)
69#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
70#define SERIAL_PORT_DFNS \
71 STD_UART_OP(1) \
72 STD_UART_OP(0)
73#endif
74
75/* DCR defines */
76/* ------------------------------------------------------------------------- */
77
78#define DCRN_CHCR_BASE 0x0F1
79#define DCRN_CHPSR_BASE 0x0B4
80#define DCRN_CPMSR_BASE 0x0BA
81#define DCRN_CPMFR_BASE 0x0B9
82#define DCRN_CPMER_BASE 0x0B8
83
84/* CPM Clocking & Power Mangement defines */
85#define IBM_CPM_PCI 0x40000000 /* PCI */
86#define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */
87#define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */
88#define IBM_CPM_EMAC0 0x00800000 /* EMAC 0 MII */
89#define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */
90#define IBM_CPM_EMMII 0 /* Shift value for MII */
91#define IBM_CPM_EMRX 1 /* Shift value for recv */
92#define IBM_CPM_EMTX 2 /* Shift value for MAC */
93#define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */
94#define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */
95#define IBM_CPM_CPU 0x00008000 /* processor core */
96#define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */
97#define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */
98#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */
99#define IBM_CPM_HDLC 0x00000800 /* HDCL */
100#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
101#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
102#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
103#define IBM_CPM_DMA 0x00000040 /* DMA controller */
104#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
105#define IBM_CPM_UART0 0x00000002 /* serial port 0 */
106#define IBM_CPM_UART1 0x00000001 /* serial port 1 */
107/* this is the default setting for devices put to sleep when booting */
108
109#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
110 | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
111 | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \
112 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \
113 | IBM_CPM_EMAC3 | IBM_CPM_PCI)
114
115#define DCRN_DMA0_BASE 0x100
116#define DCRN_DMA1_BASE 0x108
117#define DCRN_DMA2_BASE 0x110
118#define DCRN_DMA3_BASE 0x118
119#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
120#define DCRN_DMASR_BASE 0x120
121#define DCRN_EBC_BASE 0x012
122#define DCRN_DCP0_BASE 0x014
123#define DCRN_MAL_BASE 0x180
124#define DCRN_OCM0_BASE 0x018
125#define DCRN_PLB0_BASE 0x084
126#define DCRN_PLLMR_BASE 0x0B0
127#define DCRN_POB0_BASE 0x0A0
128#define DCRN_SDRAM0_BASE 0x010
129#define DCRN_UIC0_BASE 0x0C0
130#define DCRN_UIC1_BASE 0x0D0
131#define DCRN_CPC0_EPRCSR 0x0F3
132
133#define UIC0_UIC1NC 0x00000002
134
135#define CHR1_CETE 0x00000004 /* CPU external timer enable */
136#define UIC0 DCRN_UIC0_BASE
137#define UIC1 DCRN_UIC1_BASE
138
139#undef NR_UICS
140#define NR_UICS 2
141
142/* EMAC DCRN's FIXME: armin */
143#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
144#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
145#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
146#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
147#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
148#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
149#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
150#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
151
152#include <asm/ibm405.h>
153
154#endif /* __ASM_IBMNP405H_H__ */
155#endif /* __KERNEL__ */