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Marc Zyngier1a89dd92013-01-21 19:36:12 -05001/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARM_KVM_VGIC_H
20#define __ASM_ARM_KVM_VGIC_H
21
Marc Zyngierb47ef922013-01-21 19:36:14 -050022#include <linux/kernel.h>
23#include <linux/kvm.h>
Marc Zyngierb47ef922013-01-21 19:36:14 -050024#include <linux/irqreturn.h>
25#include <linux/spinlock.h>
26#include <linux/types.h>
Andre Przywara6777f772015-03-26 14:39:34 +000027#include <kvm/iodev.h>
Marc Zyngier1a89dd92013-01-21 19:36:12 -050028
Marc Zyngier5fb66da2014-07-08 12:09:05 +010029#define VGIC_NR_IRQS_LEGACY 256
Marc Zyngierb47ef922013-01-21 19:36:14 -050030#define VGIC_NR_SGIS 16
31#define VGIC_NR_PPIS 16
32#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
Marc Zyngier8f186d52014-02-04 18:13:03 +000033
34#define VGIC_V2_MAX_LRS (1 << 6)
Marc Zyngierb2fb1c02013-07-12 15:15:23 +010035#define VGIC_V3_MAX_LRS 16
Marc Zyngierc3c91832014-07-08 12:09:04 +010036#define VGIC_MAX_IRQS 1024
Andre Przywara3caa2d82014-06-02 16:26:01 +020037#define VGIC_V2_MAX_CPUS 8
Ming Leief748912015-09-02 14:31:21 +080038#define VGIC_V3_MAX_CPUS 255
Marc Zyngierb47ef922013-01-21 19:36:14 -050039
Marc Zyngier5fb66da2014-07-08 12:09:05 +010040#if (VGIC_NR_IRQS_LEGACY & 31)
Marc Zyngierb47ef922013-01-21 19:36:14 -050041#error "VGIC_NR_IRQS must be a multiple of 32"
42#endif
43
Marc Zyngier5fb66da2014-07-08 12:09:05 +010044#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
Marc Zyngierb47ef922013-01-21 19:36:14 -050045#error "VGIC_NR_IRQS must be <= 1024"
46#endif
47
48/*
49 * The GIC distributor registers describing interrupts have two parts:
50 * - 32 per-CPU interrupts (SGI + PPI)
51 * - a bunch of shared interrupts (SPI)
52 */
53struct vgic_bitmap {
Marc Zyngierc1bfb572014-07-08 12:09:01 +010054 /*
55 * - One UL per VCPU for private interrupts (assumes UL is at
56 * least 32 bits)
57 * - As many UL as necessary for shared interrupts.
58 *
59 * The private interrupts are accessed via the "private"
60 * field, one UL per vcpu (the state for vcpu n is in
61 * private[n]). The shared interrupts are accessed via the
62 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
63 */
64 unsigned long *private;
65 unsigned long *shared;
Marc Zyngierb47ef922013-01-21 19:36:14 -050066};
67
68struct vgic_bytemap {
Marc Zyngierc1bfb572014-07-08 12:09:01 +010069 /*
70 * - 8 u32 per VCPU for private interrupts
71 * - As many u32 as necessary for shared interrupts.
72 *
73 * The private interrupts are accessed via the "private"
74 * field, (the state for vcpu n is in private[n*8] to
75 * private[n*8 + 7]). The shared interrupts are accessed via
76 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
77 * shared[(n-32)/4] word).
78 */
79 u32 *private;
80 u32 *shared;
Marc Zyngierb47ef922013-01-21 19:36:14 -050081};
82
Marc Zyngier8d5c6b02013-06-03 15:55:02 +010083struct kvm_vcpu;
84
Marc Zyngier1a9b1302013-06-21 11:57:56 +010085enum vgic_type {
86 VGIC_V2, /* Good ol' GICv2 */
Marc Zyngierb2fb1c02013-07-12 15:15:23 +010087 VGIC_V3, /* New fancy GICv3 */
Marc Zyngier1a9b1302013-06-21 11:57:56 +010088};
89
Marc Zyngier8d5c6b02013-06-03 15:55:02 +010090#define LR_STATE_PENDING (1 << 0)
91#define LR_STATE_ACTIVE (1 << 1)
92#define LR_STATE_MASK (3 << 0)
93#define LR_EOI_INT (1 << 2)
Marc Zyngier32d2d802015-06-08 15:21:32 +010094#define LR_HW (1 << 3)
Marc Zyngier8d5c6b02013-06-03 15:55:02 +010095
96struct vgic_lr {
Marc Zyngier32d2d802015-06-08 15:21:32 +010097 unsigned irq:10;
98 union {
99 unsigned hwirq:10;
100 unsigned source:3;
101 };
102 unsigned state:4;
Marc Zyngier8d5c6b02013-06-03 15:55:02 +0100103};
104
Marc Zyngierbeee38b2014-02-04 17:48:10 +0000105struct vgic_vmcr {
106 u32 ctlr;
107 u32 abpr;
108 u32 bpr;
109 u32 pmr;
110};
111
Marc Zyngier8d5c6b02013-06-03 15:55:02 +0100112struct vgic_ops {
113 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
114 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
Marc Zyngier69bb2c92013-06-04 10:29:39 +0100115 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
116 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
Marc Zyngier8d6a0312013-06-04 10:33:43 +0100117 u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
Christoffer Dallae705932015-03-13 17:02:56 +0000118 void (*clear_eisr)(struct kvm_vcpu *vcpu);
Marc Zyngier495dd852013-06-04 11:02:10 +0100119 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
Marc Zyngier909d9b52013-06-04 11:24:17 +0100120 void (*enable_underflow)(struct kvm_vcpu *vcpu);
121 void (*disable_underflow)(struct kvm_vcpu *vcpu);
Marc Zyngierbeee38b2014-02-04 17:48:10 +0000122 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
123 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
Marc Zyngierda8dafd12013-06-04 11:36:38 +0100124 void (*enable)(struct kvm_vcpu *vcpu);
Marc Zyngier8d5c6b02013-06-03 15:55:02 +0100125};
126
Marc Zyngierca85f622013-06-18 19:17:28 +0100127struct vgic_params {
Marc Zyngier1a9b1302013-06-21 11:57:56 +0100128 /* vgic type */
129 enum vgic_type type;
Marc Zyngierca85f622013-06-18 19:17:28 +0100130 /* Physical address of vgic virtual cpu interface */
131 phys_addr_t vcpu_base;
132 /* Number of list registers */
133 u32 nr_lr;
134 /* Interrupt number */
135 unsigned int maint_irq;
136 /* Virtual control interface base address */
137 void __iomem *vctrl_base;
Andre Przywara3caa2d82014-06-02 16:26:01 +0200138 int max_gic_vcpus;
Andre Przywarab5d84ff2014-06-03 10:26:03 +0200139 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
140 bool can_emulate_gicv2;
Marc Zyngierca85f622013-06-18 19:17:28 +0100141};
142
Andre Przywarab26e5fd2014-06-02 16:19:12 +0200143struct vgic_vm_ops {
Andre Przywarab26e5fd2014-06-02 16:19:12 +0200144 bool (*queue_sgi)(struct kvm_vcpu *, int irq);
145 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
146 int (*init_model)(struct kvm *);
147 int (*map_resources)(struct kvm *, const struct vgic_params *);
148};
149
Andre Przywara6777f772015-03-26 14:39:34 +0000150struct vgic_io_device {
151 gpa_t addr;
152 int len;
153 const struct vgic_io_range *reg_ranges;
154 struct kvm_vcpu *redist_vcpu;
155 struct kvm_io_device dev;
156};
157
Marc Zyngier6c3d63c2014-06-23 17:37:18 +0100158struct irq_phys_map {
159 u32 virt_irq;
160 u32 phys_irq;
161 u32 irq;
162 bool active;
163};
164
165struct irq_phys_map_entry {
166 struct list_head entry;
167 struct rcu_head rcu;
168 struct irq_phys_map map;
169};
170
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500171struct vgic_dist {
Marc Zyngierb47ef922013-01-21 19:36:14 -0500172 spinlock_t lock;
Marc Zyngierf982cf42014-05-15 10:03:25 +0100173 bool in_kernel;
Marc Zyngier01ac5e32013-01-21 19:36:16 -0500174 bool ready;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500175
Andre Przywara598921362014-06-03 09:33:10 +0200176 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
177 u32 vgic_model;
178
Marc Zyngierc1bfb572014-07-08 12:09:01 +0100179 int nr_cpus;
180 int nr_irqs;
181
Marc Zyngierb47ef922013-01-21 19:36:14 -0500182 /* Virtual control interface mapping */
183 void __iomem *vctrl_base;
184
Christoffer Dall330690c2013-01-21 19:36:13 -0500185 /* Distributor and vcpu interface mapping in the guest */
186 phys_addr_t vgic_dist_base;
Andre Przywaraa0675c22014-06-07 00:54:51 +0200187 /* GICv2 and GICv3 use different mapped register blocks */
188 union {
189 phys_addr_t vgic_cpu_base;
190 phys_addr_t vgic_redist_base;
191 };
Marc Zyngierb47ef922013-01-21 19:36:14 -0500192
193 /* Distributor enabled */
194 u32 enabled;
195
196 /* Interrupt enabled (one bit per IRQ) */
197 struct vgic_bitmap irq_enabled;
198
Christoffer Dallfaa1b462014-06-14 21:54:51 +0200199 /* Level-triggered interrupt external input is asserted */
200 struct vgic_bitmap irq_level;
201
202 /*
203 * Interrupt state is pending on the distributor
204 */
Christoffer Dall227844f2014-06-09 12:27:18 +0200205 struct vgic_bitmap irq_pending;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500206
Christoffer Dallfaa1b462014-06-14 21:54:51 +0200207 /*
208 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
209 * interrupts. Essentially holds the state of the flip-flop in
210 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
211 * Once set, it is only cleared for level-triggered interrupts on
212 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
213 */
214 struct vgic_bitmap irq_soft_pend;
215
Christoffer Dalldbf20f92014-06-09 12:55:13 +0200216 /* Level-triggered interrupt queued on VCPU interface */
217 struct vgic_bitmap irq_queued;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500218
Christoffer Dall47a98b12015-03-13 17:02:54 +0000219 /* Interrupt was active when unqueue from VCPU interface */
220 struct vgic_bitmap irq_active;
221
Marc Zyngierb47ef922013-01-21 19:36:14 -0500222 /* Interrupt priority. Not used yet. */
223 struct vgic_bytemap irq_priority;
224
225 /* Level/edge triggered */
226 struct vgic_bitmap irq_cfg;
227
Marc Zyngierc1bfb572014-07-08 12:09:01 +0100228 /*
229 * Source CPU per SGI and target CPU:
230 *
231 * Each byte represent a SGI observable on a VCPU, each bit of
232 * this byte indicating if the corresponding VCPU has
233 * generated this interrupt. This is a GICv2 feature only.
234 *
235 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
236 * the SGIs observable on VCPUn.
237 */
238 u8 *irq_sgi_sources;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500239
Marc Zyngierc1bfb572014-07-08 12:09:01 +0100240 /*
241 * Target CPU for each SPI:
242 *
243 * Array of available SPI, each byte indicating the target
244 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
245 */
246 u8 *irq_spi_cpu;
247
248 /*
249 * Reverse lookup of irq_spi_cpu for faster compute pending:
250 *
251 * Array of bitmaps, one per VCPU, describing if IRQn is
252 * routed to a particular VCPU.
253 */
254 struct vgic_bitmap *irq_spi_target;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500255
Andre Przywaraa0675c22014-06-07 00:54:51 +0200256 /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
257 u32 *irq_spi_mpidr;
258
Marc Zyngierb47ef922013-01-21 19:36:14 -0500259 /* Bitmap indicating which CPU has something pending */
Marc Zyngierc1bfb572014-07-08 12:09:01 +0100260 unsigned long *irq_pending_on_cpu;
Andre Przywarab26e5fd2014-06-02 16:19:12 +0200261
Christoffer Dall47a98b12015-03-13 17:02:54 +0000262 /* Bitmap indicating which CPU has active IRQs */
263 unsigned long *irq_active_on_cpu;
264
Andre Przywarab26e5fd2014-06-02 16:19:12 +0200265 struct vgic_vm_ops vm_ops;
Andre Przywaraa9cf86f2015-03-26 14:39:35 +0000266 struct vgic_io_device dist_iodev;
Andre Przywarafb8f61a2015-03-26 14:39:37 +0000267 struct vgic_io_device *redist_iodevs;
Marc Zyngier6c3d63c2014-06-23 17:37:18 +0100268
269 /* Virtual irq to hwirq mapping */
270 spinlock_t irq_phys_map_lock;
271 struct list_head irq_phys_map_list;
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500272};
273
Marc Zyngiereede8212013-05-30 10:20:36 +0100274struct vgic_v2_cpu_if {
275 u32 vgic_hcr;
276 u32 vgic_vmcr;
277 u32 vgic_misr; /* Saved only */
Christoffer Dall2df36a52014-09-28 16:04:26 +0200278 u64 vgic_eisr; /* Saved only */
279 u64 vgic_elrsr; /* Saved only */
Marc Zyngiereede8212013-05-30 10:20:36 +0100280 u32 vgic_apr;
Marc Zyngier8f186d52014-02-04 18:13:03 +0000281 u32 vgic_lr[VGIC_V2_MAX_LRS];
Marc Zyngiereede8212013-05-30 10:20:36 +0100282};
283
Marc Zyngierb2fb1c02013-07-12 15:15:23 +0100284struct vgic_v3_cpu_if {
285#ifdef CONFIG_ARM_GIC_V3
286 u32 vgic_hcr;
287 u32 vgic_vmcr;
Andre Przywara2f5fa412014-06-03 08:58:15 +0200288 u32 vgic_sre; /* Restored only, change ignored */
Marc Zyngierb2fb1c02013-07-12 15:15:23 +0100289 u32 vgic_misr; /* Saved only */
290 u32 vgic_eisr; /* Saved only */
291 u32 vgic_elrsr; /* Saved only */
292 u32 vgic_ap0r[4];
293 u32 vgic_ap1r[4];
294 u64 vgic_lr[VGIC_V3_MAX_LRS];
295#endif
296};
297
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500298struct vgic_cpu {
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500299 /* per IRQ to LR mapping */
Marc Zyngierc1bfb572014-07-08 12:09:01 +0100300 u8 *vgic_irq_lr_map;
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500301
Christoffer Dall47a98b12015-03-13 17:02:54 +0000302 /* Pending/active/both interrupts on this VCPU */
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500303 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
Christoffer Dall47a98b12015-03-13 17:02:54 +0000304 DECLARE_BITMAP( active_percpu, VGIC_NR_PRIVATE_IRQS);
305 DECLARE_BITMAP( pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
306
307 /* Pending/active/both shared interrupts, dynamically sized */
Marc Zyngierc1bfb572014-07-08 12:09:01 +0100308 unsigned long *pending_shared;
Christoffer Dall47a98b12015-03-13 17:02:54 +0000309 unsigned long *active_shared;
310 unsigned long *pend_act_shared;
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500311
312 /* Bitmap of used/free list registers */
Marc Zyngier8f186d52014-02-04 18:13:03 +0000313 DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500314
315 /* Number of list registers on this CPU */
316 int nr_lr;
317
318 /* CPU vif control registers for world switch */
Marc Zyngiereede8212013-05-30 10:20:36 +0100319 union {
320 struct vgic_v2_cpu_if vgic_v2;
Marc Zyngierb2fb1c02013-07-12 15:15:23 +0100321 struct vgic_v3_cpu_if vgic_v3;
Marc Zyngiereede8212013-05-30 10:20:36 +0100322 };
Marc Zyngier6c3d63c2014-06-23 17:37:18 +0100323
324 /* Protected by the distributor's irq_phys_map_lock */
325 struct list_head irq_phys_map_list;
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500326};
327
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500328#define LR_EMPTY 0xff
329
Marc Zyngier495dd852013-06-04 11:02:10 +0100330#define INT_STATUS_EOI (1 << 0)
331#define INT_STATUS_UNDERFLOW (1 << 1)
332
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500333struct kvm;
334struct kvm_vcpu;
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500335
Christoffer Dallce01e4e2013-09-23 14:55:56 -0700336int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
Marc Zyngier01ac5e32013-01-21 19:36:16 -0500337int kvm_vgic_hyp_init(void);
Peter Maydell6d3cfbe2014-12-04 15:02:24 +0000338int kvm_vgic_map_resources(struct kvm *kvm);
Andre Przywara3caa2d82014-06-02 16:26:01 +0200339int kvm_vgic_get_max_vcpus(void);
Marc Zyngier6c3d63c2014-06-23 17:37:18 +0100340void kvm_vgic_early_init(struct kvm *kvm);
Andre Przywara598921362014-06-03 09:33:10 +0200341int kvm_vgic_create(struct kvm *kvm, u32 type);
Marc Zyngierc1bfb572014-07-08 12:09:01 +0100342void kvm_vgic_destroy(struct kvm *kvm);
Marc Zyngier6c3d63c2014-06-23 17:37:18 +0100343void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
Marc Zyngierc1bfb572014-07-08 12:09:01 +0100344void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500345void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
346void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
Marc Zyngier5863c2c2013-01-21 19:36:15 -0500347int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
348 bool level);
Marc Zyngier773299a2015-07-24 11:30:43 +0100349int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid,
350 struct irq_phys_map *map, bool level);
Andre Przywara6d52f352014-06-03 10:13:13 +0200351void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500352int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
Christoffer Dall47a98b12015-03-13 17:02:54 +0000353int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu);
Marc Zyngier6c3d63c2014-06-23 17:37:18 +0100354struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu,
355 int virt_irq, int irq);
356int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map);
Marc Zyngier6e84e0e2015-06-08 16:13:30 +0100357bool kvm_vgic_get_phys_irq_active(struct irq_phys_map *map);
358void kvm_vgic_set_phys_irq_active(struct irq_phys_map *map, bool active);
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500359
Marc Zyngierf982cf42014-05-15 10:03:25 +0100360#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
Christoffer Dall1f57be22014-12-09 14:30:36 +0100361#define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
Christoffer Dallc52edf52014-12-09 14:28:09 +0100362#define vgic_ready(k) ((k)->arch.vgic.ready)
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500363
Marc Zyngier8f186d52014-02-04 18:13:03 +0000364int vgic_v2_probe(struct device_node *vgic_node,
365 const struct vgic_ops **ops,
366 const struct vgic_params **params);
Marc Zyngierb2fb1c02013-07-12 15:15:23 +0100367#ifdef CONFIG_ARM_GIC_V3
368int vgic_v3_probe(struct device_node *vgic_node,
369 const struct vgic_ops **ops,
370 const struct vgic_params **params);
371#else
372static inline int vgic_v3_probe(struct device_node *vgic_node,
373 const struct vgic_ops **ops,
374 const struct vgic_params **params)
375{
376 return -ENODEV;
377}
378#endif
Marc Zyngier8f186d52014-02-04 18:13:03 +0000379
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500380#endif