blob: 5f1f9867fc70eedff4620119fead758eb7c0e2b2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-footbridge/dc21285-timer.c
3 *
4 * Copyright (C) 1998 Russell King.
5 * Copyright (C) 1998 Phil Blundell
6 */
Russell King4e8d7632011-01-28 21:00:39 +00007#include <linux/clockchips.h>
8#include <linux/clocksource.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/init.h>
10#include <linux/interrupt.h>
Thomas Gleixner55e86982006-07-01 22:32:17 +010011#include <linux/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012
13#include <asm/irq.h>
14
15#include <asm/hardware/dec21285.h>
16#include <asm/mach/time.h>
17
18#include "common.h"
19
Russell King4e8d7632011-01-28 21:00:39 +000020static cycle_t cksrc_dc21285_read(struct clocksource *cs)
Linus Torvalds1da177e2005-04-16 15:20:36 -070021{
Russell King4e8d7632011-01-28 21:00:39 +000022 return cs->mask - *CSR_TIMER2_VALUE;
Linus Torvalds1da177e2005-04-16 15:20:36 -070023}
24
Russell King4e8d7632011-01-28 21:00:39 +000025static int cksrc_dc21285_enable(struct clocksource *cs)
Linus Torvalds1da177e2005-04-16 15:20:36 -070026{
Russell King4e8d7632011-01-28 21:00:39 +000027 *CSR_TIMER2_LOAD = cs->mask;
28 *CSR_TIMER2_CLR = 0;
29 *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
30 return 0;
31}
32
Thomas Gleixnerf2e0bf22011-03-28 11:25:40 +020033static void cksrc_dc21285_disable(struct clocksource *cs)
Russell King4e8d7632011-01-28 21:00:39 +000034{
35 *CSR_TIMER2_CNTL = 0;
36}
37
38static struct clocksource cksrc_dc21285 = {
39 .name = "dc21285_timer2",
40 .rating = 200,
41 .read = cksrc_dc21285_read,
42 .enable = cksrc_dc21285_enable,
43 .disable = cksrc_dc21285_disable,
44 .mask = CLOCKSOURCE_MASK(24),
45 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
46};
47
48static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
49 struct clock_event_device *c)
50{
51 switch (mode) {
52 case CLOCK_EVT_MODE_RESUME:
53 case CLOCK_EVT_MODE_PERIODIC:
54 *CSR_TIMER1_CLR = 0;
55 *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
56 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
57 TIMER_CNTL_DIV16;
58 break;
59
60 default:
61 *CSR_TIMER1_CNTL = 0;
62 break;
63 }
64}
65
66static struct clock_event_device ckevt_dc21285 = {
67 .name = "dc21285_timer1",
68 .features = CLOCK_EVT_FEAT_PERIODIC,
69 .rating = 200,
70 .irq = IRQ_TIMER1,
71 .set_mode = ckevt_dc21285_set_mode,
72};
73
74static irqreturn_t timer1_interrupt(int irq, void *dev_id)
75{
76 struct clock_event_device *ce = dev_id;
77
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 *CSR_TIMER1_CLR = 0;
79
Russell King4e8d7632011-01-28 21:00:39 +000080 ce->event_handler(ce);
Linus Torvalds1da177e2005-04-16 15:20:36 -070081
Linus Torvalds1da177e2005-04-16 15:20:36 -070082 return IRQ_HANDLED;
83}
84
85static struct irqaction footbridge_timer_irq = {
Russell King4e8d7632011-01-28 21:00:39 +000086 .name = "dc21285_timer1",
Linus Torvalds1da177e2005-04-16 15:20:36 -070087 .handler = timer1_interrupt,
Bernhard Walleb30faba2007-05-08 00:35:39 -070088 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Russell King4e8d7632011-01-28 21:00:39 +000089 .dev_id = &ckevt_dc21285,
Linus Torvalds1da177e2005-04-16 15:20:36 -070090};
91
92/*
93 * Set up timer interrupt.
94 */
95static void __init footbridge_timer_init(void)
96{
Russell King4e8d7632011-01-28 21:00:39 +000097 struct clock_event_device *ce = &ckevt_dc21285;
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
Russell King4e8d7632011-01-28 21:00:39 +000099 clocksource_register_hz(&cksrc_dc21285, (mem_fclk_21285 + 8) / 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
Russell King4e8d7632011-01-28 21:00:39 +0000101 setup_irq(ce->irq, &footbridge_timer_irq);
102
103 clockevents_calc_mult_shift(ce, mem_fclk_21285, 5);
104 ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce);
105 ce->min_delta_ns = clockevent_delta2ns(0x000004, ce);
106
107 clockevents_register_device(ce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108}
109
110struct sys_timer footbridge_timer = {
111 .init = footbridge_timer_init,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112};