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Shawn Guo082d33d2013-04-02 13:15:16 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Anson Huang22724cf12014-01-20 20:02:38 +080013#include <dt-bindings/gpio/gpio.h>
Anson Huang8e4422a2013-12-19 16:07:24 -050014#include <dt-bindings/input/input.h>
15
Shawn Guo082d33d2013-04-02 13:15:16 +080016/ {
Sascha Hauer48f51962014-05-07 15:19:00 +020017 chosen {
18 stdout-path = &uart1;
19 };
20
Shawn Guo082d33d2013-04-02 13:15:16 +080021 memory {
22 reg = <0x10000000 0x40000000>;
23 };
24
25 regulators {
26 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080027 #address-cells = <1>;
28 #size-cells = <0>;
Shawn Guo082d33d2013-04-02 13:15:16 +080029
Shawn Guo56160e32014-02-07 23:22:50 +080030 reg_usb_otg_vbus: regulator@0 {
Shawn Guo082d33d2013-04-02 13:15:16 +080031 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080032 reg = <0>;
Shawn Guo082d33d2013-04-02 13:15:16 +080033 regulator-name = "usb_otg_vbus";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
36 gpio = <&gpio3 22 0>;
37 enable-active-high;
38 };
Nicolin Chenfdbfb432013-06-13 19:51:00 +080039
Shawn Guo56160e32014-02-07 23:22:50 +080040 reg_usb_h1_vbus: regulator@1 {
Peter Chen015fa462013-08-12 16:46:24 +080041 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080042 reg = <1>;
Peter Chen015fa462013-08-12 16:46:24 +080043 regulator-name = "usb_h1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 gpio = <&gpio1 29 0>;
47 enable-active-high;
48 };
49
Shawn Guo56160e32014-02-07 23:22:50 +080050 reg_audio: regulator@2 {
Nicolin Chenfdbfb432013-06-13 19:51:00 +080051 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080052 reg = <2>;
Nicolin Chenfdbfb432013-06-13 19:51:00 +080053 regulator-name = "wm8962-supply";
54 gpio = <&gpio4 10 0>;
55 enable-active-high;
56 };
Shawn Guo082d33d2013-04-02 13:15:16 +080057 };
58
59 gpio-keys {
60 compatible = "gpio-keys";
Anson Huang8e4422a2013-12-19 16:07:24 -050061 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_gpio_keys>;
63
64 power {
65 label = "Power Button";
Anson Huang22724cf12014-01-20 20:02:38 +080066 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
Anson Huang8e4422a2013-12-19 16:07:24 -050067 gpio-key,wakeup;
68 linux,code = <KEY_POWER>;
69 };
Shawn Guo082d33d2013-04-02 13:15:16 +080070
71 volume-up {
72 label = "Volume Up";
Anson Huang22724cf12014-01-20 20:02:38 +080073 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
Fabio Estevam6c306402013-07-19 10:40:23 -030074 gpio-key,wakeup;
Anson Huang8e4422a2013-12-19 16:07:24 -050075 linux,code = <KEY_VOLUMEUP>;
Shawn Guo082d33d2013-04-02 13:15:16 +080076 };
77
78 volume-down {
79 label = "Volume Down";
Anson Huang22724cf12014-01-20 20:02:38 +080080 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
Fabio Estevam6c306402013-07-19 10:40:23 -030081 gpio-key,wakeup;
Anson Huang8e4422a2013-12-19 16:07:24 -050082 linux,code = <KEY_VOLUMEDOWN>;
Shawn Guo082d33d2013-04-02 13:15:16 +080083 };
84 };
Nicolin Chen77b38fc2013-06-14 13:22:46 +080085
86 sound {
87 compatible = "fsl,imx6q-sabresd-wm8962",
88 "fsl,imx-audio-wm8962";
89 model = "wm8962-audio";
90 ssi-controller = <&ssi2>;
91 audio-codec = <&codec>;
92 audio-routing =
93 "Headphone Jack", "HPOUTL",
94 "Headphone Jack", "HPOUTR",
95 "Ext Spk", "SPKOUTL",
96 "Ext Spk", "SPKOUTR",
97 "MICBIAS", "AMIC",
98 "IN3R", "MICBIAS",
99 "DMIC", "MICBIAS",
100 "DMICDAT", "DMIC";
101 mux-int-port = <2>;
102 mux-ext-port = <3>;
103 };
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300104
105 backlight {
106 compatible = "pwm-backlight";
107 pwms = <&pwm1 0 5000000>;
108 brightness-levels = <0 4 8 16 32 64 128 255>;
109 default-brightness-level = <7>;
110 status = "okay";
111 };
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100112
113 leds {
114 compatible = "gpio-leds";
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_gpio_leds>;
117
118 red {
119 gpios = <&gpio1 2 0>;
120 default-state = "on";
121 };
122 };
Shawn Guo082d33d2013-04-02 13:15:16 +0800123};
124
Nicolin Chen48828702013-06-14 13:19:57 +0800125&audmux {
126 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800127 pinctrl-0 = <&pinctrl_audmux>;
Nicolin Chen48828702013-06-14 13:19:57 +0800128 status = "okay";
129};
130
Huang Shijie9110ede2013-06-21 10:19:11 +0800131&ecspi1 {
132 fsl,spi-num-chipselects = <1>;
133 cs-gpios = <&gpio4 9 0>;
134 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800135 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijie9110ede2013-06-21 10:19:11 +0800136 status = "okay";
137
138 flash: m25p80@0 {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 compatible = "st,m25p32";
142 spi-max-frequency = <20000000>;
143 reg = <0>;
144 };
145};
146
Shawn Guo082d33d2013-04-02 13:15:16 +0800147&fec {
148 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800149 pinctrl-0 = <&pinctrl_enet>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800150 phy-mode = "rgmii";
Fabio Estevamc5f592d2013-09-27 11:12:41 -0300151 phy-reset-gpios = <&gpio1 25 0>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800152 status = "okay";
153};
154
Fabio Estevamad704562014-04-22 10:04:59 -0300155&hdmi {
156 ddc-i2c-bus = <&i2c2>;
157 status = "okay";
158};
159
Nicolin Chen20426fe2013-06-13 19:51:01 +0800160&i2c1 {
161 clock-frequency = <100000>;
162 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800163 pinctrl-0 = <&pinctrl_i2c1>;
Nicolin Chen20426fe2013-06-13 19:51:01 +0800164 status = "okay";
165
166 codec: wm8962@1a {
167 compatible = "wlf,wm8962";
168 reg = <0x1a>;
Shawn Guoa94f8ec2013-07-18 14:42:28 +0800169 clocks = <&clks 201>;
Nicolin Chen20426fe2013-06-13 19:51:01 +0800170 DCVDD-supply = <&reg_audio>;
171 DBVDD-supply = <&reg_audio>;
172 AVDD-supply = <&reg_audio>;
173 CPVDD-supply = <&reg_audio>;
174 MICVDD-supply = <&reg_audio>;
175 PLLVDD-supply = <&reg_audio>;
176 SPKVDD1-supply = <&reg_audio>;
177 SPKVDD2-supply = <&reg_audio>;
178 gpio-cfg = <
179 0x0000 /* 0:Default */
180 0x0000 /* 1:Default */
181 0x0013 /* 2:FN_DMICCLK */
182 0x0000 /* 3:Default */
183 0x8014 /* 4:FN_DMICCDAT */
184 0x0000 /* 5:Default */
185 >;
186 };
187};
188
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200189&i2c2 {
190 clock-frequency = <100000>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_i2c2>;
193 status = "okay";
194
195 pmic: pfuze100@08 {
196 compatible = "fsl,pfuze100";
197 reg = <0x08>;
198
199 regulators {
200 sw1a_reg: sw1ab {
201 regulator-min-microvolt = <300000>;
202 regulator-max-microvolt = <1875000>;
203 regulator-boot-on;
204 regulator-always-on;
205 regulator-ramp-delay = <6250>;
206 };
207
208 sw1c_reg: sw1c {
209 regulator-min-microvolt = <300000>;
210 regulator-max-microvolt = <1875000>;
211 regulator-boot-on;
212 regulator-always-on;
213 regulator-ramp-delay = <6250>;
214 };
215
216 sw2_reg: sw2 {
217 regulator-min-microvolt = <800000>;
218 regulator-max-microvolt = <3300000>;
219 regulator-boot-on;
220 regulator-always-on;
221 };
222
223 sw3a_reg: sw3a {
224 regulator-min-microvolt = <400000>;
225 regulator-max-microvolt = <1975000>;
226 regulator-boot-on;
227 regulator-always-on;
228 };
229
230 sw3b_reg: sw3b {
231 regulator-min-microvolt = <400000>;
232 regulator-max-microvolt = <1975000>;
233 regulator-boot-on;
234 regulator-always-on;
235 };
236
237 sw4_reg: sw4 {
238 regulator-min-microvolt = <800000>;
239 regulator-max-microvolt = <3300000>;
240 };
241
242 swbst_reg: swbst {
243 regulator-min-microvolt = <5000000>;
244 regulator-max-microvolt = <5150000>;
245 };
246
247 snvs_reg: vsnvs {
248 regulator-min-microvolt = <1000000>;
249 regulator-max-microvolt = <3000000>;
250 regulator-boot-on;
251 regulator-always-on;
252 };
253
254 vref_reg: vrefddr {
255 regulator-boot-on;
256 regulator-always-on;
257 };
258
259 vgen1_reg: vgen1 {
260 regulator-min-microvolt = <800000>;
261 regulator-max-microvolt = <1550000>;
262 };
263
264 vgen2_reg: vgen2 {
265 regulator-min-microvolt = <800000>;
266 regulator-max-microvolt = <1550000>;
267 };
268
269 vgen3_reg: vgen3 {
270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <3300000>;
272 };
273
274 vgen4_reg: vgen4 {
275 regulator-min-microvolt = <1800000>;
276 regulator-max-microvolt = <3300000>;
277 regulator-always-on;
278 };
279
280 vgen5_reg: vgen5 {
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <3300000>;
283 regulator-always-on;
284 };
285
286 vgen6_reg: vgen6 {
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <3300000>;
289 regulator-always-on;
290 };
291 };
292 };
293};
294
Fabio Estevam38501172013-07-24 17:20:03 -0300295&i2c3 {
296 clock-frequency = <100000>;
297 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800298 pinctrl-0 = <&pinctrl_i2c3>;
Fabio Estevam38501172013-07-24 17:20:03 -0300299 status = "okay";
300
301 egalax_ts@04 {
302 compatible = "eeti,egalax_ts";
303 reg = <0x04>;
304 interrupt-parent = <&gpio6>;
305 interrupts = <7 2>;
306 wakeup-gpios = <&gpio6 7 0>;
307 };
308};
309
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800310&iomuxc {
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_hog>;
313
Shawn Guo817c27a2013-10-23 15:36:09 +0800314 imx6qdl-sabresd {
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800315 pinctrl_hog: hoggrp {
316 fsl,pins = <
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800317 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
318 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
319 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
320 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
321 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
Fabio Estevam38501172013-07-24 17:20:03 -0300322 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
Peter Chen015fa462013-08-12 16:46:24 +0800323 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
Peter Chene3c68c82013-08-12 16:51:39 +0800324 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
Fabio Estevamc5f592d2013-09-27 11:12:41 -0300325 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800326 >;
327 };
Shawn Guo817c27a2013-10-23 15:36:09 +0800328
329 pinctrl_audmux: audmuxgrp {
330 fsl,pins = <
Nicolin Chen77112dd2014-02-08 10:14:28 +0800331 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
332 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
333 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
334 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800335 >;
336 };
337
338 pinctrl_ecspi1: ecspi1grp {
339 fsl,pins = <
340 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
341 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
342 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
Fabio Estevamf3c72382014-05-14 16:53:55 -0300343 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800344 >;
345 };
346
347 pinctrl_enet: enetgrp {
348 fsl,pins = <
349 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
350 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
351 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
352 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
353 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
354 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
355 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
356 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
357 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
358 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
359 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
360 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
361 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
362 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
363 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
364 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
365 >;
366 };
367
Anson Huang8e4422a2013-12-19 16:07:24 -0500368 pinctrl_gpio_keys: gpio_keysgrp {
369 fsl,pins = <
370 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
371 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
372 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
373 >;
374 };
375
Shawn Guo817c27a2013-10-23 15:36:09 +0800376 pinctrl_i2c1: i2c1grp {
377 fsl,pins = <
378 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
379 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
380 >;
381 };
382
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200383 pinctrl_i2c2: i2c2grp {
384 fsl,pins = <
385 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
386 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
387 >;
388 };
389
Shawn Guo817c27a2013-10-23 15:36:09 +0800390 pinctrl_i2c3: i2c3grp {
391 fsl,pins = <
392 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
393 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
394 >;
395 };
396
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200397 pinctrl_pcie: pciegrp {
398 fsl,pins = <
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200399 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
400 >;
401 };
402
Shawn Guo817c27a2013-10-23 15:36:09 +0800403 pinctrl_pwm1: pwm1grp {
404 fsl,pins = <
405 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
406 >;
407 };
408
409 pinctrl_uart1: uart1grp {
410 fsl,pins = <
411 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
412 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
413 >;
414 };
415
416 pinctrl_usbotg: usbotggrp {
417 fsl,pins = <
418 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
419 >;
420 };
421
422 pinctrl_usdhc2: usdhc2grp {
423 fsl,pins = <
424 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
425 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
426 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
427 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
428 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
429 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
430 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
431 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
432 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
433 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
434 >;
435 };
436
437 pinctrl_usdhc3: usdhc3grp {
438 fsl,pins = <
439 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
440 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
441 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
442 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
443 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
444 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
445 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
446 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
447 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
448 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
449 >;
450 };
Fabio Estevame02ab39a2014-05-08 11:10:56 -0300451
452 pinctrl_usdhc4: usdhc4grp {
453 fsl,pins = <
454 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
455 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
456 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
457 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
458 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
459 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
460 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
461 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
462 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
463 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
464 >;
465 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800466 };
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100467
468 gpio_leds {
469 pinctrl_gpio_leds: gpioledsgrp {
470 fsl,pins = <
471 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
472 >;
473 };
474 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800475};
476
Shawn Guob7fb7102013-07-16 22:15:18 +0800477&ldb {
478 status = "okay";
479
480 lvds-channel@1 {
481 fsl,data-mapping = "spwg";
482 fsl,data-width = <18>;
483 status = "okay";
484
485 display-timings {
486 native-mode = <&timing0>;
487 timing0: hsd100pxn1 {
488 clock-frequency = <65000000>;
489 hactive = <1024>;
490 vactive = <768>;
491 hback-porch = <220>;
492 hfront-porch = <40>;
493 vback-porch = <21>;
494 vfront-porch = <7>;
495 hsync-len = <60>;
496 vsync-len = <10>;
497 };
498 };
499 };
500};
501
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200502&pcie {
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_pcie>;
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200505 reset-gpio = <&gpio7 12 0>;
506 status = "okay";
507};
508
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300509&pwm1 {
510 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800511 pinctrl-0 = <&pinctrl_pwm1>;
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300512 status = "okay";
513};
514
Nicolin Chen48828702013-06-14 13:19:57 +0800515&ssi2 {
516 fsl,mode = "i2s-slave";
517 status = "okay";
518};
519
Shawn Guo082d33d2013-04-02 13:15:16 +0800520&uart1 {
521 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800522 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800523 status = "okay";
524};
525
526&usbh1 {
Peter Chen015fa462013-08-12 16:46:24 +0800527 vbus-supply = <&reg_usb_h1_vbus>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800528 status = "okay";
529};
530
531&usbotg {
532 vbus-supply = <&reg_usb_otg_vbus>;
533 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800534 pinctrl-0 = <&pinctrl_usbotg>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800535 disable-over-current;
536 status = "okay";
537};
538
539&usdhc2 {
540 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800541 pinctrl-0 = <&pinctrl_usdhc2>;
Fabio Estevame3678172013-09-17 13:46:23 -0300542 bus-width = <8>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800543 cd-gpios = <&gpio2 2 0>;
544 wp-gpios = <&gpio2 3 0>;
545 status = "okay";
546};
547
548&usdhc3 {
549 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800550 pinctrl-0 = <&pinctrl_usdhc3>;
Fabio Estevame3678172013-09-17 13:46:23 -0300551 bus-width = <8>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800552 cd-gpios = <&gpio2 0 0>;
553 wp-gpios = <&gpio2 1 0>;
554 status = "okay";
555};
Fabio Estevame02ab39a2014-05-08 11:10:56 -0300556
557&usdhc4 {
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_usdhc4>;
560 bus-width = <8>;
561 non-removable;
562 no-1-8-v;
563 status = "okay";
564};