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Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Mike Frysingerb03f2032009-01-07 23:14:38 +08002 * dma.h - Blackfin DMA defines/structures/etc...
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Mike Frysingerb03f2032009-01-07 23:14:38 +08004 * Copyright 2004-2008 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
Bryan Wu1394f032007-05-06 14:50:22 -07006 */
7
8#ifndef _BLACKFIN_DMA_H_
9#define _BLACKFIN_DMA_H_
10
Bryan Wu1394f032007-05-06 14:50:22 -070011#include <linux/interrupt.h>
Mike Frysinger4c1ed6a2009-01-07 23:14:38 +080012#include <mach/dma.h>
Mike Frysingerd2e015d2009-10-09 22:18:12 +000013#include <asm/atomic.h>
Bryan Wu1394f032007-05-06 14:50:22 -070014#include <asm/blackfin.h>
Mike Frysinger4c1ed6a2009-01-07 23:14:38 +080015#include <asm/page.h>
Barry Songdd3b0e32009-11-23 03:47:24 +000016#include <asm-generic/dma.h>
Mike Frysinger6c8e75a2010-10-25 08:02:30 +000017#include <asm/bfin_dma.h>
Bryan Wu1394f032007-05-06 14:50:22 -070018
19/*-------------------------
20 * config reg bits value
21 *-------------------------*/
Mike Frysinger00d24602009-10-20 17:20:21 +000022#define DATA_SIZE_8 0
23#define DATA_SIZE_16 1
24#define DATA_SIZE_32 2
Bryan Wu1394f032007-05-06 14:50:22 -070025
Mike Frysinger00d24602009-10-20 17:20:21 +000026#define DMA_FLOW_STOP 0
27#define DMA_FLOW_AUTO 1
28#define DMA_FLOW_ARRAY 4
29#define DMA_FLOW_SMALL 6
30#define DMA_FLOW_LARGE 7
Bryan Wu1394f032007-05-06 14:50:22 -070031
Mike Frysinger00d24602009-10-20 17:20:21 +000032#define DIMENSION_LINEAR 0
33#define DIMENSION_2D 1
Bryan Wu1394f032007-05-06 14:50:22 -070034
Mike Frysinger00d24602009-10-20 17:20:21 +000035#define DIR_READ 0
36#define DIR_WRITE 1
Bryan Wu1394f032007-05-06 14:50:22 -070037
Mike Frysinger00d24602009-10-20 17:20:21 +000038#define INTR_DISABLE 0
39#define INTR_ON_BUF 2
40#define INTR_ON_ROW 3
Bryan Wu1394f032007-05-06 14:50:22 -070041
Michael Hennerich2047e402008-01-22 15:29:18 +080042#define DMA_NOSYNC_KEEP_DMA_BUF 0
Mike Frysinger00d24602009-10-20 17:20:21 +000043#define DMA_SYNC_RESTART 1
Michael Hennerich2047e402008-01-22 15:29:18 +080044
Bryan Wu1394f032007-05-06 14:50:22 -070045struct dmasg {
Mike Frysinger6ab729d2009-01-07 23:14:38 +080046 void *next_desc_addr;
Bryan Wu1394f032007-05-06 14:50:22 -070047 unsigned long start_addr;
48 unsigned short cfg;
49 unsigned short x_count;
50 short x_modify;
51 unsigned short y_count;
52 short y_modify;
53} __attribute__((packed));
54
55struct dma_register {
Mike Frysinger6ab729d2009-01-07 23:14:38 +080056 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
Bryan Wu1394f032007-05-06 14:50:22 -070057 unsigned long start_addr; /* DMA Start address register */
58
59 unsigned short cfg; /* DMA Configuration register */
60 unsigned short dummy1; /* DMA Configuration register */
61
62 unsigned long reserved;
63
64 unsigned short x_count; /* DMA x_count register */
65 unsigned short dummy2;
66
67 short x_modify; /* DMA x_modify register */
68 unsigned short dummy3;
69
70 unsigned short y_count; /* DMA y_count register */
71 unsigned short dummy4;
72
73 short y_modify; /* DMA y_modify register */
74 unsigned short dummy5;
75
Mike Frysinger6ab729d2009-01-07 23:14:38 +080076 void *curr_desc_ptr; /* DMA Current Descriptor Pointer
Bryan Wu1394f032007-05-06 14:50:22 -070077 register */
Bryan Wu452af712007-10-22 00:02:14 +080078 unsigned long curr_addr_ptr; /* DMA Current Address Pointer
Bryan Wu1394f032007-05-06 14:50:22 -070079 register */
80 unsigned short irq_status; /* DMA irq status register */
81 unsigned short dummy6;
82
83 unsigned short peripheral_map; /* DMA peripheral map register */
84 unsigned short dummy7;
85
86 unsigned short curr_x_count; /* DMA Current x-count register */
87 unsigned short dummy8;
88
89 unsigned long reserved2;
90
91 unsigned short curr_y_count; /* DMA Current y-count register */
92 unsigned short dummy9;
93
94 unsigned long reserved3;
95
96};
97
Bryan Wu1394f032007-05-06 14:50:22 -070098struct dma_channel {
Michael McTernan99532fd2009-01-07 23:14:38 +080099 const char *device_id;
Mike Frysingerd2e015d2009-10-09 22:18:12 +0000100 atomic_t chan_status;
Mike Frysinger4ce18732009-01-07 23:14:38 +0800101 volatile struct dma_register *regs;
Bryan Wu1394f032007-05-06 14:50:22 -0700102 struct dmasg *sg; /* large mode descriptor */
Michael Hennericha2ba8b12008-10-28 18:19:29 +0800103 unsigned int irq;
Bryan Wu1394f032007-05-06 14:50:22 -0700104 void *data;
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800105#ifdef CONFIG_PM
106 unsigned short saved_peripheral_map;
107#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700108};
109
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800110#ifdef CONFIG_PM
111int blackfin_dma_suspend(void);
112void blackfin_dma_resume(void);
113#endif
114
Bryan Wu1394f032007-05-06 14:50:22 -0700115/*******************************************************************************
116* DMA API's
117*******************************************************************************/
Mike Frysinger9c417a42009-01-07 23:14:39 +0800118extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
Mike Frysinger5e3bcf32010-10-25 18:11:09 +0000119extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
Mike Frysinger9c417a42009-01-07 23:14:39 +0800120extern int channel2irq(unsigned int channel);
Bryan Wu1394f032007-05-06 14:50:22 -0700121
Mike Frysinger9c417a42009-01-07 23:14:39 +0800122static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
123{
124 dma_ch[channel].regs->start_addr = addr;
125}
Mike Frysinger6ab729d2009-01-07 23:14:38 +0800126static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
Mike Frysinger9c417a42009-01-07 23:14:39 +0800127{
128 dma_ch[channel].regs->next_desc_ptr = addr;
129}
Mike Frysinger6ab729d2009-01-07 23:14:38 +0800130static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
Mike Frysinger9c417a42009-01-07 23:14:39 +0800131{
132 dma_ch[channel].regs->curr_desc_ptr = addr;
133}
134static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
135{
136 dma_ch[channel].regs->x_count = x_count;
137}
138static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
139{
140 dma_ch[channel].regs->y_count = y_count;
141}
142static inline void set_dma_x_modify(unsigned int channel, short x_modify)
143{
144 dma_ch[channel].regs->x_modify = x_modify;
145}
146static inline void set_dma_y_modify(unsigned int channel, short y_modify)
147{
148 dma_ch[channel].regs->y_modify = y_modify;
149}
150static inline void set_dma_config(unsigned int channel, unsigned short config)
151{
152 dma_ch[channel].regs->cfg = config;
153}
154static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
155{
156 dma_ch[channel].regs->curr_addr_ptr = addr;
157}
Bryan Wu1394f032007-05-06 14:50:22 -0700158
Mike Frysinger9c417a42009-01-07 23:14:39 +0800159static inline unsigned short
160set_bfin_dma_config(char direction, char flow_mode,
161 char intr_mode, char dma_mode, char width, char syncmode)
162{
163 return (direction << 1) | (width << 2) | (dma_mode << 4) |
164 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
165}
Bryan Wu1394f032007-05-06 14:50:22 -0700166
Mike Frysinger9c417a42009-01-07 23:14:39 +0800167static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
168{
169 return dma_ch[channel].regs->irq_status;
170}
171static inline unsigned short get_dma_curr_xcount(unsigned int channel)
172{
173 return dma_ch[channel].regs->curr_x_count;
174}
175static inline unsigned short get_dma_curr_ycount(unsigned int channel)
176{
177 return dma_ch[channel].regs->curr_y_count;
178}
Mike Frysinger6ab729d2009-01-07 23:14:38 +0800179static inline void *get_dma_next_desc_ptr(unsigned int channel)
Mike Frysinger9c417a42009-01-07 23:14:39 +0800180{
181 return dma_ch[channel].regs->next_desc_ptr;
182}
Mike Frysinger6ab729d2009-01-07 23:14:38 +0800183static inline void *get_dma_curr_desc_ptr(unsigned int channel)
Mike Frysinger9c417a42009-01-07 23:14:39 +0800184{
185 return dma_ch[channel].regs->curr_desc_ptr;
186}
Mike Frysinger71f5ca32009-01-07 23:14:38 +0800187static inline unsigned short get_dma_config(unsigned int channel)
188{
189 return dma_ch[channel].regs->cfg;
190}
Mike Frysinger9c417a42009-01-07 23:14:39 +0800191static inline unsigned long get_dma_curr_addr(unsigned int channel)
192{
193 return dma_ch[channel].regs->curr_addr_ptr;
194}
Bryan Wu1394f032007-05-06 14:50:22 -0700195
Mike Frysinger9c417a42009-01-07 23:14:39 +0800196static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
197{
Sonic Zhangea8538a2009-06-01 00:49:32 -0400198 /* Make sure the internal data buffers in the core are drained
199 * so that the DMA descriptors are completely written when the
200 * DMA engine goes to fetch them below.
201 */
202 SSYNC();
203
204 dma_ch[channel].regs->next_desc_ptr = sg;
Mike Frysingerd41e8002009-01-07 23:14:38 +0800205 dma_ch[channel].regs->cfg =
206 (dma_ch[channel].regs->cfg & ~(0xf << 8)) |
207 ((ndsize & 0xf) << 8);
Mike Frysinger9c417a42009-01-07 23:14:39 +0800208}
209
210static inline int dma_channel_active(unsigned int channel)
211{
Mike Frysingerd2e015d2009-10-09 22:18:12 +0000212 return atomic_read(&dma_ch[channel].chan_status);
Mike Frysinger9c417a42009-01-07 23:14:39 +0800213}
214
215static inline void disable_dma(unsigned int channel)
216{
217 dma_ch[channel].regs->cfg &= ~DMAEN;
218 SSYNC();
Mike Frysinger9c417a42009-01-07 23:14:39 +0800219}
220static inline void enable_dma(unsigned int channel)
221{
222 dma_ch[channel].regs->curr_x_count = 0;
223 dma_ch[channel].regs->curr_y_count = 0;
224 dma_ch[channel].regs->cfg |= DMAEN;
Mike Frysinger9c417a42009-01-07 23:14:39 +0800225}
Mike Frysinger9c417a42009-01-07 23:14:39 +0800226int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
227
228static inline void dma_disable_irq(unsigned int channel)
229{
230 disable_irq(dma_ch[channel].irq);
231}
Barry Song4ab069e2010-01-22 10:07:30 +0000232static inline void dma_disable_irq_nosync(unsigned int channel)
233{
234 disable_irq_nosync(dma_ch[channel].irq);
235}
Mike Frysinger9c417a42009-01-07 23:14:39 +0800236static inline void dma_enable_irq(unsigned int channel)
237{
238 enable_irq(dma_ch[channel].irq);
239}
240static inline void clear_dma_irqstat(unsigned int channel)
241{
242 dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
243}
244
Bryan Wu1394f032007-05-06 14:50:22 -0700245void *dma_memcpy(void *dest, const void *src, size_t count);
Michael Hennerichd1401e12010-06-16 09:12:10 +0000246void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
Bryan Wu1394f032007-05-06 14:50:22 -0700247void *safe_dma_memcpy(void *dest, const void *src, size_t count);
Mike Frysingerdd3dd382009-01-07 23:14:39 +0800248void blackfin_dma_early_init(void);
Robin Getzfecbd732009-04-23 20:49:43 +0000249void early_dma_memcpy(void *dest, const void *src, size_t count);
250void early_dma_memcpy_done(void);
Bryan Wu1394f032007-05-06 14:50:22 -0700251
Bryan Wu1394f032007-05-06 14:50:22 -0700252#endif