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Thomas Petazzonic7841472013-07-30 17:44:50 +02001/*
2 * Device Tree file for Marvell RD-AXPWiFiAP.
3 *
4 * Note: this board is shipped with a new generation boot loader that
5 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
Paul Bolle6cc082a2015-01-19 20:40:25 +01006 * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
7 * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
Thomas Petazzonic7841472013-07-30 17:44:50 +02008 *
9 * Copyright (C) 2013 Marvell
10 *
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 *
Gregory CLEMENTebb56672015-01-26 15:16:00 +010013 * This file is dual-licensed: you can use it either under the terms
14 * of the GPL or the X11 license, at your option. Note that this dual
15 * licensing only applies to this file, and not this project as a
16 * whole.
17 *
18 * a) This file is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of the
21 * License, or (at your option) any later version.
22 *
23 * This file is distributed in the hope that it will be useful
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * Or, alternatively
29 *
30 * b) Permission is hereby granted, free of charge, to any person
31 * obtaining a copy of this software and associated documentation
32 * files (the "Software"), to deal in the Software without
33 * restriction, including without limitation the rights to use
34 * copy, modify, merge, publish, distribute, sublicense, and/or
35 * sell copies of the Software, and to permit persons to whom the
36 * Software is furnished to do so, subject to the following
37 * conditions:
38 *
39 * The above copyright notice and this permission notice shall be
40 * included in all copies or substantial portions of the Software.
41 *
42 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
43 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
44 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
45 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
46 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
47 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
48 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
49 * OTHER DEALINGS IN THE SOFTWARE.
Thomas Petazzonic7841472013-07-30 17:44:50 +020050 */
51
52/dts-v1/;
Thomas Petazzoni29e74f82014-02-11 18:07:12 +010053#include <dt-bindings/gpio/gpio.h>
Thomas Petazzoni5c0169d2014-02-11 18:07:13 +010054#include <dt-bindings/input/input.h>
Ezequiel Garciad10ff4d2013-08-06 14:09:42 -030055#include "armada-xp-mv78230.dtsi"
Thomas Petazzonic7841472013-07-30 17:44:50 +020056
57/ {
58 model = "Marvell RD-AXPWiFiAP";
59 compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
60
61 chosen {
Thomas Petazzoni95522032015-03-03 15:41:02 +010062 stdout-path = "serial0:115200n8";
Thomas Petazzonic7841472013-07-30 17:44:50 +020063 };
64
65 memory {
66 device_type = "memory";
67 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
68 };
69
70 soc {
Ezequiel Garciad10ff4d2013-08-06 14:09:42 -030071 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
72 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
73
74 pcie-controller {
75 status = "okay";
76
77 /* First mini-PCIe port */
78 pcie@1,0 {
79 /* Port 0, Lane 0 */
80 status = "okay";
81 };
82
83 /* Second mini-PCIe port */
84 pcie@2,0 {
85 /* Port 0, Lane 1 */
86 status = "okay";
87 };
88
89 /* Renesas uPD720202 USB 3.0 controller */
90 pcie@3,0 {
91 /* Port 0, Lane 3 */
92 status = "okay";
93 };
94 };
Thomas Petazzonic7841472013-07-30 17:44:50 +020095
96 internal-regs {
Paul Bolle6cc082a2015-01-19 20:40:25 +010097 /* UART0 */
Thomas Petazzonic7841472013-07-30 17:44:50 +020098 serial@12000 {
Thomas Petazzonic7841472013-07-30 17:44:50 +020099 status = "okay";
100 };
101
Paul Bolle6cc082a2015-01-19 20:40:25 +0100102 /* UART1 */
Thomas Petazzonic7841472013-07-30 17:44:50 +0200103 serial@12100 {
Thomas Petazzonic7841472013-07-30 17:44:50 +0200104 status = "okay";
105 };
106
107 sata@a0000 {
108 nr-ports = <1>;
109 status = "okay";
110 };
111
112 mdio {
113 phy0: ethernet-phy@0 {
114 reg = <0>;
115 };
116
117 phy1: ethernet-phy@1 {
118 reg = <1>;
119 };
120 };
121
122 ethernet@70000 {
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100123 pinctrl-0 = <&ge0_rgmii_pins>;
Thomas Petazzonic7841472013-07-30 17:44:50 +0200124 pinctrl-names = "default";
125 status = "okay";
126 phy = <&phy0>;
127 phy-mode = "rgmii-id";
128 };
129 ethernet@74000 {
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100130 pinctrl-0 = <&ge1_rgmii_pins>;
Thomas Petazzonic7841472013-07-30 17:44:50 +0200131 pinctrl-names = "default";
132 status = "okay";
133 phy = <&phy1>;
134 phy-mode = "rgmii-id";
135 };
136
137 spi0: spi@10600 {
138 status = "okay";
Thomas Petazzonic7841472013-07-30 17:44:50 +0200139
140 spi-flash@0 {
141 #address-cells = <1>;
142 #size-cells = <1>;
Rafał Miłeckie9f3ed42015-05-19 13:30:46 +0200143 compatible = "n25q128a13", "jedec,spi-nor";
Thomas Petazzonic7841472013-07-30 17:44:50 +0200144 reg = <0>; /* Chip select 0 */
145 spi-max-frequency = <108000000>;
146 };
147 };
Thomas Petazzonic7841472013-07-30 17:44:50 +0200148 };
149 };
150
151 gpio_keys {
152 compatible = "gpio-keys";
153 #address-cells = <1>;
154 #size-cells = <0>;
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100155 pinctrl-0 = <&keys_pin>;
Thomas Petazzonic7841472013-07-30 17:44:50 +0200156 pinctrl-names = "default";
157
158 button@1 {
159 label = "Factory Reset Button";
Thomas Petazzoni5c0169d2014-02-11 18:07:13 +0100160 linux,code = <KEY_SETUP>;
Thomas Petazzoni29e74f82014-02-11 18:07:12 +0100161 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
Thomas Petazzonic7841472013-07-30 17:44:50 +0200162 };
163 };
164};
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200165
166&pinctrl {
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100167 pinctrl-0 = <&phy_int_pin>;
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200168 pinctrl-names = "default";
169
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100170 keys_pin: keys-pin {
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200171 marvell,pins = "mpp33";
172 marvell,function = "gpio";
173 };
174
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100175 phy_int_pin: phy-int-pin {
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200176 marvell,pins = "mpp32";
177 marvell,function = "gpio";
178 };
179};