Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1 | /* |
| 2 | * adv7842 - Analog Devices ADV7842 video decoder driver |
| 3 | * |
| 4 | * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you may redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 11 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 12 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 13 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 14 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 15 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 16 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 17 | * SOFTWARE. |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * References (c = chapter, p = page): |
Mats Randgaard | 5b64b20 | 2013-12-05 12:08:45 -0300 | [diff] [blame] | 23 | * REF_01 - Analog devices, ADV7842, |
| 24 | * Register Settings Recommendations, Rev. 1.9, April 2011 |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 25 | * REF_02 - Analog devices, Software User Guide, UG-206, |
| 26 | * ADV7842 I2C Register Maps, Rev. 0, November 2010 |
Mats Randgaard | 5b64b20 | 2013-12-05 12:08:45 -0300 | [diff] [blame] | 27 | * REF_03 - Analog devices, Hardware User Guide, UG-214, |
| 28 | * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb |
| 29 | * Decoder and Digitizer , Rev. 0, January 2011 |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 30 | */ |
| 31 | |
| 32 | |
| 33 | #include <linux/kernel.h> |
| 34 | #include <linux/module.h> |
| 35 | #include <linux/slab.h> |
| 36 | #include <linux/i2c.h> |
| 37 | #include <linux/delay.h> |
| 38 | #include <linux/videodev2.h> |
| 39 | #include <linux/workqueue.h> |
| 40 | #include <linux/v4l2-dv-timings.h> |
| 41 | #include <media/v4l2-device.h> |
| 42 | #include <media/v4l2-ctrls.h> |
| 43 | #include <media/v4l2-dv-timings.h> |
| 44 | #include <media/adv7842.h> |
| 45 | |
| 46 | static int debug; |
| 47 | module_param(debug, int, 0644); |
| 48 | MODULE_PARM_DESC(debug, "debug level (0-2)"); |
| 49 | |
| 50 | MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); |
| 51 | MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); |
| 52 | MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); |
| 53 | MODULE_LICENSE("GPL"); |
| 54 | |
| 55 | /* ADV7842 system clock frequency */ |
| 56 | #define ADV7842_fsc (28636360) |
| 57 | |
| 58 | /* |
| 59 | ********************************************************************** |
| 60 | * |
| 61 | * Arrays with configuration parameters for the ADV7842 |
| 62 | * |
| 63 | ********************************************************************** |
| 64 | */ |
| 65 | |
| 66 | struct adv7842_state { |
Martin Bugge | 7de5be4 | 2013-12-05 11:39:37 -0300 | [diff] [blame] | 67 | struct adv7842_platform_data pdata; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 68 | struct v4l2_subdev sd; |
| 69 | struct media_pad pad; |
| 70 | struct v4l2_ctrl_handler hdl; |
| 71 | enum adv7842_mode mode; |
| 72 | struct v4l2_dv_timings timings; |
| 73 | enum adv7842_vid_std_select vid_std_select; |
| 74 | v4l2_std_id norm; |
| 75 | struct { |
| 76 | u8 edid[256]; |
| 77 | u32 present; |
| 78 | } hdmi_edid; |
| 79 | struct { |
| 80 | u8 edid[256]; |
| 81 | u32 present; |
| 82 | } vga_edid; |
| 83 | struct v4l2_fract aspect_ratio; |
| 84 | u32 rgb_quantization_range; |
| 85 | bool is_cea_format; |
| 86 | struct workqueue_struct *work_queues; |
| 87 | struct delayed_work delayed_work_enable_hotplug; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 88 | bool hdmi_port_a; |
| 89 | |
| 90 | /* i2c clients */ |
| 91 | struct i2c_client *i2c_sdp_io; |
| 92 | struct i2c_client *i2c_sdp; |
| 93 | struct i2c_client *i2c_cp; |
| 94 | struct i2c_client *i2c_vdp; |
| 95 | struct i2c_client *i2c_afe; |
| 96 | struct i2c_client *i2c_hdmi; |
| 97 | struct i2c_client *i2c_repeater; |
| 98 | struct i2c_client *i2c_edid; |
| 99 | struct i2c_client *i2c_infoframe; |
| 100 | struct i2c_client *i2c_cec; |
| 101 | struct i2c_client *i2c_avlink; |
| 102 | |
| 103 | /* controls */ |
| 104 | struct v4l2_ctrl *detect_tx_5v_ctrl; |
| 105 | struct v4l2_ctrl *analog_sampling_phase_ctrl; |
| 106 | struct v4l2_ctrl *free_run_color_ctrl_manual; |
| 107 | struct v4l2_ctrl *free_run_color_ctrl; |
| 108 | struct v4l2_ctrl *rgb_quantization_range_ctrl; |
| 109 | }; |
| 110 | |
| 111 | /* Unsupported timings. This device cannot support 720p30. */ |
| 112 | static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { |
| 113 | V4L2_DV_BT_CEA_1280X720P30, |
| 114 | { } |
| 115 | }; |
| 116 | |
| 117 | static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) |
| 118 | { |
| 119 | int i; |
| 120 | |
| 121 | for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) |
| 122 | if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0)) |
| 123 | return false; |
| 124 | return true; |
| 125 | } |
| 126 | |
| 127 | struct adv7842_video_standards { |
| 128 | struct v4l2_dv_timings timings; |
| 129 | u8 vid_std; |
| 130 | u8 v_freq; |
| 131 | }; |
| 132 | |
| 133 | /* sorted by number of lines */ |
| 134 | static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { |
| 135 | /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ |
| 136 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, |
| 137 | { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, |
| 138 | { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, |
| 139 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, |
| 140 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, |
| 141 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, |
| 142 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, |
| 143 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, |
| 144 | /* TODO add 1920x1080P60_RB (CVT timing) */ |
| 145 | { }, |
| 146 | }; |
| 147 | |
| 148 | /* sorted by number of lines */ |
| 149 | static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { |
| 150 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, |
| 151 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, |
| 152 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, |
| 153 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, |
| 154 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, |
| 155 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, |
| 156 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, |
| 157 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, |
| 158 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, |
| 159 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, |
| 160 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, |
| 161 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, |
| 162 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, |
| 163 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, |
| 164 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, |
| 165 | { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, |
| 166 | { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, |
| 167 | { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, |
| 168 | { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, |
| 169 | { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ |
| 170 | /* TODO add 1600X1200P60_RB (not a DMT timing) */ |
| 171 | { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, |
| 172 | { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ |
| 173 | { }, |
| 174 | }; |
| 175 | |
| 176 | /* sorted by number of lines */ |
| 177 | static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { |
| 178 | { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, |
| 179 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, |
| 180 | { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, |
| 181 | { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, |
| 182 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, |
| 183 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, |
| 184 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, |
| 185 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, |
| 186 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, |
| 187 | { }, |
| 188 | }; |
| 189 | |
| 190 | /* sorted by number of lines */ |
| 191 | static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { |
| 192 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, |
| 193 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, |
| 194 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, |
| 195 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, |
| 196 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, |
| 197 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, |
| 198 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, |
| 199 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, |
| 200 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, |
| 201 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, |
| 202 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, |
| 203 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, |
| 204 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, |
| 205 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, |
| 206 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, |
| 207 | { }, |
| 208 | }; |
| 209 | |
| 210 | /* ----------------------------------------------------------------------- */ |
| 211 | |
| 212 | static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) |
| 213 | { |
| 214 | return container_of(sd, struct adv7842_state, sd); |
| 215 | } |
| 216 | |
| 217 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) |
| 218 | { |
| 219 | return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; |
| 220 | } |
| 221 | |
| 222 | static inline unsigned hblanking(const struct v4l2_bt_timings *t) |
| 223 | { |
| 224 | return V4L2_DV_BT_BLANKING_WIDTH(t); |
| 225 | } |
| 226 | |
| 227 | static inline unsigned htotal(const struct v4l2_bt_timings *t) |
| 228 | { |
| 229 | return V4L2_DV_BT_FRAME_WIDTH(t); |
| 230 | } |
| 231 | |
| 232 | static inline unsigned vblanking(const struct v4l2_bt_timings *t) |
| 233 | { |
| 234 | return V4L2_DV_BT_BLANKING_HEIGHT(t); |
| 235 | } |
| 236 | |
| 237 | static inline unsigned vtotal(const struct v4l2_bt_timings *t) |
| 238 | { |
| 239 | return V4L2_DV_BT_FRAME_HEIGHT(t); |
| 240 | } |
| 241 | |
| 242 | |
| 243 | /* ----------------------------------------------------------------------- */ |
| 244 | |
| 245 | static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, |
| 246 | u8 command, bool check) |
| 247 | { |
| 248 | union i2c_smbus_data data; |
| 249 | |
| 250 | if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, |
| 251 | I2C_SMBUS_READ, command, |
| 252 | I2C_SMBUS_BYTE_DATA, &data)) |
| 253 | return data.byte; |
| 254 | if (check) |
| 255 | v4l_err(client, "error reading %02x, %02x\n", |
| 256 | client->addr, command); |
| 257 | return -EIO; |
| 258 | } |
| 259 | |
| 260 | static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) |
| 261 | { |
| 262 | int i; |
| 263 | |
| 264 | for (i = 0; i < 3; i++) { |
| 265 | int ret = adv_smbus_read_byte_data_check(client, command, true); |
| 266 | |
| 267 | if (ret >= 0) { |
| 268 | if (i) |
| 269 | v4l_err(client, "read ok after %d retries\n", i); |
| 270 | return ret; |
| 271 | } |
| 272 | } |
| 273 | v4l_err(client, "read failed\n"); |
| 274 | return -EIO; |
| 275 | } |
| 276 | |
| 277 | static s32 adv_smbus_write_byte_data(struct i2c_client *client, |
| 278 | u8 command, u8 value) |
| 279 | { |
| 280 | union i2c_smbus_data data; |
| 281 | int err; |
| 282 | int i; |
| 283 | |
| 284 | data.byte = value; |
| 285 | for (i = 0; i < 3; i++) { |
| 286 | err = i2c_smbus_xfer(client->adapter, client->addr, |
| 287 | client->flags, |
| 288 | I2C_SMBUS_WRITE, command, |
| 289 | I2C_SMBUS_BYTE_DATA, &data); |
| 290 | if (!err) |
| 291 | break; |
| 292 | } |
| 293 | if (err < 0) |
| 294 | v4l_err(client, "error writing %02x, %02x, %02x\n", |
| 295 | client->addr, command, value); |
| 296 | return err; |
| 297 | } |
| 298 | |
| 299 | static void adv_smbus_write_byte_no_check(struct i2c_client *client, |
| 300 | u8 command, u8 value) |
| 301 | { |
| 302 | union i2c_smbus_data data; |
| 303 | data.byte = value; |
| 304 | |
| 305 | i2c_smbus_xfer(client->adapter, client->addr, |
| 306 | client->flags, |
| 307 | I2C_SMBUS_WRITE, command, |
| 308 | I2C_SMBUS_BYTE_DATA, &data); |
| 309 | } |
| 310 | |
| 311 | static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, |
| 312 | u8 command, unsigned length, const u8 *values) |
| 313 | { |
| 314 | union i2c_smbus_data data; |
| 315 | |
| 316 | if (length > I2C_SMBUS_BLOCK_MAX) |
| 317 | length = I2C_SMBUS_BLOCK_MAX; |
| 318 | data.block[0] = length; |
| 319 | memcpy(data.block + 1, values, length); |
| 320 | return i2c_smbus_xfer(client->adapter, client->addr, client->flags, |
| 321 | I2C_SMBUS_WRITE, command, |
| 322 | I2C_SMBUS_I2C_BLOCK_DATA, &data); |
| 323 | } |
| 324 | |
| 325 | /* ----------------------------------------------------------------------- */ |
| 326 | |
| 327 | static inline int io_read(struct v4l2_subdev *sd, u8 reg) |
| 328 | { |
| 329 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 330 | |
| 331 | return adv_smbus_read_byte_data(client, reg); |
| 332 | } |
| 333 | |
| 334 | static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 335 | { |
| 336 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 337 | |
| 338 | return adv_smbus_write_byte_data(client, reg, val); |
| 339 | } |
| 340 | |
| 341 | static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
| 342 | { |
| 343 | return io_write(sd, reg, (io_read(sd, reg) & mask) | val); |
| 344 | } |
| 345 | |
| 346 | static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) |
| 347 | { |
| 348 | struct adv7842_state *state = to_state(sd); |
| 349 | |
| 350 | return adv_smbus_read_byte_data(state->i2c_avlink, reg); |
| 351 | } |
| 352 | |
| 353 | static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 354 | { |
| 355 | struct adv7842_state *state = to_state(sd); |
| 356 | |
| 357 | return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); |
| 358 | } |
| 359 | |
| 360 | static inline int cec_read(struct v4l2_subdev *sd, u8 reg) |
| 361 | { |
| 362 | struct adv7842_state *state = to_state(sd); |
| 363 | |
| 364 | return adv_smbus_read_byte_data(state->i2c_cec, reg); |
| 365 | } |
| 366 | |
| 367 | static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 368 | { |
| 369 | struct adv7842_state *state = to_state(sd); |
| 370 | |
| 371 | return adv_smbus_write_byte_data(state->i2c_cec, reg, val); |
| 372 | } |
| 373 | |
| 374 | static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
| 375 | { |
| 376 | return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); |
| 377 | } |
| 378 | |
| 379 | static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) |
| 380 | { |
| 381 | struct adv7842_state *state = to_state(sd); |
| 382 | |
| 383 | return adv_smbus_read_byte_data(state->i2c_infoframe, reg); |
| 384 | } |
| 385 | |
| 386 | static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 387 | { |
| 388 | struct adv7842_state *state = to_state(sd); |
| 389 | |
| 390 | return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); |
| 391 | } |
| 392 | |
| 393 | static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) |
| 394 | { |
| 395 | struct adv7842_state *state = to_state(sd); |
| 396 | |
| 397 | return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); |
| 398 | } |
| 399 | |
| 400 | static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 401 | { |
| 402 | struct adv7842_state *state = to_state(sd); |
| 403 | |
| 404 | return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); |
| 405 | } |
| 406 | |
| 407 | static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
| 408 | { |
| 409 | return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); |
| 410 | } |
| 411 | |
| 412 | static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) |
| 413 | { |
| 414 | struct adv7842_state *state = to_state(sd); |
| 415 | |
| 416 | return adv_smbus_read_byte_data(state->i2c_sdp, reg); |
| 417 | } |
| 418 | |
| 419 | static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 420 | { |
| 421 | struct adv7842_state *state = to_state(sd); |
| 422 | |
| 423 | return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); |
| 424 | } |
| 425 | |
| 426 | static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
| 427 | { |
| 428 | return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); |
| 429 | } |
| 430 | |
| 431 | static inline int afe_read(struct v4l2_subdev *sd, u8 reg) |
| 432 | { |
| 433 | struct adv7842_state *state = to_state(sd); |
| 434 | |
| 435 | return adv_smbus_read_byte_data(state->i2c_afe, reg); |
| 436 | } |
| 437 | |
| 438 | static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 439 | { |
| 440 | struct adv7842_state *state = to_state(sd); |
| 441 | |
| 442 | return adv_smbus_write_byte_data(state->i2c_afe, reg, val); |
| 443 | } |
| 444 | |
| 445 | static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
| 446 | { |
| 447 | return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); |
| 448 | } |
| 449 | |
| 450 | static inline int rep_read(struct v4l2_subdev *sd, u8 reg) |
| 451 | { |
| 452 | struct adv7842_state *state = to_state(sd); |
| 453 | |
| 454 | return adv_smbus_read_byte_data(state->i2c_repeater, reg); |
| 455 | } |
| 456 | |
| 457 | static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 458 | { |
| 459 | struct adv7842_state *state = to_state(sd); |
| 460 | |
| 461 | return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); |
| 462 | } |
| 463 | |
| 464 | static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
| 465 | { |
| 466 | return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); |
| 467 | } |
| 468 | |
| 469 | static inline int edid_read(struct v4l2_subdev *sd, u8 reg) |
| 470 | { |
| 471 | struct adv7842_state *state = to_state(sd); |
| 472 | |
| 473 | return adv_smbus_read_byte_data(state->i2c_edid, reg); |
| 474 | } |
| 475 | |
| 476 | static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 477 | { |
| 478 | struct adv7842_state *state = to_state(sd); |
| 479 | |
| 480 | return adv_smbus_write_byte_data(state->i2c_edid, reg, val); |
| 481 | } |
| 482 | |
| 483 | static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) |
| 484 | { |
| 485 | struct adv7842_state *state = to_state(sd); |
| 486 | |
| 487 | return adv_smbus_read_byte_data(state->i2c_hdmi, reg); |
| 488 | } |
| 489 | |
| 490 | static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 491 | { |
| 492 | struct adv7842_state *state = to_state(sd); |
| 493 | |
| 494 | return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); |
| 495 | } |
| 496 | |
Mats Randgaard | 5b64b20 | 2013-12-05 12:08:45 -0300 | [diff] [blame] | 497 | static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
| 498 | { |
| 499 | return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); |
| 500 | } |
| 501 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 502 | static inline int cp_read(struct v4l2_subdev *sd, u8 reg) |
| 503 | { |
| 504 | struct adv7842_state *state = to_state(sd); |
| 505 | |
| 506 | return adv_smbus_read_byte_data(state->i2c_cp, reg); |
| 507 | } |
| 508 | |
| 509 | static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 510 | { |
| 511 | struct adv7842_state *state = to_state(sd); |
| 512 | |
| 513 | return adv_smbus_write_byte_data(state->i2c_cp, reg, val); |
| 514 | } |
| 515 | |
| 516 | static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
| 517 | { |
| 518 | return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); |
| 519 | } |
| 520 | |
| 521 | static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) |
| 522 | { |
| 523 | struct adv7842_state *state = to_state(sd); |
| 524 | |
| 525 | return adv_smbus_read_byte_data(state->i2c_vdp, reg); |
| 526 | } |
| 527 | |
| 528 | static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
| 529 | { |
| 530 | struct adv7842_state *state = to_state(sd); |
| 531 | |
| 532 | return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); |
| 533 | } |
| 534 | |
| 535 | static void main_reset(struct v4l2_subdev *sd) |
| 536 | { |
| 537 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 538 | |
| 539 | v4l2_dbg(1, debug, sd, "%s:\n", __func__); |
| 540 | |
| 541 | adv_smbus_write_byte_no_check(client, 0xff, 0x80); |
| 542 | |
Martin Bugge | 84aeed5 | 2013-12-05 11:56:32 -0300 | [diff] [blame] | 543 | mdelay(5); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 544 | } |
| 545 | |
| 546 | /* ----------------------------------------------------------------------- */ |
| 547 | |
| 548 | static inline bool is_digital_input(struct v4l2_subdev *sd) |
| 549 | { |
| 550 | struct adv7842_state *state = to_state(sd); |
| 551 | |
| 552 | return state->mode == ADV7842_MODE_HDMI; |
| 553 | } |
| 554 | |
| 555 | static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { |
| 556 | .type = V4L2_DV_BT_656_1120, |
Gianluca Gennari | 9b51f17 | 2013-08-30 08:29:22 -0300 | [diff] [blame] | 557 | /* keep this initialization for compatibility with GCC < 4.4.6 */ |
| 558 | .reserved = { 0 }, |
| 559 | V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, |
| 560 | V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 561 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, |
Gianluca Gennari | 9b51f17 | 2013-08-30 08:29:22 -0300 | [diff] [blame] | 562 | V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | |
| 563 | V4L2_DV_BT_CAP_CUSTOM) |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 564 | }; |
| 565 | |
| 566 | static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { |
| 567 | .type = V4L2_DV_BT_656_1120, |
Gianluca Gennari | 9b51f17 | 2013-08-30 08:29:22 -0300 | [diff] [blame] | 568 | /* keep this initialization for compatibility with GCC < 4.4.6 */ |
| 569 | .reserved = { 0 }, |
| 570 | V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, |
| 571 | V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 572 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, |
Gianluca Gennari | 9b51f17 | 2013-08-30 08:29:22 -0300 | [diff] [blame] | 573 | V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | |
| 574 | V4L2_DV_BT_CAP_CUSTOM) |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 575 | }; |
| 576 | |
| 577 | static inline const struct v4l2_dv_timings_cap * |
| 578 | adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) |
| 579 | { |
| 580 | return is_digital_input(sd) ? &adv7842_timings_cap_digital : |
| 581 | &adv7842_timings_cap_analog; |
| 582 | } |
| 583 | |
| 584 | /* ----------------------------------------------------------------------- */ |
| 585 | |
| 586 | static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) |
| 587 | { |
| 588 | struct delayed_work *dwork = to_delayed_work(work); |
| 589 | struct adv7842_state *state = container_of(dwork, |
| 590 | struct adv7842_state, delayed_work_enable_hotplug); |
| 591 | struct v4l2_subdev *sd = &state->sd; |
| 592 | int present = state->hdmi_edid.present; |
| 593 | u8 mask = 0; |
| 594 | |
| 595 | v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", |
| 596 | __func__, present); |
| 597 | |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 598 | if (present & (0x04 << ADV7842_EDID_PORT_A)) |
| 599 | mask |= 0x20; |
| 600 | if (present & (0x04 << ADV7842_EDID_PORT_B)) |
| 601 | mask |= 0x10; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 602 | io_write_and_or(sd, 0x20, 0xcf, mask); |
| 603 | } |
| 604 | |
| 605 | static int edid_write_vga_segment(struct v4l2_subdev *sd) |
| 606 | { |
| 607 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 608 | struct adv7842_state *state = to_state(sd); |
| 609 | const u8 *val = state->vga_edid.edid; |
| 610 | int err = 0; |
| 611 | int i; |
| 612 | |
| 613 | v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); |
| 614 | |
| 615 | /* HPA disable on port A and B */ |
| 616 | io_write_and_or(sd, 0x20, 0xcf, 0x00); |
| 617 | |
| 618 | /* Disable I2C access to internal EDID ram from VGA DDC port */ |
| 619 | rep_write_and_or(sd, 0x7f, 0x7f, 0x00); |
| 620 | |
| 621 | /* edid segment pointer '1' for VGA port */ |
| 622 | rep_write_and_or(sd, 0x77, 0xef, 0x10); |
| 623 | |
| 624 | for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) |
| 625 | err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, |
| 626 | I2C_SMBUS_BLOCK_MAX, val + i); |
| 627 | if (err) |
| 628 | return err; |
| 629 | |
| 630 | /* Calculates the checksums and enables I2C access |
| 631 | * to internal EDID ram from VGA DDC port. |
| 632 | */ |
| 633 | rep_write_and_or(sd, 0x7f, 0x7f, 0x80); |
| 634 | |
| 635 | for (i = 0; i < 1000; i++) { |
| 636 | if (rep_read(sd, 0x79) & 0x20) |
| 637 | break; |
| 638 | mdelay(1); |
| 639 | } |
| 640 | if (i == 1000) { |
| 641 | v4l_err(client, "error enabling edid on VGA port\n"); |
| 642 | return -EIO; |
| 643 | } |
| 644 | |
| 645 | /* enable hotplug after 200 ms */ |
| 646 | queue_delayed_work(state->work_queues, |
| 647 | &state->delayed_work_enable_hotplug, HZ / 5); |
| 648 | |
| 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | static int edid_spa_location(const u8 *edid) |
| 653 | { |
| 654 | u8 d; |
| 655 | |
| 656 | /* |
| 657 | * TODO, improve and update for other CEA extensions |
| 658 | * currently only for 1 segment (256 bytes), |
| 659 | * i.e. 1 extension block and CEA revision 3. |
| 660 | */ |
| 661 | if ((edid[0x7e] != 1) || |
| 662 | (edid[0x80] != 0x02) || |
| 663 | (edid[0x81] != 0x03)) { |
| 664 | return -EINVAL; |
| 665 | } |
| 666 | /* |
| 667 | * search Vendor Specific Data Block (tag 3) |
| 668 | */ |
| 669 | d = edid[0x82] & 0x7f; |
| 670 | if (d > 4) { |
| 671 | int i = 0x84; |
| 672 | int end = 0x80 + d; |
| 673 | do { |
| 674 | u8 tag = edid[i]>>5; |
| 675 | u8 len = edid[i] & 0x1f; |
| 676 | |
| 677 | if ((tag == 3) && (len >= 5)) |
| 678 | return i + 4; |
| 679 | i += len + 1; |
| 680 | } while (i < end); |
| 681 | } |
| 682 | return -EINVAL; |
| 683 | } |
| 684 | |
| 685 | static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) |
| 686 | { |
| 687 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 688 | struct adv7842_state *state = to_state(sd); |
| 689 | const u8 *val = state->hdmi_edid.edid; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 690 | int spa_loc = edid_spa_location(val); |
| 691 | int err = 0; |
| 692 | int i; |
| 693 | |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 694 | v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n", |
| 695 | __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 696 | |
| 697 | /* HPA disable on port A and B */ |
| 698 | io_write_and_or(sd, 0x20, 0xcf, 0x00); |
| 699 | |
| 700 | /* Disable I2C access to internal EDID ram from HDMI DDC ports */ |
| 701 | rep_write_and_or(sd, 0x77, 0xf3, 0x00); |
| 702 | |
Martin Bugge | fc2e991 | 2013-12-05 12:09:51 -0300 | [diff] [blame^] | 703 | if (!state->hdmi_edid.present) |
| 704 | return 0; |
| 705 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 706 | /* edid segment pointer '0' for HDMI ports */ |
| 707 | rep_write_and_or(sd, 0x77, 0xef, 0x00); |
| 708 | |
| 709 | for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) |
| 710 | err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, |
| 711 | I2C_SMBUS_BLOCK_MAX, val + i); |
| 712 | if (err) |
| 713 | return err; |
| 714 | |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 715 | if (spa_loc < 0) |
| 716 | spa_loc = 0xc0; /* Default value [REF_02, p. 199] */ |
| 717 | |
| 718 | if (port == ADV7842_EDID_PORT_A) { |
| 719 | rep_write(sd, 0x72, val[spa_loc]); |
| 720 | rep_write(sd, 0x73, val[spa_loc + 1]); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 721 | } else { |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 722 | rep_write(sd, 0x74, val[spa_loc]); |
| 723 | rep_write(sd, 0x75, val[spa_loc + 1]); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 724 | } |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 725 | rep_write(sd, 0x76, spa_loc & 0xff); |
| 726 | rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 727 | |
| 728 | /* Calculates the checksums and enables I2C access to internal |
| 729 | * EDID ram from HDMI DDC ports |
| 730 | */ |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 731 | rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 732 | |
| 733 | for (i = 0; i < 1000; i++) { |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 734 | if (rep_read(sd, 0x7d) & state->hdmi_edid.present) |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 735 | break; |
| 736 | mdelay(1); |
| 737 | } |
| 738 | if (i == 1000) { |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 739 | v4l_err(client, "error enabling edid on port %c\n", |
| 740 | (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 741 | return -EIO; |
| 742 | } |
| 743 | |
| 744 | /* enable hotplug after 200 ms */ |
| 745 | queue_delayed_work(state->work_queues, |
| 746 | &state->delayed_work_enable_hotplug, HZ / 5); |
| 747 | |
| 748 | return 0; |
| 749 | } |
| 750 | |
| 751 | /* ----------------------------------------------------------------------- */ |
| 752 | |
| 753 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 754 | static void adv7842_inv_register(struct v4l2_subdev *sd) |
| 755 | { |
| 756 | v4l2_info(sd, "0x000-0x0ff: IO Map\n"); |
| 757 | v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); |
| 758 | v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); |
| 759 | v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); |
| 760 | v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); |
| 761 | v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); |
| 762 | v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); |
| 763 | v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); |
| 764 | v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); |
| 765 | v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); |
| 766 | v4l2_info(sd, "0xa00-0xaff: CP Map\n"); |
| 767 | v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); |
| 768 | } |
| 769 | |
| 770 | static int adv7842_g_register(struct v4l2_subdev *sd, |
| 771 | struct v4l2_dbg_register *reg) |
| 772 | { |
| 773 | reg->size = 1; |
| 774 | switch (reg->reg >> 8) { |
| 775 | case 0: |
| 776 | reg->val = io_read(sd, reg->reg & 0xff); |
| 777 | break; |
| 778 | case 1: |
| 779 | reg->val = avlink_read(sd, reg->reg & 0xff); |
| 780 | break; |
| 781 | case 2: |
| 782 | reg->val = cec_read(sd, reg->reg & 0xff); |
| 783 | break; |
| 784 | case 3: |
| 785 | reg->val = infoframe_read(sd, reg->reg & 0xff); |
| 786 | break; |
| 787 | case 4: |
| 788 | reg->val = sdp_io_read(sd, reg->reg & 0xff); |
| 789 | break; |
| 790 | case 5: |
| 791 | reg->val = sdp_read(sd, reg->reg & 0xff); |
| 792 | break; |
| 793 | case 6: |
| 794 | reg->val = afe_read(sd, reg->reg & 0xff); |
| 795 | break; |
| 796 | case 7: |
| 797 | reg->val = rep_read(sd, reg->reg & 0xff); |
| 798 | break; |
| 799 | case 8: |
| 800 | reg->val = edid_read(sd, reg->reg & 0xff); |
| 801 | break; |
| 802 | case 9: |
| 803 | reg->val = hdmi_read(sd, reg->reg & 0xff); |
| 804 | break; |
| 805 | case 0xa: |
| 806 | reg->val = cp_read(sd, reg->reg & 0xff); |
| 807 | break; |
| 808 | case 0xb: |
| 809 | reg->val = vdp_read(sd, reg->reg & 0xff); |
| 810 | break; |
| 811 | default: |
| 812 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
| 813 | adv7842_inv_register(sd); |
| 814 | break; |
| 815 | } |
| 816 | return 0; |
| 817 | } |
| 818 | |
| 819 | static int adv7842_s_register(struct v4l2_subdev *sd, |
| 820 | const struct v4l2_dbg_register *reg) |
| 821 | { |
| 822 | u8 val = reg->val & 0xff; |
| 823 | |
| 824 | switch (reg->reg >> 8) { |
| 825 | case 0: |
| 826 | io_write(sd, reg->reg & 0xff, val); |
| 827 | break; |
| 828 | case 1: |
| 829 | avlink_write(sd, reg->reg & 0xff, val); |
| 830 | break; |
| 831 | case 2: |
| 832 | cec_write(sd, reg->reg & 0xff, val); |
| 833 | break; |
| 834 | case 3: |
| 835 | infoframe_write(sd, reg->reg & 0xff, val); |
| 836 | break; |
| 837 | case 4: |
| 838 | sdp_io_write(sd, reg->reg & 0xff, val); |
| 839 | break; |
| 840 | case 5: |
| 841 | sdp_write(sd, reg->reg & 0xff, val); |
| 842 | break; |
| 843 | case 6: |
| 844 | afe_write(sd, reg->reg & 0xff, val); |
| 845 | break; |
| 846 | case 7: |
| 847 | rep_write(sd, reg->reg & 0xff, val); |
| 848 | break; |
| 849 | case 8: |
| 850 | edid_write(sd, reg->reg & 0xff, val); |
| 851 | break; |
| 852 | case 9: |
| 853 | hdmi_write(sd, reg->reg & 0xff, val); |
| 854 | break; |
| 855 | case 0xa: |
| 856 | cp_write(sd, reg->reg & 0xff, val); |
| 857 | break; |
| 858 | case 0xb: |
| 859 | vdp_write(sd, reg->reg & 0xff, val); |
| 860 | break; |
| 861 | default: |
| 862 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
| 863 | adv7842_inv_register(sd); |
| 864 | break; |
| 865 | } |
| 866 | return 0; |
| 867 | } |
| 868 | #endif |
| 869 | |
| 870 | static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) |
| 871 | { |
| 872 | struct adv7842_state *state = to_state(sd); |
| 873 | int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl); |
| 874 | u8 reg_io_6f = io_read(sd, 0x6f); |
| 875 | int val = 0; |
| 876 | |
| 877 | if (reg_io_6f & 0x02) |
| 878 | val |= 1; /* port A */ |
| 879 | if (reg_io_6f & 0x01) |
| 880 | val |= 2; /* port B */ |
| 881 | |
| 882 | v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val); |
| 883 | |
| 884 | if (val != prev) |
| 885 | return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val); |
| 886 | return 0; |
| 887 | } |
| 888 | |
| 889 | static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, |
| 890 | u8 prim_mode, |
| 891 | const struct adv7842_video_standards *predef_vid_timings, |
| 892 | const struct v4l2_dv_timings *timings) |
| 893 | { |
| 894 | int i; |
| 895 | |
| 896 | for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { |
| 897 | if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, |
| 898 | is_digital_input(sd) ? 250000 : 1000000)) |
| 899 | continue; |
| 900 | /* video std */ |
| 901 | io_write(sd, 0x00, predef_vid_timings[i].vid_std); |
| 902 | /* v_freq and prim mode */ |
| 903 | io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); |
| 904 | return 0; |
| 905 | } |
| 906 | |
| 907 | return -1; |
| 908 | } |
| 909 | |
| 910 | static int configure_predefined_video_timings(struct v4l2_subdev *sd, |
| 911 | struct v4l2_dv_timings *timings) |
| 912 | { |
| 913 | struct adv7842_state *state = to_state(sd); |
| 914 | int err; |
| 915 | |
| 916 | v4l2_dbg(1, debug, sd, "%s\n", __func__); |
| 917 | |
| 918 | /* reset to default values */ |
| 919 | io_write(sd, 0x16, 0x43); |
| 920 | io_write(sd, 0x17, 0x5a); |
| 921 | /* disable embedded syncs for auto graphics mode */ |
| 922 | cp_write_and_or(sd, 0x81, 0xef, 0x00); |
| 923 | cp_write(sd, 0x26, 0x00); |
| 924 | cp_write(sd, 0x27, 0x00); |
| 925 | cp_write(sd, 0x28, 0x00); |
| 926 | cp_write(sd, 0x29, 0x00); |
Martin Bugge | 6251e65 | 2013-12-10 11:01:00 -0300 | [diff] [blame] | 927 | cp_write(sd, 0x8f, 0x40); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 928 | cp_write(sd, 0x90, 0x00); |
| 929 | cp_write(sd, 0xa5, 0x00); |
| 930 | cp_write(sd, 0xa6, 0x00); |
| 931 | cp_write(sd, 0xa7, 0x00); |
| 932 | cp_write(sd, 0xab, 0x00); |
| 933 | cp_write(sd, 0xac, 0x00); |
| 934 | |
| 935 | switch (state->mode) { |
| 936 | case ADV7842_MODE_COMP: |
| 937 | case ADV7842_MODE_RGB: |
| 938 | err = find_and_set_predefined_video_timings(sd, |
| 939 | 0x01, adv7842_prim_mode_comp, timings); |
| 940 | if (err) |
| 941 | err = find_and_set_predefined_video_timings(sd, |
| 942 | 0x02, adv7842_prim_mode_gr, timings); |
| 943 | break; |
| 944 | case ADV7842_MODE_HDMI: |
| 945 | err = find_and_set_predefined_video_timings(sd, |
| 946 | 0x05, adv7842_prim_mode_hdmi_comp, timings); |
| 947 | if (err) |
| 948 | err = find_and_set_predefined_video_timings(sd, |
| 949 | 0x06, adv7842_prim_mode_hdmi_gr, timings); |
| 950 | break; |
| 951 | default: |
| 952 | v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", |
| 953 | __func__, state->mode); |
| 954 | err = -1; |
| 955 | break; |
| 956 | } |
| 957 | |
| 958 | |
| 959 | return err; |
| 960 | } |
| 961 | |
| 962 | static void configure_custom_video_timings(struct v4l2_subdev *sd, |
| 963 | const struct v4l2_bt_timings *bt) |
| 964 | { |
| 965 | struct adv7842_state *state = to_state(sd); |
| 966 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 967 | u32 width = htotal(bt); |
| 968 | u32 height = vtotal(bt); |
| 969 | u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; |
| 970 | u16 cp_start_eav = width - bt->hfrontporch; |
| 971 | u16 cp_start_vbi = height - bt->vfrontporch + 1; |
| 972 | u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; |
| 973 | u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? |
| 974 | ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; |
| 975 | const u8 pll[2] = { |
| 976 | 0xc0 | ((width >> 8) & 0x1f), |
| 977 | width & 0xff |
| 978 | }; |
| 979 | |
| 980 | v4l2_dbg(2, debug, sd, "%s\n", __func__); |
| 981 | |
| 982 | switch (state->mode) { |
| 983 | case ADV7842_MODE_COMP: |
| 984 | case ADV7842_MODE_RGB: |
| 985 | /* auto graphics */ |
| 986 | io_write(sd, 0x00, 0x07); /* video std */ |
| 987 | io_write(sd, 0x01, 0x02); /* prim mode */ |
| 988 | /* enable embedded syncs for auto graphics mode */ |
| 989 | cp_write_and_or(sd, 0x81, 0xef, 0x10); |
| 990 | |
| 991 | /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ |
| 992 | /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ |
| 993 | /* IO-map reg. 0x16 and 0x17 should be written in sequence */ |
| 994 | if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { |
| 995 | v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); |
| 996 | break; |
| 997 | } |
| 998 | |
| 999 | /* active video - horizontal timing */ |
| 1000 | cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); |
| 1001 | cp_write(sd, 0x27, (cp_start_sav & 0xff)); |
| 1002 | cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); |
| 1003 | cp_write(sd, 0x29, (cp_start_eav & 0xff)); |
| 1004 | |
| 1005 | /* active video - vertical timing */ |
| 1006 | cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); |
| 1007 | cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | |
| 1008 | ((cp_end_vbi >> 8) & 0xf)); |
| 1009 | cp_write(sd, 0xa7, cp_end_vbi & 0xff); |
| 1010 | break; |
| 1011 | case ADV7842_MODE_HDMI: |
| 1012 | /* set default prim_mode/vid_std for HDMI |
Jonathan McCrohan | 39c1cb2 | 2013-10-20 21:34:01 -0300 | [diff] [blame] | 1013 | according to [REF_03, c. 4.2] */ |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1014 | io_write(sd, 0x00, 0x02); /* video std */ |
| 1015 | io_write(sd, 0x01, 0x06); /* prim mode */ |
| 1016 | break; |
| 1017 | default: |
| 1018 | v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", |
| 1019 | __func__, state->mode); |
| 1020 | break; |
| 1021 | } |
| 1022 | |
| 1023 | cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); |
| 1024 | cp_write(sd, 0x90, ch1_fr_ll & 0xff); |
| 1025 | cp_write(sd, 0xab, (height >> 4) & 0xff); |
| 1026 | cp_write(sd, 0xac, (height & 0x0f) << 4); |
| 1027 | } |
| 1028 | |
| 1029 | static void set_rgb_quantization_range(struct v4l2_subdev *sd) |
| 1030 | { |
| 1031 | struct adv7842_state *state = to_state(sd); |
| 1032 | |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1033 | v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n", |
| 1034 | __func__, state->rgb_quantization_range); |
| 1035 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1036 | switch (state->rgb_quantization_range) { |
| 1037 | case V4L2_DV_RGB_RANGE_AUTO: |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1038 | if (state->mode == ADV7842_MODE_RGB) { |
| 1039 | /* Receiving analog RGB signal |
| 1040 | * Set RGB full range (0-255) */ |
| 1041 | io_write_and_or(sd, 0x02, 0x0f, 0x10); |
| 1042 | break; |
| 1043 | } |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1044 | |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1045 | if (state->mode == ADV7842_MODE_COMP) { |
| 1046 | /* Receiving analog YPbPr signal |
| 1047 | * Set automode */ |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1048 | io_write_and_or(sd, 0x02, 0x0f, 0xf0); |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1049 | break; |
| 1050 | } |
| 1051 | |
| 1052 | if (hdmi_read(sd, 0x05) & 0x80) { |
| 1053 | /* Receiving HDMI signal |
| 1054 | * Set automode */ |
| 1055 | io_write_and_or(sd, 0x02, 0x0f, 0xf0); |
| 1056 | break; |
| 1057 | } |
| 1058 | |
| 1059 | /* Receiving DVI-D signal |
| 1060 | * ADV7842 selects RGB limited range regardless of |
| 1061 | * input format (CE/IT) in automatic mode */ |
| 1062 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { |
| 1063 | /* RGB limited range (16-235) */ |
| 1064 | io_write_and_or(sd, 0x02, 0x0f, 0x00); |
| 1065 | } else { |
| 1066 | /* RGB full range (0-255) */ |
| 1067 | io_write_and_or(sd, 0x02, 0x0f, 0x10); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1068 | } |
| 1069 | break; |
| 1070 | case V4L2_DV_RGB_RANGE_LIMITED: |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1071 | if (state->mode == ADV7842_MODE_COMP) { |
| 1072 | /* YCrCb limited range (16-235) */ |
| 1073 | io_write_and_or(sd, 0x02, 0x0f, 0x20); |
| 1074 | } else { |
| 1075 | /* RGB limited range (16-235) */ |
| 1076 | io_write_and_or(sd, 0x02, 0x0f, 0x00); |
| 1077 | } |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1078 | break; |
| 1079 | case V4L2_DV_RGB_RANGE_FULL: |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1080 | if (state->mode == ADV7842_MODE_COMP) { |
| 1081 | /* YCrCb full range (0-255) */ |
| 1082 | io_write_and_or(sd, 0x02, 0x0f, 0x60); |
| 1083 | } else { |
| 1084 | /* RGB full range (0-255) */ |
| 1085 | io_write_and_or(sd, 0x02, 0x0f, 0x10); |
| 1086 | } |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1087 | break; |
| 1088 | } |
| 1089 | } |
| 1090 | |
| 1091 | static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) |
| 1092 | { |
| 1093 | struct v4l2_subdev *sd = to_sd(ctrl); |
| 1094 | struct adv7842_state *state = to_state(sd); |
| 1095 | |
| 1096 | /* TODO SDP ctrls |
| 1097 | contrast/brightness/hue/free run is acting a bit strange, |
| 1098 | not sure if sdp csc is correct. |
| 1099 | */ |
| 1100 | switch (ctrl->id) { |
| 1101 | /* standard ctrls */ |
| 1102 | case V4L2_CID_BRIGHTNESS: |
| 1103 | cp_write(sd, 0x3c, ctrl->val); |
| 1104 | sdp_write(sd, 0x14, ctrl->val); |
| 1105 | /* ignore lsb sdp 0x17[3:2] */ |
| 1106 | return 0; |
| 1107 | case V4L2_CID_CONTRAST: |
| 1108 | cp_write(sd, 0x3a, ctrl->val); |
| 1109 | sdp_write(sd, 0x13, ctrl->val); |
| 1110 | /* ignore lsb sdp 0x17[1:0] */ |
| 1111 | return 0; |
| 1112 | case V4L2_CID_SATURATION: |
| 1113 | cp_write(sd, 0x3b, ctrl->val); |
| 1114 | sdp_write(sd, 0x15, ctrl->val); |
| 1115 | /* ignore lsb sdp 0x17[5:4] */ |
| 1116 | return 0; |
| 1117 | case V4L2_CID_HUE: |
| 1118 | cp_write(sd, 0x3d, ctrl->val); |
| 1119 | sdp_write(sd, 0x16, ctrl->val); |
| 1120 | /* ignore lsb sdp 0x17[7:6] */ |
| 1121 | return 0; |
| 1122 | /* custom ctrls */ |
| 1123 | case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: |
| 1124 | afe_write(sd, 0xc8, ctrl->val); |
| 1125 | return 0; |
| 1126 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: |
| 1127 | cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); |
| 1128 | sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); |
| 1129 | return 0; |
| 1130 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { |
| 1131 | u8 R = (ctrl->val & 0xff0000) >> 16; |
| 1132 | u8 G = (ctrl->val & 0x00ff00) >> 8; |
| 1133 | u8 B = (ctrl->val & 0x0000ff); |
| 1134 | /* RGB -> YUV, numerical approximation */ |
| 1135 | int Y = 66 * R + 129 * G + 25 * B; |
| 1136 | int U = -38 * R - 74 * G + 112 * B; |
| 1137 | int V = 112 * R - 94 * G - 18 * B; |
| 1138 | |
| 1139 | /* Scale down to 8 bits with rounding */ |
| 1140 | Y = (Y + 128) >> 8; |
| 1141 | U = (U + 128) >> 8; |
| 1142 | V = (V + 128) >> 8; |
| 1143 | /* make U,V positive */ |
| 1144 | Y += 16; |
| 1145 | U += 128; |
| 1146 | V += 128; |
| 1147 | |
| 1148 | v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); |
| 1149 | v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); |
| 1150 | |
| 1151 | /* CP */ |
| 1152 | cp_write(sd, 0xc1, R); |
| 1153 | cp_write(sd, 0xc0, G); |
| 1154 | cp_write(sd, 0xc2, B); |
| 1155 | /* SDP */ |
| 1156 | sdp_write(sd, 0xde, Y); |
| 1157 | sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); |
| 1158 | return 0; |
| 1159 | } |
| 1160 | case V4L2_CID_DV_RX_RGB_RANGE: |
| 1161 | state->rgb_quantization_range = ctrl->val; |
| 1162 | set_rgb_quantization_range(sd); |
| 1163 | return 0; |
| 1164 | } |
| 1165 | return -EINVAL; |
| 1166 | } |
| 1167 | |
| 1168 | static inline bool no_power(struct v4l2_subdev *sd) |
| 1169 | { |
| 1170 | return io_read(sd, 0x0c) & 0x24; |
| 1171 | } |
| 1172 | |
| 1173 | static inline bool no_cp_signal(struct v4l2_subdev *sd) |
| 1174 | { |
| 1175 | return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); |
| 1176 | } |
| 1177 | |
| 1178 | static inline bool is_hdmi(struct v4l2_subdev *sd) |
| 1179 | { |
| 1180 | return hdmi_read(sd, 0x05) & 0x80; |
| 1181 | } |
| 1182 | |
| 1183 | static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) |
| 1184 | { |
| 1185 | struct adv7842_state *state = to_state(sd); |
| 1186 | |
| 1187 | *status = 0; |
| 1188 | |
| 1189 | if (io_read(sd, 0x0c) & 0x24) |
| 1190 | *status |= V4L2_IN_ST_NO_POWER; |
| 1191 | |
| 1192 | if (state->mode == ADV7842_MODE_SDP) { |
| 1193 | /* status from SDP block */ |
| 1194 | if (!(sdp_read(sd, 0x5A) & 0x01)) |
| 1195 | *status |= V4L2_IN_ST_NO_SIGNAL; |
| 1196 | |
| 1197 | v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", |
| 1198 | __func__, *status); |
| 1199 | return 0; |
| 1200 | } |
| 1201 | /* status from CP block */ |
| 1202 | if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || |
| 1203 | !(cp_read(sd, 0xb1) & 0x80)) |
| 1204 | /* TODO channel 2 */ |
| 1205 | *status |= V4L2_IN_ST_NO_SIGNAL; |
| 1206 | |
| 1207 | if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) |
| 1208 | *status |= V4L2_IN_ST_NO_SIGNAL; |
| 1209 | |
| 1210 | v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", |
| 1211 | __func__, *status); |
| 1212 | |
| 1213 | return 0; |
| 1214 | } |
| 1215 | |
| 1216 | struct stdi_readback { |
| 1217 | u16 bl, lcf, lcvs; |
| 1218 | u8 hs_pol, vs_pol; |
| 1219 | bool interlaced; |
| 1220 | }; |
| 1221 | |
| 1222 | static int stdi2dv_timings(struct v4l2_subdev *sd, |
| 1223 | struct stdi_readback *stdi, |
| 1224 | struct v4l2_dv_timings *timings) |
| 1225 | { |
| 1226 | struct adv7842_state *state = to_state(sd); |
| 1227 | u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; |
| 1228 | u32 pix_clk; |
| 1229 | int i; |
| 1230 | |
| 1231 | for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { |
| 1232 | const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; |
| 1233 | |
| 1234 | if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], |
| 1235 | adv7842_get_dv_timings_cap(sd), |
| 1236 | adv7842_check_dv_timings, NULL)) |
| 1237 | continue; |
| 1238 | if (vtotal(bt) != stdi->lcf + 1) |
| 1239 | continue; |
| 1240 | if (bt->vsync != stdi->lcvs) |
| 1241 | continue; |
| 1242 | |
| 1243 | pix_clk = hfreq * htotal(bt); |
| 1244 | |
| 1245 | if ((pix_clk < bt->pixelclock + 1000000) && |
| 1246 | (pix_clk > bt->pixelclock - 1000000)) { |
| 1247 | *timings = v4l2_dv_timings_presets[i]; |
| 1248 | return 0; |
| 1249 | } |
| 1250 | } |
| 1251 | |
| 1252 | if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, |
| 1253 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | |
| 1254 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), |
| 1255 | timings)) |
| 1256 | return 0; |
| 1257 | if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, |
| 1258 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | |
| 1259 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), |
| 1260 | state->aspect_ratio, timings)) |
| 1261 | return 0; |
| 1262 | |
| 1263 | v4l2_dbg(2, debug, sd, |
| 1264 | "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", |
| 1265 | __func__, stdi->lcvs, stdi->lcf, stdi->bl, |
| 1266 | stdi->hs_pol, stdi->vs_pol); |
| 1267 | return -1; |
| 1268 | } |
| 1269 | |
| 1270 | static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) |
| 1271 | { |
| 1272 | u32 status; |
| 1273 | |
| 1274 | adv7842_g_input_status(sd, &status); |
| 1275 | if (status & V4L2_IN_ST_NO_SIGNAL) { |
| 1276 | v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); |
| 1277 | return -ENOLINK; |
| 1278 | } |
| 1279 | |
| 1280 | stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); |
| 1281 | stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); |
| 1282 | stdi->lcvs = cp_read(sd, 0xb3) >> 3; |
| 1283 | |
| 1284 | if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { |
| 1285 | stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? |
| 1286 | ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); |
| 1287 | stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? |
| 1288 | ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); |
| 1289 | } else { |
| 1290 | stdi->hs_pol = 'x'; |
| 1291 | stdi->vs_pol = 'x'; |
| 1292 | } |
| 1293 | stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; |
| 1294 | |
| 1295 | if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { |
| 1296 | v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); |
| 1297 | return -ENOLINK; |
| 1298 | } |
| 1299 | |
| 1300 | v4l2_dbg(2, debug, sd, |
| 1301 | "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", |
| 1302 | __func__, stdi->lcf, stdi->bl, stdi->lcvs, |
| 1303 | stdi->hs_pol, stdi->vs_pol, |
| 1304 | stdi->interlaced ? "interlaced" : "progressive"); |
| 1305 | |
| 1306 | return 0; |
| 1307 | } |
| 1308 | |
| 1309 | static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, |
| 1310 | struct v4l2_enum_dv_timings *timings) |
| 1311 | { |
| 1312 | return v4l2_enum_dv_timings_cap(timings, |
| 1313 | adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); |
| 1314 | } |
| 1315 | |
| 1316 | static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, |
| 1317 | struct v4l2_dv_timings_cap *cap) |
| 1318 | { |
| 1319 | *cap = *adv7842_get_dv_timings_cap(sd); |
| 1320 | return 0; |
| 1321 | } |
| 1322 | |
| 1323 | /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1324 | if the format is listed in adv7842_timings[] */ |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1325 | static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, |
| 1326 | struct v4l2_dv_timings *timings) |
| 1327 | { |
| 1328 | v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), |
| 1329 | is_digital_input(sd) ? 250000 : 1000000, |
| 1330 | adv7842_check_dv_timings, NULL); |
| 1331 | } |
| 1332 | |
| 1333 | static int adv7842_query_dv_timings(struct v4l2_subdev *sd, |
| 1334 | struct v4l2_dv_timings *timings) |
| 1335 | { |
| 1336 | struct adv7842_state *state = to_state(sd); |
| 1337 | struct v4l2_bt_timings *bt = &timings->bt; |
| 1338 | struct stdi_readback stdi = { 0 }; |
| 1339 | |
Martin Bugge | e78d834 | 2013-12-10 10:57:03 -0300 | [diff] [blame] | 1340 | v4l2_dbg(1, debug, sd, "%s:\n", __func__); |
| 1341 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1342 | /* SDP block */ |
| 1343 | if (state->mode == ADV7842_MODE_SDP) |
| 1344 | return -ENODATA; |
| 1345 | |
| 1346 | /* read STDI */ |
| 1347 | if (read_stdi(sd, &stdi)) { |
| 1348 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); |
| 1349 | return -ENOLINK; |
| 1350 | } |
| 1351 | bt->interlaced = stdi.interlaced ? |
| 1352 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1353 | |
| 1354 | if (is_digital_input(sd)) { |
Martin Bugge | e78d834 | 2013-12-10 10:57:03 -0300 | [diff] [blame] | 1355 | uint32_t freq; |
| 1356 | |
| 1357 | timings->type = V4L2_DV_BT_656_1120; |
| 1358 | bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); |
| 1359 | bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); |
| 1360 | freq = (hdmi_read(sd, 0x06) * 1000000) + |
| 1361 | ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1362 | |
| 1363 | if (is_hdmi(sd)) { |
| 1364 | /* adjust for deep color mode */ |
Martin Bugge | e78d834 | 2013-12-10 10:57:03 -0300 | [diff] [blame] | 1365 | freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1366 | } |
Martin Bugge | e78d834 | 2013-12-10 10:57:03 -0300 | [diff] [blame] | 1367 | bt->pixelclock = freq; |
| 1368 | bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1369 | hdmi_read(sd, 0x21); |
Martin Bugge | e78d834 | 2013-12-10 10:57:03 -0300 | [diff] [blame] | 1370 | bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1371 | hdmi_read(sd, 0x23); |
Martin Bugge | e78d834 | 2013-12-10 10:57:03 -0300 | [diff] [blame] | 1372 | bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1373 | hdmi_read(sd, 0x25); |
Martin Bugge | e78d834 | 2013-12-10 10:57:03 -0300 | [diff] [blame] | 1374 | bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + |
| 1375 | hdmi_read(sd, 0x2b)) / 2; |
| 1376 | bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + |
| 1377 | hdmi_read(sd, 0x2f)) / 2; |
| 1378 | bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + |
| 1379 | hdmi_read(sd, 0x33)) / 2; |
| 1380 | bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | |
| 1381 | ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); |
| 1382 | if (bt->interlaced == V4L2_DV_INTERLACED) { |
| 1383 | bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + |
| 1384 | hdmi_read(sd, 0x0c); |
| 1385 | bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + |
| 1386 | hdmi_read(sd, 0x2d)) / 2; |
| 1387 | bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + |
| 1388 | hdmi_read(sd, 0x31)) / 2; |
| 1389 | bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + |
| 1390 | hdmi_read(sd, 0x35)) / 2; |
| 1391 | } |
| 1392 | adv7842_fill_optional_dv_timings_fields(sd, timings); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1393 | } else { |
| 1394 | /* Interlaced? */ |
| 1395 | if (stdi.interlaced) { |
| 1396 | v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__); |
| 1397 | return -ERANGE; |
| 1398 | } |
| 1399 | |
| 1400 | if (stdi2dv_timings(sd, &stdi, timings)) { |
| 1401 | v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); |
| 1402 | return -ERANGE; |
| 1403 | } |
| 1404 | } |
| 1405 | |
| 1406 | if (debug > 1) |
| 1407 | v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings: ", |
| 1408 | timings, true); |
| 1409 | return 0; |
| 1410 | } |
| 1411 | |
| 1412 | static int adv7842_s_dv_timings(struct v4l2_subdev *sd, |
| 1413 | struct v4l2_dv_timings *timings) |
| 1414 | { |
| 1415 | struct adv7842_state *state = to_state(sd); |
| 1416 | struct v4l2_bt_timings *bt; |
| 1417 | int err; |
| 1418 | |
Martin Bugge | e78d834 | 2013-12-10 10:57:03 -0300 | [diff] [blame] | 1419 | v4l2_dbg(1, debug, sd, "%s:\n", __func__); |
| 1420 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1421 | if (state->mode == ADV7842_MODE_SDP) |
| 1422 | return -ENODATA; |
| 1423 | |
| 1424 | bt = &timings->bt; |
| 1425 | |
| 1426 | if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), |
| 1427 | adv7842_check_dv_timings, NULL)) |
| 1428 | return -ERANGE; |
| 1429 | |
| 1430 | adv7842_fill_optional_dv_timings_fields(sd, timings); |
| 1431 | |
| 1432 | state->timings = *timings; |
| 1433 | |
Martin Bugge | 6251e65 | 2013-12-10 11:01:00 -0300 | [diff] [blame] | 1434 | cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1435 | |
| 1436 | /* Use prim_mode and vid_std when available */ |
| 1437 | err = configure_predefined_video_timings(sd, timings); |
| 1438 | if (err) { |
| 1439 | /* custom settings when the video format |
| 1440 | does not have prim_mode/vid_std */ |
| 1441 | configure_custom_video_timings(sd, bt); |
| 1442 | } |
| 1443 | |
| 1444 | set_rgb_quantization_range(sd); |
| 1445 | |
| 1446 | |
| 1447 | if (debug > 1) |
| 1448 | v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", |
| 1449 | timings, true); |
| 1450 | return 0; |
| 1451 | } |
| 1452 | |
| 1453 | static int adv7842_g_dv_timings(struct v4l2_subdev *sd, |
| 1454 | struct v4l2_dv_timings *timings) |
| 1455 | { |
| 1456 | struct adv7842_state *state = to_state(sd); |
| 1457 | |
| 1458 | if (state->mode == ADV7842_MODE_SDP) |
| 1459 | return -ENODATA; |
| 1460 | *timings = state->timings; |
| 1461 | return 0; |
| 1462 | } |
| 1463 | |
| 1464 | static void enable_input(struct v4l2_subdev *sd) |
| 1465 | { |
| 1466 | struct adv7842_state *state = to_state(sd); |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1467 | |
| 1468 | set_rgb_quantization_range(sd); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1469 | switch (state->mode) { |
| 1470 | case ADV7842_MODE_SDP: |
| 1471 | case ADV7842_MODE_COMP: |
| 1472 | case ADV7842_MODE_RGB: |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1473 | io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ |
| 1474 | break; |
| 1475 | case ADV7842_MODE_HDMI: |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1476 | hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ |
| 1477 | io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ |
Mats Randgaard | 5b64b20 | 2013-12-05 12:08:45 -0300 | [diff] [blame] | 1478 | hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1479 | break; |
| 1480 | default: |
| 1481 | v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", |
| 1482 | __func__, state->mode); |
| 1483 | break; |
| 1484 | } |
| 1485 | } |
| 1486 | |
| 1487 | static void disable_input(struct v4l2_subdev *sd) |
| 1488 | { |
Mats Randgaard | 5b64b20 | 2013-12-05 12:08:45 -0300 | [diff] [blame] | 1489 | hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ |
| 1490 | msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1491 | io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1492 | hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ |
| 1493 | } |
| 1494 | |
| 1495 | static void sdp_csc_coeff(struct v4l2_subdev *sd, |
| 1496 | const struct adv7842_sdp_csc_coeff *c) |
| 1497 | { |
| 1498 | /* csc auto/manual */ |
| 1499 | sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); |
| 1500 | |
| 1501 | if (!c->manual) |
| 1502 | return; |
| 1503 | |
| 1504 | /* csc scaling */ |
| 1505 | sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); |
| 1506 | |
| 1507 | /* A coeff */ |
| 1508 | sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); |
| 1509 | sdp_io_write(sd, 0xe1, c->A1); |
| 1510 | sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); |
| 1511 | sdp_io_write(sd, 0xe3, c->A2); |
| 1512 | sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); |
| 1513 | sdp_io_write(sd, 0xe5, c->A3); |
| 1514 | |
| 1515 | /* A scale */ |
| 1516 | sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); |
| 1517 | sdp_io_write(sd, 0xe7, c->A4); |
| 1518 | |
| 1519 | /* B coeff */ |
| 1520 | sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); |
| 1521 | sdp_io_write(sd, 0xe9, c->B1); |
| 1522 | sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); |
| 1523 | sdp_io_write(sd, 0xeb, c->B2); |
| 1524 | sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); |
| 1525 | sdp_io_write(sd, 0xed, c->B3); |
| 1526 | |
| 1527 | /* B scale */ |
| 1528 | sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); |
| 1529 | sdp_io_write(sd, 0xef, c->B4); |
| 1530 | |
| 1531 | /* C coeff */ |
| 1532 | sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); |
| 1533 | sdp_io_write(sd, 0xf1, c->C1); |
| 1534 | sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); |
| 1535 | sdp_io_write(sd, 0xf3, c->C2); |
| 1536 | sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); |
| 1537 | sdp_io_write(sd, 0xf5, c->C3); |
| 1538 | |
| 1539 | /* C scale */ |
| 1540 | sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); |
| 1541 | sdp_io_write(sd, 0xf7, c->C4); |
| 1542 | } |
| 1543 | |
| 1544 | static void select_input(struct v4l2_subdev *sd, |
| 1545 | enum adv7842_vid_std_select vid_std_select) |
| 1546 | { |
| 1547 | struct adv7842_state *state = to_state(sd); |
| 1548 | |
| 1549 | switch (state->mode) { |
| 1550 | case ADV7842_MODE_SDP: |
| 1551 | io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ |
| 1552 | io_write(sd, 0x01, 0); /* prim mode */ |
| 1553 | /* enable embedded syncs for auto graphics mode */ |
| 1554 | cp_write_and_or(sd, 0x81, 0xef, 0x10); |
| 1555 | |
| 1556 | afe_write(sd, 0x00, 0x00); /* power up ADC */ |
| 1557 | afe_write(sd, 0xc8, 0x00); /* phase control */ |
| 1558 | |
| 1559 | io_write(sd, 0x19, 0x83); /* LLC DLL phase */ |
| 1560 | io_write(sd, 0x33, 0x40); /* LLC DLL enable */ |
| 1561 | |
| 1562 | io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ |
| 1563 | /* script says register 0xde, which don't exist in manual */ |
| 1564 | |
| 1565 | /* Manual analog input muxing mode, CVBS (6.4)*/ |
| 1566 | afe_write_and_or(sd, 0x02, 0x7f, 0x80); |
| 1567 | if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { |
| 1568 | afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ |
| 1569 | afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ |
| 1570 | } else { |
| 1571 | afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ |
| 1572 | afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ |
| 1573 | } |
| 1574 | afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ |
| 1575 | afe_write(sd, 0x12, 0x63); /* ADI recommend write */ |
| 1576 | |
| 1577 | sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ |
| 1578 | sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ |
| 1579 | |
| 1580 | /* SDP recommended settings */ |
| 1581 | sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ |
| 1582 | sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ |
| 1583 | |
| 1584 | sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ |
| 1585 | sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ |
| 1586 | sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ |
| 1587 | sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ |
| 1588 | sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ |
| 1589 | sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ |
| 1590 | sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ |
| 1591 | |
| 1592 | /* deinterlacer enabled and 3D comb */ |
| 1593 | sdp_write_and_or(sd, 0x12, 0xf6, 0x09); |
| 1594 | |
| 1595 | sdp_write(sd, 0xdd, 0x08); /* free run auto */ |
| 1596 | |
| 1597 | break; |
| 1598 | |
| 1599 | case ADV7842_MODE_COMP: |
| 1600 | case ADV7842_MODE_RGB: |
| 1601 | /* Automatic analog input muxing mode */ |
| 1602 | afe_write_and_or(sd, 0x02, 0x7f, 0x00); |
| 1603 | /* set mode and select free run resolution */ |
| 1604 | io_write(sd, 0x00, vid_std_select); /* video std */ |
| 1605 | io_write(sd, 0x01, 0x02); /* prim mode */ |
| 1606 | cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs |
| 1607 | for auto graphics mode */ |
| 1608 | |
| 1609 | afe_write(sd, 0x00, 0x00); /* power up ADC */ |
| 1610 | afe_write(sd, 0xc8, 0x00); /* phase control */ |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1611 | if (state->mode == ADV7842_MODE_COMP) { |
| 1612 | /* force to YCrCb */ |
| 1613 | io_write_and_or(sd, 0x02, 0x0f, 0x60); |
| 1614 | } else { |
| 1615 | /* force to RGB */ |
| 1616 | io_write_and_or(sd, 0x02, 0x0f, 0x10); |
| 1617 | } |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1618 | |
| 1619 | /* set ADI recommended settings for digitizer */ |
| 1620 | /* "ADV7842 Register Settings Recommendations |
| 1621 | * (rev. 1.8, November 2010)" p. 9. */ |
| 1622 | afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ |
| 1623 | afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ |
| 1624 | |
| 1625 | /* set to default gain for RGB */ |
| 1626 | cp_write(sd, 0x73, 0x10); |
| 1627 | cp_write(sd, 0x74, 0x04); |
| 1628 | cp_write(sd, 0x75, 0x01); |
| 1629 | cp_write(sd, 0x76, 0x00); |
| 1630 | |
| 1631 | cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ |
| 1632 | cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ |
| 1633 | cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ |
| 1634 | break; |
| 1635 | |
| 1636 | case ADV7842_MODE_HDMI: |
| 1637 | /* Automatic analog input muxing mode */ |
| 1638 | afe_write_and_or(sd, 0x02, 0x7f, 0x00); |
| 1639 | /* set mode and select free run resolution */ |
| 1640 | if (state->hdmi_port_a) |
| 1641 | hdmi_write(sd, 0x00, 0x02); /* select port A */ |
| 1642 | else |
| 1643 | hdmi_write(sd, 0x00, 0x03); /* select port B */ |
| 1644 | io_write(sd, 0x00, vid_std_select); /* video std */ |
| 1645 | io_write(sd, 0x01, 5); /* prim mode */ |
| 1646 | cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs |
| 1647 | for auto graphics mode */ |
| 1648 | |
| 1649 | /* set ADI recommended settings for HDMI: */ |
| 1650 | /* "ADV7842 Register Settings Recommendations |
| 1651 | * (rev. 1.8, November 2010)" p. 3. */ |
| 1652 | hdmi_write(sd, 0xc0, 0x00); |
| 1653 | hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ |
| 1654 | hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ |
| 1655 | hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ |
| 1656 | hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ |
| 1657 | hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ |
| 1658 | hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ |
| 1659 | hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ |
| 1660 | hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ |
| 1661 | hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, |
| 1662 | Improve robustness */ |
| 1663 | hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ |
| 1664 | hdmi_write(sd, 0x85, 0x1f); /* equaliser */ |
| 1665 | hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ |
| 1666 | hdmi_write(sd, 0x89, 0x04); /* equaliser */ |
| 1667 | hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ |
| 1668 | hdmi_write(sd, 0x93, 0x04); /* equaliser */ |
| 1669 | hdmi_write(sd, 0x94, 0x1e); /* equaliser */ |
| 1670 | hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ |
| 1671 | hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ |
| 1672 | hdmi_write(sd, 0x9d, 0x02); /* equaliser */ |
| 1673 | |
| 1674 | afe_write(sd, 0x00, 0xff); /* power down ADC */ |
| 1675 | afe_write(sd, 0xc8, 0x40); /* phase control */ |
| 1676 | |
| 1677 | /* set to default gain for HDMI */ |
| 1678 | cp_write(sd, 0x73, 0x10); |
| 1679 | cp_write(sd, 0x74, 0x04); |
| 1680 | cp_write(sd, 0x75, 0x01); |
| 1681 | cp_write(sd, 0x76, 0x00); |
| 1682 | |
| 1683 | /* reset ADI recommended settings for digitizer */ |
| 1684 | /* "ADV7842 Register Settings Recommendations |
| 1685 | * (rev. 2.5, June 2010)" p. 17. */ |
| 1686 | afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ |
| 1687 | afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ |
| 1688 | cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control, |
| 1689 | enable color control */ |
| 1690 | /* CP coast control */ |
| 1691 | cp_write(sd, 0xc3, 0x33); /* Component mode */ |
| 1692 | |
| 1693 | /* color space conversion, autodetect color space */ |
| 1694 | io_write_and_or(sd, 0x02, 0x0f, 0xf0); |
| 1695 | break; |
| 1696 | |
| 1697 | default: |
| 1698 | v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", |
| 1699 | __func__, state->mode); |
| 1700 | break; |
| 1701 | } |
| 1702 | } |
| 1703 | |
| 1704 | static int adv7842_s_routing(struct v4l2_subdev *sd, |
| 1705 | u32 input, u32 output, u32 config) |
| 1706 | { |
| 1707 | struct adv7842_state *state = to_state(sd); |
| 1708 | |
| 1709 | v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); |
| 1710 | |
| 1711 | switch (input) { |
| 1712 | case ADV7842_SELECT_HDMI_PORT_A: |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1713 | state->mode = ADV7842_MODE_HDMI; |
| 1714 | state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; |
| 1715 | state->hdmi_port_a = true; |
| 1716 | break; |
| 1717 | case ADV7842_SELECT_HDMI_PORT_B: |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1718 | state->mode = ADV7842_MODE_HDMI; |
| 1719 | state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; |
| 1720 | state->hdmi_port_a = false; |
| 1721 | break; |
| 1722 | case ADV7842_SELECT_VGA_COMP: |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 1723 | state->mode = ADV7842_MODE_COMP; |
| 1724 | state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; |
| 1725 | break; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1726 | case ADV7842_SELECT_VGA_RGB: |
| 1727 | state->mode = ADV7842_MODE_RGB; |
| 1728 | state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; |
| 1729 | break; |
| 1730 | case ADV7842_SELECT_SDP_CVBS: |
| 1731 | state->mode = ADV7842_MODE_SDP; |
| 1732 | state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; |
| 1733 | break; |
| 1734 | case ADV7842_SELECT_SDP_YC: |
| 1735 | state->mode = ADV7842_MODE_SDP; |
| 1736 | state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; |
| 1737 | break; |
| 1738 | default: |
| 1739 | return -EINVAL; |
| 1740 | } |
| 1741 | |
| 1742 | disable_input(sd); |
| 1743 | select_input(sd, state->vid_std_select); |
| 1744 | enable_input(sd); |
| 1745 | |
| 1746 | v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); |
| 1747 | |
| 1748 | return 0; |
| 1749 | } |
| 1750 | |
| 1751 | static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, |
| 1752 | enum v4l2_mbus_pixelcode *code) |
| 1753 | { |
| 1754 | if (index) |
| 1755 | return -EINVAL; |
| 1756 | /* Good enough for now */ |
| 1757 | *code = V4L2_MBUS_FMT_FIXED; |
| 1758 | return 0; |
| 1759 | } |
| 1760 | |
| 1761 | static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd, |
| 1762 | struct v4l2_mbus_framefmt *fmt) |
| 1763 | { |
| 1764 | struct adv7842_state *state = to_state(sd); |
| 1765 | |
| 1766 | fmt->width = state->timings.bt.width; |
| 1767 | fmt->height = state->timings.bt.height; |
| 1768 | fmt->code = V4L2_MBUS_FMT_FIXED; |
| 1769 | fmt->field = V4L2_FIELD_NONE; |
| 1770 | |
| 1771 | if (state->mode == ADV7842_MODE_SDP) { |
| 1772 | /* SPD block */ |
| 1773 | if (!(sdp_read(sd, 0x5A) & 0x01)) |
| 1774 | return -EINVAL; |
| 1775 | fmt->width = 720; |
| 1776 | /* valid signal */ |
| 1777 | if (state->norm & V4L2_STD_525_60) |
| 1778 | fmt->height = 480; |
| 1779 | else |
| 1780 | fmt->height = 576; |
| 1781 | fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; |
| 1782 | return 0; |
| 1783 | } |
| 1784 | |
| 1785 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { |
| 1786 | fmt->colorspace = (state->timings.bt.height <= 576) ? |
| 1787 | V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; |
| 1788 | } |
| 1789 | return 0; |
| 1790 | } |
| 1791 | |
| 1792 | static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) |
| 1793 | { |
| 1794 | if (enable) { |
| 1795 | /* Enable SSPD, STDI and CP locked/unlocked interrupts */ |
| 1796 | io_write(sd, 0x46, 0x9c); |
| 1797 | /* ESDP_50HZ_DET interrupt */ |
| 1798 | io_write(sd, 0x5a, 0x10); |
| 1799 | /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ |
| 1800 | io_write(sd, 0x73, 0x03); |
| 1801 | /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ |
| 1802 | io_write(sd, 0x78, 0x03); |
| 1803 | /* Enable SDP Standard Detection Change and SDP Video Detected */ |
| 1804 | io_write(sd, 0xa0, 0x09); |
| 1805 | } else { |
| 1806 | io_write(sd, 0x46, 0x0); |
| 1807 | io_write(sd, 0x5a, 0x0); |
| 1808 | io_write(sd, 0x73, 0x0); |
| 1809 | io_write(sd, 0x78, 0x0); |
| 1810 | io_write(sd, 0xa0, 0x0); |
| 1811 | } |
| 1812 | } |
| 1813 | |
| 1814 | static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) |
| 1815 | { |
| 1816 | struct adv7842_state *state = to_state(sd); |
| 1817 | u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; |
| 1818 | u8 irq_status[5]; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1819 | |
Martin Bugge | c9f1f27 | 2013-12-10 11:14:26 -0300 | [diff] [blame] | 1820 | adv7842_irq_enable(sd, false); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1821 | |
| 1822 | /* read status */ |
| 1823 | irq_status[0] = io_read(sd, 0x43); |
| 1824 | irq_status[1] = io_read(sd, 0x57); |
| 1825 | irq_status[2] = io_read(sd, 0x70); |
| 1826 | irq_status[3] = io_read(sd, 0x75); |
| 1827 | irq_status[4] = io_read(sd, 0x9d); |
| 1828 | |
| 1829 | /* and clear */ |
| 1830 | if (irq_status[0]) |
| 1831 | io_write(sd, 0x44, irq_status[0]); |
| 1832 | if (irq_status[1]) |
| 1833 | io_write(sd, 0x58, irq_status[1]); |
| 1834 | if (irq_status[2]) |
| 1835 | io_write(sd, 0x71, irq_status[2]); |
| 1836 | if (irq_status[3]) |
| 1837 | io_write(sd, 0x76, irq_status[3]); |
| 1838 | if (irq_status[4]) |
| 1839 | io_write(sd, 0x9e, irq_status[4]); |
| 1840 | |
Martin Bugge | c9f1f27 | 2013-12-10 11:14:26 -0300 | [diff] [blame] | 1841 | adv7842_irq_enable(sd, true); |
| 1842 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1843 | v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__, |
| 1844 | irq_status[0], irq_status[1], irq_status[2], |
| 1845 | irq_status[3], irq_status[4]); |
| 1846 | |
| 1847 | /* format change CP */ |
| 1848 | fmt_change_cp = irq_status[0] & 0x9c; |
| 1849 | |
| 1850 | /* format change SDP */ |
| 1851 | if (state->mode == ADV7842_MODE_SDP) |
| 1852 | fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); |
| 1853 | else |
| 1854 | fmt_change_sdp = 0; |
| 1855 | |
| 1856 | /* digital format CP */ |
| 1857 | if (is_digital_input(sd)) |
| 1858 | fmt_change_digital = irq_status[3] & 0x03; |
| 1859 | else |
| 1860 | fmt_change_digital = 0; |
| 1861 | |
| 1862 | /* notify */ |
| 1863 | if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { |
| 1864 | v4l2_dbg(1, debug, sd, |
| 1865 | "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", |
| 1866 | __func__, fmt_change_cp, fmt_change_digital, |
| 1867 | fmt_change_sdp); |
| 1868 | v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); |
| 1869 | } |
| 1870 | |
| 1871 | /* 5v cable detect */ |
| 1872 | if (irq_status[2]) |
| 1873 | adv7842_s_detect_tx_5v_ctrl(sd); |
| 1874 | |
| 1875 | if (handled) |
| 1876 | *handled = true; |
| 1877 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1878 | return 0; |
| 1879 | } |
| 1880 | |
| 1881 | static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e) |
| 1882 | { |
| 1883 | struct adv7842_state *state = to_state(sd); |
| 1884 | int err = 0; |
| 1885 | |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 1886 | if (e->pad > ADV7842_EDID_PORT_VGA) |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1887 | return -EINVAL; |
| 1888 | if (e->start_block != 0) |
| 1889 | return -EINVAL; |
| 1890 | if (e->blocks > 2) |
| 1891 | return -E2BIG; |
| 1892 | if (!e->edid) |
| 1893 | return -EINVAL; |
| 1894 | |
| 1895 | /* todo, per edid */ |
| 1896 | state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], |
| 1897 | e->edid[0x16]); |
| 1898 | |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 1899 | switch (e->pad) { |
| 1900 | case ADV7842_EDID_PORT_VGA: |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1901 | memset(&state->vga_edid.edid, 0, 256); |
| 1902 | state->vga_edid.present = e->blocks ? 0x1 : 0x0; |
| 1903 | memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks); |
| 1904 | err = edid_write_vga_segment(sd); |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 1905 | break; |
| 1906 | case ADV7842_EDID_PORT_A: |
| 1907 | case ADV7842_EDID_PORT_B: |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1908 | memset(&state->hdmi_edid.edid, 0, 256); |
| 1909 | if (e->blocks) |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 1910 | state->hdmi_edid.present |= 0x04 << e->pad; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1911 | else |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 1912 | state->hdmi_edid.present &= ~(0x04 << e->pad); |
| 1913 | memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1914 | err = edid_write_hdmi_segment(sd, e->pad); |
Mats Randgaard | 7de6fab | 2013-12-10 11:24:35 -0300 | [diff] [blame] | 1915 | break; |
| 1916 | default: |
| 1917 | return -EINVAL; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 1918 | } |
| 1919 | if (err < 0) |
| 1920 | v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); |
| 1921 | return err; |
| 1922 | } |
| 1923 | |
| 1924 | /*********** avi info frame CEA-861-E **************/ |
| 1925 | /* TODO move to common library */ |
| 1926 | |
| 1927 | struct avi_info_frame { |
| 1928 | uint8_t f17; |
| 1929 | uint8_t y10; |
| 1930 | uint8_t a0; |
| 1931 | uint8_t b10; |
| 1932 | uint8_t s10; |
| 1933 | uint8_t c10; |
| 1934 | uint8_t m10; |
| 1935 | uint8_t r3210; |
| 1936 | uint8_t itc; |
| 1937 | uint8_t ec210; |
| 1938 | uint8_t q10; |
| 1939 | uint8_t sc10; |
| 1940 | uint8_t f47; |
| 1941 | uint8_t vic; |
| 1942 | uint8_t yq10; |
| 1943 | uint8_t cn10; |
| 1944 | uint8_t pr3210; |
| 1945 | uint16_t etb; |
| 1946 | uint16_t sbb; |
| 1947 | uint16_t elb; |
| 1948 | uint16_t srb; |
| 1949 | }; |
| 1950 | |
| 1951 | static const char *y10_txt[4] = { |
| 1952 | "RGB", |
| 1953 | "YCbCr 4:2:2", |
| 1954 | "YCbCr 4:4:4", |
| 1955 | "Future", |
| 1956 | }; |
| 1957 | |
| 1958 | static const char *c10_txt[4] = { |
| 1959 | "No Data", |
| 1960 | "SMPTE 170M", |
| 1961 | "ITU-R 709", |
| 1962 | "Extended Colorimetry information valied", |
| 1963 | }; |
| 1964 | |
| 1965 | static const char *itc_txt[2] = { |
| 1966 | "No Data", |
| 1967 | "IT content", |
| 1968 | }; |
| 1969 | |
| 1970 | static const char *ec210_txt[8] = { |
| 1971 | "xvYCC601", |
| 1972 | "xvYCC709", |
| 1973 | "sYCC601", |
| 1974 | "AdobeYCC601", |
| 1975 | "AdobeRGB", |
| 1976 | "5 reserved", |
| 1977 | "6 reserved", |
| 1978 | "7 reserved", |
| 1979 | }; |
| 1980 | |
| 1981 | static const char *q10_txt[4] = { |
| 1982 | "Default", |
| 1983 | "Limited Range", |
| 1984 | "Full Range", |
| 1985 | "Reserved", |
| 1986 | }; |
| 1987 | |
| 1988 | static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf, |
| 1989 | struct avi_info_frame *avi) |
| 1990 | { |
| 1991 | avi->f17 = (buf[1] >> 7) & 0x1; |
| 1992 | avi->y10 = (buf[1] >> 5) & 0x3; |
| 1993 | avi->a0 = (buf[1] >> 4) & 0x1; |
| 1994 | avi->b10 = (buf[1] >> 2) & 0x3; |
| 1995 | avi->s10 = buf[1] & 0x3; |
| 1996 | avi->c10 = (buf[2] >> 6) & 0x3; |
| 1997 | avi->m10 = (buf[2] >> 4) & 0x3; |
| 1998 | avi->r3210 = buf[2] & 0xf; |
| 1999 | avi->itc = (buf[3] >> 7) & 0x1; |
| 2000 | avi->ec210 = (buf[3] >> 4) & 0x7; |
| 2001 | avi->q10 = (buf[3] >> 2) & 0x3; |
| 2002 | avi->sc10 = buf[3] & 0x3; |
| 2003 | avi->f47 = (buf[4] >> 7) & 0x1; |
| 2004 | avi->vic = buf[4] & 0x7f; |
| 2005 | avi->yq10 = (buf[5] >> 6) & 0x3; |
| 2006 | avi->cn10 = (buf[5] >> 4) & 0x3; |
| 2007 | avi->pr3210 = buf[5] & 0xf; |
| 2008 | avi->etb = buf[6] + 256*buf[7]; |
| 2009 | avi->sbb = buf[8] + 256*buf[9]; |
| 2010 | avi->elb = buf[10] + 256*buf[11]; |
| 2011 | avi->srb = buf[12] + 256*buf[13]; |
| 2012 | } |
| 2013 | |
| 2014 | static void print_avi_infoframe(struct v4l2_subdev *sd) |
| 2015 | { |
| 2016 | int i; |
| 2017 | uint8_t buf[14]; |
| 2018 | uint8_t avi_inf_len; |
| 2019 | struct avi_info_frame avi; |
| 2020 | |
| 2021 | if (!(hdmi_read(sd, 0x05) & 0x80)) { |
| 2022 | v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); |
| 2023 | return; |
| 2024 | } |
| 2025 | if (!(io_read(sd, 0x60) & 0x01)) { |
| 2026 | v4l2_info(sd, "AVI infoframe not received\n"); |
| 2027 | return; |
| 2028 | } |
| 2029 | |
| 2030 | if (io_read(sd, 0x88) & 0x10) { |
| 2031 | /* Note: the ADV7842 calculated incorrect checksums for InfoFrames |
| 2032 | with a length of 14 or 15. See the ADV7842 Register Settings |
| 2033 | Recommendations document for more details. */ |
| 2034 | v4l2_info(sd, "AVI infoframe checksum error\n"); |
| 2035 | return; |
| 2036 | } |
| 2037 | |
| 2038 | avi_inf_len = infoframe_read(sd, 0xe2); |
| 2039 | v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", |
| 2040 | infoframe_read(sd, 0xe1), avi_inf_len); |
| 2041 | |
| 2042 | if (infoframe_read(sd, 0xe1) != 0x02) |
| 2043 | return; |
| 2044 | |
| 2045 | for (i = 0; i < 14; i++) |
| 2046 | buf[i] = infoframe_read(sd, i); |
| 2047 | |
| 2048 | v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", |
| 2049 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], |
| 2050 | buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); |
| 2051 | |
| 2052 | parse_avi_infoframe(sd, buf, &avi); |
| 2053 | |
| 2054 | if (avi.vic) |
| 2055 | v4l2_info(sd, "\tVIC: %d\n", avi.vic); |
| 2056 | if (avi.itc) |
| 2057 | v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]); |
| 2058 | |
| 2059 | if (avi.y10) |
| 2060 | v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" : |
| 2061 | (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10])); |
| 2062 | else |
| 2063 | v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]); |
| 2064 | } |
| 2065 | |
| 2066 | static const char * const prim_mode_txt[] = { |
| 2067 | "SDP", |
| 2068 | "Component", |
| 2069 | "Graphics", |
| 2070 | "Reserved", |
| 2071 | "CVBS & HDMI AUDIO", |
| 2072 | "HDMI-Comp", |
| 2073 | "HDMI-GR", |
| 2074 | "Reserved", |
| 2075 | "Reserved", |
| 2076 | "Reserved", |
| 2077 | "Reserved", |
| 2078 | "Reserved", |
| 2079 | "Reserved", |
| 2080 | "Reserved", |
| 2081 | "Reserved", |
| 2082 | "Reserved", |
| 2083 | }; |
| 2084 | |
| 2085 | static int adv7842_sdp_log_status(struct v4l2_subdev *sd) |
| 2086 | { |
| 2087 | /* SDP (Standard definition processor) block */ |
| 2088 | uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; |
| 2089 | |
| 2090 | v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); |
| 2091 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", |
| 2092 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); |
| 2093 | |
| 2094 | v4l2_info(sd, "SDP: free run: %s\n", |
| 2095 | (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); |
| 2096 | v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? |
| 2097 | "valid SD/PR signal detected" : "invalid/no signal"); |
| 2098 | if (sdp_signal_detected) { |
| 2099 | static const char * const sdp_std_txt[] = { |
| 2100 | "NTSC-M/J", |
| 2101 | "1?", |
| 2102 | "NTSC-443", |
| 2103 | "60HzSECAM", |
| 2104 | "PAL-M", |
| 2105 | "5?", |
| 2106 | "PAL-60", |
| 2107 | "7?", "8?", "9?", "a?", "b?", |
| 2108 | "PAL-CombN", |
| 2109 | "d?", |
| 2110 | "PAL-BGHID", |
| 2111 | "SECAM" |
| 2112 | }; |
| 2113 | v4l2_info(sd, "SDP: standard %s\n", |
| 2114 | sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); |
| 2115 | v4l2_info(sd, "SDP: %s\n", |
| 2116 | (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); |
| 2117 | v4l2_info(sd, "SDP: %s\n", |
| 2118 | (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); |
| 2119 | v4l2_info(sd, "SDP: deinterlacer %s\n", |
| 2120 | (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); |
| 2121 | v4l2_info(sd, "SDP: csc %s mode\n", |
| 2122 | (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); |
| 2123 | } |
| 2124 | return 0; |
| 2125 | } |
| 2126 | |
| 2127 | static int adv7842_cp_log_status(struct v4l2_subdev *sd) |
| 2128 | { |
| 2129 | /* CP block */ |
| 2130 | struct adv7842_state *state = to_state(sd); |
| 2131 | struct v4l2_dv_timings timings; |
| 2132 | uint8_t reg_io_0x02 = io_read(sd, 0x02); |
| 2133 | uint8_t reg_io_0x21 = io_read(sd, 0x21); |
| 2134 | uint8_t reg_rep_0x77 = rep_read(sd, 0x77); |
| 2135 | uint8_t reg_rep_0x7d = rep_read(sd, 0x7d); |
| 2136 | bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; |
| 2137 | bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; |
| 2138 | bool audio_mute = io_read(sd, 0x65) & 0x40; |
| 2139 | |
| 2140 | static const char * const csc_coeff_sel_rb[16] = { |
| 2141 | "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", |
| 2142 | "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", |
| 2143 | "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", |
| 2144 | "reserved", "reserved", "reserved", "reserved", "manual" |
| 2145 | }; |
| 2146 | static const char * const input_color_space_txt[16] = { |
| 2147 | "RGB limited range (16-235)", "RGB full range (0-255)", |
| 2148 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 2149 | "xvYCC Bt.601", "xvYCC Bt.709", |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2150 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", |
| 2151 | "invalid", "invalid", "invalid", "invalid", "invalid", |
| 2152 | "invalid", "invalid", "automatic" |
| 2153 | }; |
| 2154 | static const char * const rgb_quantization_range_txt[] = { |
| 2155 | "Automatic", |
| 2156 | "RGB limited range (16-235)", |
| 2157 | "RGB full range (0-255)", |
| 2158 | }; |
| 2159 | static const char * const deep_color_mode_txt[4] = { |
| 2160 | "8-bits per channel", |
| 2161 | "10-bits per channel", |
| 2162 | "12-bits per channel", |
| 2163 | "16-bits per channel (not supported)" |
| 2164 | }; |
| 2165 | |
| 2166 | v4l2_info(sd, "-----Chip status-----\n"); |
| 2167 | v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2168 | v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", |
| 2169 | state->hdmi_port_a ? "A" : "B"); |
| 2170 | v4l2_info(sd, "EDID A %s, B %s\n", |
| 2171 | ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? |
| 2172 | "enabled" : "disabled", |
| 2173 | ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? |
| 2174 | "enabled" : "disabled"); |
| 2175 | v4l2_info(sd, "HPD A %s, B %s\n", |
| 2176 | reg_io_0x21 & 0x02 ? "enabled" : "disabled", |
| 2177 | reg_io_0x21 & 0x01 ? "enabled" : "disabled"); |
| 2178 | v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? |
| 2179 | "enabled" : "disabled"); |
| 2180 | |
| 2181 | v4l2_info(sd, "-----Signal status-----\n"); |
| 2182 | if (state->hdmi_port_a) { |
| 2183 | v4l2_info(sd, "Cable detected (+5V power): %s\n", |
| 2184 | io_read(sd, 0x6f) & 0x02 ? "true" : "false"); |
| 2185 | v4l2_info(sd, "TMDS signal detected: %s\n", |
| 2186 | (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); |
| 2187 | v4l2_info(sd, "TMDS signal locked: %s\n", |
| 2188 | (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); |
| 2189 | } else { |
| 2190 | v4l2_info(sd, "Cable detected (+5V power):%s\n", |
| 2191 | io_read(sd, 0x6f) & 0x01 ? "true" : "false"); |
| 2192 | v4l2_info(sd, "TMDS signal detected: %s\n", |
| 2193 | (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); |
| 2194 | v4l2_info(sd, "TMDS signal locked: %s\n", |
| 2195 | (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); |
| 2196 | } |
| 2197 | v4l2_info(sd, "CP free run: %s\n", |
| 2198 | (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); |
| 2199 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", |
| 2200 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, |
| 2201 | (io_read(sd, 0x01) & 0x70) >> 4); |
| 2202 | |
| 2203 | v4l2_info(sd, "-----Video Timings-----\n"); |
| 2204 | if (no_cp_signal(sd)) { |
| 2205 | v4l2_info(sd, "STDI: not locked\n"); |
| 2206 | } else { |
| 2207 | uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); |
| 2208 | uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); |
| 2209 | uint32_t lcvs = cp_read(sd, 0xb3) >> 3; |
| 2210 | uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); |
| 2211 | char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? |
| 2212 | ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); |
| 2213 | char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? |
| 2214 | ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); |
| 2215 | v4l2_info(sd, |
| 2216 | "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", |
| 2217 | lcf, bl, lcvs, fcl, |
| 2218 | (cp_read(sd, 0xb1) & 0x40) ? |
| 2219 | "interlaced" : "progressive", |
| 2220 | hs_pol, vs_pol); |
| 2221 | } |
| 2222 | if (adv7842_query_dv_timings(sd, &timings)) |
| 2223 | v4l2_info(sd, "No video detected\n"); |
| 2224 | else |
| 2225 | v4l2_print_dv_timings(sd->name, "Detected format: ", |
| 2226 | &timings, true); |
| 2227 | v4l2_print_dv_timings(sd->name, "Configured format: ", |
| 2228 | &state->timings, true); |
| 2229 | |
| 2230 | if (no_cp_signal(sd)) |
| 2231 | return 0; |
| 2232 | |
| 2233 | v4l2_info(sd, "-----Color space-----\n"); |
| 2234 | v4l2_info(sd, "RGB quantization range ctrl: %s\n", |
| 2235 | rgb_quantization_range_txt[state->rgb_quantization_range]); |
| 2236 | v4l2_info(sd, "Input color space: %s\n", |
| 2237 | input_color_space_txt[reg_io_0x02 >> 4]); |
| 2238 | v4l2_info(sd, "Output color space: %s %s, saturator %s\n", |
| 2239 | (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", |
| 2240 | (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", |
| 2241 | ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? |
| 2242 | "enabled" : "disabled"); |
| 2243 | v4l2_info(sd, "Color space conversion: %s\n", |
| 2244 | csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); |
| 2245 | |
| 2246 | if (!is_digital_input(sd)) |
| 2247 | return 0; |
| 2248 | |
| 2249 | v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); |
| 2250 | v4l2_info(sd, "HDCP encrypted content: %s\n", |
| 2251 | (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); |
| 2252 | v4l2_info(sd, "HDCP keys read: %s%s\n", |
| 2253 | (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", |
| 2254 | (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); |
| 2255 | if (!is_hdmi(sd)) |
| 2256 | return 0; |
| 2257 | |
| 2258 | v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", |
| 2259 | audio_pll_locked ? "locked" : "not locked", |
| 2260 | audio_sample_packet_detect ? "detected" : "not detected", |
| 2261 | audio_mute ? "muted" : "enabled"); |
| 2262 | if (audio_pll_locked && audio_sample_packet_detect) { |
| 2263 | v4l2_info(sd, "Audio format: %s\n", |
| 2264 | (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); |
| 2265 | } |
| 2266 | v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + |
| 2267 | (hdmi_read(sd, 0x5c) << 8) + |
| 2268 | (hdmi_read(sd, 0x5d) & 0xf0)); |
| 2269 | v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + |
| 2270 | (hdmi_read(sd, 0x5e) << 8) + |
| 2271 | hdmi_read(sd, 0x5f)); |
| 2272 | v4l2_info(sd, "AV Mute: %s\n", |
| 2273 | (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); |
| 2274 | v4l2_info(sd, "Deep color mode: %s\n", |
| 2275 | deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); |
| 2276 | |
| 2277 | print_avi_infoframe(sd); |
| 2278 | return 0; |
| 2279 | } |
| 2280 | |
| 2281 | static int adv7842_log_status(struct v4l2_subdev *sd) |
| 2282 | { |
| 2283 | struct adv7842_state *state = to_state(sd); |
| 2284 | |
| 2285 | if (state->mode == ADV7842_MODE_SDP) |
| 2286 | return adv7842_sdp_log_status(sd); |
| 2287 | return adv7842_cp_log_status(sd); |
| 2288 | } |
| 2289 | |
| 2290 | static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) |
| 2291 | { |
| 2292 | struct adv7842_state *state = to_state(sd); |
| 2293 | |
| 2294 | v4l2_dbg(1, debug, sd, "%s:\n", __func__); |
| 2295 | |
| 2296 | if (state->mode != ADV7842_MODE_SDP) |
| 2297 | return -ENODATA; |
| 2298 | |
| 2299 | if (!(sdp_read(sd, 0x5A) & 0x01)) { |
| 2300 | *std = 0; |
| 2301 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); |
| 2302 | return 0; |
| 2303 | } |
| 2304 | |
| 2305 | switch (sdp_read(sd, 0x52) & 0x0f) { |
| 2306 | case 0: |
| 2307 | /* NTSC-M/J */ |
| 2308 | *std &= V4L2_STD_NTSC; |
| 2309 | break; |
| 2310 | case 2: |
| 2311 | /* NTSC-443 */ |
| 2312 | *std &= V4L2_STD_NTSC_443; |
| 2313 | break; |
| 2314 | case 3: |
| 2315 | /* 60HzSECAM */ |
| 2316 | *std &= V4L2_STD_SECAM; |
| 2317 | break; |
| 2318 | case 4: |
| 2319 | /* PAL-M */ |
| 2320 | *std &= V4L2_STD_PAL_M; |
| 2321 | break; |
| 2322 | case 6: |
| 2323 | /* PAL-60 */ |
| 2324 | *std &= V4L2_STD_PAL_60; |
| 2325 | break; |
| 2326 | case 0xc: |
| 2327 | /* PAL-CombN */ |
| 2328 | *std &= V4L2_STD_PAL_Nc; |
| 2329 | break; |
| 2330 | case 0xe: |
| 2331 | /* PAL-BGHID */ |
| 2332 | *std &= V4L2_STD_PAL; |
| 2333 | break; |
| 2334 | case 0xf: |
| 2335 | /* SECAM */ |
| 2336 | *std &= V4L2_STD_SECAM; |
| 2337 | break; |
| 2338 | default: |
| 2339 | *std &= V4L2_STD_ALL; |
| 2340 | break; |
| 2341 | } |
| 2342 | return 0; |
| 2343 | } |
| 2344 | |
Martin Bugge | 3c4da74 | 2013-12-05 11:52:39 -0300 | [diff] [blame] | 2345 | static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) |
| 2346 | { |
| 2347 | if (s && s->adjust) { |
| 2348 | sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); |
| 2349 | sdp_io_write(sd, 0x95, s->hs_beg & 0xff); |
| 2350 | sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); |
| 2351 | sdp_io_write(sd, 0x97, s->hs_width & 0xff); |
| 2352 | sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); |
| 2353 | sdp_io_write(sd, 0x99, s->de_beg & 0xff); |
| 2354 | sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); |
| 2355 | sdp_io_write(sd, 0x9b, s->de_end & 0xff); |
| 2356 | sdp_io_write(sd, 0xac, s->de_v_beg_o); |
| 2357 | sdp_io_write(sd, 0xad, s->de_v_beg_e); |
| 2358 | sdp_io_write(sd, 0xae, s->de_v_end_o); |
| 2359 | sdp_io_write(sd, 0xaf, s->de_v_end_e); |
| 2360 | } else { |
| 2361 | /* set to default */ |
| 2362 | sdp_io_write(sd, 0x94, 0x00); |
| 2363 | sdp_io_write(sd, 0x95, 0x00); |
| 2364 | sdp_io_write(sd, 0x96, 0x00); |
| 2365 | sdp_io_write(sd, 0x97, 0x20); |
| 2366 | sdp_io_write(sd, 0x98, 0x00); |
| 2367 | sdp_io_write(sd, 0x99, 0x00); |
| 2368 | sdp_io_write(sd, 0x9a, 0x00); |
| 2369 | sdp_io_write(sd, 0x9b, 0x00); |
| 2370 | sdp_io_write(sd, 0xac, 0x04); |
| 2371 | sdp_io_write(sd, 0xad, 0x04); |
| 2372 | sdp_io_write(sd, 0xae, 0x04); |
| 2373 | sdp_io_write(sd, 0xaf, 0x04); |
| 2374 | } |
| 2375 | } |
| 2376 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2377 | static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) |
| 2378 | { |
| 2379 | struct adv7842_state *state = to_state(sd); |
Martin Bugge | 3c4da74 | 2013-12-05 11:52:39 -0300 | [diff] [blame] | 2380 | struct adv7842_platform_data *pdata = &state->pdata; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2381 | |
| 2382 | v4l2_dbg(1, debug, sd, "%s:\n", __func__); |
| 2383 | |
| 2384 | if (state->mode != ADV7842_MODE_SDP) |
| 2385 | return -ENODATA; |
| 2386 | |
Martin Bugge | 3c4da74 | 2013-12-05 11:52:39 -0300 | [diff] [blame] | 2387 | if (norm & V4L2_STD_625_50) |
| 2388 | adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); |
| 2389 | else if (norm & V4L2_STD_525_60) |
| 2390 | adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); |
| 2391 | else |
| 2392 | adv7842_s_sdp_io(sd, NULL); |
| 2393 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2394 | if (norm & V4L2_STD_ALL) { |
| 2395 | state->norm = norm; |
| 2396 | return 0; |
| 2397 | } |
| 2398 | return -EINVAL; |
| 2399 | } |
| 2400 | |
| 2401 | static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) |
| 2402 | { |
| 2403 | struct adv7842_state *state = to_state(sd); |
| 2404 | |
| 2405 | v4l2_dbg(1, debug, sd, "%s:\n", __func__); |
| 2406 | |
| 2407 | if (state->mode != ADV7842_MODE_SDP) |
| 2408 | return -ENODATA; |
| 2409 | |
| 2410 | *norm = state->norm; |
| 2411 | return 0; |
| 2412 | } |
| 2413 | |
| 2414 | /* ----------------------------------------------------------------------- */ |
| 2415 | |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 2416 | static int adv7842_core_init(struct v4l2_subdev *sd) |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2417 | { |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 2418 | struct adv7842_state *state = to_state(sd); |
| 2419 | struct adv7842_platform_data *pdata = &state->pdata; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2420 | hdmi_write(sd, 0x48, |
| 2421 | (pdata->disable_pwrdnb ? 0x80 : 0) | |
| 2422 | (pdata->disable_cable_det_rst ? 0x40 : 0)); |
| 2423 | |
| 2424 | disable_input(sd); |
| 2425 | |
| 2426 | /* power */ |
| 2427 | io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ |
| 2428 | io_write(sd, 0x15, 0x80); /* Power up pads */ |
| 2429 | |
| 2430 | /* video format */ |
| 2431 | io_write(sd, 0x02, |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 2432 | 0xf0 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2433 | pdata->alt_gamma << 3 | |
| 2434 | pdata->op_656_range << 2 | |
| 2435 | pdata->rgb_out << 1 | |
| 2436 | pdata->alt_data_sat << 0); |
| 2437 | io_write(sd, 0x03, pdata->op_format_sel); |
| 2438 | io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5); |
| 2439 | io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | |
| 2440 | pdata->insert_av_codes << 2 | |
| 2441 | pdata->replicate_av_codes << 1 | |
| 2442 | pdata->invert_cbcr << 0); |
| 2443 | |
Mats Randgaard | 5b64b20 | 2013-12-05 12:08:45 -0300 | [diff] [blame] | 2444 | /* HDMI audio */ |
| 2445 | hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ |
| 2446 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2447 | /* Drive strength */ |
| 2448 | io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 | |
| 2449 | pdata->drive_strength.clock<<2 | |
| 2450 | pdata->drive_strength.sync); |
| 2451 | |
| 2452 | /* HDMI free run */ |
| 2453 | cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); |
| 2454 | |
| 2455 | /* TODO from platform data */ |
| 2456 | cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ |
| 2457 | io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ |
| 2458 | cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ |
| 2459 | afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ |
| 2460 | |
| 2461 | afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ |
| 2462 | io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); |
| 2463 | |
| 2464 | sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); |
| 2465 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2466 | /* todo, improve settings for sdram */ |
| 2467 | if (pdata->sd_ram_size >= 128) { |
| 2468 | sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ |
| 2469 | if (pdata->sd_ram_ddr) { |
| 2470 | /* SDP setup for the AD eval board */ |
| 2471 | sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ |
| 2472 | sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ |
| 2473 | sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ |
| 2474 | sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ |
| 2475 | sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ |
| 2476 | } else { |
| 2477 | sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ |
| 2478 | sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ |
| 2479 | sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, |
| 2480 | depends on memory */ |
| 2481 | sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ |
| 2482 | sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ |
| 2483 | sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ |
| 2484 | sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ |
| 2485 | } |
| 2486 | } else { |
| 2487 | /* |
| 2488 | * Manual UG-214, rev 0 is bit confusing on this bit |
| 2489 | * but a '1' disables any signal if the Ram is active. |
| 2490 | */ |
| 2491 | sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ |
| 2492 | } |
| 2493 | |
| 2494 | select_input(sd, pdata->vid_std_select); |
| 2495 | |
| 2496 | enable_input(sd); |
| 2497 | |
| 2498 | /* disable I2C access to internal EDID ram from HDMI DDC ports */ |
| 2499 | rep_write_and_or(sd, 0x77, 0xf3, 0x00); |
| 2500 | |
| 2501 | hdmi_write(sd, 0x69, 0xa3); /* HPA manual */ |
| 2502 | /* HPA disable on port A and B */ |
| 2503 | io_write_and_or(sd, 0x20, 0xcf, 0x00); |
| 2504 | |
| 2505 | /* LLC */ |
| 2506 | /* Set phase to 16. TODO: get this from platform_data */ |
| 2507 | io_write(sd, 0x19, 0x90); |
| 2508 | io_write(sd, 0x33, 0x40); |
| 2509 | |
| 2510 | /* interrupts */ |
Martin Bugge | c9f1f27 | 2013-12-10 11:14:26 -0300 | [diff] [blame] | 2511 | io_write(sd, 0x40, 0xf2); /* Configure INT1 */ |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2512 | |
| 2513 | adv7842_irq_enable(sd, true); |
| 2514 | |
| 2515 | return v4l2_ctrl_handler_setup(sd->ctrl_handler); |
| 2516 | } |
| 2517 | |
| 2518 | /* ----------------------------------------------------------------------- */ |
| 2519 | |
| 2520 | static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) |
| 2521 | { |
| 2522 | /* |
| 2523 | * From ADV784x external Memory test.pdf |
| 2524 | * |
| 2525 | * Reset must just been performed before running test. |
| 2526 | * Recommended to reset after test. |
| 2527 | */ |
| 2528 | int i; |
| 2529 | int pass = 0; |
| 2530 | int fail = 0; |
| 2531 | int complete = 0; |
| 2532 | |
| 2533 | io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ |
| 2534 | io_write(sd, 0x01, 0x00); /* Program SDP mode */ |
| 2535 | afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */ |
| 2536 | afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */ |
| 2537 | afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */ |
| 2538 | afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */ |
| 2539 | afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */ |
| 2540 | afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ |
| 2541 | io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ |
| 2542 | io_write(sd, 0x15, 0xBA); /* Enable outputs */ |
| 2543 | sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ |
| 2544 | io_write(sd, 0xFF, 0x04); /* Reset memory controller */ |
| 2545 | |
| 2546 | mdelay(5); |
| 2547 | |
| 2548 | sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ |
| 2549 | sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ |
| 2550 | sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ |
| 2551 | sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ |
| 2552 | sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ |
| 2553 | sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ |
| 2554 | sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ |
| 2555 | sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ |
| 2556 | sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ |
| 2557 | sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ |
| 2558 | sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ |
| 2559 | |
| 2560 | mdelay(5); |
| 2561 | |
| 2562 | sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ |
| 2563 | sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ |
| 2564 | |
| 2565 | mdelay(20); |
| 2566 | |
| 2567 | for (i = 0; i < 10; i++) { |
| 2568 | u8 result = sdp_io_read(sd, 0xdb); |
| 2569 | if (result & 0x10) { |
| 2570 | complete++; |
| 2571 | if (result & 0x20) |
| 2572 | fail++; |
| 2573 | else |
| 2574 | pass++; |
| 2575 | } |
| 2576 | mdelay(20); |
| 2577 | } |
| 2578 | |
| 2579 | v4l2_dbg(1, debug, sd, |
| 2580 | "Ram Test: completed %d of %d: pass %d, fail %d\n", |
| 2581 | complete, i, pass, fail); |
| 2582 | |
| 2583 | if (!complete || fail) |
| 2584 | return -EIO; |
| 2585 | return 0; |
| 2586 | } |
| 2587 | |
| 2588 | static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, |
| 2589 | struct adv7842_platform_data *pdata) |
| 2590 | { |
| 2591 | io_write(sd, 0xf1, pdata->i2c_sdp << 1); |
| 2592 | io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); |
| 2593 | io_write(sd, 0xf3, pdata->i2c_avlink << 1); |
| 2594 | io_write(sd, 0xf4, pdata->i2c_cec << 1); |
| 2595 | io_write(sd, 0xf5, pdata->i2c_infoframe << 1); |
| 2596 | |
| 2597 | io_write(sd, 0xf8, pdata->i2c_afe << 1); |
| 2598 | io_write(sd, 0xf9, pdata->i2c_repeater << 1); |
| 2599 | io_write(sd, 0xfa, pdata->i2c_edid << 1); |
| 2600 | io_write(sd, 0xfb, pdata->i2c_hdmi << 1); |
| 2601 | |
| 2602 | io_write(sd, 0xfd, pdata->i2c_cp << 1); |
| 2603 | io_write(sd, 0xfe, pdata->i2c_vdp << 1); |
| 2604 | } |
| 2605 | |
| 2606 | static int adv7842_command_ram_test(struct v4l2_subdev *sd) |
| 2607 | { |
| 2608 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 2609 | struct adv7842_state *state = to_state(sd); |
| 2610 | struct adv7842_platform_data *pdata = client->dev.platform_data; |
| 2611 | int ret = 0; |
| 2612 | |
| 2613 | if (!pdata) |
| 2614 | return -ENODEV; |
| 2615 | |
| 2616 | if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { |
| 2617 | v4l2_info(sd, "no sdram or no ddr sdram\n"); |
| 2618 | return -EINVAL; |
| 2619 | } |
| 2620 | |
| 2621 | main_reset(sd); |
| 2622 | |
| 2623 | adv7842_rewrite_i2c_addresses(sd, pdata); |
| 2624 | |
| 2625 | /* run ram test */ |
| 2626 | ret = adv7842_ddr_ram_test(sd); |
| 2627 | |
| 2628 | main_reset(sd); |
| 2629 | |
| 2630 | adv7842_rewrite_i2c_addresses(sd, pdata); |
| 2631 | |
| 2632 | /* and re-init chip and state */ |
Hans Verkuil | 69e9ba6 | 2013-12-20 05:44:27 -0300 | [diff] [blame] | 2633 | adv7842_core_init(sd); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2634 | |
| 2635 | disable_input(sd); |
| 2636 | |
| 2637 | select_input(sd, state->vid_std_select); |
| 2638 | |
| 2639 | enable_input(sd); |
| 2640 | |
| 2641 | adv7842_s_dv_timings(sd, &state->timings); |
| 2642 | |
| 2643 | edid_write_vga_segment(sd); |
Martin Bugge | fc2e991 | 2013-12-05 12:09:51 -0300 | [diff] [blame^] | 2644 | edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); |
| 2645 | edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2646 | |
| 2647 | return ret; |
| 2648 | } |
| 2649 | |
| 2650 | static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) |
| 2651 | { |
| 2652 | switch (cmd) { |
| 2653 | case ADV7842_CMD_RAM_TEST: |
| 2654 | return adv7842_command_ram_test(sd); |
| 2655 | } |
| 2656 | return -ENOTTY; |
| 2657 | } |
| 2658 | |
| 2659 | /* ----------------------------------------------------------------------- */ |
| 2660 | |
| 2661 | static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { |
| 2662 | .s_ctrl = adv7842_s_ctrl, |
| 2663 | }; |
| 2664 | |
| 2665 | static const struct v4l2_subdev_core_ops adv7842_core_ops = { |
| 2666 | .log_status = adv7842_log_status, |
| 2667 | .g_std = adv7842_g_std, |
| 2668 | .s_std = adv7842_s_std, |
| 2669 | .ioctl = adv7842_ioctl, |
| 2670 | .interrupt_service_routine = adv7842_isr, |
| 2671 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 2672 | .g_register = adv7842_g_register, |
| 2673 | .s_register = adv7842_s_register, |
| 2674 | #endif |
| 2675 | }; |
| 2676 | |
| 2677 | static const struct v4l2_subdev_video_ops adv7842_video_ops = { |
| 2678 | .s_routing = adv7842_s_routing, |
| 2679 | .querystd = adv7842_querystd, |
| 2680 | .g_input_status = adv7842_g_input_status, |
| 2681 | .s_dv_timings = adv7842_s_dv_timings, |
| 2682 | .g_dv_timings = adv7842_g_dv_timings, |
| 2683 | .query_dv_timings = adv7842_query_dv_timings, |
| 2684 | .enum_dv_timings = adv7842_enum_dv_timings, |
| 2685 | .dv_timings_cap = adv7842_dv_timings_cap, |
| 2686 | .enum_mbus_fmt = adv7842_enum_mbus_fmt, |
| 2687 | .g_mbus_fmt = adv7842_g_mbus_fmt, |
| 2688 | .try_mbus_fmt = adv7842_g_mbus_fmt, |
| 2689 | .s_mbus_fmt = adv7842_g_mbus_fmt, |
| 2690 | }; |
| 2691 | |
| 2692 | static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { |
| 2693 | .set_edid = adv7842_set_edid, |
| 2694 | }; |
| 2695 | |
| 2696 | static const struct v4l2_subdev_ops adv7842_ops = { |
| 2697 | .core = &adv7842_core_ops, |
| 2698 | .video = &adv7842_video_ops, |
| 2699 | .pad = &adv7842_pad_ops, |
| 2700 | }; |
| 2701 | |
| 2702 | /* -------------------------- custom ctrls ---------------------------------- */ |
| 2703 | |
| 2704 | static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { |
| 2705 | .ops = &adv7842_ctrl_ops, |
| 2706 | .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, |
| 2707 | .name = "Analog Sampling Phase", |
| 2708 | .type = V4L2_CTRL_TYPE_INTEGER, |
| 2709 | .min = 0, |
| 2710 | .max = 0x1f, |
| 2711 | .step = 1, |
| 2712 | .def = 0, |
| 2713 | }; |
| 2714 | |
| 2715 | static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { |
| 2716 | .ops = &adv7842_ctrl_ops, |
| 2717 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, |
| 2718 | .name = "Free Running Color, Manual", |
| 2719 | .type = V4L2_CTRL_TYPE_BOOLEAN, |
| 2720 | .max = 1, |
| 2721 | .step = 1, |
| 2722 | .def = 1, |
| 2723 | }; |
| 2724 | |
| 2725 | static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { |
| 2726 | .ops = &adv7842_ctrl_ops, |
| 2727 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, |
| 2728 | .name = "Free Running Color", |
| 2729 | .type = V4L2_CTRL_TYPE_INTEGER, |
| 2730 | .max = 0xffffff, |
| 2731 | .step = 0x1, |
| 2732 | }; |
| 2733 | |
| 2734 | |
| 2735 | static void adv7842_unregister_clients(struct adv7842_state *state) |
| 2736 | { |
| 2737 | if (state->i2c_avlink) |
| 2738 | i2c_unregister_device(state->i2c_avlink); |
| 2739 | if (state->i2c_cec) |
| 2740 | i2c_unregister_device(state->i2c_cec); |
| 2741 | if (state->i2c_infoframe) |
| 2742 | i2c_unregister_device(state->i2c_infoframe); |
| 2743 | if (state->i2c_sdp_io) |
| 2744 | i2c_unregister_device(state->i2c_sdp_io); |
| 2745 | if (state->i2c_sdp) |
| 2746 | i2c_unregister_device(state->i2c_sdp); |
| 2747 | if (state->i2c_afe) |
| 2748 | i2c_unregister_device(state->i2c_afe); |
| 2749 | if (state->i2c_repeater) |
| 2750 | i2c_unregister_device(state->i2c_repeater); |
| 2751 | if (state->i2c_edid) |
| 2752 | i2c_unregister_device(state->i2c_edid); |
| 2753 | if (state->i2c_hdmi) |
| 2754 | i2c_unregister_device(state->i2c_hdmi); |
| 2755 | if (state->i2c_cp) |
| 2756 | i2c_unregister_device(state->i2c_cp); |
| 2757 | if (state->i2c_vdp) |
| 2758 | i2c_unregister_device(state->i2c_vdp); |
| 2759 | } |
| 2760 | |
| 2761 | static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, |
| 2762 | u8 addr, u8 io_reg) |
| 2763 | { |
| 2764 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 2765 | |
| 2766 | io_write(sd, io_reg, addr << 1); |
| 2767 | return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); |
| 2768 | } |
| 2769 | |
| 2770 | static int adv7842_probe(struct i2c_client *client, |
| 2771 | const struct i2c_device_id *id) |
| 2772 | { |
| 2773 | struct adv7842_state *state; |
| 2774 | struct adv7842_platform_data *pdata = client->dev.platform_data; |
| 2775 | struct v4l2_ctrl_handler *hdl; |
| 2776 | struct v4l2_subdev *sd; |
| 2777 | u16 rev; |
| 2778 | int err; |
| 2779 | |
| 2780 | /* Check if the adapter supports the needed features */ |
| 2781 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) |
| 2782 | return -EIO; |
| 2783 | |
| 2784 | v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", |
| 2785 | client->addr << 1); |
| 2786 | |
| 2787 | if (!pdata) { |
| 2788 | v4l_err(client, "No platform data!\n"); |
| 2789 | return -ENODEV; |
| 2790 | } |
| 2791 | |
| 2792 | state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL); |
| 2793 | if (!state) { |
| 2794 | v4l_err(client, "Could not allocate adv7842_state memory!\n"); |
| 2795 | return -ENOMEM; |
| 2796 | } |
| 2797 | |
Martin Bugge | 7de5be4 | 2013-12-05 11:39:37 -0300 | [diff] [blame] | 2798 | /* platform data */ |
| 2799 | state->pdata = *pdata; |
| 2800 | |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2801 | sd = &state->sd; |
| 2802 | v4l2_i2c_subdev_init(sd, client, &adv7842_ops); |
| 2803 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2804 | state->mode = pdata->mode; |
| 2805 | |
Martin Bugge | 8e4e363 | 2013-12-05 11:55:48 -0300 | [diff] [blame] | 2806 | state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2807 | |
| 2808 | /* i2c access to adv7842? */ |
| 2809 | rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | |
| 2810 | adv_smbus_read_byte_data_check(client, 0xeb, false); |
| 2811 | if (rev != 0x2012) { |
| 2812 | v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); |
| 2813 | rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | |
| 2814 | adv_smbus_read_byte_data_check(client, 0xeb, false); |
| 2815 | } |
| 2816 | if (rev != 0x2012) { |
| 2817 | v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", |
| 2818 | client->addr << 1, rev); |
| 2819 | return -ENODEV; |
| 2820 | } |
| 2821 | |
| 2822 | if (pdata->chip_reset) |
| 2823 | main_reset(sd); |
| 2824 | |
| 2825 | /* control handlers */ |
| 2826 | hdl = &state->hdl; |
| 2827 | v4l2_ctrl_handler_init(hdl, 6); |
| 2828 | |
| 2829 | /* add in ascending ID order */ |
| 2830 | v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, |
| 2831 | V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); |
| 2832 | v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, |
| 2833 | V4L2_CID_CONTRAST, 0, 255, 1, 128); |
| 2834 | v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, |
| 2835 | V4L2_CID_SATURATION, 0, 255, 1, 128); |
| 2836 | v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, |
| 2837 | V4L2_CID_HUE, 0, 128, 1, 0); |
| 2838 | |
| 2839 | /* custom controls */ |
| 2840 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, |
| 2841 | V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); |
| 2842 | state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, |
| 2843 | &adv7842_ctrl_analog_sampling_phase, NULL); |
| 2844 | state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, |
| 2845 | &adv7842_ctrl_free_run_color_manual, NULL); |
| 2846 | state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, |
| 2847 | &adv7842_ctrl_free_run_color, NULL); |
| 2848 | state->rgb_quantization_range_ctrl = |
| 2849 | v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, |
| 2850 | V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, |
| 2851 | 0, V4L2_DV_RGB_RANGE_AUTO); |
| 2852 | sd->ctrl_handler = hdl; |
| 2853 | if (hdl->error) { |
| 2854 | err = hdl->error; |
| 2855 | goto err_hdl; |
| 2856 | } |
| 2857 | state->detect_tx_5v_ctrl->is_private = true; |
| 2858 | state->rgb_quantization_range_ctrl->is_private = true; |
| 2859 | state->analog_sampling_phase_ctrl->is_private = true; |
| 2860 | state->free_run_color_ctrl_manual->is_private = true; |
| 2861 | state->free_run_color_ctrl->is_private = true; |
| 2862 | |
| 2863 | if (adv7842_s_detect_tx_5v_ctrl(sd)) { |
| 2864 | err = -ENODEV; |
| 2865 | goto err_hdl; |
| 2866 | } |
| 2867 | |
| 2868 | state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3); |
| 2869 | state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4); |
| 2870 | state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5); |
| 2871 | state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2); |
| 2872 | state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1); |
| 2873 | state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8); |
| 2874 | state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9); |
| 2875 | state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa); |
| 2876 | state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb); |
| 2877 | state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd); |
| 2878 | state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe); |
| 2879 | if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe || |
| 2880 | !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe || |
| 2881 | !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi || |
| 2882 | !state->i2c_cp || !state->i2c_vdp) { |
| 2883 | err = -ENOMEM; |
| 2884 | v4l2_err(sd, "failed to create all i2c clients\n"); |
| 2885 | goto err_i2c; |
| 2886 | } |
| 2887 | |
| 2888 | /* work queues */ |
| 2889 | state->work_queues = create_singlethread_workqueue(client->name); |
| 2890 | if (!state->work_queues) { |
| 2891 | v4l2_err(sd, "Could not create work queue\n"); |
| 2892 | err = -ENOMEM; |
| 2893 | goto err_i2c; |
| 2894 | } |
| 2895 | |
| 2896 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, |
| 2897 | adv7842_delayed_work_enable_hotplug); |
| 2898 | |
| 2899 | state->pad.flags = MEDIA_PAD_FL_SOURCE; |
| 2900 | err = media_entity_init(&sd->entity, 1, &state->pad, 0); |
| 2901 | if (err) |
| 2902 | goto err_work_queues; |
| 2903 | |
Martin Bugge | 7de5be4 | 2013-12-05 11:39:37 -0300 | [diff] [blame] | 2904 | err = adv7842_core_init(sd); |
Hans Verkuil | a89bcd4 | 2013-08-22 06:14:22 -0300 | [diff] [blame] | 2905 | if (err) |
| 2906 | goto err_entity; |
| 2907 | |
| 2908 | v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, |
| 2909 | client->addr << 1, client->adapter->name); |
| 2910 | return 0; |
| 2911 | |
| 2912 | err_entity: |
| 2913 | media_entity_cleanup(&sd->entity); |
| 2914 | err_work_queues: |
| 2915 | cancel_delayed_work(&state->delayed_work_enable_hotplug); |
| 2916 | destroy_workqueue(state->work_queues); |
| 2917 | err_i2c: |
| 2918 | adv7842_unregister_clients(state); |
| 2919 | err_hdl: |
| 2920 | v4l2_ctrl_handler_free(hdl); |
| 2921 | return err; |
| 2922 | } |
| 2923 | |
| 2924 | /* ----------------------------------------------------------------------- */ |
| 2925 | |
| 2926 | static int adv7842_remove(struct i2c_client *client) |
| 2927 | { |
| 2928 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
| 2929 | struct adv7842_state *state = to_state(sd); |
| 2930 | |
| 2931 | adv7842_irq_enable(sd, false); |
| 2932 | |
| 2933 | cancel_delayed_work(&state->delayed_work_enable_hotplug); |
| 2934 | destroy_workqueue(state->work_queues); |
| 2935 | v4l2_device_unregister_subdev(sd); |
| 2936 | media_entity_cleanup(&sd->entity); |
| 2937 | adv7842_unregister_clients(to_state(sd)); |
| 2938 | v4l2_ctrl_handler_free(sd->ctrl_handler); |
| 2939 | return 0; |
| 2940 | } |
| 2941 | |
| 2942 | /* ----------------------------------------------------------------------- */ |
| 2943 | |
| 2944 | static struct i2c_device_id adv7842_id[] = { |
| 2945 | { "adv7842", 0 }, |
| 2946 | { } |
| 2947 | }; |
| 2948 | MODULE_DEVICE_TABLE(i2c, adv7842_id); |
| 2949 | |
| 2950 | /* ----------------------------------------------------------------------- */ |
| 2951 | |
| 2952 | static struct i2c_driver adv7842_driver = { |
| 2953 | .driver = { |
| 2954 | .owner = THIS_MODULE, |
| 2955 | .name = "adv7842", |
| 2956 | }, |
| 2957 | .probe = adv7842_probe, |
| 2958 | .remove = adv7842_remove, |
| 2959 | .id_table = adv7842_id, |
| 2960 | }; |
| 2961 | |
| 2962 | module_i2c_driver(adv7842_driver); |