blob: 15c595e0a63b62893647b1a1429cd8acd057132f [file] [log] [blame]
Zhi Wang0ad35fe2016-06-16 08:07:00 -04001/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
Zhi Wang12d14cc2016-08-30 11:06:17 +080022 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 *
27 * Contributors:
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 *
Zhi Wang0ad35fe2016-06-16 08:07:00 -040031 */
32
33#ifndef _GVT_H_
34#define _GVT_H_
35
36#include "debug.h"
37#include "hypercall.h"
Zhi Wang12d14cc2016-08-30 11:06:17 +080038#include "mmio.h"
Zhi Wang82d375d2016-07-05 12:40:49 -040039#include "reg.h"
Zhi Wangc8fe6a682015-09-17 09:22:08 +080040#include "interrupt.h"
Zhi Wang2707e442016-03-28 23:23:16 +080041#include "gtt.h"
Zhi Wang04d348a2016-04-25 18:28:56 -040042#include "display.h"
43#include "edid.h"
Zhi Wang8453d672016-05-01 02:48:25 -040044#include "execlist.h"
Zhi Wang28c4c6c2016-05-01 05:22:47 -040045#include "scheduler.h"
Zhi Wang4b639602016-05-01 17:09:58 -040046#include "sched_policy.h"
Zhi Wang17865712016-05-01 19:02:37 -040047#include "render.h"
Zhi Wangbe1da702016-05-03 18:26:57 -040048#include "cmd_parser.h"
Zhi Wang0ad35fe2016-06-16 08:07:00 -040049
50#define GVT_MAX_VGPU 8
51
52enum {
53 INTEL_GVT_HYPERVISOR_XEN = 0,
54 INTEL_GVT_HYPERVISOR_KVM,
55};
56
57struct intel_gvt_host {
58 bool initialized;
59 int hypervisor_type;
60 struct intel_gvt_mpt *mpt;
61};
62
63extern struct intel_gvt_host intel_gvt_host;
64
65/* Describe per-platform limitations. */
66struct intel_gvt_device_info {
67 u32 max_support_vgpus;
Zhi Wang579cea52016-06-30 12:45:34 -040068 u32 cfg_space_size;
Zhi Wangc8fe6a682015-09-17 09:22:08 +080069 u32 mmio_size;
Zhi Wang579cea52016-06-30 12:45:34 -040070 u32 mmio_bar;
Zhi Wangc8fe6a682015-09-17 09:22:08 +080071 unsigned long msi_cap_offset;
Zhi Wang2707e442016-03-28 23:23:16 +080072 u32 gtt_start_offset;
73 u32 gtt_entry_size;
74 u32 gtt_entry_size_shift;
Zhi Wangbe1da702016-05-03 18:26:57 -040075 int gmadr_bytes_in_cmd;
76 u32 max_surface_size;
Zhi Wang0ad35fe2016-06-16 08:07:00 -040077};
78
Zhi Wang28a60de2016-09-02 12:41:29 +080079/* GM resources owned by a vGPU */
80struct intel_vgpu_gm {
81 u64 aperture_sz;
82 u64 hidden_sz;
83 struct drm_mm_node low_gm_node;
84 struct drm_mm_node high_gm_node;
85};
86
87#define INTEL_GVT_MAX_NUM_FENCES 32
88
89/* Fences owned by a vGPU */
90struct intel_vgpu_fence {
91 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
92 u32 base;
93 u32 size;
94};
95
Zhi Wang82d375d2016-07-05 12:40:49 -040096struct intel_vgpu_mmio {
97 void *vreg;
98 void *sreg;
Zhi Wange39c5ad2016-09-02 13:33:29 +080099 bool disable_warn_untrack;
Zhi Wang82d375d2016-07-05 12:40:49 -0400100};
101
102#define INTEL_GVT_MAX_CFG_SPACE_SZ 256
103#define INTEL_GVT_MAX_BAR_NUM 4
104
105struct intel_vgpu_pci_bar {
106 u64 size;
107 bool tracked;
108};
109
110struct intel_vgpu_cfg_space {
111 unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
112 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
113};
114
115#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
116
Zhi Wang04d348a2016-04-25 18:28:56 -0400117#define INTEL_GVT_MAX_PIPE 4
118
Zhi Wangc8fe6a682015-09-17 09:22:08 +0800119struct intel_vgpu_irq {
120 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
Zhi Wang04d348a2016-04-25 18:28:56 -0400121 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
122 INTEL_GVT_EVENT_MAX);
Zhi Wangc8fe6a682015-09-17 09:22:08 +0800123};
124
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400125struct intel_vgpu_opregion {
126 void *va;
127 u32 gfn[INTEL_GVT_OPREGION_PAGES];
128 struct page *pages[INTEL_GVT_OPREGION_PAGES];
129};
130
131#define vgpu_opregion(vgpu) (&(vgpu->opregion))
132
Zhi Wang04d348a2016-04-25 18:28:56 -0400133#define INTEL_GVT_MAX_PORT 5
134
135struct intel_vgpu_display {
136 struct intel_vgpu_i2c_edid i2c_edid;
137 struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT];
138 struct intel_vgpu_sbi sbi;
139};
140
Zhi Wang0ad35fe2016-06-16 08:07:00 -0400141struct intel_vgpu {
142 struct intel_gvt *gvt;
143 int id;
144 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
Zhi Wang82d375d2016-07-05 12:40:49 -0400145 bool active;
146 bool resetting;
Zhi Wang4b639602016-05-01 17:09:58 -0400147 void *sched_data;
Zhi Wang28a60de2016-09-02 12:41:29 +0800148
149 struct intel_vgpu_fence fence;
150 struct intel_vgpu_gm gm;
Zhi Wang82d375d2016-07-05 12:40:49 -0400151 struct intel_vgpu_cfg_space cfg_space;
152 struct intel_vgpu_mmio mmio;
Zhi Wangc8fe6a682015-09-17 09:22:08 +0800153 struct intel_vgpu_irq irq;
Zhi Wang2707e442016-03-28 23:23:16 +0800154 struct intel_vgpu_gtt gtt;
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400155 struct intel_vgpu_opregion opregion;
Zhi Wang04d348a2016-04-25 18:28:56 -0400156 struct intel_vgpu_display display;
Zhi Wang8453d672016-05-01 02:48:25 -0400157 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400158 struct list_head workload_q_head[I915_NUM_ENGINES];
159 struct kmem_cache *workloads;
Zhi Wange4734052016-05-01 07:42:16 -0400160 atomic_t running_workload_num;
Zhi Wang17865712016-05-01 19:02:37 -0400161 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
Zhi Wange4734052016-05-01 07:42:16 -0400162 struct i915_gem_context *shadow_ctx;
163 struct notifier_block shadow_ctx_notifier_block;
Zhi Wang28a60de2016-09-02 12:41:29 +0800164};
165
166struct intel_gvt_gm {
167 unsigned long vgpu_allocated_low_gm_size;
168 unsigned long vgpu_allocated_high_gm_size;
169};
170
171struct intel_gvt_fence {
172 unsigned long vgpu_allocated_fence_num;
Zhi Wang0ad35fe2016-06-16 08:07:00 -0400173};
174
Zhi Wang12d14cc2016-08-30 11:06:17 +0800175#define INTEL_GVT_MMIO_HASH_BITS 9
176
177struct intel_gvt_mmio {
178 u32 *mmio_attribute;
179 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
180};
181
Zhi Wang579cea52016-06-30 12:45:34 -0400182struct intel_gvt_firmware {
183 void *cfg_space;
184 void *mmio;
185 bool firmware_loaded;
186};
187
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400188struct intel_gvt_opregion {
189 void *opregion_va;
190 u32 opregion_pa;
191};
192
Zhi Wang0ad35fe2016-06-16 08:07:00 -0400193struct intel_gvt {
194 struct mutex lock;
Zhi Wang0ad35fe2016-06-16 08:07:00 -0400195 struct drm_i915_private *dev_priv;
196 struct idr vgpu_idr; /* vGPU IDR pool */
197
198 struct intel_gvt_device_info device_info;
Zhi Wang28a60de2016-09-02 12:41:29 +0800199 struct intel_gvt_gm gm;
200 struct intel_gvt_fence fence;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800201 struct intel_gvt_mmio mmio;
Zhi Wang579cea52016-06-30 12:45:34 -0400202 struct intel_gvt_firmware firmware;
Zhi Wangc8fe6a682015-09-17 09:22:08 +0800203 struct intel_gvt_irq irq;
Zhi Wang2707e442016-03-28 23:23:16 +0800204 struct intel_gvt_gtt gtt;
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400205 struct intel_gvt_opregion opregion;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400206 struct intel_gvt_workload_scheduler scheduler;
Zhi Wangbe1da702016-05-03 18:26:57 -0400207 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
Zhi Wang04d348a2016-04-25 18:28:56 -0400208
209 struct task_struct *service_thread;
210 wait_queue_head_t service_thread_wq;
211 unsigned long service_request;
Zhi Wang0ad35fe2016-06-16 08:07:00 -0400212};
213
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +0800214static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
215{
216 return i915->gvt;
217}
218
Zhi Wang04d348a2016-04-25 18:28:56 -0400219enum {
220 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
221};
222
223static inline void intel_gvt_request_service(struct intel_gvt *gvt,
224 int service)
225{
226 set_bit(service, (void *)&gvt->service_request);
227 wake_up(&gvt->service_thread_wq);
228}
229
Zhi Wang579cea52016-06-30 12:45:34 -0400230void intel_gvt_free_firmware(struct intel_gvt *gvt);
231int intel_gvt_load_firmware(struct intel_gvt *gvt);
232
Zhi Wang28a60de2016-09-02 12:41:29 +0800233/* Aperture/GM space definitions for GVT device */
234#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
235#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
236
237#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)
Zhi Wange39c5ad2016-09-02 13:33:29 +0800238#define gvt_ggtt_sz(gvt) \
239 ((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3)
Zhi Wang28a60de2016-09-02 12:41:29 +0800240#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
241
242#define gvt_aperture_gmadr_base(gvt) (0)
243#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
244 + gvt_aperture_sz(gvt) - 1)
245
246#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
247 + gvt_aperture_sz(gvt))
248#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
249 + gvt_hidden_sz(gvt) - 1)
250
251#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)
252
253/* Aperture/GM space definitions for vGPU */
254#define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
255#define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
256#define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
257#define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
258
259#define vgpu_aperture_pa_base(vgpu) \
260 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
261
262#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
263
264#define vgpu_aperture_pa_end(vgpu) \
265 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
266
267#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
268#define vgpu_aperture_gmadr_end(vgpu) \
269 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
270
271#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
272#define vgpu_hidden_gmadr_end(vgpu) \
273 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
274
275#define vgpu_fence_base(vgpu) (vgpu->fence.base)
276#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
277
278struct intel_vgpu_creation_params {
279 __u64 handle;
280 __u64 low_gm_sz; /* in MB */
281 __u64 high_gm_sz; /* in MB */
282 __u64 fence_sz;
283 __s32 primary;
284 __u64 vgpu_id;
285};
286
287int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
288 struct intel_vgpu_creation_params *param);
289void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
290void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
291 u32 fence, u64 value);
292
Zhi Wang82d375d2016-07-05 12:40:49 -0400293/* Macros for easily accessing vGPU virtual/shadow register */
294#define vgpu_vreg(vgpu, reg) \
295 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
296#define vgpu_vreg8(vgpu, reg) \
297 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
298#define vgpu_vreg16(vgpu, reg) \
299 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
300#define vgpu_vreg64(vgpu, reg) \
301 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
302#define vgpu_sreg(vgpu, reg) \
303 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
304#define vgpu_sreg8(vgpu, reg) \
305 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
306#define vgpu_sreg16(vgpu, reg) \
307 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
308#define vgpu_sreg64(vgpu, reg) \
309 (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
310
311#define for_each_active_vgpu(gvt, vgpu, id) \
312 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
313 for_each_if(vgpu->active)
314
315static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
316 u32 offset, u32 val, bool low)
317{
318 u32 *pval;
319
320 /* BAR offset should be 32 bits algiend */
321 offset = rounddown(offset, 4);
322 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
323
324 if (low) {
325 /*
326 * only update bit 31 - bit 4,
327 * leave the bit 3 - bit 0 unchanged.
328 */
329 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
330 }
331}
332
333struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
334 struct intel_vgpu_creation_params *
335 param);
336
337void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
338
Zhi Wang2707e442016-03-28 23:23:16 +0800339/* validating GM functions */
340#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
341 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
342 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
343
344#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
345 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
346 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
347
348#define vgpu_gmadr_is_valid(vgpu, gmadr) \
349 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
350 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
351
352#define gvt_gmadr_is_aperture(gvt, gmadr) \
353 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
354 (gmadr <= gvt_aperture_gmadr_end(gvt)))
355
356#define gvt_gmadr_is_hidden(gvt, gmadr) \
357 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
358 (gmadr <= gvt_hidden_gmadr_end(gvt)))
359
360#define gvt_gmadr_is_valid(gvt, gmadr) \
361 (gvt_gmadr_is_aperture(gvt, gmadr) || \
362 gvt_gmadr_is_hidden(gvt, gmadr))
363
364bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
365int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
366int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
367int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
368 unsigned long *h_index);
369int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
370 unsigned long *g_index);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400371
372int intel_vgpu_emulate_cfg_read(void *__vgpu, unsigned int offset,
373 void *p_data, unsigned int bytes);
374
375int intel_vgpu_emulate_cfg_write(void *__vgpu, unsigned int offset,
376 void *p_data, unsigned int bytes);
377
378void intel_gvt_clean_opregion(struct intel_gvt *gvt);
379int intel_gvt_init_opregion(struct intel_gvt *gvt);
380
381void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
382int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);
383
384int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
385
Zhi Wang0ad35fe2016-06-16 08:07:00 -0400386#include "mpt.h"
387
388#endif