| commit | 174bbb37a32febb2d0c21148c8d2dab186e37a47 | [log] [tgz] |
|---|---|---|
| author | Siddhartha Agrawal <agrawals@codeaurora.org> | Fri Sep 05 10:44:54 2014 -0700 |
| committer | Narendra Muppalla <NarendraM@codeaurora.org> | Fri Jan 13 15:41:21 2017 -0800 |
| tree | d92a548e536d704d76afa383285960f760e48751 | |
| parent | a91de84b7874d5fa95477005179b66c97723bc36 [diff] |
clk: msm: mdss: Add support for DSI PLL 1 clock registration Setup DSI 1 PLL clock heirarchy. This is needed for instances where we need to turn off the second pll in case of current leak issue. Change-Id: I694af1fa9591b2345709687c9e7b1d69f15b56a9 Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org> Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>