| Qualcomm Technologies, Inc. OSM Bindings |
| |
| Operating State Manager (OSM) is a hardware engine used by some Qualcomm |
| Technologies, Inc. (QTI) SoCs to manage frequency and voltage scaling |
| in hardware. OSM is capable of controlling frequency and voltage requests |
| for multiple clusters via the existence of multiple OSM domains. |
| |
| Properties: |
| - compatible |
| Usage: required |
| Value type: <string> |
| Definition: must be "qcom,clk-cpu-osm", "qcom,clk-cpu-osm-v2" or |
| "qcom,clk-cpu-osm-sdm670". |
| |
| - reg |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Addresses and sizes for the memory of the OSM controller. |
| |
| - reg-names |
| Usage: required |
| Value type: <stringlist> |
| Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base", |
| "osm_perfcl_base". |
| Must be specified in the same order as the corresponding |
| addresses are specified in the reg property. |
| |
| - l3-devs |
| Usage: optional |
| Value type: <phandle> |
| Definition: List of phandles to devices that the OPP tables with the L3 |
| frequency and voltage mappings are loaded for. |
| |
| - clock-names |
| Usage: required |
| Value type: <string> |
| Definition: Must be "aux_clk". |
| |
| - clocks |
| Usage: required |
| Value type: <phandle> |
| Definition: Phandle to the aux clock device. |
| |
| Example: |
| clock_cpucc: qcom,cpucc@0x17d41000 { |
| compatible = "qcom,clk-cpu-osm"; |
| reg = <0x17d41000 0x1400>, |
| <0x17d43000 0x1400>, |
| <0x17d45800 0x1400>; |
| reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base"; |
| |
| l3-devs = <&phandle0 &phandle1 &phandle2>; |
| |
| clock-names = "xo_ao"; |
| clocks = <&clock_rpmh RPMH_CXO_CLK_A>; |
| #clock-cells = <1>; |
| }; |