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Deepak Katragadda7abd9312016-12-21 14:18:00 -08001Qualcomm Technologies, Inc. OSM Bindings
2
3Operating State Manager (OSM) is a hardware engine used by some Qualcomm
4Technologies, Inc. (QTI) SoCs to manage frequency and voltage scaling
5in hardware. OSM is capable of controlling frequency and voltage requests
6for multiple clusters via the existence of multiple OSM domains.
7
8Properties:
9- compatible
10 Usage: required
11 Value type: <string>
Odelu Kukatla3799c7c2017-08-20 20:48:45 +053012 Definition: must be "qcom,clk-cpu-osm", "qcom,clk-cpu-osm-v2" or
13 "qcom,clk-cpu-osm-sdm670".
Deepak Katragadda7abd9312016-12-21 14:18:00 -080014
15- reg
16 Usage: required
17 Value type: <prop-encoded-array>
Deepak Katragaddacc3e9472017-07-07 10:30:15 -070018 Definition: Addresses and sizes for the memory of the OSM controller.
Deepak Katragadda7abd9312016-12-21 14:18:00 -080019
20- reg-names
21 Usage: required
22 Value type: <stringlist>
23 Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base",
Deepak Katragaddacc3e9472017-07-07 10:30:15 -070024 "osm_perfcl_base".
Deepak Katragadda7abd9312016-12-21 14:18:00 -080025 Must be specified in the same order as the corresponding
26 addresses are specified in the reg property.
Deepak Katragaddaeda782e2017-10-12 11:06:28 -070027
28- l3-devs
29 Usage: optional
30 Value type: <phandle>
31 Definition: List of phandles to devices that the OPP tables with the L3
32 frequency and voltage mappings are loaded for.
33
Deepak Katragadda7abd9312016-12-21 14:18:00 -080034- clock-names
35 Usage: required
36 Value type: <string>
37 Definition: Must be "aux_clk".
38
39- clocks
40 Usage: required
41 Value type: <phandle>
42 Definition: Phandle to the aux clock device.
43
44Example:
45 clock_cpucc: qcom,cpucc@0x17d41000 {
46 compatible = "qcom,clk-cpu-osm";
47 reg = <0x17d41000 0x1400>,
48 <0x17d43000 0x1400>,
Deepak Katragaddacc3e9472017-07-07 10:30:15 -070049 <0x17d45800 0x1400>;
50 reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
Deepak Katragadda7abd9312016-12-21 14:18:00 -080051
Deepak Katragaddaeda782e2017-10-12 11:06:28 -070052 l3-devs = <&phandle0 &phandle1 &phandle2>;
53
Deepak Katragadda7abd9312016-12-21 14:18:00 -080054 clock-names = "xo_ao";
55 clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
56 #clock-cells = <1>;
Deepak Katragadda7abd9312016-12-21 14:18:00 -080057 };